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clk_prepare_enable() may fail, so let's check its return value and propagate it
in the case of error.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"
parallel display support / DVI needs the original setting to work
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Rogerio Pimentel <rpimentel.silva@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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partial fix of changes from
"staging: drm/imx: Add support for VGA via TVE on i.MX53"
Have to check for vsync_pin instead of hsync_pin to set Vsync_pol.
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Rogerio Pimentel <rpimentel.silva@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This adds display interface timings for the Television Encoder
connected to IPU DI1 on i.MX53 and adds some configuration
glue code to select which IPU signal generators / pins are to
be used for HSYNC/VSYNC signals.
The default configuration is pin2/pin3 for hsync/vsync. The
VGA connector on i.MX53-QSB uses pin7/pin8, and the analog
part of the DVI-I connector on MBa53 connects to pin4/pin6.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Currently when ipuv3 is probed we have:
imx-ipuv3 40000000.ipu: DI0 base: 0x5e040000 remapped to a08aa000
imx-ipuv3 40000000.ipu: DI1 base: 0x5e048000 remapped to a08ac000
imx-ipuv3 40000000.ipu: IPUv3EX probed
The DI base address and the remapped address are more interesting for debug
purposes, so mark this message as dev_dbg instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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The IPU is the Image Processing Unit found on i.MX51/53/6 SoCs. It
features several units for image processing, this patch adds support
for the units needed for Framebuffer support, namely:
- Display Controller (dc)
- Display Interface (di)
- Display Multi Fifo Controller (dmfc)
- Display Processor (dp)
- Image DMA Controller (idmac)
This patch is based on the Freescale driver, but follows a different
approach. The Freescale code implements logical idmac channels and
the handling of the subunits is hidden in common idmac code pathes
in big switch/case statements. This patch instead just provides code
and resource management for the different subunits. The user, in this
case the framebuffer driver, decides how the different units play
together.
The IPU has other units missing in this patch:
- CMOS Sensor Interface (csi)
- Video Deinterlacer (vdi)
- Sensor Multi FIFO Controler (smfc)
- Image Converter (ic)
- Image Rotator (irt)
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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