From 1f6bb110424334e2cf726ca703c0f9441b402922 Mon Sep 17 00:00:00 2001 From: Wang Dongsheng Date: Tue, 17 Sep 2013 10:21:50 +0800 Subject: fsl/powerpc: fix cpu_setup_fsl_booke.S build error when we use corenet32_smp_defconfig. Occur, the following error: cpu_setup_fsl_booke.S:83: undefined reference to `.has_pw20_altivec_idle' cpu_setup_fsl_booke.S:108: undefined reference to `.has_pw20_altivec_idle' The root cause is "bl .has_pw20_altivec_idle", the "." is only for 64bit, should be "bl has_pw20_altivec_idle". Signed-off-by: Wang Dongsheng Change-Id: I13b654b400313a351e50b4105eabb9affa013c34 Reviewed-on: http://git.am.freescale.net:8181/4779 Tested-by: Review Code-CDREVIEW Reviewed-by: Zhao Chenhui-B35336 Reviewed-by: Rivera Jose-B46482 diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index c39bbfb..f5ee308 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -80,7 +80,7 @@ _GLOBAL(has_pw20_altivec_idle) #define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ _GLOBAL(setup_pw20_idle) mflr r10 - bl .has_pw20_altivec_idle + bl has_pw20_altivec_idle mtlr r10 cmpwi r3, 0 beq 2f @@ -105,7 +105,7 @@ _GLOBAL(setup_pw20_idle) #define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ _GLOBAL(setup_altivec_idle) mflr r10 - bl .has_pw20_altivec_idle + bl has_pw20_altivec_idle mtlr r10 cmpwi r3, 0 beq 2f -- cgit v0.10.2