From fa5e2936424e920f2ae217961b877aa1ac890442 Mon Sep 17 00:00:00 2001
From: Minghuan Lian <Minghuan.Lian@freescale.com>
Date: Tue, 30 Jul 2013 11:34:27 +0800
Subject: powerpc/dts: fix sRIO and RMan error interrupts for b4860

For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO and RMan EISR bit
value of error interrupts in dts node.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: I3eacf5ebee6da5ac847d6ab93fe1e38a07e57176
Reviewed-on: http://git.am.freescale.net:8181/3616
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>

diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index a166d1c..d2192e7 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -376,7 +376,7 @@
 
 &rio {
 	compatible = "fsl,srio";
-	interrupts = <16 2 1 11>;
+	interrupts = <16 2 1 20>;
 	#address-cells = <2>;
 	#size-cells = <2>;
 	fsl,iommu-parent = <&pamu0>;
@@ -521,5 +521,6 @@
 /include/ "qoriq-rman-0.dtsi"
 	rman: rman@1e0000 {
 		fsl,qman-channels-id = <0x820 0x821>;
+		interrupts = <16 2 1 20>;
 	};
 };
-- 
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