From 43b3e1898206a1e385c9cb06f6040ea83a58b638 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 4 Apr 2011 09:32:46 +0100 Subject: ARM: 6860/1: OMAP4: Move the privately used SMP boot functions to OMAP specific header. Header files in arch/arm/*/include/mach included from arch/arm/include/asm/*.h are there to provide necessary definitions for either the rest of the kernel or the ARM specific parts. They shouldn't be polluted with *any* platform private stuff which is not absolutely necessary to satisfy the rest of the kernel. Hence move the OMAP specific SMP boot functions to different header instead of keeping them in 'plat/smp.h' which gets included indirectly by linux/smp.h The patch is outcome of the discussion in below thread: http://www.spinics.net/lists/arm-kernel/msg120363.html Cc: Tony Lindgren Signed-off-by: Santosh Shilimkar Signed-off-by: Russell King diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index de441c0..e4bd87619 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -33,4 +33,11 @@ extern void __iomem *gic_dist_base_addr; extern void __init gic_init_irq(void); extern void omap_smc1(u32 fn, u32 arg); +#ifdef CONFIG_SMP +/* Needed for secondary core boot */ +extern void omap_secondary_startup(void); +extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); +extern void omap_auxcoreboot_addr(u32 cpu_addr); +extern u32 omap_read_auxcoreboot0(void); +#endif #endif diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h index 7a10257..416e9d5 100644 --- a/arch/arm/plat-omap/include/plat/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h @@ -19,12 +19,6 @@ #include -/* Needed for secondary core boot */ -extern void omap_secondary_startup(void); -extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); -extern void omap_auxcoreboot_addr(u32 cpu_addr); -extern u32 omap_read_auxcoreboot0(void); - /* * We use Soft IRQ1 as the IPI */ -- cgit v0.10.2 From a35d4e58737116fd4126c240a1faeb735839435e Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 7 Apr 2011 19:50:10 +0100 Subject: ARM: 6871/1: Use asm-generic/sizes.h Commit d232b12 (asm-generic headers: add sizes.h, 2011-01-15) introduced a generic sizes.h. Use that instead of the ARM specific version. Cc: Arnd Bergmann Signed-off-by: Stephen Boyd Signed-off-by: Russell King diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h index 316bb2b..154b89b 100644 --- a/arch/arm/include/asm/sizes.h +++ b/arch/arm/include/asm/sizes.h @@ -16,44 +16,6 @@ /* Size definitions * Copyright (C) ARM Limited 1998. All rights reserved. */ +#include -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_16 0x00000010 -#define SZ_32 0x00000020 -#define SZ_64 0x00000040 -#define SZ_128 0x00000080 -#define SZ_256 0x00000100 -#define SZ_512 0x00000200 - -#define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_48M 0x03000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ +#define SZ_48M (SZ_32M + SZ_16M) -- cgit v0.10.2 From 16dc062b42459e6ddd244c2bc8255cac45db47e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 27 Apr 2011 09:45:33 +0100 Subject: ARM: 6888/1: remove ns9xxx port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The port is actually unmaintained and only received global cleanups and a few build fixes since mid 2008. Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 377a7a5..0c23b52 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -554,18 +554,6 @@ config ARCH_KS8695 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. -config ARCH_NS9XXX - bool "NetSilicon NS9xxx" - select CPU_ARM926T - select GENERIC_GPIO - select GENERIC_CLOCKEVENTS - select HAVE_CLK - help - Say Y here if you intend to run this kernel on a NetSilicon NS9xxx - System. - - - config ARCH_W90X900 bool "Nuvoton W90X900 CPU" select CPU_ARM926T @@ -951,8 +939,6 @@ source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" source "arch/arm/plat-nomadik/Kconfig" -source "arch/arm/mach-ns9xxx/Kconfig" - source "arch/arm/mach-nuc93x/Kconfig" source "arch/arm/plat-omap/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c7d321a..d88a69b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -164,7 +164,6 @@ machine-$(CONFIG_ARCH_MXC91231) := mxc91231 machine-$(CONFIG_ARCH_MXS) := mxs machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik -machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx machine-$(CONFIG_ARCH_OMAP1) := omap1 machine-$(CONFIG_ARCH_OMAP2) := omap2 machine-$(CONFIG_ARCH_OMAP3) := omap2 diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig deleted file mode 100644 index 1f528a0..0000000 --- a/arch/arm/configs/ns9xxx_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_NS9XXX=y -CONFIG_MACH_CC9P9360DEV=y -CONFIG_MACH_CC9P9360JS=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_FPE_NWFPE=y -CONFIG_NET=y -CONFIG_PACKET=m -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_SYN_COOKIES=y -CONFIG_MTD=m -CONFIG_MTD_CONCAT=m -CONFIG_MTD_CHAR=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_CFI=m -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_PHYSMAP=m -CONFIG_BLK_DEV_LOOP=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=m -CONFIG_I2C_GPIO=m -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m -CONFIG_LEDS_GPIO=m -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_RTC_CLASS=m -CONFIG_EXT2_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig deleted file mode 100644 index dd0cd5a..0000000 --- a/arch/arm/mach-ns9xxx/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -if ARCH_NS9XXX - -menu "NS9xxx Implementations" - -config NS9XXX_HAVE_SERIAL8250 - bool - -config PROCESSOR_NS9360 - bool - -config MODULE_CC9P9360 - bool - select PROCESSOR_NS9360 - -config BOARD_A9M9750DEV - select NS9XXX_HAVE_SERIAL8250 - bool - -config BOARD_JSCC9P9360 - bool - -config MACH_CC9P9360DEV - bool "ConnectCore 9P 9360 on an A9M9750 Devboard" - select MODULE_CC9P9360 - select BOARD_A9M9750DEV - help - Say Y here if you are using the Digi ConnectCore 9P 9360 - on an A9M9750 Development Board. - -config MACH_CC9P9360JS - bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard" - select MODULE_CC9P9360 - select BOARD_JSCC9P9360 - help - Say Y here if you are using the Digi ConnectCore 9P 9360 - on an JSCC9P9360 Development Board. - -endmenu - -endif diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile deleted file mode 100644 index 41efaf9..0000000 --- a/arch/arm/mach-ns9xxx/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -obj-y := clock.o generic.o gpio.o irq.o - -obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o -obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o - -obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o - -obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o -obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o - -# platform devices -obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot deleted file mode 100644 index 5465491..0000000 --- a/arch/arm/mach-ns9xxx/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ -zreladdr-y := 0x8000 -params_phys-y := 0x100 diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c deleted file mode 100644 index e27687d..0000000 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-a9m9750dev.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "board-a9m9750dev.h" - -static struct map_desc board_a9m9750dev_io_desc[] __initdata = { - { /* FPGA on CS0 */ - .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)), - .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)), - .length = NS9XXX_CS0STAT_LENGTH, - .type = MT_DEVICE, - }, -}; - -void __init board_a9m9750dev_map_io(void) -{ - iotable_init(board_a9m9750dev_io_desc, - ARRAY_SIZE(board_a9m9750dev_io_desc)); -} - -static void a9m9750dev_fpga_ack_irq(struct irq_data *d) -{ - /* nothing */ -} - -static void a9m9750dev_fpga_mask_irq(struct irq_data *d) -{ - u8 ier; - - ier = __raw_readb(FPGA_IER); - - ier &= ~(1 << (d->irq - FPGA_IRQ(0))); - - __raw_writeb(ier, FPGA_IER); -} - -static void a9m9750dev_fpga_maskack_irq(struct irq_data *d) -{ - a9m9750dev_fpga_mask_irq(d); - a9m9750dev_fpga_ack_irq(d); -} - -static void a9m9750dev_fpga_unmask_irq(struct irq_data *d) -{ - u8 ier; - - ier = __raw_readb(FPGA_IER); - - ier |= 1 << (d->irq - FPGA_IRQ(0)); - - __raw_writeb(ier, FPGA_IER); -} - -static struct irq_chip a9m9750dev_fpga_chip = { - .irq_ack = a9m9750dev_fpga_ack_irq, - .irq_mask = a9m9750dev_fpga_mask_irq, - .irq_mask_ack = a9m9750dev_fpga_maskack_irq, - .irq_unmask = a9m9750dev_fpga_unmask_irq, -}; - -static void a9m9750dev_fpga_demux_handler(unsigned int irq, - struct irq_desc *desc) -{ - u8 stat = __raw_readb(FPGA_ISR); - - desc->irq_data.chip->irq_mask_ack(&desc->irq_data); - - while (stat != 0) { - int irqno = fls(stat) - 1; - - stat &= ~(1 << irqno); - - generic_handle_irq(FPGA_IRQ(irqno)); - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -void __init board_a9m9750dev_init_irq(void) -{ - u32 eic; - int i; - - if (gpio_request(11, "board a9m9750dev extirq2") == 0) - ns9360_gpio_configure(11, 0, 1); - else - printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n", - __func__); - - for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { - irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip, - handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - - /* IRQ_NS9XXX_EXT2: level sensitive + active low */ - eic = __raw_readl(SYS_EIC(2)); - REGSET(eic, SYS_EIC, PLTY, AL); - REGSET(eic, SYS_EIC, LVEDG, LEVEL); - __raw_writel(eic, SYS_EIC(2)); - - irq_set_chained_handler(IRQ_NS9XXX_EXT2, - a9m9750dev_fpga_demux_handler); -} - -void __init board_a9m9750dev_init_machine(void) -{ - u32 reg; - - /* setup static CS0: memory base ... */ - reg = __raw_readl(SYS_SMCSSMB(0)); - REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12); - __raw_writel(reg, SYS_SMCSSMB(0)); - - /* ... and mask */ - reg = __raw_readl(SYS_SMCSSMM(0)); - REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff); - REGSET(reg, SYS_SMCSSMM, CSEx, EN); - __raw_writel(reg, SYS_SMCSSMM(0)); - - /* setup static CS0: memory configuration */ - reg = __raw_readl(MEM_SMC(0)); - REGSET(reg, MEM_SMC, PSMC, OFF); - REGSET(reg, MEM_SMC, BSMC, OFF); - REGSET(reg, MEM_SMC, EW, OFF); - REGSET(reg, MEM_SMC, PB, 1); - REGSET(reg, MEM_SMC, PC, AL); - REGSET(reg, MEM_SMC, PM, DIS); - REGSET(reg, MEM_SMC, MW, 8); - __raw_writel(reg, MEM_SMC(0)); - - /* setup static CS0: timing */ - __raw_writel(0x2, MEM_SMWED(0)); - __raw_writel(0x2, MEM_SMOED(0)); - __raw_writel(0x6, MEM_SMRD(0)); - __raw_writel(0x6, MEM_SMWD(0)); -} diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.h b/arch/arm/mach-ns9xxx/board-a9m9750dev.h deleted file mode 100644 index edc75ab..0000000 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-a9m9750dev.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include - -void __init board_a9m9750dev_map_io(void); -void __init board_a9m9750dev_init_machine(void); -void __init board_a9m9750dev_init_irq(void); diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.c b/arch/arm/mach-ns9xxx/board-jscc9p9360.c deleted file mode 100644 index 4bd3eec..0000000 --- a/arch/arm/mach-ns9xxx/board-jscc9p9360.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-jscc9p9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include "board-jscc9p9360.h" - -void __init board_jscc9p9360_init_machine(void) -{ - /* TODO: reserve GPIOs for push buttons, etc pp */ -} - diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.h b/arch/arm/mach-ns9xxx/board-jscc9p9360.h deleted file mode 100644 index 1a81a07..0000000 --- a/arch/arm/mach-ns9xxx/board-jscc9p9360.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-jscc9p9360.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include - -void __init board_jscc9p9360_init_machine(void); diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c deleted file mode 100644 index cf81cbc..0000000 --- a/arch/arm/mach-ns9xxx/clock.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/clock.c - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include - -#include "clock.h" - -static LIST_HEAD(clocks); -static DEFINE_SPINLOCK(clk_lock); - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *ret = NULL, *retgen = NULL; - unsigned long flags; - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - spin_lock_irqsave(&clk_lock, flags); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0) { - if (p->id == idno) { - if (!try_module_get(p->owner)) - continue; - ret = p; - break; - } else if (p->id == -1) - /* remember match with id == -1 in case there is - * no clock for idno */ - retgen = p; - } - } - - if (!ret && retgen && try_module_get(retgen->owner)) - ret = retgen; - - if (ret) - ++ret->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret ? ret : ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); - --clk->refcount; -} -EXPORT_SYMBOL(clk_put); - -static int clk_enable_unlocked(struct clk *clk) -{ - int ret = 0; - if (clk->parent) { - ret = clk_enable_unlocked(clk->parent); - if (ret) - return ret; - } - - if (clk->usage++ == 0 && clk->endisable) - ret = clk->endisable(clk, 1); - - return ret; -} - -int clk_enable(struct clk *clk) -{ - int ret; - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - ret = clk_enable_unlocked(clk); - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -static void clk_disable_unlocked(struct clk *clk) -{ - if (--clk->usage == 0 && clk->endisable) - clk->endisable(clk, 0); - - if (clk->parent) - clk_disable_unlocked(clk->parent); -} - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - clk_disable_unlocked(clk); - - spin_unlock_irqrestore(&clk_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (clk->get_rate) - return clk->get_rate(clk); - - if (clk->rate) - return clk->rate; - - if (clk->parent) - return clk_get_rate(clk->parent); - - return 0; -} -EXPORT_SYMBOL(clk_get_rate); - -int clk_register(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - list_add(&clk->node, &clocks); - - if (clk->parent) - ++clk->parent->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} - -int clk_unregister(struct clk *clk) -{ - int ret = 0; - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - if (clk->usage || clk->refcount) - ret = -EBUSY; - else - list_del(&clk->node); - - if (clk->parent) - --clk->parent->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret; -} - -#if defined CONFIG_DEBUG_FS - -#include -#include - -static int clk_debugfs_show(struct seq_file *s, void *null) -{ - unsigned long flags; - struct clk *p; - - spin_lock_irqsave(&clk_lock, flags); - - list_for_each_entry(p, &clocks, node) - seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n", - p->name, p->id, p->usage, p->refcount, - p->usage ? clk_get_rate(p) : 0); - - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} - -static int clk_debugfs_open(struct inode *inode, struct file *file) -{ - return single_open(file, clk_debugfs_show, NULL); -} - -static const struct file_operations clk_debugfs_operations = { - .open = clk_debugfs_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init clk_debugfs_init(void) -{ - struct dentry *dentry; - - dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL, - &clk_debugfs_operations); - return IS_ERR(dentry) ? PTR_ERR(dentry) : 0; -} -subsys_initcall(clk_debugfs_init); - -#endif /* if defined CONFIG_DEBUG_FS */ diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h deleted file mode 100644 index b86c30d..0000000 --- a/arch/arm/mach-ns9xxx/clock.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/clock.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __NS9XXX_CLOCK_H -#define __NS9XXX_CLOCK_H - -#include - -struct clk { - struct module *owner; - const char *name; - int id; - - struct clk *parent; - - unsigned long rate; - int (*endisable)(struct clk *, int enable); - unsigned long (*get_rate)(struct clk *); - - struct list_head node; - unsigned long refcount; - unsigned long usage; -}; - -int clk_register(struct clk *clk); -int clk_unregister(struct clk *clk); - -#endif /* ifndef __NS9XXX_CLOCK_H */ diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c deleted file mode 100644 index 1e0f467..0000000 --- a/arch/arm/mach-ns9xxx/generic.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/generic.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include -#include - -#include "generic.h" - -void __init ns9xxx_init_machine(void) -{ -} diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h deleted file mode 100644 index 8249319..0000000 --- a/arch/arm/mach-ns9xxx/generic.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/generic.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include -#include - -void __init ns9xxx_init_irq(void); -void __init ns9xxx_init_machine(void); diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c deleted file mode 100644 index 377330c..0000000 --- a/arch/arm/mach-ns9xxx/gpio-ns9360.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio-ns9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include - -#include "gpio-ns9360.h" - -static inline int ns9360_valid_gpio(unsigned gpio) -{ - return gpio <= 72; -} - -static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio) -{ - if (gpio < 56) - return BBU_GCONFb1(gpio / 8); - else - /* - * this could be optimised away on - * ns9750 only builds, but it isn't ... - */ - return BBU_GCONFb2((gpio - 56) / 8); -} - -static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio) -{ - if (gpio < 32) - return BBU_GCTRL1; - else if (gpio < 64) - return BBU_GCTRL2; - else - /* this could be optimised away on ns9750 only builds */ - return BBU_GCTRL3; -} - -static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio) -{ - if (gpio < 32) - return BBU_GSTAT1; - else if (gpio < 64) - return BBU_GSTAT2; - else - /* this could be optimised away on ns9750 only builds */ - return BBU_GSTAT3; -} - -/* - * each gpio can serve for 4 different purposes [0..3]. These are called - * "functions" and passed in the parameter func. Functions 0-2 are always some - * special things, function 3 is GPIO. If func == 3 dir specifies input or - * output, and with inv you can enable an inverter (independent of func). - */ -int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func) -{ - void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio); - u32 confval; - - confval = __raw_readl(conf); - REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); - REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); - REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); - __raw_writel(confval, conf); - - return 0; -} - -int ns9360_gpio_configure(unsigned gpio, int inv, int func) -{ - if (likely(ns9360_valid_gpio(gpio))) { - if (func == 3) { - printk(KERN_WARNING "use gpio_direction_input " - "or gpio_direction_output\n"); - return -EINVAL; - } else - return __ns9360_gpio_configure(gpio, 0, inv, func); - } else - return -EINVAL; -} -EXPORT_SYMBOL(ns9360_gpio_configure); - -int ns9360_gpio_get_value(unsigned gpio) -{ - void __iomem *stat = ns9360_gpio_get_gstataddr(gpio); - int ret; - - ret = 1 & (__raw_readl(stat) >> (gpio & 31)); - - return ret; -} - -void ns9360_gpio_set_value(unsigned gpio, int value) -{ - void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio); - u32 ctrlval; - - ctrlval = __raw_readl(ctrl); - - if (value) - ctrlval |= 1 << (gpio & 31); - else - ctrlval &= ~(1 << (gpio & 31)); - - __raw_writel(ctrlval, ctrl); -} diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h deleted file mode 100644 index 131cd17..0000000 --- a/arch/arm/mach-ns9xxx/gpio-ns9360.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio-ns9360.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func); -int ns9360_gpio_get_value(unsigned gpio); -void ns9360_gpio_set_value(unsigned gpio, int value); diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c deleted file mode 100644 index 5503ca0..0000000 --- a/arch/arm/mach-ns9xxx/gpio.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "gpio-ns9360.h" - -#if defined(CONFIG_PROCESSOR_NS9360) -#define GPIO_MAX 72 -#elif defined(CONFIG_PROCESSOR_NS9750) -#define GPIO_MAX 49 -#endif - -/* protects BBU_GCONFx and BBU_GCTRLx */ -static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock); - -/* only access gpiores with atomic ops */ -static DECLARE_BITMAP(gpiores, GPIO_MAX + 1); - -static inline int ns9xxx_valid_gpio(unsigned gpio) -{ -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - return gpio <= 72; - else -#endif -#if defined(CONFIG_PROCESSOR_NS9750) - if (processor_is_ns9750()) - return gpio <= 49; - else -#endif - { - BUG(); - return 0; - } -} - -int gpio_request(unsigned gpio, const char *label) -{ - if (likely(ns9xxx_valid_gpio(gpio))) - return test_and_set_bit(gpio, gpiores) ? -EBUSY : 0; - else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_request); - -void gpio_free(unsigned gpio) -{ - might_sleep(); - clear_bit(gpio, gpiores); - return; -} -EXPORT_SYMBOL(gpio_free); - -int gpio_direction_input(unsigned gpio) -{ - if (likely(ns9xxx_valid_gpio(gpio))) { - int ret = -EINVAL; - unsigned long flags; - - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ret = __ns9360_gpio_configure(gpio, 0, 0, 3); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); - - return ret; - - } else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_direction_input); - -int gpio_direction_output(unsigned gpio, int value) -{ - if (likely(ns9xxx_valid_gpio(gpio))) { - int ret = -EINVAL; - unsigned long flags; - - gpio_set_value(gpio, value); - - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ret = __ns9360_gpio_configure(gpio, 1, 0, 3); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); - - return ret; - } else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_direction_output); - -int gpio_get_value(unsigned gpio) -{ -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - return ns9360_gpio_get_value(gpio); - else -#endif - { - BUG(); - return -EINVAL; - } -} -EXPORT_SYMBOL(gpio_get_value); - -void gpio_set_value(unsigned gpio, int value) -{ - unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ns9360_gpio_set_value(gpio, value); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); -} -EXPORT_SYMBOL(gpio_set_value); diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h deleted file mode 100644 index 19ca6de..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/board.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/board.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -#include - -#define board_is_a9m9750dev() (0 \ - || machine_is_cc9p9750dev() \ - ) - -#define board_is_a9mvali() (0 \ - || machine_is_cc9p9750val() \ - ) - -#define board_is_jscc9p9210() (0 \ - || machine_is_cc9p9210js() \ - ) - -#define board_is_jscc9p9215() (0 \ - || machine_is_cc9p9215js() \ - ) - -#define board_is_jscc9p9360() (0 \ - || machine_is_cc9p9360js() \ - ) - -#define board_is_uncbas() (0 \ - || machine_is_cc7ucamry() \ - ) - -#endif /* ifndef __ASM_ARCH_BOARD_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S deleted file mode 100644 index 5a2acbd..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/debug-macro.S - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include - -#include - - .macro addruart, rp, rv - ldr \rp, =NS9XXX_CSxSTAT_PHYS(0) - ldr \rv, =io_p2v(NS9XXX_CSxSTAT_PHYS(0)) - .endm - -#define UART_SHIFT 2 -#include diff --git a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S deleted file mode 100644 index 71ca031..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/entry-macro.S - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include - - .macro get_irqnr_preamble, base, tmp - ldr \base, =SYS_ISRADDR - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)] - cmp \irqstat, #0 - ldrne \irqnr, [\base] - .endm - - .macro disable_fiq - .endm diff --git a/arch/arm/mach-ns9xxx/include/mach/gpio.h b/arch/arm/mach-ns9xxx/include/mach/gpio.h deleted file mode 100644 index 5eb3490..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/gpio.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/gpio.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. -*/ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#include - -int gpio_request(unsigned gpio, const char *label); - -void gpio_free(unsigned gpio); - -int ns9xxx_gpio_configure(unsigned gpio, int inv, int func); - -int gpio_direction_input(unsigned gpio); - -int gpio_direction_output(unsigned gpio, int value); - -int gpio_get_value(unsigned gpio); - -void gpio_set_value(unsigned gpio, int value); - -/* - * ns9xxx can use gpio pins to trigger an irq, but it's not generic - * enough to be supported by the gpio_to_irq/irq_to_gpio interface - */ -static inline int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -/* get the cansleep() stubs */ -#include - -#endif /* ifndef __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h deleted file mode 100644 index 7663112..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/hardware.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/hardware.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * NetSilicon NS9xxx internal mapping: - * - * physical <--> virtual - * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff - * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff - */ -#define io_p2v(x) (0xf0000000 \ - + (((x) & 0xf0000000) >> 4) \ - + ((x) & 0x00ffffff)) - -#define io_v2p(x) ((((x) & 0x0f000000) << 4) \ - + ((x) & 0x00ffffff)) - -#define __REGSHIFT(mask) ((mask) & (-(mask))) - -#define __REGBIT(bit) ((u32)1 << (bit)) -#define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit)) -#define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask)) - -#ifndef __ASSEMBLY__ - -# define __REG(x) ((void __iomem __force *)io_p2v((x))) -# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y))) - -# define __REGSET(var, field, value) \ - ((var) = (((var) & ~((field) & ~(value))) | (value))) - -# define REGSET(var, reg, field, value) \ - __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value) - -# define REGSET_IDX(var, reg, field, idx, value) \ - __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx))) - -# define REGSETIM(var, reg, field, value) \ - __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value))) - -# define REGSETIM_IDX(var, reg, field, idx, value) \ - __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value))) - -# define __REGGET(var, field) \ - (((var) & (field))) - -# define REGGET(var, reg, field) \ - __REGGET(var, reg ## _ ## field) - -# define REGGET_IDX(var, reg, field, idx) \ - __REGGET(var, reg ## _ ## field((idx))) - -# define REGGETIM(var, reg, field) \ - __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) - -# define REGGETIM_IDX(var, reg, field, idx) \ - __REGGET(var, reg ## _ ## field((idx))) / \ - __REGSHIFT(reg ## _ ## field((idx))) - -#else - -# define __REG(x) io_p2v(x) -# define __REG2(x, y) io_p2v((x) + 4 * (y)) - -#endif - -#endif /* ifndef __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h deleted file mode 100644 index f08451d..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/io.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/io.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff /* XXX */ - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) -#define __mem_isa(a) (IO_BASE + (a)) - -#endif /* ifndef __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/irqs.h b/arch/arm/mach-ns9xxx/include/mach/irqs.h deleted file mode 100644 index 1348394..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/irqs.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/irqs.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* NetSilicon 9360 */ -#define IRQ_NS9XXX_WATCHDOG 0 -#define IRQ_NS9XXX_AHBBUSERR 1 -#define IRQ_NS9360_BBUSAGG 2 -/* irq 3 is reserved for NS9360 */ -#define IRQ_NS9XXX_ETHRX 4 -#define IRQ_NS9XXX_ETHTX 5 -#define IRQ_NS9XXX_ETHPHY 6 -#define IRQ_NS9360_LCD 7 -#define IRQ_NS9360_SERBRX 8 -#define IRQ_NS9360_SERBTX 9 -#define IRQ_NS9360_SERARX 10 -#define IRQ_NS9360_SERATX 11 -#define IRQ_NS9360_SERCRX 12 -#define IRQ_NS9360_SERCTX 13 -#define IRQ_NS9360_I2C 14 -#define IRQ_NS9360_BBUSDMA 15 -#define IRQ_NS9360_TIMER0 16 -#define IRQ_NS9360_TIMER1 17 -#define IRQ_NS9360_TIMER2 18 -#define IRQ_NS9360_TIMER3 19 -#define IRQ_NS9360_TIMER4 20 -#define IRQ_NS9360_TIMER5 21 -#define IRQ_NS9360_TIMER6 22 -#define IRQ_NS9360_TIMER7 23 -#define IRQ_NS9360_RTC 24 -#define IRQ_NS9360_USBHOST 25 -#define IRQ_NS9360_USBDEVICE 26 -#define IRQ_NS9360_IEEE1284 27 -#define IRQ_NS9XXX_EXT0 28 -#define IRQ_NS9XXX_EXT1 29 -#define IRQ_NS9XXX_EXT2 30 -#define IRQ_NS9XXX_EXT3 31 - -#define BBUS_IRQ(irq) (32 + irq) - -#define IRQ_BBUS_DMA BBUS_IRQ(0) -#define IRQ_BBUS_SERBRX BBUS_IRQ(2) -#define IRQ_BBUS_SERBTX BBUS_IRQ(3) -#define IRQ_BBUS_SERARX BBUS_IRQ(4) -#define IRQ_BBUS_SERATX BBUS_IRQ(5) -#define IRQ_BBUS_SERCRX BBUS_IRQ(6) -#define IRQ_BBUS_SERCTX BBUS_IRQ(7) -#define IRQ_BBUS_SERDRX BBUS_IRQ(8) -#define IRQ_BBUS_SERDTX BBUS_IRQ(9) -#define IRQ_BBUS_I2C BBUS_IRQ(10) -#define IRQ_BBUS_1284 BBUS_IRQ(11) -#define IRQ_BBUS_UTIL BBUS_IRQ(12) -#define IRQ_BBUS_RTC BBUS_IRQ(13) -#define IRQ_BBUS_USBHST BBUS_IRQ(14) -#define IRQ_BBUS_USBDEV BBUS_IRQ(15) -#define IRQ_BBUS_AHBDMA1 BBUS_IRQ(24) -#define IRQ_BBUS_AHBDMA2 BBUS_IRQ(25) - -/* - * these Interrupts are specific for the a9m9750dev board. - * They are generated by an FPGA that interrupts the CPU on - * IRQ_NS9360_EXT2 - */ -#define FPGA_IRQ(irq) (64 + irq) - -#define IRQ_FPGA_UARTA FPGA_IRQ(0) -#define IRQ_FPGA_UARTB FPGA_IRQ(1) -#define IRQ_FPGA_UARTC FPGA_IRQ(2) -#define IRQ_FPGA_UARTD FPGA_IRQ(3) -#define IRQ_FPGA_TOUCH FPGA_IRQ(4) -#define IRQ_FPGA_CF FPGA_IRQ(5) -#define IRQ_FPGA_CAN0 FPGA_IRQ(6) -#define IRQ_FPGA_CAN1 FPGA_IRQ(7) - -#define NR_IRQS 72 - -#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h deleted file mode 100644 index 5c65aee..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/memory.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/memory.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. -*/ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* x in [0..3] */ -#define NS9XXX_CSxSTAT_PHYS(x) UL(((x) + 4) << 28) - -#define NS9XXX_CS0STAT_LENGTH UL(0x1000) -#define NS9XXX_CS1STAT_LENGTH UL(0x1000) -#define NS9XXX_CS2STAT_LENGTH UL(0x1000) -#define NS9XXX_CS3STAT_LENGTH UL(0x1000) - -#define PLAT_PHYS_OFFSET UL(0x00000000) - -#endif diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h deleted file mode 100644 index 628e975..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/module.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/module.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_MODULE_H -#define __ASM_ARCH_MODULE_H - -#include - -#define module_is_cc7ucamry() (0 \ - || machine_is_cc7ucamry() \ - ) - -#define module_is_cc9c() (0 \ - ) - -#define module_is_cc9p9210() (0 \ - || machine_is_cc9p9210() \ - || machine_is_cc9p9210js() \ - ) - -#define module_is_cc9p9215() (0 \ - || machine_is_cc9p9215() \ - || machine_is_cc9p9215js() \ - ) - -#define module_is_cc9p9360() (0 \ - || machine_is_cc9p9360dev() \ - || machine_is_cc9p9360js() \ - ) - -#define module_is_cc9p9750() (0 \ - || machine_is_a9m9750() \ - || machine_is_cc9p9750js() \ - || machine_is_cc9p9750val() \ - ) - -#define module_is_ccw9c() (0 \ - ) - -#define module_is_inc20otter() (0 \ - || machine_is_inc20otter() \ - ) - -#define module_is_otter() (0 \ - || machine_is_otter() \ - ) - -#endif /* ifndef __ASM_ARCH_MODULE_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h deleted file mode 100644 index f41deda..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_PROCESSORNS9360_H -#define __ASM_ARCH_PROCESSORNS9360_H - -#include - -void ns9360_reset(char mode); - -unsigned long ns9360_systemclock(void) __attribute__((const)); - -static inline unsigned long ns9360_cpuclock(void) __attribute__((const)); -static inline unsigned long ns9360_cpuclock(void) -{ - return ns9360_systemclock() / 2; -} - -void __init ns9360_map_io(void); - -extern struct sys_timer ns9360_timer; - -int ns9360_gpio_configure(unsigned gpio, int inv, int func); - -#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/processor.h b/arch/arm/mach-ns9xxx/include/mach/processor.h deleted file mode 100644 index 9f77f74..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/processor.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/processor.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_PROCESSOR_H -#define __ASM_ARCH_PROCESSOR_H - -#include - -#define processor_is_ns9210() (0 \ - || module_is_cc7ucamry() \ - || module_is_cc9p9210() \ - || module_is_inc20otter() \ - || module_is_otter() \ - ) - -#define processor_is_ns9215() (0 \ - || module_is_cc9p9215() \ - ) - -#define processor_is_ns9360() (0 \ - || module_is_cc9p9360() \ - || module_is_cc9c() \ - || module_is_ccw9c() \ - ) - -#define processor_is_ns9750() (0 \ - || module_is_cc9p9750() \ - ) - -#define processor_is_ns921x() (0 \ - || processor_is_ns9210() \ - || processor_is_ns9215() \ - ) - -#endif /* ifndef __ASM_ARCH_PROCESSOR_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h deleted file mode 100644 index af227c0..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-bbu.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSBBU_H -#define __ASM_ARCH_REGSBBU_H - -#include - -/* BBus Utility */ - -/* GPIO Configuration Registers block 1 */ -/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is - * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register - * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */ -#define BBU_GCONFb1(x) __REG2(0x90600010, (x)) -#define BBU_GCONFb2(x) __REG2(0x90600100, (x)) - -#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2)) -#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0) -#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1) -#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2)) -#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0) -#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1) -#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2) -#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0) -#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1) -#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2) -#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3) - -#define BBU_GCTRL1 __REG(0x90600030) -#define BBU_GCTRL2 __REG(0x90600034) -#define BBU_GCTRL3 __REG(0x90600120) - -#define BBU_GSTAT1 __REG(0x90600040) -#define BBU_GSTAT2 __REG(0x90600044) -#define BBU_GSTAT3 __REG(0x90600130) - -#endif /* ifndef __ASM_ARCH_REGSBBU_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h deleted file mode 100644 index cd15936..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSBOARDA9M9750_H -#define __ASM_ARCH_REGSBOARDA9M9750_H - -#include - -#define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0)) -#define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08) -#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10) -#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18) - -#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50) -#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60) - -#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h deleted file mode 100644 index f1625bf..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-mem.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSMEM_H -#define __ASM_ARCH_REGSMEM_H - -#include - -/* Memory Module */ - -/* Control register */ -#define MEM_CTRL __REG(0xa0700000) - -/* Status register */ -#define MEM_STAT __REG(0xa0700004) - -/* Configuration register */ -#define MEM_CONF __REG(0xa0700008) - -/* Dynamic Memory Control register */ -#define MEM_DMCTRL __REG(0xa0700020) - -/* Dynamic Memory Refresh Timer */ -#define MEM_DMRT __REG(0xa0700024) - -/* Dynamic Memory Read Configuration register */ -#define MEM_DMRC __REG(0xa0700028) - -/* Dynamic Memory Precharge Command Period (tRP) */ -#define MEM_DMPCP __REG(0xa0700030) - -/* Dynamic Memory Active to Precharge Command Period (tRAS) */ -#define MEM_DMAPCP __REG(0xa0700034) - -/* Dynamic Memory Self-Refresh Exit Time (tSREX) */ -#define MEM_DMSRET __REG(0xa0700038) - -/* Dynamic Memory Last Data Out to Active Time (tAPR) */ -#define MEM_DMLDOAT __REG(0xa070003c) - -/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */ -#define MEM_DMDIACT __REG(0xa0700040) - -/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */ -#define MEM_DMWRT __REG(0xa0700044) - -/* Dynamic Memory Active to Active Command Period (tRC) */ -#define MEM_DMAACP __REG(0xa0700048) - -/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */ -#define MEM_DMARP __REG(0xa070004c) - -/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */ -#define MEM_DMESRAC __REG(0xa0700050) - -/* Dynamic Memory Active Bank A to Active B Time (tRRD) */ -#define MEM_DMABAABT __REG(0xa0700054) - -/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */ -#define MEM_DMLMACT __REG(0xa0700058) - -/* Static Memory Extended Wait */ -#define MEM_SMEW __REG(0xa0700080) - -/* Dynamic Memory Configuration Register x */ -#define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3) - -/* Dynamic Memory RAS and CAS Delay x */ -#define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3) - -/* Static Memory Configuration Register x */ -#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3) - -/* Static Memory Configuration Register x: Write protect */ -#define MEM_SMC_PSMC __REGBIT(20) -#define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0) -#define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1) - -/* Static Memory Configuration Register x: Buffer enable */ -#define MEM_SMC_BSMC __REGBIT(19) -#define MEM_SMC_BSMC_OFF __REGVAL(MEM_SMC_BSMC, 0) -#define MEM_SMC_BSMC_ON __REGVAL(MEM_SMC_BSMC, 1) - -/* Static Memory Configuration Register x: Extended Wait */ -#define MEM_SMC_EW __REGBIT(8) -#define MEM_SMC_EW_OFF __REGVAL(MEM_SMC_EW, 0) -#define MEM_SMC_EW_ON __REGVAL(MEM_SMC_EW, 1) - -/* Static Memory Configuration Register x: Byte lane state */ -#define MEM_SMC_PB __REGBIT(7) -#define MEM_SMC_PB_0 __REGVAL(MEM_SMC_PB, 0) -#define MEM_SMC_PB_1 __REGVAL(MEM_SMC_PB, 1) - -/* Static Memory Configuration Register x: Chip select polarity */ -#define MEM_SMC_PC __REGBIT(6) -#define MEM_SMC_PC_AL __REGVAL(MEM_SMC_PC, 0) -#define MEM_SMC_PC_AH __REGVAL(MEM_SMC_PC, 1) - -/* static memory configuration register x: page mode*/ -#define MEM_SMC_PM __REGBIT(3) -#define MEM_SMC_PM_DIS __REGVAL(MEM_SMC_PM, 0) -#define MEM_SMC_PM_ASYNC __REGVAL(MEM_SMC_PM, 1) - -/* static memory configuration register x: Memory width */ -#define MEM_SMC_MW __REGBITS(1, 0) -#define MEM_SMC_MW_8 __REGVAL(MEM_SMC_MW, 0) -#define MEM_SMC_MW_16 __REGVAL(MEM_SMC_MW, 1) -#define MEM_SMC_MW_32 __REGVAL(MEM_SMC_MW, 2) - -/* Static Memory Write Enable Delay x */ -#define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3) - -/* Static Memory Output Enable Delay x */ -#define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3) - -/* Static Memory Read Delay x */ -#define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3) - -/* Static Memory Page Mode Read Delay 0 */ -#define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3) - -/* Static Memory Write Delay */ -#define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3) - -/* Static Memory Turn Round Delay x */ -#define MEM_SWT(x) __REG2(0xa0700218, (x) << 3) - -#endif /* ifndef __ASM_ARCH_REGSMEM_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h deleted file mode 100644 index 14f91df..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_REGSSYSCOMMON_H -#define __ASM_ARCH_REGSSYSCOMMON_H -#include - -/* Interrupt Vector Address Register Level x */ -#define SYS_IVA(x) __REG2(0xa09000c4, (x)) - -/* Interrupt Configuration registers */ -#define SYS_IC(x) __REG2(0xa0900144, (x)) - -/* ISRADDR */ -#define SYS_ISRADDR __REG(0xa0900164) - -/* Interrupt Status Active */ -#define SYS_ISA __REG(0xa0900168) - -/* Interrupt Status Raw */ -#define SYS_ISR __REG(0xa090016c) - -#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h deleted file mode 100644 index 8ff254d..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSSYSNS9360_H -#define __ASM_ARCH_REGSSYSNS9360_H - -#include - -/* System Control Module */ - -/* AHB Arbiter Gen Configuration */ -#define SYS_AHBAGENCONF __REG(0xa0900000) - -/* BRC */ -#define SYS_BRC(x) __REG2(0xa0900004, (x)) - -/* Timer x Reload Count register */ -#define SYS_TRC(x) __REG2(0xa0900044, (x)) - -/* Timer x Read register */ -#define SYS_TR(x) __REG2(0xa0900084, (x)) - -/* Timer Interrupt Status register */ -#define SYS_TIS __REG(0xa0900170) - -/* PLL Configuration register */ -#define SYS_PLL __REG(0xa0900188) - -/* PLL FS status */ -#define SYS_PLL_FS __REGBITS(24, 23) - -/* PLL ND status */ -#define SYS_PLL_ND __REGBITS(20, 16) - -/* PLL Configuration register: PLL SW change */ -#define SYS_PLL_SWC __REGBIT(15) -#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0) -#define SYS_PLL_SWC_YES __REGVAL(SYS_PLL_SWC, 1) - -/* Timer x Control register */ -#define SYS_TC(x) __REG2(0xa0900190, (x)) - -/* Timer x Control register: Timer enable */ -#define SYS_TCx_TEN __REGBIT(15) -#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0) -#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1) - -/* Timer x Control register: CPU debug mode */ -#define SYS_TCx_TDBG __REGBIT(10) -#define SYS_TCx_TDBG_CONT __REGVAL(SYS_TCx_TDBG, 0) -#define SYS_TCx_TDBG_STOP __REGVAL(SYS_TCx_TDBG, 1) - -/* Timer x Control register: Interrupt clear */ -#define SYS_TCx_INTC __REGBIT(9) -#define SYS_TCx_INTC_UNSET __REGVAL(SYS_TCx_INTC, 0) -#define SYS_TCx_INTC_SET __REGVAL(SYS_TCx_INTC, 1) - -/* Timer x Control register: Timer clock select */ -#define SYS_TCx_TLCS __REGBITS(8, 6) -#define SYS_TCx_TLCS_CPU __REGVAL(SYS_TCx_TLCS, 0) /* CPU clock */ -#define SYS_TCx_TLCS_DIV2 __REGVAL(SYS_TCx_TLCS, 1) /* CPU clock / 2 */ -#define SYS_TCx_TLCS_DIV4 __REGVAL(SYS_TCx_TLCS, 2) /* CPU clock / 4 */ -#define SYS_TCx_TLCS_DIV8 __REGVAL(SYS_TCx_TLCS, 3) /* CPU clock / 8 */ -#define SYS_TCx_TLCS_DIV16 __REGVAL(SYS_TCx_TLCS, 4) /* CPU clock / 16 */ -#define SYS_TCx_TLCS_DIV32 __REGVAL(SYS_TCx_TLCS, 5) /* CPU clock / 32 */ -#define SYS_TCx_TLCS_DIV64 __REGVAL(SYS_TCx_TLCS, 6) /* CPU clock / 64 */ -#define SYS_TCx_TLCS_EXT __REGVAL(SYS_TCx_TLCS, 7) - -/* Timer x Control register: Timer mode */ -#define SYS_TCx_TM __REGBITS(5, 4) -#define SYS_TCx_TM_IEE __REGVAL(SYS_TCx_TM, 0) /* Internal timer or external event */ -#define SYS_TCx_TM_ELL __REGVAL(SYS_TCx_TM, 1) /* External low-level, gated timer */ -#define SYS_TCx_TM_EHL __REGVAL(SYS_TCx_TM, 2) /* External high-level, gated timer */ -#define SYS_TCx_TM_CONCAT __REGVAL(SYS_TCx_TM, 3) /* Concatenate the lower timer. */ - -/* Timer x Control register: Interrupt select */ -#define SYS_TCx_INTS __REGBIT(3) -#define SYS_TCx_INTS_DIS __REGVAL(SYS_TCx_INTS, 0) -#define SYS_TCx_INTS_EN __REGVAL(SYS_TCx_INTS, 1) - -/* Timer x Control register: Up/down select */ -#define SYS_TCx_UDS __REGBIT(2) -#define SYS_TCx_UDS_UP __REGVAL(SYS_TCx_UDS, 0) -#define SYS_TCx_UDS_DOWN __REGVAL(SYS_TCx_UDS, 1) - -/* Timer x Control register: 32- or 16-bit timer */ -#define SYS_TCx_TSZ __REGBIT(1) -#define SYS_TCx_TSZ_16 __REGVAL(SYS_TCx_TSZ, 0) -#define SYS_TCx_TSZ_32 __REGVAL(SYS_TCx_TSZ, 1) - -/* Timer x Control register: Reload enable */ -#define SYS_TCx_REN __REGBIT(0) -#define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0) -#define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1) - -/* System Memory Chip Select x Dynamic Memory Base */ -#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1) - -/* System Memory Chip Select x Dynamic Memory Mask */ -#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1) - -/* System Memory Chip Select x Static Memory Base */ -#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1) - -/* System Memory Chip Select x Static Memory Base: Chip select x base */ -#define SYS_SMCSSMB_CSxB __REGBITS(31, 12) - -/* System Memory Chip Select x Static Memory Mask */ -#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1) - -/* System Memory Chip Select x Static Memory Mask: Chip select x mask */ -#define SYS_SMCSSMM_CSxM __REGBITS(31, 12) - -/* System Memory Chip Select x Static Memory Mask: Chip select x enable */ -#define SYS_SMCSSMM_CSEx __REGBIT(0) -#define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0) -#define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1) - -/* General purpose, user-defined ID register */ -#define SYS_GENID __REG(0xa0900210) - -/* External Interrupt x Control register */ -#define SYS_EIC(x) __REG2(0xa0900214, (x)) - -/* External Interrupt x Control register: Status */ -#define SYS_EIC_STS __REGBIT(3) - -/* External Interrupt x Control register: Clear */ -#define SYS_EIC_CLR __REGBIT(2) - -/* External Interrupt x Control register: Polarity */ -#define SYS_EIC_PLTY __REGBIT(1) -#define SYS_EIC_PLTY_AH __REGVAL(SYS_EIC_PLTY, 0) -#define SYS_EIC_PLTY_AL __REGVAL(SYS_EIC_PLTY, 1) - -/* External Interrupt x Control register: Level edge */ -#define SYS_EIC_LVEDG __REGBIT(0) -#define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0) -#define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1) - -#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h deleted file mode 100644 index 1561588..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/system.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/system.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include -#include -#include - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ -#ifdef CONFIG_PROCESSOR_NS9360 - if (processor_is_ns9360()) - ns9360_reset(mode); - else -#endif - BUG(); - - BUG(); -} - -#endif /* ifndef __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/timex.h b/arch/arm/mach-ns9xxx/include/mach/timex.h deleted file mode 100644 index 734a8d8..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/timex.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/timex.h - * - * Copyright (C) 2005-2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* - * value for CLOCK_TICK_RATE stolen from arch/arm/mach-s3c2410/include/mach/timex.h. - * See there for an explanation. - */ -#define CLOCK_TICK_RATE 12000000 - -#endif /* ifndef __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h deleted file mode 100644 index 770a68c..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/uncompress.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include - -#define __REG(x) ((void __iomem __force *)(x)) - -static void putc_dummy(char c, void __iomem *base) -{ - /* nothing */ -} - -static int timeout; - -static void putc_ns9360(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (__raw_readl(base + 8) & (1 << 3)) { - __raw_writeb(c, base + 16); - timeout = 0x10000; - break; - } - } while (timeout); -} - -static void putc_a9m9750dev(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (__raw_readb(base + 5) & (1 << 5)) { - __raw_writeb(c, base); - timeout = 0x10000; - break; - } - } while (timeout); - -} - -static void putc_ns921x(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (!(__raw_readl(base) & (1 << 11))) { - __raw_writeb(c, base + 0x0028); - timeout = 0x10000; - break; - } - } while (timeout); -} - -#define MSCS __REG(0xA0900184) - -#define NS9360_UARTA __REG(0x90200040) -#define NS9360_UARTB __REG(0x90200000) -#define NS9360_UARTC __REG(0x90300000) -#define NS9360_UARTD __REG(0x90300040) - -#define NS9360_UART_ENABLED(base) \ - (__raw_readl(NS9360_UARTA) & (1 << 31)) - -#define A9M9750DEV_UARTA __REG(0x40000000) - -#define NS921XSYS_CLOCK __REG(0xa090017c) -#define NS921X_UARTA __REG(0x90010000) -#define NS921X_UARTB __REG(0x90018000) -#define NS921X_UARTC __REG(0x90020000) -#define NS921X_UARTD __REG(0x90028000) - -#define NS921X_UART_ENABLED(base) \ - (__raw_readl((base) + 0x1000) & (1 << 29)) - -static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base) -{ - timeout = 0x10000; - if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) { - /* ns9360 or ns9750 */ - if (NS9360_UART_ENABLED(NS9360_UARTA)) { - *putc = putc_ns9360; - *base = NS9360_UARTA; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTB)) { - *putc = putc_ns9360; - *base = NS9360_UARTB; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTC)) { - *putc = putc_ns9360; - *base = NS9360_UARTC; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTD)) { - *putc = putc_ns9360; - *base = NS9360_UARTD; - return; - } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) { - *putc = putc_a9m9750dev; - *base = A9M9750DEV_UARTA; - return; - } - } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) { - /* ns921x */ - u32 clock = __raw_readl(NS921XSYS_CLOCK); - - if ((clock & (1 << 1)) && - NS921X_UART_ENABLED(NS921X_UARTA)) { - *putc = putc_ns921x; - *base = NS921X_UARTA; - return; - } else if ((clock & (1 << 2)) && - NS921X_UART_ENABLED(NS921X_UARTB)) { - *putc = putc_ns921x; - *base = NS921X_UARTB; - return; - } else if ((clock & (1 << 3)) && - NS921X_UART_ENABLED(NS921X_UARTC)) { - *putc = putc_ns921x; - *base = NS921X_UARTC; - return; - } else if ((clock & (1 << 4)) && - NS921X_UART_ENABLED(NS921X_UARTD)) { - *putc = putc_ns921x; - *base = NS921X_UARTD; - return; - } - } - - *putc = putc_dummy; -} - -void (*myputc)(char, void __iomem *); -void __iomem *base; - -static void putc(char c) -{ - myputc(c, base); -} - -static void arch_decomp_setup(void) -{ - autodetect(&myputc, &base); -} -#define arch_decomp_wdog() - -static void flush(void) -{ - /* nothing */ -} - -#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h deleted file mode 100644 index c865197..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/vmalloc.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END (0xf0000000UL) - -#endif /* ifndef __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c deleted file mode 100644 index 37ab0a2..0000000 --- a/arch/arm/mach-ns9xxx/irq.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/irq.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include - -#include "generic.h" - -/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */ -#define irq2prio(i) (i) -#define prio2irq(p) (p) - -static void ns9xxx_mask_irq(struct irq_data *d) -{ - /* XXX: better use cpp symbols */ - int prio = irq2prio(d->irq); - u32 ic = __raw_readl(SYS_IC(prio / 4)); - ic &= ~(1 << (7 + 8 * (3 - (prio & 3)))); - __raw_writel(ic, SYS_IC(prio / 4)); -} - -static void ns9xxx_eoi_irq(struct irq_data *d) -{ - __raw_writel(0, SYS_ISRADDR); -} - -static void ns9xxx_unmask_irq(struct irq_data *d) -{ - /* XXX: better use cpp symbols */ - int prio = irq2prio(d->irq); - u32 ic = __raw_readl(SYS_IC(prio / 4)); - ic |= 1 << (7 + 8 * (3 - (prio & 3))); - __raw_writel(ic, SYS_IC(prio / 4)); -} - -static struct irq_chip ns9xxx_chip = { - .irq_eoi = ns9xxx_eoi_irq, - .irq_mask = ns9xxx_mask_irq, - .irq_unmask = ns9xxx_unmask_irq, -}; - -void __init ns9xxx_init_irq(void) -{ - int i; - - /* disable all IRQs */ - for (i = 0; i < 8; ++i) - __raw_writel(prio2irq(4 * i) << 24 | - prio2irq(4 * i + 1) << 16 | - prio2irq(4 * i + 2) << 8 | - prio2irq(4 * i + 3), - SYS_IC(i)); - - for (i = 0; i < 32; ++i) - __raw_writel(prio2irq(i), SYS_IVA(i)); - - for (i = 0; i <= 31; ++i) { - irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq); - set_irq_flags(i, IRQF_VALID); - irq_set_status_flags(i, IRQ_LEVEL); - } -} diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c deleted file mode 100644 index 2858417..0000000 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include - -#include - -#include "board-a9m9750dev.h" -#include "generic.h" - -static void __init mach_cc9p9360dev_map_io(void) -{ - ns9360_map_io(); - board_a9m9750dev_map_io(); -} - -static void __init mach_cc9p9360dev_init_irq(void) -{ - ns9xxx_init_irq(); - board_a9m9750dev_init_irq(); -} - -static void __init mach_cc9p9360dev_init_machine(void) -{ - ns9xxx_init_machine(); - board_a9m9750dev_init_machine(); -} - -MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard") - .map_io = mach_cc9p9360dev_map_io, - .init_irq = mach_cc9p9360dev_init_irq, - .init_machine = mach_cc9p9360dev_init_machine, - .timer = &ns9360_timer, - .boot_params = 0x100, -MACHINE_END diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c deleted file mode 100644 index 729f68d..0000000 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/mach-cc9p9360js.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include - -#include - -#include "board-jscc9p9360.h" -#include "generic.h" - -static void __init mach_cc9p9360js_init_machine(void) -{ - ns9xxx_init_machine(); - board_jscc9p9360_init_machine(); -} - -MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") - .map_io = ns9360_map_io, - .init_irq = ns9xxx_init_irq, - .init_machine = mach_cc9p9360js_init_machine, - .timer = &ns9360_timer, - .boot_params = 0x100, -MACHINE_END diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c deleted file mode 100644 index 463e924..0000000 --- a/arch/arm/mach-ns9xxx/plat-serial8250.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/plat-serial8250.c - * - * Copyright (C) 2008 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include -#include - -#include -#include - -#define DRIVER_NAME "serial8250" - -static int __init ns9xxx_plat_serial8250_init(void) -{ - struct plat_serial8250_port *pdata; - struct platform_device *pdev; - int ret = -ENOMEM; - int i; - - if (!board_is_a9m9750dev()) - return -ENODEV; - - pdev = platform_device_alloc(DRIVER_NAME, 0); - if (!pdev) - goto err; - - pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL); - if (!pdata) - goto err; - - pdev->dev.platform_data = pdata; - - pdata[0].iobase = FPGA_UARTA_BASE; - pdata[1].iobase = FPGA_UARTB_BASE; - pdata[2].iobase = FPGA_UARTC_BASE; - pdata[3].iobase = FPGA_UARTD_BASE; - - for (i = 0; i < 4; ++i) { - pdata[i].membase = (void __iomem *)pdata[i].iobase; - pdata[i].mapbase = pdata[i].iobase; - pdata[i].iotype = UPIO_MEM; - pdata[i].uartclk = 18432000; - pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; - } - - pdata[0].irq = IRQ_FPGA_UARTA; - pdata[1].irq = IRQ_FPGA_UARTB; - pdata[2].irq = IRQ_FPGA_UARTC; - pdata[3].irq = IRQ_FPGA_UARTD; - - ret = platform_device_add(pdev); - if (ret) { -err: - platform_device_put(pdev); - - printk(KERN_WARNING "Could not add %s (errno=%d)\n", - DRIVER_NAME, ret); - } - - return 0; -} - -arch_initcall(ns9xxx_plat_serial8250_init); diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c deleted file mode 100644 index aed1999..0000000 --- a/arch/arm/mach-ns9xxx/processor-ns9360.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/processor-ns9360.c - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include - -#include -#include -#include -#include - -void ns9360_reset(char mode) -{ - u32 reg; - - reg = __raw_readl(SYS_PLL) >> 16; - REGSET(reg, SYS_PLL, SWC, YES); - __raw_writel(reg, SYS_PLL); -} - -#define CRYSTAL 29491200 /* Hz */ -unsigned long ns9360_systemclock(void) -{ - u32 pll = __raw_readl(SYS_PLL); - return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) - >> REGGETIM(pll, SYS_PLL, FS); -} - -static struct map_desc ns9360_io_desc[] __initdata = { - { /* BBus */ - .virtual = io_p2v(0x90000000), - .pfn = __phys_to_pfn(0x90000000), - .length = 0x00700000, - .type = MT_DEVICE, - }, { /* AHB */ - .virtual = io_p2v(0xa0100000), - .pfn = __phys_to_pfn(0xa0100000), - .length = 0x00900000, - .type = MT_DEVICE, - }, -}; - -void __init ns9360_map_io(void) -{ - iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc)); -} diff --git a/arch/arm/mach-ns9xxx/time-ns9360.c b/arch/arm/mach-ns9xxx/time-ns9360.c deleted file mode 100644 index 9ca32f5..0000000 --- a/arch/arm/mach-ns9xxx/time-ns9360.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/time-ns9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include "generic.h" - -#define TIMER_CLOCKSOURCE 0 -#define TIMER_CLOCKEVENT 1 -static u32 latch; - -static cycle_t ns9360_clocksource_read(struct clocksource *cs) -{ - return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); -} - -static struct clocksource ns9360_clocksource = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE), - .rating = 300, - .read = ns9360_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static void ns9360_clockevent_setmode(enum clock_event_mode mode, - struct clock_event_device *clk) -{ - u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); - REGSET(tc, SYS_TCx, REN, EN); - REGSET(tc, SYS_TCx, INTS, EN); - REGSET(tc, SYS_TCx, TEN, EN); - break; - - case CLOCK_EVT_MODE_ONESHOT: - REGSET(tc, SYS_TCx, REN, DIS); - REGSET(tc, SYS_TCx, INTS, EN); - - /* fall through */ - - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - default: - REGSET(tc, SYS_TCx, TEN, DIS); - break; - } - - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); -} - -static int ns9360_clockevent_setnextevent(unsigned long evt, - struct clock_event_device *clk) -{ - u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - - if (REGGET(tc, SYS_TCx, TEN)) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - } - - REGSET(tc, SYS_TCx, TEN, EN); - - __raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT)); - - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - - return 0; -} - -static struct clock_event_device ns9360_clockevent_device = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), - .shift = 20, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = ns9360_clockevent_setmode, - .set_next_event = ns9360_clockevent_setnextevent, -}; - -static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id) -{ - int timerno = irq - IRQ_NS9360_TIMER0; - u32 tc; - - struct clock_event_device *evt = &ns9360_clockevent_device; - - /* clear irq */ - tc = __raw_readl(SYS_TC(timerno)); - if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(timerno)); - } - REGSET(tc, SYS_TCx, INTC, SET); - __raw_writel(tc, SYS_TC(timerno)); - REGSET(tc, SYS_TCx, INTC, UNSET); - __raw_writel(tc, SYS_TC(timerno)); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction ns9360_clockevent_action = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = ns9360_clockevent_handler, -}; - -static void __init ns9360_timer_init(void) -{ - int tc; - - tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE)); - if (REGGET(tc, SYS_TCx, TEN)) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); - } - - __raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE)); - - REGSET(tc, SYS_TCx, TEN, EN); - REGSET(tc, SYS_TCx, TDBG, STOP); - REGSET(tc, SYS_TCx, TLCS, CPU); - REGSET(tc, SYS_TCx, TM, IEE); - REGSET(tc, SYS_TCx, INTS, DIS); - REGSET(tc, SYS_TCx, UDS, UP); - REGSET(tc, SYS_TCx, TSZ, 32); - REGSET(tc, SYS_TCx, REN, EN); - - __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); - - clocksource_register_hz(&ns9360_clocksource, ns9360_cpuclock()); - - latch = SH_DIV(ns9360_cpuclock(), HZ, 0); - - tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - REGSET(tc, SYS_TCx, TEN, DIS); - REGSET(tc, SYS_TCx, TDBG, STOP); - REGSET(tc, SYS_TCx, TLCS, CPU); - REGSET(tc, SYS_TCx, TM, IEE); - REGSET(tc, SYS_TCx, INTS, DIS); - REGSET(tc, SYS_TCx, UDS, DOWN); - REGSET(tc, SYS_TCx, TSZ, 32); - REGSET(tc, SYS_TCx, REN, EN); - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - - ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(), - NSEC_PER_SEC, ns9360_clockevent_device.shift); - ns9360_clockevent_device.max_delta_ns = - clockevent_delta2ns(-1, &ns9360_clockevent_device); - ns9360_clockevent_device.min_delta_ns = - clockevent_delta2ns(1, &ns9360_clockevent_device); - - ns9360_clockevent_device.cpumask = cpumask_of(0); - clockevents_register_device(&ns9360_clockevent_device); - - setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT, - &ns9360_clockevent_action); -} - -struct sys_timer ns9360_timer = { - .init = ns9360_timer_init, -}; -- cgit v0.10.2 From a98253e8006a016bcb49c2d9c77041266ea3c5f5 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 29 Apr 2011 15:06:39 +0200 Subject: ARM: mach-mxs: add stmp378x-devb STMP378x and MX23 are the same and just relabeled. There is a mach-stmp378x, however, it has a lot of reinvented interfaces, leaking all sorts of mach-specific functions into the drivers. One example is the dmaengine which does not use the linux dmaengine-API but some privately exported symbols. This makes generic use of the drivers impossible. mach-mxs does it better, so convert the board to mach-mxs. After that, it is possible to delete all stmp-specific code which should ease further ARM-consolidation. Compile tested only due to no hardware (seems not available anymore). Signed-off-by: Wolfram Sang Acked-by: Shawn Guo Signed-off-by: Russell King diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4522fbb..edacefa 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -17,6 +17,16 @@ config SOC_IMX28 comment "MXS platforms:" +config MACH_STMP378X_DEVB + bool "Support STMP378x_devb Platform" + select SOC_IMX23 + select MXS_HAVE_AMBA_DUART + select MXS_HAVE_PLATFORM_AUART + select MXS_HAVE_PLATFORM_MXS_MMC + help + Include support for STMP378x-devb platform. This includes specific + configurations for the board and its peripherals. + config MACH_MX23EVK bool "Support MX23EVK Platform" select SOC_IMX23 diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 2f1f614..58e8923 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o +obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o obj-$(CONFIG_MODULE_TX28) += module-tx28.o diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c new file mode 100644 index 0000000..7f38d82 --- /dev/null +++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c @@ -0,0 +1,120 @@ +/* + * board setup for STMP378x-Development-Board + * + * based on mx23evk board setup and information gained form the original + * plat-stmp based board setup, now converted to mach-mxs. + * + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "devices-mx23.h" + +#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) +#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) + +#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL) + +static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = { + /* duart (extended setup missing in old boardcode, too */ + MX23_PAD_PWM0__DUART_RX, + MX23_PAD_PWM1__DUART_TX, + + /* auart */ + MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART, + + /* mmc */ + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_CMD__SSP1_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DETECT__SSP1_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_SSP1_SCK__SSP1_SCK | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */ + MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */ +}; + +static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = { + .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT, +}; + +static struct spi_board_info spi_board_info[] __initdata = { +#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) + { + .modalias = "enc28j60", + .max_speed_hz = 6 * 1000 * 1000, + .bus_num = 1, + .chip_select = 0, + .platform_data = NULL, + }, +#endif +}; + +static void __init stmp378x_dvb_init(void) +{ + int ret; + + mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, + ARRAY_SIZE(stmp378x_dvb_pads)); + + mx23_add_duart(); + mx23_add_auart0(); + + /* power on mmc slot */ + ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, + GPIOF_OUT_INIT_LOW, "mmc0-slot-power"); + if (ret) + pr_warn("could not power mmc (%d)\n", ret); + + mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata); + + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +} + +static void __init stmp378x_dvb_timer_init(void) +{ + mx23_clocks_init(); +} + +static struct sys_timer stmp378x_dvb_timer = { + .init = stmp378x_dvb_timer_init, +}; + +MACHINE_START(STMP378X, "STMP378X") + .map_io = mx23_map_io, + .init_irq = mx23_init_irq, + .init_machine = stmp378x_dvb_init, + .timer = &stmp378x_dvb_timer, +MACHINE_END -- cgit v0.10.2 From cde7c41feaa06cb6bfc748b2fc3c7d809091c2b0 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 29 Apr 2011 15:06:40 +0200 Subject: ARM: configs: add defconfig for mach-mxs Covers MX23, MX28 and STMP378x. Signed-off-by: Wolfram Sang Cc: Shawn Guo Signed-off-by: Russell King diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig new file mode 100644 index 0000000..2bf2243 --- /dev/null +++ b/arch/arm/configs/mxs_defconfig @@ -0,0 +1,129 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_MXS=y +CONFIG_MACH_STMP378X_DEVB=y +CONFIG_MACH_TX28=y +# CONFIG_ARM_THUMB is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_AUTO_ZRELADDR=y +CONFIG_FPE_NWFPE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_DEV=m +CONFIG_CAN_FLEXCAN=m +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_BLK_DEV is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_ENC28J60=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=m +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MXS=m +CONFIG_SPI=y +CONFIG_SPI_GPIO=m +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_DISPLAY_SUPPORT=m +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_MXS=y +CONFIG_RTC_CLASS=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_DMADEVICES=y +CONFIG_MXS_DMA=y +CONFIG_EXT3_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_PRINTK_TIME=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_TIMER_STATS=y +CONFIG_PROVE_LOCKING=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y +CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_STRICT_DEVMEM=y +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m -- cgit v0.10.2 From 7635965891761a732a610aa7ad9371de742ef52b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 29 Apr 2011 15:06:41 +0200 Subject: ARM: mach-stmp37xx: remove mach This mach has not seen any updates since the initial inclusion besides generic cleanup. Furthermore: - It has a lot of reinvented interfaces, leaking all sorts of mach-related includes into the drivers. One example is the dmaengine which does not use the linux dmaengine-API but some privately exported symbols. So, drivers cannot be reused. mach-mxs is very similar and does it better. - It can be doubted that this worked at all. Check the DMA routines in stmp37xx.c for copy/paste bugs. A lot of APBX-related stuff is actually writing into registers for APBH. - There is only one board defined (which I couldn't find any trace of despite being a development board). In this board, only two devices have resources, the debug uart and the application uart. Neither of those have the needed custom drivers merged (and never will). debug uart is amba-pl011 which has an in-kernel driver without the mach-specific-stuff. appuart has a driver which was introduced for mach-mxs, and this one is reusable for a properly done mach. So, this single board registers only unsupported devices and the generic code looks suspicious and has poor design. Delete this stuff. If there is interest, it is wiser to restart using mach-mxs. Signed-off-by: Wolfram Sang Acked-by: Shawn Guo Signed-off-by: Russell King diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c7d321a..23ecbda 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -186,7 +186,6 @@ machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_STMP378X) := stmp378x -machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx machine-$(CONFIG_ARCH_TCC8K) := tcc8k machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_U300) := u300 diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig deleted file mode 100644 index 564a5cc..0000000 --- a/arch/arm/configs/stmp37xx_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-default" -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_STMP3XXX=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NET_SCHED=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=4 -CONFIG_BLK_DEV_RAM_SIZE=6144 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_INPUT_POLLDEV=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=m -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_BOOT_TRACER=y -CONFIG_STACK_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_DEBUG_LL=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC16=y diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile deleted file mode 100644 index 57deffd..0000000 --- a/arch/arm/mach-stmp37xx/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o -obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot deleted file mode 100644 index 1568ad4..0000000 --- a/arch/arm/mach-stmp37xx/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x40008000 -params_phys-y := 0x40000100 -initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S deleted file mode 100644 index fed2787..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Low-level IRQ helper macros for Freescale STMP37XX - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #0xf0000000 @ vm address of IRQ controller - ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT - cmp \irqnr, #0x3f - movne \irqstat, #0 @ Ack this IRQ - strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR - moveqs \irqnr, #0 @ Zero flag set for no IRQ - - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h deleted file mode 100644 index 98f1293..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/irqs.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Freescale STMP37XX interrupts - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef _ASM_ARCH_IRQS_H -#define _ASM_ARCH_IRQS_H - -#define IRQ_DEBUG_UART 0 -#define IRQ_COMMS_RX 1 -#define IRQ_COMMS_TX 1 -#define IRQ_SSP2_ERROR 2 -#define IRQ_VDD5V 3 -#define IRQ_HEADPHONE_SHORT 4 -#define IRQ_DAC_DMA 5 -#define IRQ_DAC_ERROR 6 -#define IRQ_ADC_DMA 7 -#define IRQ_ADC_ERROR 8 -#define IRQ_SPDIF_DMA 9 -#define IRQ_SAIF2_DMA 9 -#define IRQ_SPDIF_ERROR 10 -#define IRQ_SAIF1_IRQ 10 -#define IRQ_SAIF2_IRQ 10 -#define IRQ_USB_CTRL 11 -#define IRQ_USB_WAKEUP 12 -#define IRQ_GPMI_DMA 13 -#define IRQ_SSP1_DMA 14 -#define IRQ_SSP_ERROR 15 -#define IRQ_GPIO0 16 -#define IRQ_GPIO1 17 -#define IRQ_GPIO2 18 -#define IRQ_SAIF1_DMA 19 -#define IRQ_SSP2_DMA 20 -#define IRQ_ECC8_IRQ 21 -#define IRQ_RTC_ALARM 22 -#define IRQ_UARTAPP_TX_DMA 23 -#define IRQ_UARTAPP_INTERNAL 24 -#define IRQ_UARTAPP_RX_DMA 25 -#define IRQ_I2C_DMA 26 -#define IRQ_I2C_ERROR 27 -#define IRQ_TIMER0 28 -#define IRQ_TIMER1 29 -#define IRQ_TIMER2 30 -#define IRQ_TIMER3 31 -#define IRQ_BATT_BRNOUT 32 -#define IRQ_VDDD_BRNOUT 33 -#define IRQ_VDDIO_BRNOUT 34 -#define IRQ_VDD18_BRNOUT 35 -#define IRQ_TOUCH_DETECT 36 -#define IRQ_LRADC_CH0 37 -#define IRQ_LRADC_CH1 38 -#define IRQ_LRADC_CH2 39 -#define IRQ_LRADC_CH3 40 -#define IRQ_LRADC_CH4 41 -#define IRQ_LRADC_CH5 42 -#define IRQ_LRADC_CH6 43 -#define IRQ_LRADC_CH7 44 -#define IRQ_LCDIF_DMA 45 -#define IRQ_LCDIF_ERROR 46 -#define IRQ_DIGCTL_DEBUG_TRAP 47 -#define IRQ_RTC_1MSEC 48 -#define IRQ_DRI_DMA 49 -#define IRQ_DRI_ATTENTION 50 -#define IRQ_GPMI_ATTENTION 51 -#define IRQ_IR 52 -#define IRQ_DCP_VMI 53 -#define IRQ_DCP 54 -#define IRQ_RESERVED_55 55 -#define IRQ_RESERVED_56 56 -#define IRQ_RESERVED_57 57 -#define IRQ_RESERVED_58 58 -#define IRQ_RESERVED_59 59 -#define SW_IRQ_60 60 -#define SW_IRQ_61 61 -#define SW_IRQ_62 62 -#define SW_IRQ_63 63 - -#define NR_REAL_IRQS 64 -#define NR_IRQS (NR_REAL_IRQS + 32 * 3) - -/* TIMER and BRNOUT are FIQ capable */ -#define FIQ_START IRQ_TIMER0 - -/* Hard disk IRQ is a GPMI attention IRQ */ -#define IRQ_HARDDISK IRQ_GPMI_ATTENTION - -#endif /* _ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h deleted file mode 100644 index d56de0c..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/pins.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Freescale STMP37XX SoC pin multiplexing - * - * Author: Vladislav Buzov - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_PINS_H -#define __ASM_ARCH_PINS_H - -/* - * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware - * interface this pin belongs to. - */ - -/* Bank 0 */ -#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) -#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) -#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) -#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) -#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) -#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) -#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) -#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) -#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) -#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) -#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) -#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) -#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) -#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) -#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) -#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) -#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16) -#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17) -#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18) -#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) -#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20) -#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21) -#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22) -#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23) -#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) -#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) -#define PINID_UART2_CTS STMP3XXX_PINID(0, 26) -#define PINID_UART2_RTS STMP3XXX_PINID(0, 27) -#define PINID_UART2_RX STMP3XXX_PINID(0, 28) -#define PINID_UART2_TX STMP3XXX_PINID(0, 29) - -/* Bank 1 */ -#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) -#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) -#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) -#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) -#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) -#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) -#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) -#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) -#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) -#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) -#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) -#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) -#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) -#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) -#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) -#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) -#define PINID_LCD_RESET STMP3XXX_PINID(1, 16) -#define PINID_LCD_RS STMP3XXX_PINID(1, 17) -#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18) -#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19) -#define PINID_LCD_CS STMP3XXX_PINID(1, 20) -#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21) -#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22) -#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23) -#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24) -#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25) -#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26) -#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27) -#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28) - -/* Bank 2 */ -#define PINID_PWM0 STMP3XXX_PINID(2, 0) -#define PINID_PWM1 STMP3XXX_PINID(2, 1) -#define PINID_PWM2 STMP3XXX_PINID(2, 2) -#define PINID_PWM3 STMP3XXX_PINID(2, 3) -#define PINID_PWM4 STMP3XXX_PINID(2, 4) -#define PINID_I2C_SCL STMP3XXX_PINID(2, 5) -#define PINID_I2C_SDA STMP3XXX_PINID(2, 6) -#define PINID_ROTTARYA STMP3XXX_PINID(2, 7) -#define PINID_ROTTARYB STMP3XXX_PINID(2, 8) -#define PINID_EMI_CKE STMP3XXX_PINID(2, 9) -#define PINID_EMI_RASN STMP3XXX_PINID(2, 10) -#define PINID_EMI_CASN STMP3XXX_PINID(2, 11) -#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12) -#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13) -#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14) -#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15) -#define PINID_EMI_A00 STMP3XXX_PINID(2, 16) -#define PINID_EMI_A01 STMP3XXX_PINID(2, 17) -#define PINID_EMI_A02 STMP3XXX_PINID(2, 18) -#define PINID_EMI_A03 STMP3XXX_PINID(2, 19) -#define PINID_EMI_A04 STMP3XXX_PINID(2, 20) -#define PINID_EMI_A05 STMP3XXX_PINID(2, 21) -#define PINID_EMI_A06 STMP3XXX_PINID(2, 22) -#define PINID_EMI_A07 STMP3XXX_PINID(2, 23) -#define PINID_EMI_A08 STMP3XXX_PINID(2, 24) -#define PINID_EMI_A09 STMP3XXX_PINID(2, 25) -#define PINID_EMI_A10 STMP3XXX_PINID(2, 26) -#define PINID_EMI_A11 STMP3XXX_PINID(2, 27) -#define PINID_EMI_A12 STMP3XXX_PINID(2, 28) -#define PINID_EMI_A13 STMP3XXX_PINID(2, 29) -#define PINID_EMI_A14 STMP3XXX_PINID(2, 30) -#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) - -/* Bank 3 */ -#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) -#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) -#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) -#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) -#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) -#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) -#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) -#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) -#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) -#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) -#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) -#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) -#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) -#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) -#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) -#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) -#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16) -#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17) -#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18) -#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19) -#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) -#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) - -#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h deleted file mode 100644 index a323aa9..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * stmp37xx: APBH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBH -#define _MACH_REGS_APBH - -#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) - -#define HW_APBH_CTRL0 0x0 -#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBH_CTRL0_RESET_CHANNEL 16 -#define BM_APBH_CTRL0_CLKGATE 0x40000000 -#define BM_APBH_CTRL0_SFTRST 0x80000000 - -#define HW_APBH_CTRL1 0x10 -#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 -#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 - -#define HW_APBH_DEVSEL 0x20 - -#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBH_CHn_NXTCMDAR 0x50 - -#define BM_APBH_CHn_CMD_MODE 0x00000003 -#define BP_APBH_CHn_CMD_MODE 0x00000001 -#define BV_APBH_CHn_CMD_MODE_NOOP 0 -#define BV_APBH_CHn_CMD_MODE_WRITE 1 -#define BV_APBH_CHn_CMD_MODE_READ 2 -#define BV_APBH_CHn_CMD_MODE_SENSE 3 -#define BM_APBH_CHn_CMD_CHAIN 0x00000004 -#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 -#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 -#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBH_CHn_CMD_CMDWORDS 12 -#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBH_CHn_CMD_XFER_COUNT 16 - -#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBH_CHn_SEMA 0x80 -#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBH_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h deleted file mode 100644 index 6d080cd..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * stmp37xx: APBX register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBX -#define _MACH_REGS_APBX - -#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) - -#define HW_APBX_CTRL0 0x0 -#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBX_CTRL0_RESET_CHANNEL 16 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 -#define BM_APBX_CTRL0_SFTRST 0x80000000 - -#define HW_APBX_CTRL1 0x10 - -#define HW_APBX_DEVSEL 0x20 - -#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBX_CHn_NXTCMDAR 0x50 -#define BM_APBX_CHn_CMD_MODE 0x00000003 -#define BP_APBX_CHn_CMD_MODE 0x00000001 -#define BV_APBX_CHn_CMD_MODE_NOOP 0 -#define BV_APBX_CHn_CMD_MODE_WRITE 1 -#define BV_APBX_CHn_CMD_MODE_READ 2 -#define BV_APBX_CHn_CMD_MODE_SENSE 3 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBX_CHn_CMD_XFER_COUNT 16 - -#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70) -#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70) -#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70) -#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70) -#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70) -#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70) -#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70) -#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70) -#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70) -#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70) -#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70) -#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70) -#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70) -#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70) -#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70) -#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70) - -#define HW_APBX_CHn_BAR 0x70 - -#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBX_CHn_SEMA 0x80 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBX_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h deleted file mode 100644 index 3b511f9..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * stmp37xx: AUDIOIN register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) - -#define HW_AUDIOIN_CTRL 0x0 -#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define BP_AUDIOIN_CTRL_RUN 0 -#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 -#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOIN_STAT 0x10 - -#define HW_AUDIOIN_ADCSRR 0x20 - -#define HW_AUDIOIN_ADCVOLUME 0x30 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF -#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 -#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 - -#define HW_AUDIOIN_ADCDEBUG 0x40 - -#define HW_AUDIOIN_ADCVOL 0x50 -#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F -#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 -#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 -#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 -#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 -#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 -#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 -#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 -#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 - -#define HW_AUDIOIN_MICLINE 0x60 - -#define HW_AUDIOIN_ANACLKCTRL 0x70 -#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOIN_DATA 0x80 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h deleted file mode 100644 index ca1942b..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * stmp37xx: AUDIOOUT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) - -#define HW_AUDIOOUT_CTRL 0x0 -#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define BP_AUDIOOUT_CTRL_RUN 0 -#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 -#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOOUT_STAT 0x10 - -#define HW_AUDIOOUT_DACSRR 0x20 -#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF -#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 -#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 -#define BP_AUDIOOUT_DACSRR_SRC_INT 16 -#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 -#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 -#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 -#define BP_AUDIOOUT_DACSRR_BASEMULT 28 - -#define HW_AUDIOOUT_DACVOLUME 0x30 -#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 -#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 -#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_DACDEBUG 0x40 - -#define HW_AUDIOOUT_HPVOL 0x50 -#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 -#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 - -#define HW_AUDIOOUT_PWRDN 0x70 -#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 -#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 -#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 -#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 -#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 -#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000 - -#define HW_AUDIOOUT_REFCTRL 0x80 -#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 -#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 -#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 -#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 -#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 -#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 -#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 -#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 -#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 -#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 -#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 -#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 -#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 - -#define HW_AUDIOOUT_ANACTRL 0x90 -#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 -#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 - -#define HW_AUDIOOUT_TEST 0xA0 -#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 -#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 - -#define HW_AUDIOOUT_BISTCTRL 0xB0 - -#define HW_AUDIOOUT_BISTSTAT0 0xC0 - -#define HW_AUDIOOUT_BISTSTAT1 0xD0 - -#define HW_AUDIOOUT_ANACLKCTRL 0xE0 -#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOOUT_DATA 0xF0 - -#define HW_AUDIOOUT_LINEOUTCTRL 0x100 -#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F -#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0 -#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00 -#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8 -#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000 -#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12 -#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000 -#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20 -#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000 -#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_VERSION 0x200 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h deleted file mode 100644 index 47f5c92..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * stmp37xx: CLKCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_CLKCTRL -#define _MACH_REGS_CLKCTRL - -#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) - -#define HW_CLKCTRL_PLLCTRL0 0x0 -#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 - -#define HW_CLKCTRL_CPU 0x20 -#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F -#define BP_CLKCTRL_CPU_DIV_CPU 0 - -#define HW_CLKCTRL_HBUS 0x30 -#define BM_CLKCTRL_HBUS_DIV 0x0000001F -#define BP_CLKCTRL_HBUS_DIV 0 - -#define HW_CLKCTRL_XBUS 0x40 - -#define HW_CLKCTRL_XTAL 0x50 - -#define HW_CLKCTRL_PIX 0x60 -#define BM_CLKCTRL_PIX_DIV 0x00007FFF -#define BP_CLKCTRL_PIX_DIV 0 -#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 - -#define HW_CLKCTRL_SSP 0x70 - -#define HW_CLKCTRL_GPMI 0x80 - -#define HW_CLKCTRL_SPDIF 0x90 - -#define HW_CLKCTRL_EMI 0xA0 - -#define HW_CLKCTRL_IR 0xB0 - -#define HW_CLKCTRL_SAIF 0xC0 - -#define HW_CLKCTRL_FRAC 0xD0 -#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 -#define BP_CLKCTRL_FRAC_EMIFRAC 8 -#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 -#define BP_CLKCTRL_FRAC_PIXFRAC 16 -#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 - -#define HW_CLKCTRL_CLKSEQ 0xE0 -#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 - -#define HW_CLKCTRL_RESET 0xF0 -#define BM_CLKCTRL_RESET_DIG 0x00000001 -#define BP_CLKCTRL_RESET_DIG 0 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h deleted file mode 100644 index ba1bbe2..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * stmp37xx: DIGCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000) - -#define HW_DIGCTL_CTRL 0x0 -#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h deleted file mode 100644 index 3b6d990..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp37xx: ECC8 register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) - -#define HW_ECC8_CTRL 0x0 -#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_ECC8_CTRL_COMPLETE_IRQ 0 -#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 -#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 - -#define HW_ECC8_STATUS0 0x10 -#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_ECC8_STATUS0_CORRECTED 0x00000008 -#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 -#define BP_ECC8_STATUS0_STATUS_AUX 8 -#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_ECC8_STATUS0_COMPLETED_CE 16 - -#define HW_ECC8_STATUS1 0x20 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h deleted file mode 100644 index f2b304f..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp37xx: GPMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000) -#define REGS_GPMI_PHYS 0x8000C000 -#define REGS_GPMI_SIZE 0x2000 - -#define HW_GPMI_CTRL0 0x0 -#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_GPMI_CTRL0_XFER_COUNT 0 -#define BM_GPMI_CTRL0_CS 0x00300000 -#define BP_GPMI_CTRL0_CS 20 -#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 -#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 -#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 -#define BP_GPMI_CTRL0_COMMAND_MODE 24 -#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 -#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 -#define BM_GPMI_CTRL0_RUN 0x20000000 -#define BM_GPMI_CTRL0_CLKGATE 0x40000000 -#define BM_GPMI_CTRL0_SFTRST 0x80000000 -#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 -#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 -#define BP_GPMI_ECCCTRL_ECC_CMD 13 - -#define HW_GPMI_CTRL1 0x60 -#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003 -#define BP_GPMI_CTRL1_GPMI_MODE 0 -#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 -#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 -#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 -#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 -#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000 -#define BP_GPMI_CTRL1_DSAMPLE_TIME 12 - -#define HW_GPMI_TIMING0 0x70 -#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF -#define BP_GPMI_TIMING0_DATA_SETUP 0 -#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 -#define BP_GPMI_TIMING0_DATA_HOLD 8 - -#define HW_GPMI_TIMING1 0x80 -#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 -#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h deleted file mode 100644 index 35882a9..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * stmp37xx: I2C register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) -#define REGS_I2C_PHYS 0x80058000 -#define REGS_I2C_SIZE 0x2000 - -#define HW_I2C_CTRL0 0x0 -#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_I2C_CTRL0_XFER_COUNT 0 -#define BM_I2C_CTRL0_DIRECTION 0x00010000 -#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 -#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 -#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 -#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 -#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 -#define BM_I2C_CTRL0_CLKGATE 0x40000000 -#define BM_I2C_CTRL0_SFTRST 0x80000000 - -#define HW_I2C_TIMING0 0x10 - -#define HW_I2C_TIMING1 0x20 - -#define HW_I2C_TIMING2 0x30 - -#define HW_I2C_CTRL1 0x40 -#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 -#define BP_I2C_CTRL1_SLAVE_IRQ 0 -#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 -#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 -#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 -#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 -#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 -#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 -#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 -#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 - -#define HW_I2C_VERSION 0x90 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h deleted file mode 100644 index 3b7c922..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * stmp37xx: ICOLL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_ICOLL -#define _MACH_REGS_ICOLL - -#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) - -#define HW_ICOLL_VECTOR 0x0 - -#define HW_ICOLL_LEVELACK 0x10 - -#define HW_ICOLL_CTRL 0x20 -#define BM_ICOLL_CTRL_CLKGATE 0x40000000 -#define BM_ICOLL_CTRL_SFTRST 0x80000000 - -#define HW_ICOLL_STAT 0x30 - -#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10) -#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10) -#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10) -#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10) - -#define HW_ICOLL_PRIORITYn 0x60 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h deleted file mode 100644 index 72514e8..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * stmp37xx: LCDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) -#define REGS_LCDIF_PHYS 0x80030000 -#define REGS_LCDIF_SIZE 0x2000 - -#define HW_LCDIF_CTRL 0x0 -#define BM_LCDIF_CTRL_COUNT 0x0000FFFF -#define BP_LCDIF_CTRL_COUNT 0 -#define BM_LCDIF_CTRL_RUN 0x00010000 -#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000 -#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000 -#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000 -#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000 -#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000 -#define BP_LCDIF_CTRL_DATA_SWIZZLE 21 -#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000 -#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000 -#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25 -#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000 -#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000 -#define BM_LCDIF_CTRL_CLKGATE 0x40000000 -#define BM_LCDIF_CTRL_SFTRST 0x80000000 - -#define HW_LCDIF_CTRL1 0x10 -#define BM_LCDIF_CTRL1_RESET 0x00000001 -#define BP_LCDIF_CTRL1_RESET 0 -#define BM_LCDIF_CTRL1_MODE86 0x00000002 -#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 -#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 -#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 -#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 -#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 -#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 - -#define HW_LCDIF_TIMING 0x20 - -#define HW_LCDIF_VDCTRL0 0x30 -#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF -#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 -#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 -#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 -#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 -#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 -#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 -#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 -#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 - -#define HW_LCDIF_VDCTRL1 0x40 -#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF -#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 -#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000 -#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20 - -#define HW_LCDIF_VDCTRL2 0x50 -#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF -#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800 -#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11 -#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000 -#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23 - -#define HW_LCDIF_VDCTRL3 0x60 -#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF -#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 -#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000 -#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12 -#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h deleted file mode 100644 index cc7b470..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * stmp37xx: LRADC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) - -#define HW_LRADC_CTRL0 0x0 -#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF -#define BP_LRADC_CTRL0_SCHEDULE 0 -#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 -#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 -#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 -#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 -#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 -#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 -#define BM_LRADC_CTRL0_CLKGATE 0x40000000 -#define BM_LRADC_CTRL0_SFTRST 0x80000000 - -#define HW_LRADC_CTRL1 0x10 -#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 -#define BP_LRADC_CTRL1_LRADC0_IRQ 0 -#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 -#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 -#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 -#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 - -#define HW_LRADC_CTRL2 0x20 -#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 -#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 -#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 -#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 -#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 -#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 - -#define HW_LRADC_CTRL3 0x30 -#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 -#define BP_LRADC_CTRL3_CYCLE_TIME 8 - -#define HW_LRADC_STATUS 0x40 -#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 -#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 - -#define HW_LRADC_CH0 (0x50 + 0 * 0x10) -#define HW_LRADC_CH1 (0x50 + 1 * 0x10) -#define HW_LRADC_CH2 (0x50 + 2 * 0x10) -#define HW_LRADC_CH3 (0x50 + 3 * 0x10) -#define HW_LRADC_CH4 (0x50 + 4 * 0x10) -#define HW_LRADC_CH5 (0x50 + 5 * 0x10) -#define HW_LRADC_CH6 (0x50 + 6 * 0x10) -#define HW_LRADC_CH7 (0x50 + 7 * 0x10) - -#define HW_LRADC_CHn 0x50 -#define BM_LRADC_CHn_VALUE 0x0003FFFF -#define BP_LRADC_CHn_VALUE 0 -#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 -#define BP_LRADC_CHn_NUM_SAMPLES 24 -#define BM_LRADC_CHn_ACCUMULATE 0x20000000 - -#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10) -#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10) -#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10) -#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10) - -#define HW_LRADC_DELAYn 0xD0 -#define BM_LRADC_DELAYn_DELAY 0x000007FF -#define BP_LRADC_DELAYn_DELAY 0 -#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 -#define BP_LRADC_DELAYn_LOOP_COUNT 11 -#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 -#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 -#define BM_LRADC_DELAYn_KICK 0x00100000 -#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 -#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 - -#define HW_LRADC_CTRL4 0x140 -#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 -#define BP_LRADC_CTRL4_LRADC6SELECT 24 -#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 -#define BP_LRADC_CTRL4_LRADC7SELECT 28 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h deleted file mode 100644 index d5efce2..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * stmp37xx: PINCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x300 -#define HW_PINCTRL_PULL1 0x310 -#define HW_PINCTRL_PULL2 0x320 -#define HW_PINCTRL_PULL3 0x330 - -#define HW_PINCTRL_DOUT0 0x400 -#define HW_PINCTRL_DOUT1 0x410 -#define HW_PINCTRL_DOUT2 0x420 - -#define HW_PINCTRL_DIN0 0x500 -#define HW_PINCTRL_DIN1 0x510 -#define HW_PINCTRL_DIN2 0x520 - -#define HW_PINCTRL_DOE0 0x600 -#define HW_PINCTRL_DOE1 0x610 -#define HW_PINCTRL_DOE2 0x620 - -#define HW_PINCTRL_PIN2IRQ0 0x700 -#define HW_PINCTRL_PIN2IRQ1 0x710 -#define HW_PINCTRL_PIN2IRQ2 0x720 - -#define HW_PINCTRL_IRQEN0 0x800 -#define HW_PINCTRL_IRQEN1 0x810 -#define HW_PINCTRL_IRQEN2 0x820 - -#define HW_PINCTRL_IRQLEVEL0 0x900 -#define HW_PINCTRL_IRQLEVEL1 0x910 -#define HW_PINCTRL_IRQLEVEL2 0x920 - -#define HW_PINCTRL_IRQPOL0 0xA00 -#define HW_PINCTRL_IRQPOL1 0xA10 -#define HW_PINCTRL_IRQPOL2 0xA20 - -#define HW_PINCTRL_IRQSTAT0 0xB00 -#define HW_PINCTRL_IRQSTAT1 0xB10 -#define HW_PINCTRL_IRQSTAT2 0xB20 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h deleted file mode 100644 index 0e733d7..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-power.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * stmp37xx: POWER register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_POWER -#define _MACH_REGS_POWER - -#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) - -#define HW_POWER_CTRL 0x0 -#define BM_POWER_CTRL_CLKGATE 0x40000000 - -#define HW_POWER_5VCTRL 0x10 - -#define HW_POWER_MINPWR 0x20 - -#define HW_POWER_CHARGE 0x30 - -#define HW_POWER_VDDDCTRL 0x40 - -#define HW_POWER_VDDACTRL 0x50 - -#define HW_POWER_VDDIOCTRL 0x60 -#define BM_POWER_VDDIOCTRL_TRG 0x0000001F -#define BP_POWER_VDDIOCTRL_TRG 0 - -#define HW_POWER_STS 0xB0 -#define BM_POWER_STS_VBUSVALID 0x00000002 -#define BM_POWER_STS_BVALID 0x00000004 -#define BM_POWER_STS_AVALID 0x00000008 -#define BM_POWER_STS_DC_OK 0x00000100 - -#define HW_POWER_RESET 0xE0 - -#define HW_POWER_DEBUG 0xF0 -#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 -#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h deleted file mode 100644 index 15966a1..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * stmp37xx: PWM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) - -#define HW_PWM_CTRL 0x0 -#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 -#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 - -#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20) -#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20) -#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20) -#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20) - -#define HW_PWM_ACTIVEn 0x10 -#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF -#define BP_PWM_ACTIVEn_ACTIVE 0 -#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 -#define BP_PWM_ACTIVEn_INACTIVE 16 - -#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20) -#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20) -#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20) -#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20) - -#define HW_PWM_PERIODn 0x20 -#define BM_PWM_PERIODn_PERIOD 0x0000FFFF -#define BP_PWM_PERIODn_PERIOD 0 -#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 -#define BP_PWM_PERIODn_ACTIVE_STATE 16 -#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 -#define BP_PWM_PERIODn_INACTIVE_STATE 18 -#define BM_PWM_PERIODn_CDIV 0x00700000 -#define BP_PWM_PERIODn_CDIV 20 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h deleted file mode 100644 index fac40ed..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * stmp37xx: RTC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000) -#define REGS_RTC_PHYS 0x8005C000 -#define REGS_RTC_SIZE 0x2000 - -#define HW_RTC_CTRL 0x0 -#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 -#define BP_RTC_CTRL_ALARM_IRQ_EN 0 -#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 -#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 -#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 -#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 - -#define HW_RTC_STAT 0x10 -#define BM_RTC_STAT_NEW_REGS 0x0000FF00 -#define BP_RTC_STAT_NEW_REGS 8 -#define BM_RTC_STAT_STALE_REGS 0x00FF0000 -#define BP_RTC_STAT_STALE_REGS 16 -#define BM_RTC_STAT_RTC_PRESENT 0x80000000 - -#define HW_RTC_SECONDS 0x30 - -#define HW_RTC_ALARM 0x40 - -#define HW_RTC_WATCHDOG 0x50 - -#define HW_RTC_PERSISTENT0 0x60 -#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 -#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 -#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 -#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 -#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 -#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 -#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 - -#define HW_RTC_PERSISTENT1 0x70 - -#define HW_RTC_VERSION 0xD0 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h deleted file mode 100644 index cbde891..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * stmp37xx: SSP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000) -#define REGS_SSP1_PHYS 0x80010000 -#define REGS_SSP2_PHYS 0x80034000 -#define REGS_SSP_SIZE 0x2000 - -#define HW_SSP_CTRL0 0x0 -#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_SSP_CTRL0_XFER_COUNT 0 -#define BM_SSP_CTRL0_ENABLE 0x00010000 -#define BM_SSP_CTRL0_GET_RESP 0x00020000 -#define BM_SSP_CTRL0_LONG_RESP 0x00080000 -#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 -#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 -#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 -#define BP_SSP_CTRL0_BUS_WIDTH 22 -#define BM_SSP_CTRL0_DATA_XFER 0x01000000 -#define BM_SSP_CTRL0_READ 0x02000000 -#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 -#define BM_SSP_CTRL0_LOCK_CS 0x08000000 -#define BM_SSP_CTRL0_RUN 0x20000000 -#define BM_SSP_CTRL0_CLKGATE 0x40000000 -#define BM_SSP_CTRL0_SFTRST 0x80000000 - -#define HW_SSP_CMD0 0x10 -#define BM_SSP_CMD0_CMD 0x000000FF -#define BP_SSP_CMD0_CMD 0 -#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 -#define BP_SSP_CMD0_BLOCK_COUNT 8 -#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 -#define BP_SSP_CMD0_BLOCK_SIZE 16 -#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 -#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF -#define BP_SSP_CMD1_CMD_ARG 0 - -#define HW_SSP_TIMING 0x50 -#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF -#define BP_SSP_TIMING_CLOCK_RATE 0 -#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 -#define BP_SSP_TIMING_CLOCK_DIVIDE 8 -#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 -#define BP_SSP_TIMING_TIMEOUT 16 - -#define HW_SSP_CTRL1 0x60 -#define BM_SSP_CTRL1_SSP_MODE 0x0000000F -#define BP_SSP_CTRL1_SSP_MODE 0 -#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 -#define BP_SSP_CTRL1_WORD_LENGTH 4 -#define BM_SSP_CTRL1_POLARITY 0x00000200 -#define BM_SSP_CTRL1_PHASE 0x00000400 -#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 -#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 -#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 -#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 - -#define HW_SSP_DATA 0x70 - -#define HW_SSP_SDRESP0 0x80 - -#define HW_SSP_SDRESP1 0x90 - -#define HW_SSP_SDRESP2 0xA0 - -#define HW_SSP_SDRESP3 0xB0 - -#define HW_SSP_STATUS 0xC0 -#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 -#define BM_SSP_STATUS_TIMEOUT 0x00001000 -#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 -#define BM_SSP_STATUS_RESP_ERR 0x00008000 -#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 -#define BM_SSP_STATUS_CARD_DETECT 0x10000000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h deleted file mode 100644 index 4af0f6e..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * stmp37xx: TIMROT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_TIMROT -#define _MACH_REGS_TIMROT - -#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) - -#define HW_TIMROT_ROTCTRL 0x0 -#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 -#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 - -#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) -#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) -#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) - -#define HW_TIMROT_TIMCTRLn 0x20 -#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F -#define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 -#define BP_TIMROT_TIMCTRLn_PRESCALE 4 -#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 -#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 -#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 -#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 - -#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) -#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) -#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) - -#define HW_TIMROT_TIMCOUNTn 0x30 -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h deleted file mode 100644 index 0594275..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * stmp37xx: UARTAPP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000) -#define REGS_UARTAPP1_PHYS 0x8006C000 -#define REGS_UARTAPP_SIZE 0x2000 - -#define HW_UARTAPP_CTRL0 0x0 -#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL0_XFER_COUNT 0 -#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 -#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 -#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 -#define BM_UARTAPP_CTRL0_RUN 0x20000000 -#define BM_UARTAPP_CTRL0_SFTRST 0x80000000 -#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL1_XFER_COUNT 0 -#define BM_UARTAPP_CTRL1_RUN 0x10000000 - -#define HW_UARTAPP_CTRL2 0x20 -#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 -#define BP_UARTAPP_CTRL2_UARTEN 0 -#define BM_UARTAPP_CTRL2_TXE 0x00000100 -#define BM_UARTAPP_CTRL2_RXE 0x00000200 -#define BM_UARTAPP_CTRL2_RTS 0x00000800 -#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 -#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 -#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 -#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 -#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 - -#define HW_UARTAPP_LINECTRL 0x30 -#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define BP_UARTAPP_LINECTRL_BRK 0 -#define BM_UARTAPP_LINECTRL_PEN 0x00000002 -#define BM_UARTAPP_LINECTRL_EPS 0x00000004 -#define BM_UARTAPP_LINECTRL_STP2 0x00000008 -#define BM_UARTAPP_LINECTRL_FEN 0x00000010 -#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 -#define BP_UARTAPP_LINECTRL_WLEN 5 -#define BM_UARTAPP_LINECTRL_SPS 0x00000080 -#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 -#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 -#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 -#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 - -#define HW_UARTAPP_INTR 0x50 -#define BM_UARTAPP_INTR_CTSMIS 0x00000002 -#define BM_UARTAPP_INTR_RTIS 0x00000040 -#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 -#define BM_UARTAPP_INTR_RXIEN 0x00100000 -#define BM_UARTAPP_INTR_RTIEN 0x00400000 - -#define HW_UARTAPP_DATA 0x60 - -#define HW_UARTAPP_STAT 0x70 -#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF -#define BP_UARTAPP_STAT_RXCOUNT 0 -#define BM_UARTAPP_STAT_FERR 0x00010000 -#define BM_UARTAPP_STAT_PERR 0x00020000 -#define BM_UARTAPP_STAT_BERR 0x00040000 -#define BM_UARTAPP_STAT_OERR 0x00080000 -#define BM_UARTAPP_STAT_RXFE 0x01000000 -#define BM_UARTAPP_STAT_TXFF 0x02000000 -#define BM_UARTAPP_STAT_TXFE 0x08000000 -#define BM_UARTAPP_STAT_CTS 0x10000000 - -#define HW_UARTAPP_VERSION 0x90 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h deleted file mode 100644 index b810deb..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * stmp378x: UARTDBG register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) -#define REGS_UARTDBG_PHYS 0x80070000 -#define REGS_UARTDBG_SIZE 0x2000 - -#define HW_UARTDBGDR 0x00000000 -#define BP_UARTDBGDR_UNAVAILABLE 16 -#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) -#define BP_UARTDBGDR_RESERVED 12 -#define BM_UARTDBGDR_RESERVED 0x0000F000 -#define BF_UARTDBGDR_RESERVED(v) \ - (((v) << 12) & BM_UARTDBGDR_RESERVED) -#define BM_UARTDBGDR_OE 0x00000800 -#define BM_UARTDBGDR_BE 0x00000400 -#define BM_UARTDBGDR_PE 0x00000200 -#define BM_UARTDBGDR_FE 0x00000100 -#define BP_UARTDBGDR_DATA 0 -#define BM_UARTDBGDR_DATA 0x000000FF -#define BF_UARTDBGDR_DATA(v) \ - (((v) << 0) & BM_UARTDBGDR_DATA) -#define HW_UARTDBGRSR_ECR 0x00000004 -#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 -#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) -#define BP_UARTDBGRSR_ECR_EC 4 -#define BM_UARTDBGRSR_ECR_EC 0x000000F0 -#define BF_UARTDBGRSR_ECR_EC(v) \ - (((v) << 4) & BM_UARTDBGRSR_ECR_EC) -#define BM_UARTDBGRSR_ECR_OE 0x00000008 -#define BM_UARTDBGRSR_ECR_BE 0x00000004 -#define BM_UARTDBGRSR_ECR_PE 0x00000002 -#define BM_UARTDBGRSR_ECR_FE 0x00000001 -#define HW_UARTDBGFR 0x00000018 -#define BP_UARTDBGFR_UNAVAILABLE 16 -#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGFR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) -#define BP_UARTDBGFR_RESERVED 9 -#define BM_UARTDBGFR_RESERVED 0x0000FE00 -#define BF_UARTDBGFR_RESERVED(v) \ - (((v) << 9) & BM_UARTDBGFR_RESERVED) -#define BM_UARTDBGFR_RI 0x00000100 -#define BM_UARTDBGFR_TXFE 0x00000080 -#define BM_UARTDBGFR_RXFF 0x00000040 -#define BM_UARTDBGFR_TXFF 0x00000020 -#define BM_UARTDBGFR_RXFE 0x00000010 -#define BM_UARTDBGFR_BUSY 0x00000008 -#define BM_UARTDBGFR_DCD 0x00000004 -#define BM_UARTDBGFR_DSR 0x00000002 -#define BM_UARTDBGFR_CTS 0x00000001 -#define HW_UARTDBGILPR 0x00000020 -#define BP_UARTDBGILPR_UNAVAILABLE 8 -#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGILPR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) -#define BP_UARTDBGILPR_ILPDVSR 0 -#define BM_UARTDBGILPR_ILPDVSR 0x000000FF -#define BF_UARTDBGILPR_ILPDVSR(v) \ - (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) -#define HW_UARTDBGIBRD 0x00000024 -#define BP_UARTDBGIBRD_UNAVAILABLE 16 -#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) -#define BP_UARTDBGIBRD_BAUD_DIVINT 0 -#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF -#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ - (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) -#define HW_UARTDBGFBRD 0x00000028 -#define BP_UARTDBGFBRD_UNAVAILABLE 8 -#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) -#define BP_UARTDBGFBRD_RESERVED 6 -#define BM_UARTDBGFBRD_RESERVED 0x000000C0 -#define BF_UARTDBGFBRD_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGFBRD_RESERVED) -#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 -#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F -#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ - (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) -#define HW_UARTDBGLCR_H 0x0000002c -#define BP_UARTDBGLCR_H_UNAVAILABLE 16 -#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) -#define BP_UARTDBGLCR_H_RESERVED 8 -#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 -#define BF_UARTDBGLCR_H_RESERVED(v) \ - (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) -#define BM_UARTDBGLCR_H_SPS 0x00000080 -#define BP_UARTDBGLCR_H_WLEN 5 -#define BM_UARTDBGLCR_H_WLEN 0x00000060 -#define BF_UARTDBGLCR_H_WLEN(v) \ - (((v) << 5) & BM_UARTDBGLCR_H_WLEN) -#define BM_UARTDBGLCR_H_FEN 0x00000010 -#define BM_UARTDBGLCR_H_STP2 0x00000008 -#define BM_UARTDBGLCR_H_EPS 0x00000004 -#define BM_UARTDBGLCR_H_PEN 0x00000002 -#define BM_UARTDBGLCR_H_BRK 0x00000001 -#define HW_UARTDBGCR 0x00000030 -#define BP_UARTDBGCR_UNAVAILABLE 16 -#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGCR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) -#define BM_UARTDBGCR_CTSEN 0x00008000 -#define BM_UARTDBGCR_RTSEN 0x00004000 -#define BM_UARTDBGCR_OUT2 0x00002000 -#define BM_UARTDBGCR_OUT1 0x00001000 -#define BM_UARTDBGCR_RTS 0x00000800 -#define BM_UARTDBGCR_DTR 0x00000400 -#define BM_UARTDBGCR_RXE 0x00000200 -#define BM_UARTDBGCR_TXE 0x00000100 -#define BM_UARTDBGCR_LBE 0x00000080 -#define BP_UARTDBGCR_RESERVED 3 -#define BM_UARTDBGCR_RESERVED 0x00000078 -#define BF_UARTDBGCR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGCR_RESERVED) -#define BM_UARTDBGCR_SIRLP 0x00000004 -#define BM_UARTDBGCR_SIREN 0x00000002 -#define BM_UARTDBGCR_UARTEN 0x00000001 -#define HW_UARTDBGIFLS 0x00000034 -#define BP_UARTDBGIFLS_UNAVAILABLE 16 -#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) -#define BP_UARTDBGIFLS_RESERVED 6 -#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 -#define BF_UARTDBGIFLS_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGIFLS_RESERVED) -#define BP_UARTDBGIFLS_RXIFLSEL 3 -#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 -#define BF_UARTDBGIFLS_RXIFLSEL(v) \ - (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) -#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 -#define BP_UARTDBGIFLS_TXIFLSEL 0 -#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 -#define BF_UARTDBGIFLS_TXIFLSEL(v) \ - (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) -#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 -#define HW_UARTDBGIMSC 0x00000038 -#define BP_UARTDBGIMSC_UNAVAILABLE 16 -#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) -#define BP_UARTDBGIMSC_RESERVED 11 -#define BM_UARTDBGIMSC_RESERVED 0x0000F800 -#define BF_UARTDBGIMSC_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGIMSC_RESERVED) -#define BM_UARTDBGIMSC_OEIM 0x00000400 -#define BM_UARTDBGIMSC_BEIM 0x00000200 -#define BM_UARTDBGIMSC_PEIM 0x00000100 -#define BM_UARTDBGIMSC_FEIM 0x00000080 -#define BM_UARTDBGIMSC_RTIM 0x00000040 -#define BM_UARTDBGIMSC_TXIM 0x00000020 -#define BM_UARTDBGIMSC_RXIM 0x00000010 -#define BM_UARTDBGIMSC_DSRMIM 0x00000008 -#define BM_UARTDBGIMSC_DCDMIM 0x00000004 -#define BM_UARTDBGIMSC_CTSMIM 0x00000002 -#define BM_UARTDBGIMSC_RIMIM 0x00000001 -#define HW_UARTDBGRIS 0x0000003c -#define BP_UARTDBGRIS_UNAVAILABLE 16 -#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGRIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) -#define BP_UARTDBGRIS_RESERVED 11 -#define BM_UARTDBGRIS_RESERVED 0x0000F800 -#define BF_UARTDBGRIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGRIS_RESERVED) -#define BM_UARTDBGRIS_OERIS 0x00000400 -#define BM_UARTDBGRIS_BERIS 0x00000200 -#define BM_UARTDBGRIS_PERIS 0x00000100 -#define BM_UARTDBGRIS_FERIS 0x00000080 -#define BM_UARTDBGRIS_RTRIS 0x00000040 -#define BM_UARTDBGRIS_TXRIS 0x00000020 -#define BM_UARTDBGRIS_RXRIS 0x00000010 -#define BM_UARTDBGRIS_DSRRMIS 0x00000008 -#define BM_UARTDBGRIS_DCDRMIS 0x00000004 -#define BM_UARTDBGRIS_CTSRMIS 0x00000002 -#define BM_UARTDBGRIS_RIRMIS 0x00000001 -#define HW_UARTDBGMIS 0x00000040 -#define BP_UARTDBGMIS_UNAVAILABLE 16 -#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGMIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) -#define BP_UARTDBGMIS_RESERVED 11 -#define BM_UARTDBGMIS_RESERVED 0x0000F800 -#define BF_UARTDBGMIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGMIS_RESERVED) -#define BM_UARTDBGMIS_OEMIS 0x00000400 -#define BM_UARTDBGMIS_BEMIS 0x00000200 -#define BM_UARTDBGMIS_PEMIS 0x00000100 -#define BM_UARTDBGMIS_FEMIS 0x00000080 -#define BM_UARTDBGMIS_RTMIS 0x00000040 -#define BM_UARTDBGMIS_TXMIS 0x00000020 -#define BM_UARTDBGMIS_RXMIS 0x00000010 -#define BM_UARTDBGMIS_DSRMMIS 0x00000008 -#define BM_UARTDBGMIS_DCDMMIS 0x00000004 -#define BM_UARTDBGMIS_CTSMMIS 0x00000002 -#define BM_UARTDBGMIS_RIMMIS 0x00000001 -#define HW_UARTDBGICR 0x00000044 -#define BP_UARTDBGICR_UNAVAILABLE 16 -#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGICR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) -#define BP_UARTDBGICR_RESERVED 11 -#define BM_UARTDBGICR_RESERVED 0x0000F800 -#define BF_UARTDBGICR_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGICR_RESERVED) -#define BM_UARTDBGICR_OEIC 0x00000400 -#define BM_UARTDBGICR_BEIC 0x00000200 -#define BM_UARTDBGICR_PEIC 0x00000100 -#define BM_UARTDBGICR_FEIC 0x00000080 -#define BM_UARTDBGICR_RTIC 0x00000040 -#define BM_UARTDBGICR_TXIC 0x00000020 -#define BM_UARTDBGICR_RXIC 0x00000010 -#define BM_UARTDBGICR_DSRMIC 0x00000008 -#define BM_UARTDBGICR_DCDMIC 0x00000004 -#define BM_UARTDBGICR_CTSMIC 0x00000002 -#define BM_UARTDBGICR_RIMIC 0x00000001 -#define HW_UARTDBGDMACR 0x00000048 -#define BP_UARTDBGDMACR_UNAVAILABLE 16 -#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) -#define BP_UARTDBGDMACR_RESERVED 3 -#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 -#define BF_UARTDBGDMACR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGDMACR_RESERVED) -#define BM_UARTDBGDMACR_DMAONERR 0x00000004 -#define BM_UARTDBGDMACR_TXDMAE 0x00000002 -#define BM_UARTDBGDMACR_RXDMAE 0x00000001 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h deleted file mode 100644 index 9145e22..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * stmp37xx: USBCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTL_PHYS 0x80000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h deleted file mode 100644 index 1a2ae9c..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * stmp37xx: USBCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTRL_PHYS 0x80080000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h deleted file mode 100644 index b7fce0f..0000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp37xx: USBPHY register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000) - -#define HW_USBPHY_PWD 0x0 - -#define HW_USBPHY_CTRL 0x30 -#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001 -#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0 -#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 -#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 -#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 -#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 -#define BM_USBPHY_CTRL_CLKGATE 0x40000000 -#define BM_USBPHY_CTRL_SFTRST 0x80000000 - -#define HW_USBPHY_STATUS 0x40 -#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 -#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c deleted file mode 100644 index a9aed06..0000000 --- a/arch/arm/mach-stmp37xx/stmp37xx.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Freescale STMP37XX platform support - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include "stmp37xx.h" - -/* - * IRQ handling - */ -static void stmp37xx_ack_irq(struct irq_data *d) -{ - /* Disable IRQ */ - stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); - - /* ACK current interrupt */ - __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - -static void stmp37xx_mask_irq(struct irq_data *d) -{ - /* IRQ disable */ - stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); -} - -static void stmp37xx_unmask_irq(struct irq_data *d) -{ - /* IRQ enable */ - stmp3xxx_setl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); -} - -static struct irq_chip stmp37xx_chip = { - .irq_ack = stmp37xx_ack_irq, - .irq_mask = stmp37xx_mask_irq, - .irq_unmask = stmp37xx_unmask_irq, -}; - -void __init stmp37xx_init_irq(void) -{ - stmp3xxx_init_irq(&stmp37xx_chip); -} - -/* - * DMA interrupt handling - */ -void stmp3xxx_arch_dma_enable_interrupt(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)), - REGS_APBH_BASE + HW_APBH_CTRL1); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)), - REGS_APBX_BASE + HW_APBX_CTRL1); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); - -void stmp3xxx_arch_dma_clear_interrupt(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), - REGS_APBH_BASE + HW_APBH_CTRL1); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), - REGS_APBX_BASE + HW_APBX_CTRL1); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); - -int stmp3xxx_arch_dma_is_interrupt(int channel) -{ - int r = 0; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - - case STMP3XXX_BUS_APBX: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); - -void stmp3xxx_arch_dma_reset_channel(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - /* Reset channel and wait for it to complete */ - stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL, - REGS_APBH_BASE + HW_APBH_CTRL0); - while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) & - (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) - cpu_relax(); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL, - REGS_APBX_BASE + HW_APBX_CTRL0); - while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) & - (chbit << BP_APBX_CTRL0_RESET_CHANNEL)) - cpu_relax(); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); - -void stmp3xxx_arch_dma_freeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze); - -void stmp3xxx_arch_dma_unfreeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze); - -/* - * The registers are all very closely mapped, so we might as well map them all - * with a single mapping - * - * Logical Physical - * f0000000 80000000 On-chip registers - * f1000000 00000000 32k on-chip SRAM - */ -static struct map_desc stmp37xx_io_desc[] __initdata = { - { - .virtual = (u32)STMP3XXX_REGS_BASE, - .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE), - .length = SZ_1M, - .type = MT_DEVICE - }, - { - .virtual = (u32)STMP3XXX_OCRAM_BASE, - .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE), - .length = STMP3XXX_OCRAM_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init stmp37xx_map_io(void) -{ - iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc)); -} diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h deleted file mode 100644 index 0b75fb7..0000000 --- a/arch/arm/mach-stmp37xx/stmp37xx.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X internal functions and data declarations - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __MACH_STMP37XX_H -#define __MACH_STMP37XX_H - -void stmp37xx_map_io(void); -void stmp37xx_init_irq(void); - -#endif /* __MACH_STMP37XX_H */ diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c deleted file mode 100644 index 311d855..0000000 --- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Freescale STMP37XX development board support - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include "stmp37xx.h" - -/* - * List of STMP37xx development board specific devices - */ -static struct platform_device *stmp37xx_devb_devices[] = { - &stmp3xxx_dbguart, - &stmp3xxx_appuart, -}; - -static struct pin_desc dbguart_pins_0[] = { - { PINID_PWM0, PIN_FUN3, }, - { PINID_PWM1, PIN_FUN3, }, -}; - -struct pin_desc appuart_pins_0[] = { - { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -}; - -static struct pin_group appuart_pins[] = { - [0] = { - .pins = appuart_pins_0, - .nr_pins = ARRAY_SIZE(appuart_pins_0), - }, - /* 37xx has the only app uart */ -}; - -static struct pin_group dbguart_pins[] = { - [0] = { - .pins = dbguart_pins_0, - .nr_pins = ARRAY_SIZE(dbguart_pins_0), - }, -}; - -static int dbguart_pins_control(int id, int request) -{ - int r = 0; - - if (request) - r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart"); - else - stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart"); - return r; -} - - -static void __init stmp37xx_devb_init(void) -{ - stmp3xxx_pinmux_init(NR_REAL_IRQS); - - /* Init STMP3xxx platform */ - stmp3xxx_init(); - - stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; - stmp3xxx_appuart.dev.platform_data = appuart_pins; - - /* Add STMP37xx development board devices */ - platform_add_devices(stmp37xx_devb_devices, - ARRAY_SIZE(stmp37xx_devb_devices)); -} - -MACHINE_START(STMP37XX, "STMP37XX") - .boot_params = 0x40000100, - .map_io = stmp37xx_map_io, - .init_irq = stmp37xx_init_irq, - .timer = &stmp3xxx_timer, - .init_machine = stmp37xx_devb_init, -MACHINE_END diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig index 2cf37c3..dcdbe32 100644 --- a/arch/arm/plat-stmp3xxx/Kconfig +++ b/arch/arm/plat-stmp3xxx/Kconfig @@ -5,12 +5,6 @@ menu "Freescale STMP3xxx implementations" choice prompt "Select STMP3xxx chip family" -config ARCH_STMP37XX - bool "Freescale SMTP37xx" - select CPU_ARM926T - ---help--- - STMP37xx refers to 3700 through 3769 chips - config ARCH_STMP378X bool "Freescale STMP378x" select CPU_ARM926T @@ -22,10 +16,6 @@ endchoice choice prompt "Select STMP3xxx board type" -config MACH_STMP37XX - depends on ARCH_STMP37XX - bool "Freescale STMP37xx development board" - config MACH_STMP378X depends on ARCH_STMP378X bool "Freescale STMP378x development board" -- cgit v0.10.2 From f295dc6874bf271253f70cb75a483d4a23911117 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 29 Apr 2011 15:06:42 +0200 Subject: ARM: mach-stmp378x: remove mach This mach has not seen any updates since the initial inclusion besides generic cleanup. Furthermore: - The i.MX23 covered in mach-mxs is just a renamed version of the STMP378x. - mach-stmp378x has a lot of reinvented interfaces, leaking all sorts of mach-related includes into the drivers. One example is the dmaengine which does not use the linux dmaengine-API but some privately exported symbols. So drivers cannot be reused. mach-mxs does it better. - There is only one board defined (which I couldn't find any trace of despite being a development board). It has been converted to mach-mxs in a previous patch. Since the only user of this mach was converted, it means that mach-stmp378x can go. Signed-off-by: Wolfram Sang Acked-by: Shawn Guo Signed-off-by: Russell King diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 23ecbda..ca473b1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -185,7 +185,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos4 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile -machine-$(CONFIG_ARCH_STMP378X) := stmp378x machine-$(CONFIG_ARCH_TCC8K) := tcc8k machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_U300) := u300 diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig deleted file mode 100644 index 1079c2b..0000000 --- a/arch/arm/configs/stmp378x_defconfig +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-default" -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_STMP3XXX=y -CONFIG_ARCH_STMP378X=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NET_SCHED=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -CONFIG_MTD=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_GLUEBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=4 -CONFIG_BLK_DEV_RAM_SIZE=6144 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_INPUT_POLLDEV=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=m -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_SELFTEST=y -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_SLAB=y -CONFIG_DEBUG_SLAB_LEAK=y -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_PROVE_LOCKING=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_KOBJECT=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_BOOT_TRACER=y -CONFIG_STACK_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC16=y diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile deleted file mode 100644 index d156f76..0000000 --- a/arch/arm/mach-stmp378x/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o -obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot deleted file mode 100644 index 1568ad4..0000000 --- a/arch/arm/mach-stmp378x/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x40008000 -params_phys-y := 0x40000100 -initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S deleted file mode 100644 index 731a922..0000000 --- a/arch/arm/mach-stmp378x/include/mach/entry-macro.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Low-level IRQ helper macros for Freescale STMP378X - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #0xf0000000 @ vm address of IRQ controller - ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT - cmp \irqnr, #0x7f - moveqs \irqnr, #0 @ Zero flag set for no IRQ - - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h deleted file mode 100644 index cc59673..0000000 --- a/arch/arm/mach-stmp378x/include/mach/irqs.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Freescale STMP378X interrupts - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#define IRQ_DEBUG_UART 0 -#define IRQ_COMMS_RX 1 -#define IRQ_COMMS_TX 1 -#define IRQ_SSP2_ERROR 2 -#define IRQ_VDD5V 3 -#define IRQ_HEADPHONE_SHORT 4 -#define IRQ_DAC_DMA 5 -#define IRQ_DAC_ERROR 6 -#define IRQ_ADC_DMA 7 -#define IRQ_ADC_ERROR 8 -#define IRQ_SPDIF_DMA 9 -#define IRQ_SAIF2_DMA 9 -#define IRQ_SPDIF_ERROR 10 -#define IRQ_SAIF1_IRQ 10 -#define IRQ_SAIF2_IRQ 10 -#define IRQ_USB_CTRL 11 -#define IRQ_USB_WAKEUP 12 -#define IRQ_GPMI_DMA 13 -#define IRQ_SSP1_DMA 14 -#define IRQ_SSP_ERROR 15 -#define IRQ_GPIO0 16 -#define IRQ_GPIO1 17 -#define IRQ_GPIO2 18 -#define IRQ_SAIF1_DMA 19 -#define IRQ_SSP2_DMA 20 -#define IRQ_ECC8_IRQ 21 -#define IRQ_RTC_ALARM 22 -#define IRQ_UARTAPP_TX_DMA 23 -#define IRQ_UARTAPP_INTERNAL 24 -#define IRQ_UARTAPP_RX_DMA 25 -#define IRQ_I2C_DMA 26 -#define IRQ_I2C_ERROR 27 -#define IRQ_TIMER0 28 -#define IRQ_TIMER1 29 -#define IRQ_TIMER2 30 -#define IRQ_TIMER3 31 -#define IRQ_BATT_BRNOUT 32 -#define IRQ_VDDD_BRNOUT 33 -#define IRQ_VDDIO_BRNOUT 34 -#define IRQ_VDD18_BRNOUT 35 -#define IRQ_TOUCH_DETECT 36 -#define IRQ_LRADC_CH0 37 -#define IRQ_LRADC_CH1 38 -#define IRQ_LRADC_CH2 39 -#define IRQ_LRADC_CH3 40 -#define IRQ_LRADC_CH4 41 -#define IRQ_LRADC_CH5 42 -#define IRQ_LRADC_CH6 43 -#define IRQ_LRADC_CH7 44 -#define IRQ_LCDIF_DMA 45 -#define IRQ_LCDIF_ERROR 46 -#define IRQ_DIGCTL_DEBUG_TRAP 47 -#define IRQ_RTC_1MSEC 48 -#define IRQ_DRI_DMA 49 -#define IRQ_DRI_ATTENTION 50 -#define IRQ_GPMI_ATTENTION 51 -#define IRQ_IR 52 -#define IRQ_DCP_VMI 53 -#define IRQ_DCP 54 -#define IRQ_BCH 56 -#define IRQ_PXP 57 -#define IRQ_UARTAPP2_TX_DMA 58 -#define IRQ_UARTAPP2_INTERNAL 59 -#define IRQ_UARTAPP2_RX_DMA 60 -#define IRQ_VDAC_DETECT 61 -#define IRQ_VDD5V_DROOP 64 -#define IRQ_DCDC4P2_BO 65 - - -#define NR_REAL_IRQS 128 -#define NR_IRQS (NR_REAL_IRQS + 32 * 3) - -/* All interrupts are FIQ capable */ -#define FIQ_START IRQ_DEBUG_UART - -/* Hard disk IRQ is a GPMI attention IRQ */ -#define IRQ_HARDDISK IRQ_GPMI_ATTENTION diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h deleted file mode 100644 index 93f952d..0000000 --- a/arch/arm/mach-stmp378x/include/mach/pins.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Freescale STMP378X SoC pin multiplexing - * - * Author: Vladislav Buzov - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_PINS_H -#define __ASM_ARCH_PINS_H - -/* - * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware - * interface this pin belongs to. - */ - -/* Bank 0 */ -#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) -#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) -#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) -#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) -#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) -#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) -#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) -#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) -#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) -#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) -#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) -#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) -#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) -#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) -#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) -#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) -#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16) -#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17) -#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18) -#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) -#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20) -#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21) -#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22) -#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23) -#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) -#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) -#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26) -#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27) -#define PINID_AUART1_RX STMP3XXX_PINID(0, 28) -#define PINID_AUART1_TX STMP3XXX_PINID(0, 29) -#define PINID_I2C_SCL STMP3XXX_PINID(0, 30) -#define PINID_I2C_SDA STMP3XXX_PINID(0, 31) - -/* Bank 1 */ -#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) -#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) -#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) -#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) -#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) -#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) -#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) -#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) -#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) -#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) -#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) -#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) -#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) -#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) -#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) -#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) -#define PINID_LCD_D16 STMP3XXX_PINID(1, 16) -#define PINID_LCD_D17 STMP3XXX_PINID(1, 17) -#define PINID_LCD_RESET STMP3XXX_PINID(1, 18) -#define PINID_LCD_RS STMP3XXX_PINID(1, 19) -#define PINID_LCD_WR STMP3XXX_PINID(1, 20) -#define PINID_LCD_CS STMP3XXX_PINID(1, 21) -#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22) -#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23) -#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24) -#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25) -#define PINID_PWM0 STMP3XXX_PINID(1, 26) -#define PINID_PWM1 STMP3XXX_PINID(1, 27) -#define PINID_PWM2 STMP3XXX_PINID(1, 28) -#define PINID_PWM3 STMP3XXX_PINID(1, 29) -#define PINID_PWM4 STMP3XXX_PINID(1, 30) - -/* Bank 2 */ -#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0) -#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1) -#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2) -#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3) -#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4) -#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5) -#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6) -#define PINID_ROTARYA STMP3XXX_PINID(2, 7) -#define PINID_ROTARYB STMP3XXX_PINID(2, 8) -#define PINID_EMI_A00 STMP3XXX_PINID(2, 9) -#define PINID_EMI_A01 STMP3XXX_PINID(2, 10) -#define PINID_EMI_A02 STMP3XXX_PINID(2, 11) -#define PINID_EMI_A03 STMP3XXX_PINID(2, 12) -#define PINID_EMI_A04 STMP3XXX_PINID(2, 13) -#define PINID_EMI_A05 STMP3XXX_PINID(2, 14) -#define PINID_EMI_A06 STMP3XXX_PINID(2, 15) -#define PINID_EMI_A07 STMP3XXX_PINID(2, 16) -#define PINID_EMI_A08 STMP3XXX_PINID(2, 17) -#define PINID_EMI_A09 STMP3XXX_PINID(2, 18) -#define PINID_EMI_A10 STMP3XXX_PINID(2, 19) -#define PINID_EMI_A11 STMP3XXX_PINID(2, 20) -#define PINID_EMI_A12 STMP3XXX_PINID(2, 21) -#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22) -#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23) -#define PINID_EMI_CASN STMP3XXX_PINID(2, 24) -#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25) -#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26) -#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27) -#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28) -#define PINID_EMI_CKE STMP3XXX_PINID(2, 29) -#define PINID_EMI_RASN STMP3XXX_PINID(2, 30) -#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) - -/* Bank 3 */ -#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) -#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) -#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) -#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) -#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) -#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) -#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) -#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) -#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) -#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) -#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) -#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) -#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) -#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) -#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) -#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) -#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16) -#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17) -#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18) -#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19) -#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) -#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) - -#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h deleted file mode 100644 index dbcf85b..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * stmp378x: APBH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBH -#define _MACH_REGS_APBH - -#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) -#define REGS_APBH_PHYS 0x80004000 -#define REGS_APBH_SIZE 0x2000 - -#define HW_APBH_CTRL0 0x0 -#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBH_CTRL0_RESET_CHANNEL 16 -#define BM_APBH_CTRL0_CLKGATE 0x40000000 -#define BM_APBH_CTRL0_SFTRST 0x80000000 - -#define HW_APBH_CTRL1 0x10 -#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 -#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 - -#define HW_APBH_CTRL2 0x20 - -#define HW_APBH_DEVSEL 0x30 - -#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBH_CHn_NXTCMDAR 0x50 - -#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBH_CHn_CMD_COMMAND 0x00000003 -#define BP_APBH_CHn_CMD_COMMAND 0 -#define BM_APBH_CHn_CMD_CHAIN 0x00000004 -#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 -#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 -#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBH_CHn_CMD_CMDWORDS 12 -#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBH_CHn_CMD_XFER_COUNT 16 - -#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBH_CHn_SEMA 0x80 -#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBH_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h deleted file mode 100644 index 3b934a4..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * stmp378x: APBX register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBX -#define _MACH_REGS_APBX - -#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) -#define REGS_APBX_PHYS 0x80024000 -#define REGS_APBX_SIZE 0x2000 - -#define HW_APBX_CTRL0 0x0 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 -#define BM_APBX_CTRL0_SFTRST 0x80000000 - -#define HW_APBX_CTRL1 0x10 - -#define HW_APBX_CTRL2 0x20 - -#define HW_APBX_CHANNEL_CTRL 0x30 -#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 -#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 - -#define HW_APBX_DEVSEL 0x40 - -#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70) -#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70) -#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70) -#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70) -#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70) -#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70) -#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70) -#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70) -#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70) -#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70) -#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70) -#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70) -#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70) -#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70) -#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70) -#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70) - -#define HW_APBX_CHn_NXTCMDAR 0x110 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBX_CHn_CMD_XFER_COUNT 16 - -#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70) -#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70) -#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70) -#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70) -#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70) -#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70) -#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70) -#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70) -#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70) -#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70) -#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70) -#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70) -#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70) -#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70) -#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70) -#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70) - -#define HW_APBX_CHn_BAR 0x130 - -#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70) -#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70) -#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70) -#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70) -#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70) -#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70) -#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70) -#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70) -#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70) -#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70) -#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70) -#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70) -#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70) -#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70) -#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70) -#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70) - -#define HW_APBX_CHn_SEMA 0x140 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBX_CHn_SEMA_PHORE 16 - -#endif - diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h deleted file mode 100644 index 641ac61..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp378x: AUDIOIN register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) -#define REGS_AUDIOIN_PHYS 0x8004C000 -#define REGS_AUDIOIN_SIZE 0x2000 - -#define HW_AUDIOIN_CTRL 0x0 -#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define BP_AUDIOIN_CTRL_RUN 0 -#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 -#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOIN_STAT 0x10 - -#define HW_AUDIOIN_ADCSRR 0x20 - -#define HW_AUDIOIN_ADCVOLUME 0x30 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF -#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 -#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 - -#define HW_AUDIOIN_ADCDEBUG 0x40 - -#define HW_AUDIOIN_ADCVOL 0x50 -#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F -#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 -#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 -#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 -#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 -#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 -#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 -#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 -#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 - -#define HW_AUDIOIN_MICLINE 0x60 - -#define HW_AUDIOIN_ANACLKCTRL 0x70 -#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOIN_DATA 0x80 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h deleted file mode 100644 index f533e23..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * stmp378x: AUDIOOUT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) -#define REGS_AUDIOOUT_PHYS 0x80048000 -#define REGS_AUDIOOUT_SIZE 0x2000 - -#define HW_AUDIOOUT_CTRL 0x0 -#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define BP_AUDIOOUT_CTRL_RUN 0 -#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 -#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOOUT_STAT 0x10 - -#define HW_AUDIOOUT_DACSRR 0x20 -#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF -#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 -#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 -#define BP_AUDIOOUT_DACSRR_SRC_INT 16 -#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 -#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 -#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 -#define BP_AUDIOOUT_DACSRR_BASEMULT 28 - -#define HW_AUDIOOUT_DACVOLUME 0x30 -#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 -#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 -#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_DACDEBUG 0x40 - -#define HW_AUDIOOUT_HPVOL 0x50 -#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 -#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 - -#define HW_AUDIOOUT_PWRDN 0x70 -#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 -#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 -#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 -#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 -#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 -#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000 - -#define HW_AUDIOOUT_REFCTRL 0x80 -#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 -#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 -#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 -#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 -#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 -#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 -#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 -#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 -#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 -#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 -#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 -#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 -#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 - -#define HW_AUDIOOUT_ANACTRL 0x90 -#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 -#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 - -#define HW_AUDIOOUT_TEST 0xA0 -#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 -#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 - -#define HW_AUDIOOUT_BISTCTRL 0xB0 - -#define HW_AUDIOOUT_BISTSTAT0 0xC0 - -#define HW_AUDIOOUT_BISTSTAT1 0xD0 - -#define HW_AUDIOOUT_ANACLKCTRL 0xE0 -#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOOUT_DATA 0xF0 - -#define HW_AUDIOOUT_SPEAKERCTRL 0x100 -#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000 - -#define HW_AUDIOOUT_VERSION 0x200 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h deleted file mode 100644 index 532d246..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * stmp378x: BCH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000) -#define REGS_BCH_PHYS 0x8000A000 -#define REGS_BCH_SIZE 0x2000 - -#define HW_BCH_CTRL 0x0 -#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_BCH_CTRL_COMPLETE_IRQ 0 -#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 - -#define HW_BCH_STATUS0 0x10 -#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_BCH_STATUS0_CORRECTED 0x00000008 -#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 -#define BP_BCH_STATUS0_STATUS_BLK0 8 -#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_BCH_STATUS0_COMPLETED_CE 16 - -#define HW_BCH_LAYOUTSELECT 0x70 - -#define HW_BCH_FLASH0LAYOUT0 0x80 -#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 -#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 -#define BP_BCH_FLASH0LAYOUT0_ECC0 12 -#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 -#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 -#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 -#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 -#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 -#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 -#define BP_BCH_FLASH0LAYOUT1_ECCN 12 -#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 -#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 - -#define HW_BCH_BLOCKNAME 0x150 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h deleted file mode 100644 index 7c546af..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * stmp378x: CLKCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_CLKCTRL -#define _MACH_REGS_CLKCTRL - -#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) -#define REGS_CLKCTRL_PHYS 0x80040000 -#define REGS_CLKCTRL_SIZE 0x2000 - -#define HW_CLKCTRL_PLLCTRL0 0x0 -#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 - -#define HW_CLKCTRL_CPU 0x20 -#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F -#define BP_CLKCTRL_CPU_DIV_CPU 0 - -#define HW_CLKCTRL_HBUS 0x30 -#define BM_CLKCTRL_HBUS_DIV 0x0000001F -#define BP_CLKCTRL_HBUS_DIV 0 -#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 - -#define HW_CLKCTRL_XBUS 0x40 - -#define HW_CLKCTRL_XTAL 0x50 -#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 - -#define HW_CLKCTRL_PIX 0x60 -#define BM_CLKCTRL_PIX_DIV 0x00000FFF -#define BP_CLKCTRL_PIX_DIV 0 -#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 - -#define HW_CLKCTRL_SSP 0x70 - -#define HW_CLKCTRL_GPMI 0x80 - -#define HW_CLKCTRL_SPDIF 0x90 - -#define HW_CLKCTRL_EMI 0xA0 -#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F -#define BP_CLKCTRL_EMI_DIV_EMI 0 -#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 -#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 -#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 -#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 - -#define HW_CLKCTRL_IR 0xB0 - -#define HW_CLKCTRL_SAIF 0xC0 - -#define HW_CLKCTRL_TV 0xD0 - -#define HW_CLKCTRL_ETM 0xE0 - -#define HW_CLKCTRL_FRAC 0xF0 -#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 -#define BP_CLKCTRL_FRAC_EMIFRAC 8 -#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 -#define BP_CLKCTRL_FRAC_PIXFRAC 16 -#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 - -#define HW_CLKCTRL_FRAC1 0x100 - -#define HW_CLKCTRL_CLKSEQ 0x110 -#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 - -#define HW_CLKCTRL_RESET 0x120 -#define BM_CLKCTRL_RESET_DIG 0x00000001 -#define BP_CLKCTRL_RESET_DIG 0 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h deleted file mode 100644 index fdedd00..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * stmp378x: DCP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000) -#define REGS_DCP_PHYS 0x80028000 -#define REGS_DCP_SIZE 0x2000 - -#define HW_DCP_CTRL 0x0 -#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF -#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 -#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000 -#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000 -#define BM_DCP_CTRL_CLKGATE 0x40000000 -#define BM_DCP_CTRL_SFTRST 0x80000000 - -#define HW_DCP_STAT 0x10 -#define BM_DCP_STAT_IRQ 0x0000000F -#define BP_DCP_STAT_IRQ 0 - -#define HW_DCP_CHANNELCTRL 0x20 -#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF -#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 - -#define HW_DCP_CONTEXT 0x50 -#define BM_DCP_PACKET1_INTERRUPT 0x00000001 -#define BP_DCP_PACKET1_INTERRUPT 0 -#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002 -#define BM_DCP_PACKET1_CHAIN 0x00000004 -#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008 -#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020 -#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040 -#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100 -#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200 -#define BM_DCP_PACKET1_OTP_KEY 0x00000400 -#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800 -#define BM_DCP_PACKET1_HASH_INIT 0x00001000 -#define BM_DCP_PACKET1_HASH_TERM 0x00002000 -#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F -#define BP_DCP_PACKET2_CIPHER_SELECT 0 -#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0 -#define BP_DCP_PACKET2_CIPHER_MODE 4 -#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00 -#define BP_DCP_PACKET2_KEY_SELECT 8 -#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000 -#define BP_DCP_PACKET2_HASH_SELECT 16 -#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000 -#define BP_DCP_PACKET2_CIPHER_CFG 24 - -#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40) -#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40) -#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40) -#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40) - -#define HW_DCP_CHnCMDPTR 0x100 - -#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40) -#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40) -#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40) -#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40) - -#define HW_DCP_CHnSEMA 0x110 -#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF -#define BP_DCP_CHnSEMA_INCREMENT 0 - -#define HW_DCP_CH0STAT (0x120 + 0 * 0x40) -#define HW_DCP_CH1STAT (0x120 + 1 * 0x40) -#define HW_DCP_CH2STAT (0x120 + 2 * 0x40) -#define HW_DCP_CH3STAT (0x120 + 3 * 0x40) - -#define HW_DCP_CHnSTAT 0x120 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h deleted file mode 100644 index 5293005..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * stmp378x: DIGCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000) -#define REGS_DIGCTL_PHYS 0x8001C000 -#define REGS_DIGCTL_SIZE 0x2000 - -#define HW_DIGCTL_CTRL 0x0 -#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 - -#define HW_DIGCTL_ARMCACHE 0x2B0 -#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 -#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 -#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 -#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 -#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 -#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 -#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 -#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 -#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 -#define BP_DIGCTL_ARMCACHE_VALID_SS 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h deleted file mode 100644 index 0285143..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * stmp378x: DRAM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000) -#define REGS_DRAM_PHYS 0x800E0000 -#define REGS_DRAM_SIZE 0x2000 - -#define HW_DRAM_CTL06 0x18 - -#define HW_DRAM_CTL08 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h deleted file mode 100644 index da25f7e..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * stmp378x: DRI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000) -#define REGS_DRI_PHYS 0x80074000 -#define REGS_DRI_SIZE 0x2000 - -#define HW_DRI_CTRL 0x0 -#define BM_DRI_CTRL_RUN 0x00000001 -#define BP_DRI_CTRL_RUN 0 -#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004 -#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008 -#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400 -#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800 -#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000 -#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000 -#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000 -#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 -#define BM_DRI_CTRL_CLKGATE 0x40000000 -#define BM_DRI_CTRL_SFTRST 0x80000000 - -#define HW_DRI_TIMING 0x10 -#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF -#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 -#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000 -#define BP_DRI_TIMING_PILOT_REP_RATE 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h deleted file mode 100644 index cc353be..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * stmp378x: ECC8 register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) -#define REGS_ECC8_PHYS 0x80008000 -#define REGS_ECC8_SIZE 0x2000 - -#define HW_ECC8_CTRL 0x0 -#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_ECC8_CTRL_COMPLETE_IRQ 0 -#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 -#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 - -#define HW_ECC8_STATUS0 0x10 -#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_ECC8_STATUS0_CORRECTED 0x00000008 -#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 -#define BP_ECC8_STATUS0_STATUS_AUX 8 -#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_ECC8_STATUS0_COMPLETED_CE 16 - -#define HW_ECC8_STATUS1 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h deleted file mode 100644 index 98773fc..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * stmp378x: EMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000) -#define REGS_EMI_PHYS 0x80020000 -#define REGS_EMI_SIZE 0x2000 - -#define HW_EMI_STAT 0x10 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h deleted file mode 100644 index 2cc8bbe..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * stmp378x: GPMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000) -#define REGS_GPMI_PHYS 0x8000C000 -#define REGS_GPMI_SIZE 0x2000 - -#define HW_GPMI_CTRL0 0x0 -#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_GPMI_CTRL0_XFER_COUNT 0 -#define BM_GPMI_CTRL0_CS 0x00300000 -#define BP_GPMI_CTRL0_CS 20 -#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 -#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 -#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 -#define BP_GPMI_CTRL0_ADDRESS 17 -#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 -#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 -#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 -#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 -#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 -#define BP_GPMI_CTRL0_COMMAND_MODE 24 -#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 -#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 -#define BM_GPMI_CTRL0_RUN 0x20000000 -#define BM_GPMI_CTRL0_CLKGATE 0x40000000 -#define BM_GPMI_CTRL0_SFTRST 0x80000000 -#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF -#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 -#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 -#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 -#define BP_GPMI_ECCCTRL_ECC_CMD 13 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3 - -#define HW_GPMI_CTRL1 0x60 -#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 -#define BP_GPMI_CTRL1_GPMI_MODE 0 -#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 -#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 -#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 -#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 -#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 -#define BP_GPMI_CTRL1_RDN_DELAY 12 -#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 - -#define HW_GPMI_TIMING0 0x70 -#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF -#define BP_GPMI_TIMING0_DATA_SETUP 0 -#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 -#define BP_GPMI_TIMING0_DATA_HOLD 8 -#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 -#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 - -#define HW_GPMI_TIMING1 0x80 -#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 -#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h deleted file mode 100644 index 13a234c..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * stmp378x: I2C register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) -#define REGS_I2C_PHYS 0x80058000 -#define REGS_I2C_SIZE 0x2000 - -#define HW_I2C_CTRL0 0x0 -#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_I2C_CTRL0_XFER_COUNT 0 -#define BM_I2C_CTRL0_DIRECTION 0x00010000 -#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 -#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 -#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 -#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 -#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 -#define BM_I2C_CTRL0_CLKGATE 0x40000000 -#define BM_I2C_CTRL0_SFTRST 0x80000000 - -#define HW_I2C_TIMING0 0x10 - -#define HW_I2C_TIMING1 0x20 - -#define HW_I2C_TIMING2 0x30 - -#define HW_I2C_CTRL1 0x40 -#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 -#define BP_I2C_CTRL1_SLAVE_IRQ 0 -#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 -#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 -#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 -#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 -#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 -#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 -#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 -#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 - -#define HW_I2C_VERSION 0x90 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h deleted file mode 100644 index f996e80..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * stmp378x: ICOLL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_ICOLL -#define _MACH_REGS_ICOLL - -#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) -#define REGS_ICOLL_PHYS 0x80000000 -#define REGS_ICOLL_SIZE 0x2000 - -#define HW_ICOLL_VECTOR 0x0 - -#define HW_ICOLL_LEVELACK 0x10 -#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F -#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 - -#define HW_ICOLL_CTRL 0x20 -#define BM_ICOLL_CTRL_CLKGATE 0x40000000 -#define BM_ICOLL_CTRL_SFTRST 0x80000000 - -#define HW_ICOLL_STAT 0x70 - -#define HW_ICOLL_INTERRUPTn 0x120 - -#define HW_ICOLL_INTERRUPTn 0x120 -#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h deleted file mode 100644 index a5b4ef1..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * stmp378x: IR register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000) -#define REGS_IR_PHYS 0x80078000 -#define REGS_IR_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h deleted file mode 100644 index 9cdbef4..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * stmp378x: LCDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) -#define REGS_LCDIF_PHYS 0x80030000 -#define REGS_LCDIF_SIZE 0x2000 - -#define HW_LCDIF_CTRL 0x0 -#define BM_LCDIF_CTRL_RUN 0x00000001 -#define BP_LCDIF_CTRL_RUN 0 -#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 -#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 -#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 -#define BP_LCDIF_CTRL_WORD_LENGTH 8 -#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 -#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 -#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 -#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 -#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 -#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 -#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 -#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 -#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 -#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 -#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 -#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 -#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 -#define BM_LCDIF_CTRL_CLKGATE 0x40000000 -#define BM_LCDIF_CTRL_SFTRST 0x80000000 - -#define HW_LCDIF_CTRL1 0x10 -#define BM_LCDIF_CTRL1_RESET 0x00000001 -#define BP_LCDIF_CTRL1_RESET 0 -#define BM_LCDIF_CTRL1_MODE86 0x00000002 -#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 -#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 -#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 -#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 -#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 -#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 -#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 -#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 - -#define HW_LCDIF_TRANSFER_COUNT 0x20 -#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF -#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 -#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 -#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 - -#define HW_LCDIF_CUR_BUF 0x30 - -#define HW_LCDIF_NEXT_BUF 0x40 - -#define HW_LCDIF_TIMING 0x60 - -#define HW_LCDIF_VDCTRL0 0x70 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF -#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 -#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 -#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 -#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 -#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 -#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 -#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 -#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 - -#define HW_LCDIF_VDCTRL1 0x80 -#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF -#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 - -#define HW_LCDIF_VDCTRL2 0x90 -#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF -#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 -#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 -#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 - -#define HW_LCDIF_VDCTRL3 0xA0 -#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF -#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 -#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 -#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 - -#define HW_LCDIF_VDCTRL4 0xB0 -#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF -#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 - -#define HW_LCDIF_DVICTRL0 0xC0 -#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF -#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 -#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 -#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 -#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 -#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 - -#define HW_LCDIF_DVICTRL1 0xD0 -#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF -#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 -#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 -#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 -#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 - -#define HW_LCDIF_DVICTRL2 0xE0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 -#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 -#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 - -#define HW_LCDIF_DVICTRL3 0xF0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 -#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 - -#define HW_LCDIF_DVICTRL4 0x100 -#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF -#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 -#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 -#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 -#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 -#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 -#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 -#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 - -#define HW_LCDIF_CSC_COEFF0 0x110 -#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 -#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 -#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 -#define BP_LCDIF_CSC_COEFF0_C0 16 - -#define HW_LCDIF_CSC_COEFF1 0x120 -#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF -#define BP_LCDIF_CSC_COEFF1_C1 0 -#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 -#define BP_LCDIF_CSC_COEFF1_C2 16 - -#define HW_LCDIF_CSC_COEFF2 0x130 -#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF -#define BP_LCDIF_CSC_COEFF2_C3 0 -#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 -#define BP_LCDIF_CSC_COEFF2_C4 16 - -#define HW_LCDIF_CSC_COEFF3 0x140 -#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF -#define BP_LCDIF_CSC_COEFF3_C5 0 -#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 -#define BP_LCDIF_CSC_COEFF3_C6 16 - -#define HW_LCDIF_CSC_COEFF4 0x150 -#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF -#define BP_LCDIF_CSC_COEFF4_C7 0 -#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 -#define BP_LCDIF_CSC_COEFF4_C8 16 - -#define HW_LCDIF_CSC_OFFSET 0x160 -#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF -#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 -#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 -#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 - -#define HW_LCDIF_CSC_LIMIT 0x170 -#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF -#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 -#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 -#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 -#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 -#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 - -#define HW_LCDIF_STAT 0x1D0 -#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h deleted file mode 100644 index cb8cb06..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * stmp378x: LRADC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) -#define REGS_LRADC_PHYS 0x80050000 -#define REGS_LRADC_SIZE 0x2000 - -#define HW_LRADC_CTRL0 0x0 -#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF -#define BP_LRADC_CTRL0_SCHEDULE 0 -#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 -#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 -#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 -#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 -#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 -#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 -#define BM_LRADC_CTRL0_CLKGATE 0x40000000 -#define BM_LRADC_CTRL0_SFTRST 0x80000000 - -#define HW_LRADC_CTRL1 0x10 -#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 -#define BP_LRADC_CTRL1_LRADC0_IRQ 0 -#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 -#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 -#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 -#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 - -#define HW_LRADC_CTRL2 0x20 -#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 -#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 -#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 -#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 -#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 -#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 - -#define HW_LRADC_CTRL3 0x30 -#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 -#define BP_LRADC_CTRL3_CYCLE_TIME 8 - -#define HW_LRADC_STATUS 0x40 -#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 -#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 - -#define HW_LRADC_CH0 (0x50 + 0 * 0x10) -#define HW_LRADC_CH1 (0x50 + 1 * 0x10) -#define HW_LRADC_CH2 (0x50 + 2 * 0x10) -#define HW_LRADC_CH3 (0x50 + 3 * 0x10) -#define HW_LRADC_CH4 (0x50 + 4 * 0x10) -#define HW_LRADC_CH5 (0x50 + 5 * 0x10) -#define HW_LRADC_CH6 (0x50 + 6 * 0x10) -#define HW_LRADC_CH7 (0x50 + 7 * 0x10) - -#define HW_LRADC_CHn 0x50 -#define BM_LRADC_CHn_VALUE 0x0003FFFF -#define BP_LRADC_CHn_VALUE 0 -#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 -#define BP_LRADC_CHn_NUM_SAMPLES 24 -#define BM_LRADC_CHn_ACCUMULATE 0x20000000 - -#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10) -#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10) -#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10) -#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10) - -#define HW_LRADC_DELAYn 0xD0 -#define BM_LRADC_DELAYn_DELAY 0x000007FF -#define BP_LRADC_DELAYn_DELAY 0 -#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 -#define BP_LRADC_DELAYn_LOOP_COUNT 11 -#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 -#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 -#define BM_LRADC_DELAYn_KICK 0x00100000 -#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 -#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 - -#define HW_LRADC_CTRL4 0x140 -#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 -#define BP_LRADC_CTRL4_LRADC6SELECT 24 -#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 -#define BP_LRADC_CTRL4_LRADC7SELECT 28 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h deleted file mode 100644 index f0af64d..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * stmp378x: OCOTP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000) -#define REGS_OCOTP_PHYS 0x8002C000 -#define REGS_OCOTP_SIZE 0x2000 - -#define HW_OCOTP_CTRL 0x0 -#define BM_OCOTP_CTRL_BUSY 0x00000100 -#define BM_OCOTP_CTRL_ERROR 0x00000200 -#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 -#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 -#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 -#define BP_OCOTP_CTRL_WR_UNLOCK 16 - -#define HW_OCOTP_DATA 0x10 - -#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10) -#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10) -#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10) -#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10) - -#define HW_OCOTP_CUSTn 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h deleted file mode 100644 index 50d90ea..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * stmp378x: PINCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) -#define REGS_PINCTRL_PHYS 0x80018000 -#define REGS_PINCTRL_SIZE 0x2000 - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x400 -#define HW_PINCTRL_PULL1 0x410 -#define HW_PINCTRL_PULL2 0x420 -#define HW_PINCTRL_PULL3 0x430 - -#define HW_PINCTRL_DOUT0 0x500 -#define HW_PINCTRL_DOUT1 0x510 -#define HW_PINCTRL_DOUT2 0x520 - -#define HW_PINCTRL_DIN0 0x600 -#define HW_PINCTRL_DIN1 0x610 -#define HW_PINCTRL_DIN2 0x620 - -#define HW_PINCTRL_DOE0 0x700 -#define HW_PINCTRL_DOE1 0x710 -#define HW_PINCTRL_DOE2 0x720 - -#define HW_PINCTRL_PIN2IRQ0 0x800 -#define HW_PINCTRL_PIN2IRQ1 0x810 -#define HW_PINCTRL_PIN2IRQ2 0x820 - -#define HW_PINCTRL_IRQEN0 0x900 -#define HW_PINCTRL_IRQEN1 0x910 -#define HW_PINCTRL_IRQEN2 0x920 - -#define HW_PINCTRL_IRQLEVEL0 0xA00 -#define HW_PINCTRL_IRQLEVEL1 0xA10 -#define HW_PINCTRL_IRQLEVEL2 0xA20 - -#define HW_PINCTRL_IRQPOL0 0xB00 -#define HW_PINCTRL_IRQPOL1 0xB10 -#define HW_PINCTRL_IRQPOL2 0xB20 - -#define HW_PINCTRL_IRQSTAT0 0xC00 -#define HW_PINCTRL_IRQSTAT1 0xC10 -#define HW_PINCTRL_IRQSTAT2 0xC20 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h deleted file mode 100644 index e454c83..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-power.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp378x: POWER register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_POWER -#define _MACH_REGS_POWER - -#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) -#define REGS_POWER_PHYS 0x80044000 -#define REGS_POWER_SIZE 0x2000 - -#define HW_POWER_CTRL 0x0 -#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 -#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 -#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 -#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 -#define BM_POWER_CTRL_CLKGATE 0x40000000 - -#define HW_POWER_5VCTRL 0x10 -#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 - -#define HW_POWER_MINPWR 0x20 - -#define HW_POWER_CHARGE 0x30 - -#define HW_POWER_VDDDCTRL 0x40 - -#define HW_POWER_VDDACTRL 0x50 - -#define HW_POWER_VDDIOCTRL 0x60 -#define BM_POWER_VDDIOCTRL_TRG 0x0000001F -#define BP_POWER_VDDIOCTRL_TRG 0 - -#define HW_POWER_STS 0xC0 -#define BM_POWER_STS_VBUSVALID 0x00000002 -#define BM_POWER_STS_BVALID 0x00000004 -#define BM_POWER_STS_AVALID 0x00000008 -#define BM_POWER_STS_DC_OK 0x00000200 - -#define HW_POWER_RESET 0x100 - -#define HW_POWER_DEBUG 0x110 -#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 -#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h deleted file mode 100644 index 0d0f9e5..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * stmp378x: PWM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) -#define REGS_PWM_PHYS 0x80064000 -#define REGS_PWM_SIZE 0x2000 - -#define HW_PWM_CTRL 0x0 -#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 -#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 - -#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20) -#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20) -#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20) -#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20) - -#define HW_PWM_ACTIVEn 0x10 -#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF -#define BP_PWM_ACTIVEn_ACTIVE 0 -#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 -#define BP_PWM_ACTIVEn_INACTIVE 16 - -#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20) -#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20) -#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20) -#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20) - -#define HW_PWM_PERIODn 0x20 -#define BM_PWM_PERIODn_PERIOD 0x0000FFFF -#define BP_PWM_PERIODn_PERIOD 0 -#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 -#define BP_PWM_PERIODn_ACTIVE_STATE 16 -#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 -#define BP_PWM_PERIODn_INACTIVE_STATE 18 -#define BM_PWM_PERIODn_CDIV 0x00700000 -#define BP_PWM_PERIODn_CDIV 20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h deleted file mode 100644 index 54d2978..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * stmp378x: PXP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000) -#define REGS_PXP_PHYS 0x8002A000 -#define REGS_PXP_SIZE 0x2000 - -#define HW_PXP_CTRL 0x0 -#define BM_PXP_CTRL_ENABLE 0x00000001 -#define BP_PXP_CTRL_ENABLE 0 -#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 -#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0 -#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 -#define BM_PXP_CTRL_ROTATE 0x00000300 -#define BP_PXP_CTRL_ROTATE 8 -#define BM_PXP_CTRL_HFLIP 0x00000400 -#define BM_PXP_CTRL_VFLIP 0x00000800 -#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 -#define BP_PXP_CTRL_S0_FORMAT 12 -#define BM_PXP_CTRL_SCALE 0x00040000 -#define BM_PXP_CTRL_CROP 0x00080000 - -#define HW_PXP_STAT 0x10 -#define BM_PXP_STAT_IRQ 0x00000001 -#define BP_PXP_STAT_IRQ 0 - -#define HW_PXP_RGBBUF 0x20 - -#define HW_PXP_RGBSIZE 0x40 -#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF -#define BP_PXP_RGBSIZE_HEIGHT 0 -#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000 -#define BP_PXP_RGBSIZE_WIDTH 12 - -#define HW_PXP_S0BUF 0x50 - -#define HW_PXP_S0UBUF 0x60 - -#define HW_PXP_S0VBUF 0x70 - -#define HW_PXP_S0PARAM 0x80 -#define BM_PXP_S0PARAM_HEIGHT 0x000000FF -#define BP_PXP_S0PARAM_HEIGHT 0 -#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 -#define BP_PXP_S0PARAM_WIDTH 8 -#define BM_PXP_S0PARAM_YBASE 0x00FF0000 -#define BP_PXP_S0PARAM_YBASE 16 -#define BM_PXP_S0PARAM_XBASE 0xFF000000 -#define BP_PXP_S0PARAM_XBASE 24 - -#define HW_PXP_S0BACKGROUND 0x90 - -#define HW_PXP_S0CROP 0xA0 -#define BM_PXP_S0CROP_HEIGHT 0x000000FF -#define BP_PXP_S0CROP_HEIGHT 0 -#define BM_PXP_S0CROP_WIDTH 0x0000FF00 -#define BP_PXP_S0CROP_WIDTH 8 -#define BM_PXP_S0CROP_YBASE 0x00FF0000 -#define BP_PXP_S0CROP_YBASE 16 -#define BM_PXP_S0CROP_XBASE 0xFF000000 -#define BP_PXP_S0CROP_XBASE 24 - -#define HW_PXP_S0SCALE 0xB0 -#define BM_PXP_S0SCALE_XSCALE 0x00003FFF -#define BP_PXP_S0SCALE_XSCALE 0 -#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000 -#define BP_PXP_S0SCALE_YSCALE 16 - -#define HW_PXP_CSCCOEFF0 0xD0 - -#define HW_PXP_CSCCOEFF1 0xE0 - -#define HW_PXP_CSCCOEFF2 0xF0 - -#define HW_PXP_S0COLORKEYLOW 0x180 - -#define HW_PXP_S0COLORKEYHIGH 0x190 - -#define HW_PXP_OL0 (0x200 + 0 * 0x40) -#define HW_PXP_OL1 (0x200 + 1 * 0x40) -#define HW_PXP_OL2 (0x200 + 2 * 0x40) -#define HW_PXP_OL3 (0x200 + 3 * 0x40) -#define HW_PXP_OL4 (0x200 + 4 * 0x40) -#define HW_PXP_OL5 (0x200 + 5 * 0x40) -#define HW_PXP_OL6 (0x200 + 6 * 0x40) -#define HW_PXP_OL7 (0x200 + 7 * 0x40) - -#define HW_PXP_OLn 0x200 - -#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40) -#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40) -#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40) -#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40) -#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40) -#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40) -#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40) -#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40) - -#define HW_PXP_OLnSIZE 0x210 -#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF -#define BP_PXP_OLnSIZE_HEIGHT 0 -#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 -#define BP_PXP_OLnSIZE_WIDTH 8 - -#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40) -#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40) -#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40) -#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40) -#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40) -#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40) -#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40) -#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40) - -#define HW_PXP_OLnPARAM 0x220 -#define BM_PXP_OLnPARAM_ENABLE 0x00000001 -#define BP_PXP_OLnPARAM_ENABLE 0 -#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 -#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 -#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 -#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 -#define BP_PXP_OLnPARAM_FORMAT 4 -#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 -#define BP_PXP_OLnPARAM_ALPHA 8 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h deleted file mode 100644 index b8dbd67..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * stmp378x: RTC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000) -#define REGS_RTC_PHYS 0x8005C000 -#define REGS_RTC_SIZE 0x2000 - -#define HW_RTC_CTRL 0x0 -#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 -#define BP_RTC_CTRL_ALARM_IRQ_EN 0 -#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 -#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 -#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 -#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 - -#define HW_RTC_STAT 0x10 -#define BM_RTC_STAT_NEW_REGS 0x0000FF00 -#define BP_RTC_STAT_NEW_REGS 8 -#define BM_RTC_STAT_STALE_REGS 0x00FF0000 -#define BP_RTC_STAT_STALE_REGS 16 -#define BM_RTC_STAT_RTC_PRESENT 0x80000000 - -#define HW_RTC_SECONDS 0x30 - -#define HW_RTC_ALARM 0x40 - -#define HW_RTC_WATCHDOG 0x50 - -#define HW_RTC_PERSISTENT0 0x60 -#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 -#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 -#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 -#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 -#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 -#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 -#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 - -#define HW_RTC_PERSISTENT1 0x70 -#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF -#define BP_RTC_PERSISTENT1_GENERAL 0 - -#define HW_RTC_VERSION 0xD0 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h deleted file mode 100644 index 6df4176..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * stmp378x: SAIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SAIF_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h deleted file mode 100644 index 8015398..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * stmp378x: SPDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000) -#define REGS_SPDIF_PHYS 0x80054000 -#define REGS_SPDIF_SIZE 0x2000 - -#define HW_SPDIF_CTRL 0x0 -#define BM_SPDIF_CTRL_RUN 0x00000001 -#define BP_SPDIF_CTRL_RUN 0 -#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 -#define BM_SPDIF_CTRL_CLKGATE 0x40000000 -#define BM_SPDIF_CTRL_SFTRST 0x80000000 - -#define HW_SPDIF_STAT 0x10 - -#define HW_SPDIF_FRAMECTRL 0x20 - -#define HW_SPDIF_SRR 0x30 -#define BM_SPDIF_SRR_RATE 0x000FFFFF -#define BP_SPDIF_SRR_RATE 0 -#define BM_SPDIF_SRR_BASEMULT 0x70000000 -#define BP_SPDIF_SRR_BASEMULT 28 - -#define HW_SPDIF_DEBUG 0x40 - -#define HW_SPDIF_DATA 0x50 - -#define HW_SPDIF_VERSION 0x60 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h deleted file mode 100644 index 28aacf0..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * stmp378x: SSP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000) -#define REGS_SSP1_PHYS 0x80010000 -#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000) -#define REGS_SSP2_PHYS 0x80034000 -#define REGS_SSP_SIZE 0x2000 - -#define HW_SSP_CTRL0 0x0 -#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_SSP_CTRL0_XFER_COUNT 0 -#define BM_SSP_CTRL0_ENABLE 0x00010000 -#define BM_SSP_CTRL0_GET_RESP 0x00020000 -#define BM_SSP_CTRL0_LONG_RESP 0x00080000 -#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 -#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 -#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 -#define BP_SSP_CTRL0_BUS_WIDTH 22 -#define BM_SSP_CTRL0_DATA_XFER 0x01000000 -#define BM_SSP_CTRL0_READ 0x02000000 -#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 -#define BM_SSP_CTRL0_LOCK_CS 0x08000000 -#define BM_SSP_CTRL0_RUN 0x20000000 -#define BM_SSP_CTRL0_CLKGATE 0x40000000 -#define BM_SSP_CTRL0_SFTRST 0x80000000 - -#define HW_SSP_CMD0 0x10 -#define BM_SSP_CMD0_CMD 0x000000FF -#define BP_SSP_CMD0_CMD 0 -#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 -#define BP_SSP_CMD0_BLOCK_COUNT 8 -#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 -#define BP_SSP_CMD0_BLOCK_SIZE 16 -#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 -#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF -#define BP_SSP_CMD1_CMD_ARG 0 - -#define HW_SSP_TIMING 0x50 -#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF -#define BP_SSP_TIMING_CLOCK_RATE 0 -#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 -#define BP_SSP_TIMING_CLOCK_DIVIDE 8 -#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 -#define BP_SSP_TIMING_TIMEOUT 16 - -#define HW_SSP_CTRL1 0x60 -#define BM_SSP_CTRL1_SSP_MODE 0x0000000F -#define BP_SSP_CTRL1_SSP_MODE 0 -#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 -#define BP_SSP_CTRL1_WORD_LENGTH 4 -#define BM_SSP_CTRL1_POLARITY 0x00000200 -#define BM_SSP_CTRL1_PHASE 0x00000400 -#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 -#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 -#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 -#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 - -#define HW_SSP_DATA 0x70 - -#define HW_SSP_SDRESP0 0x80 - -#define HW_SSP_SDRESP1 0x90 - -#define HW_SSP_SDRESP2 0xA0 - -#define HW_SSP_SDRESP3 0xB0 - -#define HW_SSP_STATUS 0xC0 -#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 -#define BM_SSP_STATUS_TIMEOUT 0x00001000 -#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 -#define BM_SSP_STATUS_RESP_ERR 0x00008000 -#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 -#define BM_SSP_STATUS_CARD_DETECT 0x10000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h deleted file mode 100644 index 08343a8..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * stmp378x: SYDMA register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000) -#define REGS_SYDMA_PHYS 0x80026000 -#define REGS_SYDMA_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h deleted file mode 100644 index b552795..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * stmp378x: TIMROT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_TIMROT -#define _MACH_REGS_TIMROT - -#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) -#define REGS_TIMROT_PHYS 0x80068000 -#define REGS_TIMROT_SIZE 0x2000 - -#define HW_TIMROT_ROTCTRL 0x0 -#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 -#define BP_TIMROT_ROTCTRL_SELECT_A 0 -#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 -#define BP_TIMROT_ROTCTRL_SELECT_B 4 -#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 -#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 -#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 -#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 -#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 -#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 -#define BP_TIMROT_ROTCTRL_DIVIDER 16 -#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 -#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 -#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 - -#define HW_TIMROT_ROTCOUNT 0x10 -#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF -#define BP_TIMROT_ROTCOUNT_UPDOWN 0 - -#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) -#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) -#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) - -#define HW_TIMROT_TIMCTRLn 0x20 -#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F -#define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 -#define BP_TIMROT_TIMCTRLn_PRESCALE 4 -#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 -#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 -#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 -#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 - -#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) -#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) -#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) - -#define HW_TIMROT_TIMCOUNTn 0x30 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h deleted file mode 100644 index 7f895cb..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * stmp378x: TVENC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000) -#define REGS_TVENC_PHYS 0x80038000 -#define REGS_TVENC_SIZE 0x2000 - -#define HW_TVENC_CTRL 0x0 -#define BM_TVENC_CTRL_CLKGATE 0x40000000 -#define BM_TVENC_CTRL_SFTRST 0x80000000 - -#define HW_TVENC_CONFIG 0x10 -#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007 -#define BP_TVENC_CONFIG_ENCD_MODE 0 -#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070 -#define BP_TVENC_CONFIG_SYNC_MODE 4 -#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200 -#define BM_TVENC_CONFIG_CGAIN 0x0000C000 -#define BP_TVENC_CONFIG_CGAIN 14 -#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000 -#define BP_TVENC_CONFIG_YGAIN_SEL 16 -#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000 - -#define HW_TVENC_SYNCOFFSET 0x30 - -#define HW_TVENC_COLORSUB0 0xC0 - -#define HW_TVENC_COLORBURST 0x140 -#define BM_TVENC_COLORBURST_PBA 0x00FF0000 -#define BP_TVENC_COLORBURST_PBA 16 -#define BM_TVENC_COLORBURST_NBA 0xFF000000 -#define BP_TVENC_COLORBURST_NBA 24 - -#define HW_TVENC_MACROVISION0 0x150 - -#define HW_TVENC_MACROVISION1 0x160 - -#define HW_TVENC_MACROVISION2 0x170 - -#define HW_TVENC_MACROVISION3 0x180 - -#define HW_TVENC_MACROVISION4 0x190 - -#define HW_TVENC_DACCTRL 0x1A0 -#define BM_TVENC_DACCTRL_RVAL 0x00000070 -#define BP_TVENC_DACCTRL_RVAL 4 -#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100 -#define BM_TVENC_DACCTRL_PWRUP1 0x00001000 -#define BM_TVENC_DACCTRL_GAINUP 0x00040000 -#define BM_TVENC_DACCTRL_GAINDN 0x00080000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h deleted file mode 100644 index a251e68..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * stmp378x: UARTAPP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000) -#define REGS_UARTAPP1_PHYS 0x8006C000 -#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000) -#define REGS_UARTAPP2_PHYS 0x8006E000 -#define REGS_UARTAPP_SIZE 0x2000 - -#define HW_UARTAPP_CTRL0 0x0 -#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL0_XFER_COUNT 0 -#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 -#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 -#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 -#define BM_UARTAPP_CTRL0_RUN 0x20000000 -#define BM_UARTAPP_CTRL0_SFTRST 0x80000000 -#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL1_XFER_COUNT 0 -#define BM_UARTAPP_CTRL1_RUN 0x10000000 - -#define HW_UARTAPP_CTRL2 0x20 -#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 -#define BP_UARTAPP_CTRL2_UARTEN 0 -#define BM_UARTAPP_CTRL2_TXE 0x00000100 -#define BM_UARTAPP_CTRL2_RXE 0x00000200 -#define BM_UARTAPP_CTRL2_RTS 0x00000800 -#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 -#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 -#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 -#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 -#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 - -#define HW_UARTAPP_LINECTRL 0x30 -#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define BP_UARTAPP_LINECTRL_BRK 0 -#define BM_UARTAPP_LINECTRL_PEN 0x00000002 -#define BM_UARTAPP_LINECTRL_EPS 0x00000004 -#define BM_UARTAPP_LINECTRL_STP2 0x00000008 -#define BM_UARTAPP_LINECTRL_FEN 0x00000010 -#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 -#define BP_UARTAPP_LINECTRL_WLEN 5 -#define BM_UARTAPP_LINECTRL_SPS 0x00000080 -#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 -#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 -#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 -#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 - -#define HW_UARTAPP_INTR 0x50 -#define BM_UARTAPP_INTR_CTSMIS 0x00000002 -#define BM_UARTAPP_INTR_RTIS 0x00000040 -#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 -#define BM_UARTAPP_INTR_RXIEN 0x00100000 -#define BM_UARTAPP_INTR_RTIEN 0x00400000 - -#define HW_UARTAPP_DATA 0x60 - -#define HW_UARTAPP_STAT 0x70 -#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF -#define BP_UARTAPP_STAT_RXCOUNT 0 -#define BM_UARTAPP_STAT_FERR 0x00010000 -#define BM_UARTAPP_STAT_PERR 0x00020000 -#define BM_UARTAPP_STAT_BERR 0x00040000 -#define BM_UARTAPP_STAT_OERR 0x00080000 -#define BM_UARTAPP_STAT_RXFE 0x01000000 -#define BM_UARTAPP_STAT_TXFF 0x02000000 -#define BM_UARTAPP_STAT_TXFE 0x08000000 -#define BM_UARTAPP_STAT_CTS 0x10000000 - -#define HW_UARTAPP_VERSION 0x90 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h deleted file mode 100644 index b810deb..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * stmp378x: UARTDBG register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) -#define REGS_UARTDBG_PHYS 0x80070000 -#define REGS_UARTDBG_SIZE 0x2000 - -#define HW_UARTDBGDR 0x00000000 -#define BP_UARTDBGDR_UNAVAILABLE 16 -#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) -#define BP_UARTDBGDR_RESERVED 12 -#define BM_UARTDBGDR_RESERVED 0x0000F000 -#define BF_UARTDBGDR_RESERVED(v) \ - (((v) << 12) & BM_UARTDBGDR_RESERVED) -#define BM_UARTDBGDR_OE 0x00000800 -#define BM_UARTDBGDR_BE 0x00000400 -#define BM_UARTDBGDR_PE 0x00000200 -#define BM_UARTDBGDR_FE 0x00000100 -#define BP_UARTDBGDR_DATA 0 -#define BM_UARTDBGDR_DATA 0x000000FF -#define BF_UARTDBGDR_DATA(v) \ - (((v) << 0) & BM_UARTDBGDR_DATA) -#define HW_UARTDBGRSR_ECR 0x00000004 -#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 -#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) -#define BP_UARTDBGRSR_ECR_EC 4 -#define BM_UARTDBGRSR_ECR_EC 0x000000F0 -#define BF_UARTDBGRSR_ECR_EC(v) \ - (((v) << 4) & BM_UARTDBGRSR_ECR_EC) -#define BM_UARTDBGRSR_ECR_OE 0x00000008 -#define BM_UARTDBGRSR_ECR_BE 0x00000004 -#define BM_UARTDBGRSR_ECR_PE 0x00000002 -#define BM_UARTDBGRSR_ECR_FE 0x00000001 -#define HW_UARTDBGFR 0x00000018 -#define BP_UARTDBGFR_UNAVAILABLE 16 -#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGFR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) -#define BP_UARTDBGFR_RESERVED 9 -#define BM_UARTDBGFR_RESERVED 0x0000FE00 -#define BF_UARTDBGFR_RESERVED(v) \ - (((v) << 9) & BM_UARTDBGFR_RESERVED) -#define BM_UARTDBGFR_RI 0x00000100 -#define BM_UARTDBGFR_TXFE 0x00000080 -#define BM_UARTDBGFR_RXFF 0x00000040 -#define BM_UARTDBGFR_TXFF 0x00000020 -#define BM_UARTDBGFR_RXFE 0x00000010 -#define BM_UARTDBGFR_BUSY 0x00000008 -#define BM_UARTDBGFR_DCD 0x00000004 -#define BM_UARTDBGFR_DSR 0x00000002 -#define BM_UARTDBGFR_CTS 0x00000001 -#define HW_UARTDBGILPR 0x00000020 -#define BP_UARTDBGILPR_UNAVAILABLE 8 -#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGILPR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) -#define BP_UARTDBGILPR_ILPDVSR 0 -#define BM_UARTDBGILPR_ILPDVSR 0x000000FF -#define BF_UARTDBGILPR_ILPDVSR(v) \ - (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) -#define HW_UARTDBGIBRD 0x00000024 -#define BP_UARTDBGIBRD_UNAVAILABLE 16 -#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) -#define BP_UARTDBGIBRD_BAUD_DIVINT 0 -#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF -#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ - (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) -#define HW_UARTDBGFBRD 0x00000028 -#define BP_UARTDBGFBRD_UNAVAILABLE 8 -#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) -#define BP_UARTDBGFBRD_RESERVED 6 -#define BM_UARTDBGFBRD_RESERVED 0x000000C0 -#define BF_UARTDBGFBRD_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGFBRD_RESERVED) -#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 -#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F -#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ - (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) -#define HW_UARTDBGLCR_H 0x0000002c -#define BP_UARTDBGLCR_H_UNAVAILABLE 16 -#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) -#define BP_UARTDBGLCR_H_RESERVED 8 -#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 -#define BF_UARTDBGLCR_H_RESERVED(v) \ - (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) -#define BM_UARTDBGLCR_H_SPS 0x00000080 -#define BP_UARTDBGLCR_H_WLEN 5 -#define BM_UARTDBGLCR_H_WLEN 0x00000060 -#define BF_UARTDBGLCR_H_WLEN(v) \ - (((v) << 5) & BM_UARTDBGLCR_H_WLEN) -#define BM_UARTDBGLCR_H_FEN 0x00000010 -#define BM_UARTDBGLCR_H_STP2 0x00000008 -#define BM_UARTDBGLCR_H_EPS 0x00000004 -#define BM_UARTDBGLCR_H_PEN 0x00000002 -#define BM_UARTDBGLCR_H_BRK 0x00000001 -#define HW_UARTDBGCR 0x00000030 -#define BP_UARTDBGCR_UNAVAILABLE 16 -#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGCR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) -#define BM_UARTDBGCR_CTSEN 0x00008000 -#define BM_UARTDBGCR_RTSEN 0x00004000 -#define BM_UARTDBGCR_OUT2 0x00002000 -#define BM_UARTDBGCR_OUT1 0x00001000 -#define BM_UARTDBGCR_RTS 0x00000800 -#define BM_UARTDBGCR_DTR 0x00000400 -#define BM_UARTDBGCR_RXE 0x00000200 -#define BM_UARTDBGCR_TXE 0x00000100 -#define BM_UARTDBGCR_LBE 0x00000080 -#define BP_UARTDBGCR_RESERVED 3 -#define BM_UARTDBGCR_RESERVED 0x00000078 -#define BF_UARTDBGCR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGCR_RESERVED) -#define BM_UARTDBGCR_SIRLP 0x00000004 -#define BM_UARTDBGCR_SIREN 0x00000002 -#define BM_UARTDBGCR_UARTEN 0x00000001 -#define HW_UARTDBGIFLS 0x00000034 -#define BP_UARTDBGIFLS_UNAVAILABLE 16 -#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) -#define BP_UARTDBGIFLS_RESERVED 6 -#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 -#define BF_UARTDBGIFLS_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGIFLS_RESERVED) -#define BP_UARTDBGIFLS_RXIFLSEL 3 -#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 -#define BF_UARTDBGIFLS_RXIFLSEL(v) \ - (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) -#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 -#define BP_UARTDBGIFLS_TXIFLSEL 0 -#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 -#define BF_UARTDBGIFLS_TXIFLSEL(v) \ - (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) -#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 -#define HW_UARTDBGIMSC 0x00000038 -#define BP_UARTDBGIMSC_UNAVAILABLE 16 -#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) -#define BP_UARTDBGIMSC_RESERVED 11 -#define BM_UARTDBGIMSC_RESERVED 0x0000F800 -#define BF_UARTDBGIMSC_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGIMSC_RESERVED) -#define BM_UARTDBGIMSC_OEIM 0x00000400 -#define BM_UARTDBGIMSC_BEIM 0x00000200 -#define BM_UARTDBGIMSC_PEIM 0x00000100 -#define BM_UARTDBGIMSC_FEIM 0x00000080 -#define BM_UARTDBGIMSC_RTIM 0x00000040 -#define BM_UARTDBGIMSC_TXIM 0x00000020 -#define BM_UARTDBGIMSC_RXIM 0x00000010 -#define BM_UARTDBGIMSC_DSRMIM 0x00000008 -#define BM_UARTDBGIMSC_DCDMIM 0x00000004 -#define BM_UARTDBGIMSC_CTSMIM 0x00000002 -#define BM_UARTDBGIMSC_RIMIM 0x00000001 -#define HW_UARTDBGRIS 0x0000003c -#define BP_UARTDBGRIS_UNAVAILABLE 16 -#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGRIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) -#define BP_UARTDBGRIS_RESERVED 11 -#define BM_UARTDBGRIS_RESERVED 0x0000F800 -#define BF_UARTDBGRIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGRIS_RESERVED) -#define BM_UARTDBGRIS_OERIS 0x00000400 -#define BM_UARTDBGRIS_BERIS 0x00000200 -#define BM_UARTDBGRIS_PERIS 0x00000100 -#define BM_UARTDBGRIS_FERIS 0x00000080 -#define BM_UARTDBGRIS_RTRIS 0x00000040 -#define BM_UARTDBGRIS_TXRIS 0x00000020 -#define BM_UARTDBGRIS_RXRIS 0x00000010 -#define BM_UARTDBGRIS_DSRRMIS 0x00000008 -#define BM_UARTDBGRIS_DCDRMIS 0x00000004 -#define BM_UARTDBGRIS_CTSRMIS 0x00000002 -#define BM_UARTDBGRIS_RIRMIS 0x00000001 -#define HW_UARTDBGMIS 0x00000040 -#define BP_UARTDBGMIS_UNAVAILABLE 16 -#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGMIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) -#define BP_UARTDBGMIS_RESERVED 11 -#define BM_UARTDBGMIS_RESERVED 0x0000F800 -#define BF_UARTDBGMIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGMIS_RESERVED) -#define BM_UARTDBGMIS_OEMIS 0x00000400 -#define BM_UARTDBGMIS_BEMIS 0x00000200 -#define BM_UARTDBGMIS_PEMIS 0x00000100 -#define BM_UARTDBGMIS_FEMIS 0x00000080 -#define BM_UARTDBGMIS_RTMIS 0x00000040 -#define BM_UARTDBGMIS_TXMIS 0x00000020 -#define BM_UARTDBGMIS_RXMIS 0x00000010 -#define BM_UARTDBGMIS_DSRMMIS 0x00000008 -#define BM_UARTDBGMIS_DCDMMIS 0x00000004 -#define BM_UARTDBGMIS_CTSMMIS 0x00000002 -#define BM_UARTDBGMIS_RIMMIS 0x00000001 -#define HW_UARTDBGICR 0x00000044 -#define BP_UARTDBGICR_UNAVAILABLE 16 -#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGICR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) -#define BP_UARTDBGICR_RESERVED 11 -#define BM_UARTDBGICR_RESERVED 0x0000F800 -#define BF_UARTDBGICR_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGICR_RESERVED) -#define BM_UARTDBGICR_OEIC 0x00000400 -#define BM_UARTDBGICR_BEIC 0x00000200 -#define BM_UARTDBGICR_PEIC 0x00000100 -#define BM_UARTDBGICR_FEIC 0x00000080 -#define BM_UARTDBGICR_RTIC 0x00000040 -#define BM_UARTDBGICR_TXIC 0x00000020 -#define BM_UARTDBGICR_RXIC 0x00000010 -#define BM_UARTDBGICR_DSRMIC 0x00000008 -#define BM_UARTDBGICR_DCDMIC 0x00000004 -#define BM_UARTDBGICR_CTSMIC 0x00000002 -#define BM_UARTDBGICR_RIMIC 0x00000001 -#define HW_UARTDBGDMACR 0x00000048 -#define BP_UARTDBGDMACR_UNAVAILABLE 16 -#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) -#define BP_UARTDBGDMACR_RESERVED 3 -#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 -#define BF_UARTDBGDMACR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGDMACR_RESERVED) -#define BM_UARTDBGDMACR_DMAONERR 0x00000004 -#define BM_UARTDBGDMACR_TXDMAE 0x00000002 -#define BM_UARTDBGDMACR_RXDMAE 0x00000001 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h deleted file mode 100644 index 25112c1..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * stmp378x: USBCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTRL_PHYS 0x80080000 -#define REGS_USBCTRL_SIZE 0x2000 - -#define HW_USBCTRL_USBCMD 0x140 -#define BM_USBCTRL_USBCMD_RS 0x00000001 -#define BP_USBCTRL_USBCMD_RS 0 -#define BM_USBCTRL_USBCMD_RST 0x00000002 - -#define HW_USBCTRL_USBINTR 0x148 -#define BM_USBCTRL_USBINTR_UE 0x00000001 -#define BP_USBCTRL_USBINTR_UE 0 - -#define HW_USBCTRL_PORTSC1 0x184 -#define BM_USBCTRL_PORTSC1_PHCD 0x00800000 - -#define HW_USBCTRL_OTGSC 0x1A4 -#define BM_USBCTRL_OTGSC_ID 0x00000100 -#define BM_USBCTRL_OTGSC_IDIS 0x00010000 -#define BM_USBCTRL_OTGSC_IDIE 0x01000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h deleted file mode 100644 index 11f3b73..0000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp378x: USBPHY register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000) -#define REGS_USBPHY_PHYS 0x8007C000 -#define REGS_USBPHY_SIZE 0x2000 - -#define HW_USBPHY_PWD 0x0 - -#define HW_USBPHY_CTRL 0x30 -#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 -#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 -#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 -#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 -#define BM_USBPHY_CTRL_CLKGATE 0x40000000 -#define BM_USBPHY_CTRL_SFTRST 0x80000000 - -#define HW_USBPHY_STATUS 0x40 -#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 -#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c deleted file mode 100644 index c2f9fe0..0000000 --- a/arch/arm/mach-stmp378x/stmp378x.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Freescale STMP378X platform support - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "stmp378x.h" -/* - * IRQ handling - */ -static void stmp378x_ack_irq(struct irq_data *d) -{ - /* Tell ICOLL to release IRQ line */ - __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); - - /* ACK current interrupt */ - __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */, - REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - -static void stmp378x_mask_irq(struct irq_data *d) -{ - /* IRQ disable */ - stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE, - REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10); -} - -static void stmp378x_unmask_irq(struct irq_data *d) -{ - /* IRQ enable */ - stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE, - REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10); -} - -static struct irq_chip stmp378x_chip = { - .irq_ack = stmp378x_ack_irq, - .irq_mask = stmp378x_mask_irq, - .irq_unmask = stmp378x_unmask_irq, -}; - -void __init stmp378x_init_irq(void) -{ - stmp3xxx_init_irq(&stmp378x_chip); -} - -/* - * DMA interrupt handling - */ -void stmp3xxx_arch_dma_enable_interrupt(int channel) -{ - void __iomem *c1, *c2; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c1 = REGS_APBH_BASE + HW_APBH_CTRL1; - c2 = REGS_APBH_BASE + HW_APBH_CTRL2; - break; - - case STMP3XXX_BUS_APBX: - c1 = REGS_APBX_BASE + HW_APBX_CTRL1; - c2 = REGS_APBX_BASE + HW_APBX_CTRL2; - break; - - default: - return; - } - stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1); - stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); - -void stmp3xxx_arch_dma_clear_interrupt(int channel) -{ - void __iomem *c1, *c2; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c1 = REGS_APBH_BASE + HW_APBH_CTRL1; - c2 = REGS_APBH_BASE + HW_APBH_CTRL2; - break; - - case STMP3XXX_BUS_APBX: - c1 = REGS_APBX_BASE + HW_APBX_CTRL1; - c2 = REGS_APBX_BASE + HW_APBX_CTRL2; - break; - - default: - return; - } - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1); - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); - -int stmp3xxx_arch_dma_is_interrupt(int channel) -{ - int r = 0; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - - case STMP3XXX_BUS_APBX: - r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); - -void stmp3xxx_arch_dma_reset_channel(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - void __iomem *c0; - u32 mask; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c0 = REGS_APBH_BASE + HW_APBH_CTRL0; - mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL; - break; - case STMP3XXX_BUS_APBX: - c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL; - mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL; - break; - default: - return; - } - - /* Reset channel and wait for it to complete */ - stmp3xxx_setl(mask, c0); - while (__raw_readl(c0) & mask) - cpu_relax(); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); - -void stmp3xxx_arch_dma_freeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - u32 mask = 1 << chbit; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze); - -void stmp3xxx_arch_dma_unfreeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - u32 mask = 1 << chbit; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze); - -/* - * The registers are all very closely mapped, so we might as well map them all - * with a single mapping - * - * Logical Physical - * f0000000 80000000 On-chip registers - * f1000000 00000000 32k on-chip SRAM - */ - -static struct map_desc stmp378x_io_desc[] __initdata = { - { - .virtual = (u32)STMP3XXX_REGS_BASE, - .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE), - .length = STMP3XXX_REGS_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (u32)STMP3XXX_OCRAM_BASE, - .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE), - .length = STMP3XXX_OCRAM_SIZE, - .type = MT_DEVICE, - }, -}; - - -static u64 common_dmamask = DMA_BIT_MASK(32); - -/* - * devices that are present only on stmp378x, not on all 3xxx boards: - * PxP - * I2C - */ -static struct resource pxp_resource[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_PXP_PHYS, - .end = REGS_PXP_PHYS + REGS_PXP_SIZE, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_PXP, - .end = IRQ_PXP, - }, -}; - -struct platform_device stmp378x_pxp = { - .name = "stmp3xxx-pxp", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(pxp_resource), - .resource = pxp_resource, -}; - -static struct resource i2c_resources[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_I2C_ERROR, - .end = IRQ_I2C_ERROR, - }, { - .flags = IORESOURCE_MEM, - .start = REGS_I2C_PHYS, - .end = REGS_I2C_PHYS + REGS_I2C_SIZE, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX), - }, -}; - -struct platform_device stmp378x_i2c = { - .name = "i2c_stmp3xxx", - .id = 0, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = i2c_resources, - .num_resources = ARRAY_SIZE(i2c_resources), -}; - -void __init stmp378x_map_io(void) -{ - iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc)); -} diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h deleted file mode 100644 index 0dc15b3..0000000 --- a/arch/arm/mach-stmp378x/stmp378x.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X internal functions and data declarations - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __MACH_STMP378X_H -#define __MACH_STMP378X_H - -void stmp378x_map_io(void); -void stmp378x_init_irq(void); - -extern struct platform_device stmp378x_pxp, stmp378x_i2c; -#endif /* __MACH_STMP378X_COMMON_H */ diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c deleted file mode 100644 index 0615884..0000000 --- a/arch/arm/mach-stmp378x/stmp378x_devb.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Freescale STMP378X development board support - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "stmp378x.h" - -static struct platform_device *devices[] = { - &stmp3xxx_dbguart, - &stmp3xxx_appuart, - &stmp3xxx_watchdog, - &stmp3xxx_touchscreen, - &stmp3xxx_rtc, - &stmp3xxx_keyboard, - &stmp3xxx_framebuffer, - &stmp3xxx_backlight, - &stmp3xxx_rotdec, - &stmp3xxx_persistent, - &stmp3xxx_dcp_bootstream, - &stmp3xxx_dcp, - &stmp3xxx_battery, - &stmp378x_pxp, - &stmp378x_i2c, -}; - -static struct pin_desc i2c_pins_desc[] = { - { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, -}; - -static struct pin_group i2c_pins = { - .pins = i2c_pins_desc, - .nr_pins = ARRAY_SIZE(i2c_pins_desc), -}; - -static struct pin_desc dbguart_pins_0[] = { - { PINID_PWM0, PIN_FUN3, }, - { PINID_PWM1, PIN_FUN3, }, -}; - -static struct pin_group dbguart_pins[] = { - [0] = { - .pins = dbguart_pins_0, - .nr_pins = ARRAY_SIZE(dbguart_pins_0), - }, -}; - -static int dbguart_pins_control(int id, int request) -{ - int r = 0; - - if (request) - r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart"); - else - stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart"); - return r; -} - -static struct pin_desc appuart_pins_0[] = { - { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -}; - -static struct pin_desc appuart_pins_1[] = { -#if 0 /* enable these when second appuart will be connected */ - { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -#endif -}; - -static struct pin_desc mmc_pins_desc[] = { - { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 }, - { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 }, -}; - -static struct pin_group mmc_pins = { - .pins = mmc_pins_desc, - .nr_pins = ARRAY_SIZE(mmc_pins_desc), -}; - -static int stmp3xxxmmc_get_wp(void) -{ - return gpio_get_value(PINID_PWM4); -} - -static int stmp3xxxmmc_hw_init_ssp1(void) -{ - int ret; - - ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc"); - if (ret) - goto out; - - /* Configure write protect GPIO pin */ - ret = gpio_request(PINID_PWM4, "mmc wp"); - if (ret) - goto out_wp; - - gpio_direction_input(PINID_PWM4); - - /* Configure POWER pin as gpio to drive power to MMC slot */ - ret = gpio_request(PINID_PWM3, "mmc power"); - if (ret) - goto out_power; - - gpio_direction_output(PINID_PWM3, 0); - mdelay(100); - - return 0; - -out_power: - gpio_free(PINID_PWM4); -out_wp: - stmp3xxx_release_pin_group(&mmc_pins, "mmc"); -out: - return ret; -} - -static void stmp3xxxmmc_hw_release_ssp1(void) -{ - gpio_free(PINID_PWM3); - gpio_free(PINID_PWM4); - stmp3xxx_release_pin_group(&mmc_pins, "mmc"); -} - -static void stmp3xxxmmc_cmd_pullup_ssp1(int enable) -{ - stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc"); -} - -static unsigned long -stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz) -{ - struct clk *ssp, *parent; - char *p; - long r; - - ssp = clk_get(NULL, "ssp"); - - /* using SSP1, no timeout, clock rate 1 */ - writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) | - BF(0xFFFF, SSP_TIMING_TIMEOUT), - base + HW_SSP_TIMING); - - p = (hz > 1000000) ? "io" : "osc_24M"; - parent = clk_get(NULL, p); - clk_set_parent(ssp, parent); - r = clk_set_rate(ssp, 2 * hz / 1000); - clk_put(parent); - clk_put(ssp); - - return hz; -} - -static struct stmp3xxxmmc_platform_data mmc_data = { - .hw_init = stmp3xxxmmc_hw_init_ssp1, - .hw_release = stmp3xxxmmc_hw_release_ssp1, - .get_wp = stmp3xxxmmc_get_wp, - .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1, - .setclock = stmp3xxxmmc_setclock_ssp1, -}; - - -static struct pin_group appuart_pins[] = { - [0] = { - .pins = appuart_pins_0, - .nr_pins = ARRAY_SIZE(appuart_pins_0), - }, - [1] = { - .pins = appuart_pins_1, - .nr_pins = ARRAY_SIZE(appuart_pins_1), - }, -}; - -static struct pin_desc ssp1_pins_desc[] = { - { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, }, - { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, - { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, - { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, -}; - -static struct pin_desc ssp2_pins_desc[] = { - { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, }, - { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, - { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, - { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, -}; - -static struct pin_group ssp1_pins = { - .pins = ssp1_pins_desc, - .nr_pins = ARRAY_SIZE(ssp1_pins_desc), -}; - -static struct pin_group ssp2_pins = { - .pins = ssp1_pins_desc, - .nr_pins = ARRAY_SIZE(ssp2_pins_desc), -}; - -static struct pin_desc gpmi_pins_desc[] = { - { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, -}; - -static struct pin_group gpmi_pins = { - .pins = gpmi_pins_desc, - .nr_pins = ARRAY_SIZE(gpmi_pins_desc), -}; - -static struct mtd_partition gpmi_partitions[] = { - [0] = { - .name = "boot", - .size = 10 * SZ_1M, - .offset = 0, - }, - [1] = { - .name = "data", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct gpmi_platform_data gpmi_data = { - .pins = &gpmi_pins, - .nr_parts = ARRAY_SIZE(gpmi_partitions), - .parts = gpmi_partitions, - .part_types = { "cmdline", NULL }, -}; - -static struct spi_board_info spi_board_info[] __initdata = { -#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) - { - .modalias = "enc28j60", - .max_speed_hz = 6 * 1000 * 1000, - .bus_num = 1, - .chip_select = 0, - .platform_data = NULL, - }, -#endif -}; - -static void __init stmp378x_devb_init(void) -{ - stmp3xxx_pinmux_init(NR_REAL_IRQS); - - /* init stmp3xxx platform */ - stmp3xxx_init(); - - stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; - stmp3xxx_appuart.dev.platform_data = appuart_pins; - stmp3xxx_mmc.dev.platform_data = &mmc_data; - stmp3xxx_gpmi.dev.platform_data = &gpmi_data; - stmp3xxx_spi1.dev.platform_data = &ssp1_pins; - stmp3xxx_spi2.dev.platform_data = &ssp2_pins; - stmp378x_i2c.dev.platform_data = &i2c_pins; - - /* register spi devices */ - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - - /* add board's devices */ - platform_add_devices(devices, ARRAY_SIZE(devices)); - - /* add devices selected by command line ssp1= and ssp2= options */ - stmp3xxx_ssp1_device_register(); - stmp3xxx_ssp2_device_register(); -} - -MACHINE_START(STMP378X, "STMP378X") - .boot_params = 0x40000100, - .map_io = stmp378x_map_io, - .init_irq = stmp378x_init_irq, - .timer = &stmp3xxx_timer, - .init_machine = stmp378x_devb_init, -MACHINE_END diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig index dcdbe32..e6e312b6 100644 --- a/arch/arm/plat-stmp3xxx/Kconfig +++ b/arch/arm/plat-stmp3xxx/Kconfig @@ -2,26 +2,6 @@ if ARCH_STMP3XXX menu "Freescale STMP3xxx implementations" -choice - prompt "Select STMP3xxx chip family" - -config ARCH_STMP378X - bool "Freescale STMP378x" - select CPU_ARM926T - ---help--- - STMP378x refers to 3780 through 3789 chips - -endchoice - -choice - prompt "Select STMP3xxx board type" - -config MACH_STMP378X - depends on ARCH_STMP378X - bool "Freescale STMP378x development board" - -endchoice - endmenu endif -- cgit v0.10.2 From 041f10d46f97c87f8ae1cdb4117682214732cc45 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 29 Apr 2011 15:06:43 +0200 Subject: ARM: plat-stmp: remove plat Now that both users of plat-stmp have been deleted in previous patches, delete the platform, too. Signed-off-by: Wolfram Sang Acked-by: Shawn Guo Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 377a7a5..c9f69e0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -378,16 +378,6 @@ config ARCH_MXS help Support for Freescale MXS-based family of processors -config ARCH_STMP3XXX - bool "Freescale STMP3xxx" - select CPU_ARM926T - select CLKDEV_LOOKUP - select ARCH_REQUIRE_GPIOLIB - select GENERIC_CLOCKEVENTS - select USB_ARCH_HAS_EHCI - help - Support for systems based on the Freescale 3xxx CPUs. - config ARCH_NETX bool "Hilscher NetX based" select CPU_ARM926T @@ -1005,8 +995,6 @@ source "arch/arm/mach-exynos4/Kconfig" source "arch/arm/mach-shmobile/Kconfig" -source "arch/arm/plat-stmp3xxx/Kconfig" - source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-u300/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ca473b1..692c481 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -205,7 +205,6 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_S3C64XX) := samsung -plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx plat-$(CONFIG_ARCH_TCC_926) := tcc plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_NOMADIK) := nomadik diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig deleted file mode 100644 index e6e312b6..0000000 --- a/arch/arm/plat-stmp3xxx/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if ARCH_STMP3XXX - -menu "Freescale STMP3xxx implementations" - -endmenu - -endif diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile deleted file mode 100644 index 31dd518..0000000 --- a/arch/arm/plat-stmp3xxx/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the linux kernel. -# -# Object file lists. -obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c deleted file mode 100644 index 2e712e1..0000000 --- a/arch/arm/plat-stmp3xxx/clock.c +++ /dev/null @@ -1,1134 +0,0 @@ -/* - * Clock manipulation routines for Freescale STMP37XX/STMP378X - * - * Author: Vitaly Wool - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define DEBUG -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "clock.h" - -static DEFINE_SPINLOCK(clocks_lock); - -static struct clk osc_24M; -static struct clk pll_clk; -static struct clk cpu_clk; -static struct clk hclk; - -static int propagate_rate(struct clk *); - -static inline int clk_is_busy(struct clk *clk) -{ - return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit); -} - -static inline int clk_good(struct clk *clk) -{ - return clk && !IS_ERR(clk) && clk->ops; -} - -static int std_clk_enable(struct clk *clk) -{ - if (clk->enable_reg) { - u32 clk_reg = __raw_readl(clk->enable_reg); - if (clk->enable_negate) - clk_reg &= ~(1 << clk->enable_shift); - else - clk_reg |= (1 << clk->enable_shift); - __raw_writel(clk_reg, clk->enable_reg); - if (clk->enable_wait) - udelay(clk->enable_wait); - return 0; - } else - return -EINVAL; -} - -static int std_clk_disable(struct clk *clk) -{ - if (clk->enable_reg) { - u32 clk_reg = __raw_readl(clk->enable_reg); - if (clk->enable_negate) - clk_reg |= (1 << clk->enable_shift); - else - clk_reg &= ~(1 << clk->enable_shift); - __raw_writel(clk_reg, clk->enable_reg); - return 0; - } else - return -EINVAL; -} - -static int io_set_rate(struct clk *clk, u32 rate) -{ - u32 reg_frac, clkctrl_frac; - int i, ret = 0, mask = 0x1f; - - clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate; - - if (clkctrl_frac < 18 || clkctrl_frac > 35) { - ret = -EINVAL; - goto out; - } - - reg_frac = __raw_readl(clk->scale_reg); - reg_frac &= ~(mask << clk->scale_shift); - __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift), - clk->scale_reg); - if (clk->busy_reg) { - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) - ret = -ETIMEDOUT; - else - ret = 0; - } -out: - return ret; -} - -static long io_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - int mask = 0x1f; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - clk->rate = rate; - - return rate; -} - -static long per_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - long div; - const int mask = 0xff; - - if (clk->enable_reg && - !(__raw_readl(clk->enable_reg) & clk->enable_shift)) - clk->rate = 0; - else { - div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - if (div) - rate /= div; - clk->rate = rate; - } - - return clk->rate; -} - -static int per_set_rate(struct clk *clk, u32 rate) -{ - int ret = -EINVAL; - int div = (clk->parent->rate + rate - 1) / rate; - u32 reg_frac; - const int mask = 0xff; - int try = 10; - int i = -1; - - if (div == 0 || div > mask) - goto out; - - reg_frac = __raw_readl(clk->scale_reg); - reg_frac &= ~(mask << clk->scale_shift); - - while (try--) { - __raw_writel(reg_frac | (div << clk->scale_shift), - clk->scale_reg); - - if (clk->busy_reg) { - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - } - if (i) - break; - } - - if (!i) - ret = -ETIMEDOUT; - else - ret = 0; - -out: - if (ret != 0) - printk(KERN_ERR "%s: error %d\n", __func__, ret); - return ret; -} - -static long lcdif_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - long div; - const int mask = 0xff; - - div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - if (div) { - rate /= div; - div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) & - BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC; - rate /= div; - } - clk->rate = rate; - - return rate; -} - -static int lcdif_set_rate(struct clk *clk, u32 rate) -{ - int ret = 0; - /* - * On 3700, we can get most timings exact by modifying ref_pix - * and the divider, but keeping the phase timings at 1 (2 - * phases per cycle). - * - * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz, - * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns. - * - * ns_cycle >= 2*18e3/(18*480) = 25/6 - * ns_cycle <= 2*35e3/(18*480) = 875/108 - * - * Multiply the ns_cycle by 'div' to lengthen it until it fits the - * bounds. This is the divider we'll use after ref_pix. - * - * 6 * ns_cycle >= 25 * div - * 108 * ns_cycle <= 875 * div - */ - u32 ns_cycle = 1000000 / rate; - u32 div, reg_val; - u32 lowest_result = (u32) -1; - u32 lowest_div = 0, lowest_fracdiv = 0; - - for (div = 1; div < 256; ++div) { - u32 fracdiv; - u32 ps_result; - int lower_bound = 6 * ns_cycle >= 25 * div; - int upper_bound = 108 * ns_cycle <= 875 * div; - if (!lower_bound) - break; - if (!upper_bound) - continue; - /* - * Found a matching div. Calculate fractional divider needed, - * rounded up. - */ - fracdiv = ((clk->parent->rate / 1000 * 18 / 2) * - ns_cycle + 1000 * div - 1) / - (1000 * div); - if (fracdiv < 18 || fracdiv > 35) { - ret = -EINVAL; - goto out; - } - /* Calculate the actual cycle time this results in */ - ps_result = 6250 * div * fracdiv / 27; - - /* Use the fastest result that doesn't break ns_cycle */ - if (ps_result <= lowest_result) { - lowest_result = ps_result; - lowest_div = div; - lowest_fracdiv = fracdiv; - } - } - - if (div >= 256 || lowest_result == (u32) -1) { - ret = -EINVAL; - goto out; - } - pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz " - "PIXCLK=%uMHz cycle=%u.%03uns\n", - lowest_fracdiv, lowest_div, - 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div, - lowest_result / 1000, lowest_result % 1000); - - /* Program ref_pix phase fractional divider */ - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC; - reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC); - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - - /* Ungate PFD */ - stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX, - REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - - /* Program pix divider */ - reg_val = __raw_readl(clk->scale_reg); - reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); - reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV); - __raw_writel(reg_val, clk->scale_reg); - - /* Wait for divider update */ - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - ret = -ETIMEDOUT; - goto out; - } - } - - /* Switch to ref_pix source */ - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); - reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX; - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); - -out: - return ret; -} - - -static int cpu_set_rate(struct clk *clk, u32 rate) -{ - u32 reg_val; - - if (rate < 24000) - return -EINVAL; - else if (rate == 24000) { - /* switch to the 24M source */ - clk_set_parent(clk, &osc_24M); - } else { - int i; - u32 clkctrl_cpu = 1; - u32 c = clkctrl_cpu; - u32 clkctrl_frac = 1; - u32 val; - for ( ; c < 0x40; c++) { - u32 f = (pll_clk.rate*18/c + rate/2) / rate; - int s1, s2; - - if (f < 18 || f > 35) - continue; - s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate; - s2 = pll_clk.rate*18/c/f - rate; - pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2); - if (abs(s1) > abs(s2)) { - clkctrl_cpu = c; - clkctrl_frac = f; - } - if (s2 == 0) - break; - }; - pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__, - clkctrl_cpu, clkctrl_frac); - if (c == 0x40) { - int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - - rate; - if (abs(d) > 100 || - clkctrl_frac < 18 || clkctrl_frac > 35) - return -EINVAL; - } - - /* 4.6.2 */ - val = __raw_readl(clk->scale_reg); - val &= ~(0x3f << clk->scale_shift); - val |= clkctrl_frac; - clk_set_parent(clk, &osc_24M); - udelay(10); - __raw_writel(val, clk->scale_reg); - /* ungate */ - __raw_writel(1<<7, clk->scale_reg + 8); - /* write clkctrl_cpu */ - clk->saved_div = clkctrl_cpu; - - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - reg_val &= ~0x3F; - reg_val |= clkctrl_cpu; - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up CPU divisor\n"); - return -ETIMEDOUT; - } - clk_set_parent(clk, &pll_clk); - clk->saved_div = 0; - udelay(10); - } - return 0; -} - -static long cpu_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; - rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f; - rate = ((rate + 9) / 10) * 10; - clk->rate = rate; - - return rate; -} - -static long cpu_round_rate(struct clk *clk, u32 rate) -{ - unsigned long r = 0; - - if (rate <= 24000) - r = 24000; - else { - u32 clkctrl_cpu = 1; - u32 clkctrl_frac; - do { - clkctrl_frac = - (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate; - if (clkctrl_frac > 35) - continue; - if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 == - rate / 10) - break; - } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate); - if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate) - clkctrl_cpu--; - pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__, - clkctrl_cpu, clkctrl_frac); - if (clkctrl_frac < 18) - clkctrl_frac = 18; - if (clkctrl_frac > 35) - clkctrl_frac = 35; - - r = pll_clk.rate * 18; - r /= clkctrl_frac; - r /= clkctrl_cpu; - r = 10 * ((r + 9) / 10); - } - return r; -} - -static long emi_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; - rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f; - clk->rate = rate; - - return rate; -} - -static int clkseq_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -EINVAL; - int shift = 8; - - /* bypass? */ - if (parent == &osc_24M) - shift = 4; - - if (clk->bypass_reg) { -#ifdef CONFIG_ARCH_STMP378X - u32 hbus_val, cpu_val; - - if (clk == &cpu_clk && shift == 4) { - hbus_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_HBUS); - cpu_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_CPU); - - hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV); - clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; - cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; - cpu_val |= 1; - - if (machine_is_stmp378x()) { - __raw_writel(hbus_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - __raw_writel(cpu_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - hclk.rate = 0; - } - } else if (clk == &cpu_clk && shift == 8) { - hbus_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_HBUS); - cpu_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_CPU); - hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV); - hbus_val |= 2; - cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; - if (clk->saved_div) - cpu_val |= clk->saved_div; - else - cpu_val |= 2; - - if (machine_is_stmp378x()) { - __raw_writel(hbus_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - __raw_writel(cpu_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - hclk.rate = 0; - } - } -#endif - __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift); - - ret = 0; - } - - return ret; -} - -static int hbus_set_rate(struct clk *clk, u32 rate) -{ - u8 div = 0; - int is_frac = 0; - u32 clkctrl_hbus; - struct clk *parent = clk->parent; - - pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, - parent->rate); - - if (rate > parent->rate) - return -EINVAL; - - if (((parent->rate + rate/2) / rate) * rate != parent->rate && - parent->rate / rate < 32) { - pr_debug("%s: switching to fractional mode\n", __func__); - is_frac = 1; - } - - if (is_frac) - div = (32 * rate + parent->rate / 2) / parent->rate; - else - div = (parent->rate + rate - 1) / rate; - pr_debug("%s: div calculated is %d\n", __func__, div); - if (!div || div > 0x1f) - return -EINVAL; - - clk_set_parent(&cpu_clk, &osc_24M); - udelay(10); - clkctrl_hbus = __raw_readl(clk->scale_reg); - clkctrl_hbus &= ~0x3f; - clkctrl_hbus |= div; - clkctrl_hbus |= (is_frac << 5); - - __raw_writel(clkctrl_hbus, clk->scale_reg); - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up CPU divisor\n"); - return -ETIMEDOUT; - } - } - clk_set_parent(&cpu_clk, &pll_clk); - __raw_writel(clkctrl_hbus, clk->scale_reg); - udelay(10); - return 0; -} - -static long hbus_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - - if (__raw_readl(clk->scale_reg) & 0x20) { - rate *= __raw_readl(clk->scale_reg) & 0x1f; - rate /= 32; - } else - rate /= __raw_readl(clk->scale_reg) & 0x1f; - clk->rate = rate; - - return rate; -} - -static int xbus_set_rate(struct clk *clk, u32 rate) -{ - u16 div = 0; - u32 clkctrl_xbus; - - pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, - clk->parent->rate); - - div = (clk->parent->rate + rate - 1) / rate; - pr_debug("%s: div calculated is %d\n", __func__, div); - if (!div || div > 0x3ff) - return -EINVAL; - - clkctrl_xbus = __raw_readl(clk->scale_reg); - clkctrl_xbus &= ~0x3ff; - clkctrl_xbus |= div; - __raw_writel(clkctrl_xbus, clk->scale_reg); - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up xbus divisor\n"); - return -ETIMEDOUT; - } - } - return 0; -} - -static long xbus_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - - rate /= __raw_readl(clk->scale_reg) & 0x3ff; - clk->rate = rate; - - return rate; -} - - -/* Clock ops */ - -static struct clk_ops std_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = per_get_rate, - .set_rate = per_set_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops min_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, -}; - -static struct clk_ops cpu_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = cpu_get_rate, - .set_rate = cpu_set_rate, - .round_rate = cpu_round_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops io_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = io_get_rate, - .set_rate = io_set_rate, -}; - -static struct clk_ops hbus_ops = { - .get_rate = hbus_get_rate, - .set_rate = hbus_set_rate, -}; - -static struct clk_ops xbus_ops = { - .get_rate = xbus_get_rate, - .set_rate = xbus_set_rate, -}; - -static struct clk_ops lcdif_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = lcdif_get_rate, - .set_rate = lcdif_set_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops emi_ops = { - .get_rate = emi_get_rate, -}; - -/* List of on-chip clocks */ - -static struct clk osc_24M = { - .flags = FIXED_RATE | ENABLED, - .rate = 24000, -}; - -static struct clk pll_clk = { - .parent = &osc_24M, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, - .enable_shift = 16, - .enable_wait = 10, - .flags = FIXED_RATE | ENABLED, - .rate = 480000, - .ops = &min_ops, -}; - -static struct clk cpu_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 0, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 7, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU, - .busy_bit = 28, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &cpu_ops, -}; - -static struct clk io_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .enable_shift = 31, - .enable_negate = 1, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 24, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &io_ops, -}; - -static struct clk hclk = { - .parent = &cpu_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 7, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, - .busy_bit = 29, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &hbus_ops, -}; - -static struct clk xclk = { - .parent = &osc_24M, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, - .busy_bit = 31, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &xbus_ops, -}; - -static struct clk uart_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 31, - .enable_negate = 1, - .flags = ENABLED, - .ops = &min_ops, -}; - -static struct clk audio_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 30, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk pwm_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 29, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk dri_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 28, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk digctl_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 27, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk timer_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 26, - .enable_negate = 1, - .flags = ENABLED, - .ops = &min_ops, -}; - -static struct clk lcdif_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 1, - .flags = NEEDS_SET_PARENT, - .ops = &lcdif_ops, -}; - -static struct clk ssp_clk = { - .parent = &io_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .enable_shift = 31, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 5, - .enable_negate = 1, - .flags = NEEDS_SET_PARENT, - .ops = &std_ops, -}; - -static struct clk gpmi_clk = { - .parent = &io_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 4, - .flags = NEEDS_SET_PARENT, - .ops = &std_ops, -}; - -static struct clk spdif_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF, - .enable_shift = 31, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk emi_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, - .enable_shift = 31, - .enable_negate = 1, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 8, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, - .busy_bit = 28, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 6, - .flags = ENABLED, - .ops = &emi_ops, -}; - -static struct clk ir_clk = { - .parent = &io_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 3, - .ops = &min_ops, -}; - -static struct clk saif_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 0, - .ops = &std_ops, -}; - -static struct clk usb_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, - .enable_shift = 18, - .enable_negate = 1, - .ops = &min_ops, -}; - -/* list of all the clocks */ -static struct clk_lookup onchip_clks[] = { - { - .con_id = "osc_24M", - .clk = &osc_24M, - }, { - .con_id = "pll", - .clk = &pll_clk, - }, { - .con_id = "cpu", - .clk = &cpu_clk, - }, { - .con_id = "hclk", - .clk = &hclk, - }, { - .con_id = "xclk", - .clk = &xclk, - }, { - .con_id = "io", - .clk = &io_clk, - }, { - .con_id = "uart", - .clk = &uart_clk, - }, { - .con_id = "audio", - .clk = &audio_clk, - }, { - .con_id = "pwm", - .clk = &pwm_clk, - }, { - .con_id = "dri", - .clk = &dri_clk, - }, { - .con_id = "digctl", - .clk = &digctl_clk, - }, { - .con_id = "timer", - .clk = &timer_clk, - }, { - .con_id = "lcdif", - .clk = &lcdif_clk, - }, { - .con_id = "ssp", - .clk = &ssp_clk, - }, { - .con_id = "gpmi", - .clk = &gpmi_clk, - }, { - .con_id = "spdif", - .clk = &spdif_clk, - }, { - .con_id = "emi", - .clk = &emi_clk, - }, { - .con_id = "ir", - .clk = &ir_clk, - }, { - .con_id = "saif", - .clk = &saif_clk, - }, { - .con_id = "usb", - .clk = &usb_clk, - }, -}; - -static int __init propagate_rate(struct clk *clk) -{ - struct clk_lookup *cl; - - for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks); - cl++) { - if (unlikely(!clk_good(cl->clk))) - continue; - if (cl->clk->parent == clk && cl->clk->ops->get_rate) { - cl->clk->ops->get_rate(cl->clk); - if (cl->clk->flags & RATE_PROPAGATES) - propagate_rate(cl->clk); - } - } - - return 0; -} - -/* Exported API */ -unsigned long clk_get_rate(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return 0; - - if (clk->rate != 0) - return clk->rate; - - if (clk->ops->get_rate != NULL) - return clk->ops->get_rate(clk); - - return clk_get_rate(clk->parent); -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(!clk_good(clk))) - return 0; - - if (clk->ops->round_rate) - return clk->ops->round_rate(clk, rate); - - return 0; -} -EXPORT_SYMBOL(clk_round_rate); - -static inline int close_enough(long rate1, long rate2) -{ - return rate1 && !((rate2 - rate1) * 1000 / rate1); -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - if (unlikely(!clk_good(clk))) - goto out; - - if (clk->flags & FIXED_RATE || !clk->ops->set_rate) - goto out; - - else if (!close_enough(clk->rate, rate)) { - ret = clk->ops->set_rate(clk, rate); - if (ret < 0) - goto out; - clk->rate = rate; - if (clk->flags & RATE_PROPAGATES) - propagate_rate(clk); - } else - ret = 0; - -out: - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_enable(struct clk *clk) -{ - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - return -EINVAL; - - if (clk->parent) - clk_enable(clk->parent); - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - clk->usage++; - if (clk->ops && clk->ops->enable) - clk->ops->enable(clk); - - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - return 0; -} -EXPORT_SYMBOL(clk_enable); - -static void local_clk_disable(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return; - - if (clk->usage == 0 && clk->ops->disable) - clk->ops->disable(clk); - - if (clk->parent) - local_clk_disable(clk->parent); -} - -void clk_disable(struct clk *clk) -{ - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - return; - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - if ((--clk->usage) == 0 && clk->ops->disable) - clk->ops->disable(clk); - - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - if (clk->parent) - clk_disable(clk->parent); -} -EXPORT_SYMBOL(clk_disable); - -/* Some additional API */ -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -ENODEV; - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - goto out; - - if (!clk->ops->set_parent) - goto out; - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - ret = clk->ops->set_parent(clk, parent); - if (!ret) { - /* disable if usage count is 0 */ - local_clk_disable(parent); - - parent->usage += clk->usage; - clk->parent->usage -= clk->usage; - - /* disable if new usage count is 0 */ - local_clk_disable(clk->parent); - - clk->parent = parent; - } - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - -out: - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return NULL; - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -static int __init clk_init(void) -{ - struct clk_lookup *cl; - struct clk_ops *ops; - - spin_lock_init(&clocks_lock); - - for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks); - cl++) { - if (cl->clk->flags & ENABLED) - clk_enable(cl->clk); - else - local_clk_disable(cl->clk); - - ops = cl->clk->ops; - - if ((cl->clk->flags & NEEDS_INITIALIZATION) && - ops && ops->set_rate) - ops->set_rate(cl->clk, cl->clk->rate); - - if (cl->clk->flags & FIXED_RATE) { - if (cl->clk->flags & RATE_PROPAGATES) - propagate_rate(cl->clk); - } else { - if (ops && ops->get_rate) - ops->get_rate(cl->clk); - } - - if (cl->clk->flags & NEEDS_SET_PARENT) { - if (ops && ops->set_parent) - ops->set_parent(cl->clk, cl->clk->parent); - } - } - clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks)); - return 0; -} - -arch_initcall(clk_init); diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h deleted file mode 100644 index a6611e1..0000000 --- a/arch/arm/plat-stmp3xxx/clock.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Clock control driver for Freescale STMP37XX/STMP378X - internal header file - * - * Author: Vitaly Wool - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__ -#define __ARCH_ARM_STMX3XXX_CLOCK_H__ - -#ifndef __ASSEMBLER__ - -struct clk_ops { - int (*enable) (struct clk *); - int (*disable) (struct clk *); - long (*get_rate) (struct clk *); - long (*round_rate) (struct clk *, u32); - int (*set_rate) (struct clk *, u32); - int (*set_parent) (struct clk *, struct clk *); -}; - -struct clk { - struct clk *parent; - u32 rate; - u32 flags; - u8 scale_shift; - u8 enable_shift; - u8 bypass_shift; - u8 busy_bit; - s8 usage; - int enable_wait; - int enable_negate; - u32 saved_div; - void __iomem *enable_reg; - void __iomem *scale_reg; - void __iomem *bypass_reg; - void __iomem *busy_reg; - struct clk_ops *ops; -}; - -#endif /* __ASSEMBLER__ */ - -/* Flags */ -#define RATE_PROPAGATES (1<<0) -#define NEEDS_INITIALIZATION (1<<1) -#define PARENT_SET_RATE (1<<2) -#define FIXED_RATE (1<<3) -#define ENABLED (1<<4) -#define NEEDS_SET_PARENT (1<<5) - -#endif diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c deleted file mode 100644 index 37b8a09..0000000 --- a/arch/arm/plat-stmp3xxx/core.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X core routines - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include - -#include -#include -#include -#include - -static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable) -{ - u32 c; - int timeout; - - /* the process of software reset of IP block is done - in several steps: - - - clear SFTRST and wait for block is enabled; - - clear clock gating (CLKGATE bit); - - set the SFTRST again and wait for block is in reset; - - clear SFTRST and wait for reset completion. - */ - c = __raw_readl(hwreg); - c &= ~(1<<31); /* clear SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<31)) == 0) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when enabling\n", - __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<30); /* clear CLKGATE */ - __raw_writel(c, hwreg); - - if (!just_enable) { - c = __raw_readl(hwreg); - c |= (1<<31); /* now again set SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* poll until CLKGATE set */ - if (__raw_readl(hwreg) & (1<<30)) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when resetting\n", - __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<31); /* clear SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<31)) == 0) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when enabling " - "after reset\n", __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<30); /* clear CLKGATE */ - __raw_writel(c, hwreg); - } - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<30)) == 0) - break; - - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when unclockgating\n", - __func__, hwreg); - return -ETIME; - } - - return 0; -} - -int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable) -{ - int try = 10; - int r; - - while (try--) { - r = __stmp3xxx_reset_block(hwreg, just_enable); - if (!r) - break; - pr_debug("%s: try %d failed\n", __func__, 10 - try); - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_reset_block); - -struct platform_device stmp3xxx_dbguart = { - .name = "stmp3xxx-dbguart", - .id = -1, -}; - -void __init stmp3xxx_init(void) -{ - /* Turn off auto-slow and other tricks */ - stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - - stmp3xxx_dma_init(); -} diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c deleted file mode 100644 index 68fed4b..0000000 --- a/arch/arm/plat-stmp3xxx/devices.c +++ /dev/null @@ -1,389 +0,0 @@ -/* -* Freescale STMP37XX/STMP378X platform devices -* -* Embedded Alley Solutions, Inc -* -* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. -* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. -*/ - -/* -* The code contained herein is licensed under the GNU General Public -* License. You may obtain a copy of the GNU General Public License -* Version 2 or later at the following locations: -* -* http://www.opensource.org/licenses/gpl-license.html -* http://www.gnu.org/copyleft/gpl.html -*/ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static u64 common_dmamask = DMA_BIT_MASK(32); - -static struct resource appuart_resources[] = { - { - .start = IRQ_UARTAPP_INTERNAL, - .end = IRQ_UARTAPP_INTERNAL, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_UARTAPP_RX_DMA, - .end = IRQ_UARTAPP_RX_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_UARTAPP_TX_DMA, - .end = IRQ_UARTAPP_TX_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = REGS_UARTAPP1_PHYS, - .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE, - .flags = IORESOURCE_MEM, - }, { - /* Rx DMA channel */ - .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX), - .flags = IORESOURCE_DMA, - }, { - /* Tx DMA channel */ - .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX), - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device stmp3xxx_appuart = { - .name = "stmp3xxx-appuart", - .id = 0, - .resource = appuart_resources, - .num_resources = ARRAY_SIZE(appuart_resources), - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device stmp3xxx_watchdog = { - .name = "stmp3xxx_wdt", - .id = -1, -}; - -static struct resource ts_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_TOUCH_DETECT, - .end = IRQ_TOUCH_DETECT, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_LRADC_CH5, - .end = IRQ_LRADC_CH5, - }, -}; - -struct platform_device stmp3xxx_touchscreen = { - .name = "stmp3xxx_ts", - .id = -1, - .resource = ts_resource, - .num_resources = ARRAY_SIZE(ts_resource), -}; - -/* -* Keypad device -*/ -struct platform_device stmp3xxx_keyboard = { - .name = "stmp3xxx-keyboard", - .id = -1, -}; - -static struct resource gpmi_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_GPMI_PHYS, - .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_GPMI_DMA, - .end = IRQ_GPMI_DMA, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH), - }, -}; - -struct platform_device stmp3xxx_gpmi = { - .name = "gpmi", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = gpmi_resources, - .num_resources = ARRAY_SIZE(gpmi_resources), -}; - -static struct resource mmc1_resource[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_SSP1_PHYS, - .end = REGS_SSP1_PHYS + REGS_SSP_SIZE, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_SSP1_DMA, - .end = IRQ_SSP1_DMA, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_SSP_ERROR, - .end = IRQ_SSP_ERROR, - }, -}; - -struct platform_device stmp3xxx_mmc = { - .name = "stmp3xxx-mmc", - .id = 1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = mmc1_resource, - .num_resources = ARRAY_SIZE(mmc1_resource), -}; - -static struct resource usb_resources[] = { - { - .start = REGS_USBCTRL_PHYS, - .end = REGS_USBCTRL_PHYS + SZ_4K, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_USB_CTRL, - .end = IRQ_USB_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_udc = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = usb_resources, - .num_resources = ARRAY_SIZE(usb_resources), -}; - -struct platform_device stmp3xxx_ehci = { - .name = "fsl-ehci", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = usb_resources, - .num_resources = ARRAY_SIZE(usb_resources), -}; - -static struct resource rtc_resources[] = { - { - .start = REGS_RTC_PHYS, - .end = REGS_RTC_PHYS + REGS_RTC_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_RTC_ALARM, - .end = IRQ_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_RTC_1MSEC, - .end = IRQ_RTC_1MSEC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_rtc = { - .name = "stmp3xxx-rtc", - .id = -1, - .resource = rtc_resources, - .num_resources = ARRAY_SIZE(rtc_resources), -}; - -static struct resource ssp1_resources[] = { - { - .start = REGS_SSP1_PHYS, - .end = REGS_SSP1_PHYS + REGS_SSP_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_SSP1_DMA, - .end = IRQ_SSP1_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .flags = IORESOURCE_DMA, - }, -}; - -static struct resource ssp2_resources[] = { - { - .start = REGS_SSP2_PHYS, - .end = REGS_SSP2_PHYS + REGS_SSP_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_SSP2_DMA, - .end = IRQ_SSP2_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH), - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device stmp3xxx_spi1 = { - .name = "stmp3xxx_ssp", - .id = 1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = ssp1_resources, - .num_resources = ARRAY_SIZE(ssp1_resources), -}; - -struct platform_device stmp3xxx_spi2 = { - .name = "stmp3xxx_ssp", - .id = 2, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = ssp2_resources, - .num_resources = ARRAY_SIZE(ssp2_resources), -}; - -static struct resource fb_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_LCDIF_DMA, - .end = IRQ_LCDIF_DMA, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_LCDIF_ERROR, - .end = IRQ_LCDIF_ERROR, - }, { - .flags = IORESOURCE_MEM, - .start = REGS_LCDIF_PHYS, - .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE, - }, -}; - -struct platform_device stmp3xxx_framebuffer = { - .name = "stmp3xxx-fb", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(fb_resource), - .resource = fb_resource, -}; - -#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \ - static char *cmdline_device_##name; \ - static int cmdline_device_##name##_setup(char *dev) \ - { \ - cmdline_device_##name = dev + 1; \ - return 0; \ - } \ - __setup(#name, cmdline_device_##name##_setup); \ - int stmp3xxx_##name##_device_register(void) \ - { \ - struct platform_device *d = NULL; \ - if (!cmdline_device_##name || \ - !strcmp(cmdline_device_##name, #dev1)) \ - d = &stmp3xxx_##dev1; \ - else if (!strcmp(cmdline_device_##name, #dev2)) \ - d = &stmp3xxx_##dev2; \ - else \ - printk(KERN_ERR"Unknown %s assignment '%s'.\n", \ - #name, cmdline_device_##name); \ - return d ? platform_device_register(d) : -ENOENT; \ - } - -CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1) -CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2) - -struct platform_device stmp3xxx_backlight = { - .name = "stmp3xxx-bl", - .id = -1, -}; - -struct platform_device stmp3xxx_rotdec = { - .name = "stmp3xxx-rotdec", - .id = -1, -}; - -struct platform_device stmp3xxx_persistent = { - .name = "stmp3xxx-persistent", - .id = -1, -}; - -struct platform_device stmp3xxx_dcp_bootstream = { - .name = "stmp3xxx-dcpboot", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dcp_resources[] = { - { - .start = IRQ_DCP_VMI, - .end = IRQ_DCP_VMI, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_DCP, - .end = IRQ_DCP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_dcp = { - .name = "stmp3xxx-dcp", - .id = -1, - .resource = dcp_resources, - .num_resources = ARRAY_SIZE(dcp_resources), - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource battery_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_VDD5V, - .end = IRQ_VDD5V, - }, -}; - -struct platform_device stmp3xxx_battery = { - .name = "stmp3xxx-battery", - .resource = battery_resource, - .num_resources = ARRAY_SIZE(battery_resource), -}; diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c deleted file mode 100644 index b4dcf8c..0000000 --- a/arch/arm/plat-stmp3xxx/dma.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * DMA helper routines for Freescale STMP37XX/STMP378X - * - * Author: dmitry pervushin - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command); -static const size_t pool_alignment = 8; -static struct stmp3xxx_dma_user { - void *pool; - int inuse; - const char *name; -} channels[MAX_DMA_CHANNELS]; - -#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS) -#define IS_USED(ch) (channels[ch].inuse) - -int stmp3xxx_dma_request(int ch, struct device *dev, const char *name) -{ - struct stmp3xxx_dma_user *user; - int err = 0; - - user = channels + ch; - if (!IS_VALID_CHANNEL(ch)) { - err = -ENODEV; - goto out; - } - if (IS_USED(ch)) { - err = -EBUSY; - goto out; - } - /* Create a pool to allocate dma commands from */ - user->pool = dma_pool_create(name, dev, pool_item_size, - pool_alignment, PAGE_SIZE); - if (user->pool == NULL) { - err = -ENOMEM; - goto out; - } - user->name = name; - user->inuse++; -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_request); - -int stmp3xxx_dma_release(int ch) -{ - struct stmp3xxx_dma_user *user = channels + ch; - int err = 0; - - if (!IS_VALID_CHANNEL(ch)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(ch)) { - err = -EBUSY; - goto out; - } - BUG_ON(user->pool == NULL); - dma_pool_destroy(user->pool); - user->inuse--; -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_release); - -int stmp3xxx_dma_read_semaphore(int channel) -{ - int sem = -1; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + - STMP3XXX_DMA_CHANNEL(channel) * 0x70); - sem &= BM_APBH_CHn_SEMA_PHORE; - sem >>= BP_APBH_CHn_SEMA_PHORE; - break; - - case STMP3XXX_BUS_APBX: - sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + - STMP3XXX_DMA_CHANNEL(channel) * 0x70); - sem &= BM_APBX_CHn_SEMA_PHORE; - sem >>= BP_APBX_CHn_SEMA_PHORE; - break; - default: - BUG(); - } - return sem; -} -EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore); - -int stmp3xxx_dma_allocate_command(int channel, - struct stmp3xxx_dma_descriptor *descriptor) -{ - struct stmp3xxx_dma_user *user = channels + channel; - int err = 0; - - if (!IS_VALID_CHANNEL(channel)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(channel)) { - err = -EBUSY; - goto out; - } - if (descriptor == NULL) { - err = -EINVAL; - goto out; - } - - /* Allocate memory for a command from the buffer */ - descriptor->command = - dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle); - - /* Check it worked */ - if (!descriptor->command) { - err = -ENOMEM; - goto out; - } - - memset(descriptor->command, 0, pool_item_size); -out: - WARN_ON(err); - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_allocate_command); - -int stmp3xxx_dma_free_command(int channel, - struct stmp3xxx_dma_descriptor *descriptor) -{ - int err = 0; - - if (!IS_VALID_CHANNEL(channel)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(channel)) { - err = -EBUSY; - goto out; - } - - /* Return the command memory to the pool */ - dma_pool_free(channels[channel].pool, descriptor->command, - descriptor->handle); - - /* Initialise descriptor so we're not tempted to use it */ - descriptor->command = NULL; - descriptor->handle = 0; - descriptor->virtual_buf_ptr = NULL; - descriptor->next_descr = NULL; - - WARN_ON(err); -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_free_command); - -void stmp3xxx_dma_go(int channel, - struct stmp3xxx_dma_descriptor *head, u32 semaphore) -{ - int ch = STMP3XXX_DMA_CHANNEL(channel); - void __iomem *c, *s; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch; - s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch; - break; - - case STMP3XXX_BUS_APBX: - c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch; - s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch; - break; - - default: - return; - } - - /* Set next command */ - __raw_writel(head->handle, c); - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - __raw_writel(semaphore, s); -} -EXPORT_SYMBOL(stmp3xxx_dma_go); - -int stmp3xxx_dma_running(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + - 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & - BM_APBH_CHn_SEMA_PHORE; - - case STMP3XXX_BUS_APBX: - return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + - 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & - BM_APBX_CHn_SEMA_PHORE; - default: - BUG(); - return 0; - } -} -EXPORT_SYMBOL(stmp3xxx_dma_running); - -/* - * Circular dma chain management - */ -void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain) -{ - int i; - - for (i = 0; i < chain->total_count; i++) - stmp3xxx_dma_free_command( - STMP3XXX_DMA(chain->channel, chain->bus), - &chain->chain[i]); -} -EXPORT_SYMBOL(stmp3xxx_dma_free_chain); - -int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, - struct stmp3xxx_dma_descriptor descriptors[], - unsigned items) -{ - int i; - int err = 0; - - if (items == 0) - return err; - - for (i = 0; i < items; i++) { - err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]); - if (err) { - WARN_ON(err); - /* - * Couldn't allocate the whole chain. - * deallocate what has been allocated - */ - if (i) { - do { - stmp3xxx_dma_free_command(ch, - &descriptors - [i]); - } while (i-- > 0); - } - return err; - } - - /* link them! */ - if (i > 0) { - descriptors[i - 1].next_descr = &descriptors[i]; - descriptors[i - 1].command->next = - descriptors[i].handle; - } - } - - /* make list circular */ - descriptors[items - 1].next_descr = &descriptors[0]; - descriptors[items - 1].command->next = descriptors[0].handle; - - chain->total_count = items; - chain->chain = descriptors; - chain->free_index = 0; - chain->active_index = 0; - chain->cooked_index = 0; - chain->free_count = items; - chain->active_count = 0; - chain->cooked_count = 0; - chain->bus = STMP3XXX_DMA_BUS(ch); - chain->channel = STMP3XXX_DMA_CHANNEL(ch); - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_make_chain); - -void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain) -{ - BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus))); - chain->free_index = 0; - chain->active_index = 0; - chain->cooked_index = 0; - chain->free_count = chain->total_count; - chain->active_count = 0; - chain->cooked_count = 0; -} -EXPORT_SYMBOL(stmp37xx_circ_clear_chain); - -void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain, - unsigned count) -{ - BUG_ON(chain->cooked_count < count); - - chain->cooked_count -= count; - chain->cooked_index += count; - chain->cooked_index %= chain->total_count; - chain->free_count += count; -} -EXPORT_SYMBOL(stmp37xx_circ_advance_free); - -void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, - unsigned count) -{ - void __iomem *c; - u32 mask_clr, mask; - BUG_ON(chain->free_count < count); - - chain->free_count -= count; - chain->free_index += count; - chain->free_index %= chain->total_count; - chain->active_count += count; - - switch (chain->bus) { - case STMP3XXX_BUS_APBH: - c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel; - mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA; - mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA); - break; - case STMP3XXX_BUS_APBX: - c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel; - mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA; - mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA); - break; - default: - BUG(); - return; - } - - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - stmp3xxx_clearl(mask_clr, c); - stmp3xxx_setl(mask, c); -} -EXPORT_SYMBOL(stmp37xx_circ_advance_active); - -unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain) -{ - unsigned cooked; - - cooked = chain->active_count - - stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus)); - - chain->active_count -= cooked; - chain->active_index += cooked; - chain->active_index %= chain->total_count; - - chain->cooked_count += cooked; - - return cooked; -} -EXPORT_SYMBOL(stmp37xx_circ_advance_cooked); - -void stmp3xxx_dma_set_alt_target(int channel, int function) -{ -#if defined(CONFIG_ARCH_STMP37XX) - unsigned bits = 4; -#elif defined(CONFIG_ARCH_STMP378X) - unsigned bits = 2; -#else -#error wrong arch -#endif - int shift = STMP3XXX_DMA_CHANNEL(channel) * bits; - unsigned mask = (1<= (1< - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_CPU_H -#define __ASM_PLAT_CPU_H - -#ifdef CONFIG_ARCH_STMP37XX -#define cpu_is_stmp37xx() (1) -#else -#define cpu_is_stmp37xx() (0) -#endif - -#ifdef CONFIG_ARCH_STMP378X -#define cpu_is_stmp378x() (1) -#else -#define cpu_is_stmp378x() (0) -#endif - -#endif /* __ASM_PLAT_CPU_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S deleted file mode 100644 index d3a0985..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Debugging macro include header - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro addruart, rp, rv - mov \rp, #0x00070000 - add \rv, \rp, #0xf0000000 @ virtual base - add \rp, \rp, #0x80000000 @ physical base - .endm - - .macro senduart,rd,rx - strb \rd, [\rx, #0] @ data register at 0 - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full - bne 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy - bne 1001b - .endm diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h deleted file mode 100644 index 7c58557..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/dma.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X DMA helper interface - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_STMP3XXX_DMA_H -#define __ASM_PLAT_STMP3XXX_DMA_H - -#include -#include - -#if !defined(MAX_PIO_WORDS) -#define MAX_PIO_WORDS (15) -#endif - -#define STMP3XXX_BUS_APBH 0 -#define STMP3XXX_BUS_APBX 1 -#define STMP3XXX_DMA_MAX_CHANNEL 16 -#define STMP3XXX_DMA_BUS(dma) ((dma) / 16) -#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16) -#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel)) -#define MAX_DMA_ADDRESS 0xffffffff -#define MAX_DMA_CHANNELS 32 - -struct stmp3xxx_dma_command { - u32 next; - u32 cmd; - union { - u32 buf_ptr; - u32 alternate; - }; - u32 pio_words[MAX_PIO_WORDS]; -}; - -struct stmp3xxx_dma_descriptor { - struct stmp3xxx_dma_command *command; - dma_addr_t handle; - - /* The virtual address of the buffer pointer */ - void *virtual_buf_ptr; - /* The next descriptor in a the DMA chain (optional) */ - struct stmp3xxx_dma_descriptor *next_descr; -}; - -struct stmp37xx_circ_dma_chain { - unsigned total_count; - struct stmp3xxx_dma_descriptor *chain; - - unsigned free_index; - unsigned free_count; - unsigned active_index; - unsigned active_count; - unsigned cooked_index; - unsigned cooked_count; - - int bus; - unsigned channel; -}; - -static inline struct stmp3xxx_dma_descriptor - *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain) -{ - return &(chain->chain[chain->free_index]); -} - -static inline struct stmp3xxx_dma_descriptor - *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain) -{ - return &(chain->chain[chain->cooked_index]); -} - -int stmp3xxx_dma_request(int ch, struct device *dev, const char *name); -int stmp3xxx_dma_release(int ch); -int stmp3xxx_dma_allocate_command(int ch, - struct stmp3xxx_dma_descriptor *descriptor); -int stmp3xxx_dma_free_command(int ch, - struct stmp3xxx_dma_descriptor *descriptor); -void stmp3xxx_dma_continue(int channel, u32 semaphore); -void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head, - u32 semaphore); -int stmp3xxx_dma_running(int ch); -int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, - struct stmp3xxx_dma_descriptor descriptors[], - unsigned items); -void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain); -void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain); -void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain, - unsigned count); -void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, - unsigned count); -unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain); -int stmp3xxx_dma_read_semaphore(int ch); -void stmp3xxx_dma_init(void); -void stmp3xxx_dma_set_alt_target(int ch, int target); -void stmp3xxx_dma_suspend(void); -void stmp3xxx_dma_resume(void); - -/* - * STMP37xx and STMP378x have different DMA control - * registers layout - */ - -void stmp3xxx_arch_dma_freeze(int ch); -void stmp3xxx_arch_dma_unfreeze(int ch); -void stmp3xxx_arch_dma_reset_channel(int ch); -void stmp3xxx_arch_dma_enable_interrupt(int ch); -void stmp3xxx_arch_dma_clear_interrupt(int ch); -int stmp3xxx_arch_dma_is_interrupt(int ch); - -static inline void stmp3xxx_dma_reset_channel(int ch) -{ - stmp3xxx_arch_dma_reset_channel(ch); -} - - -static inline void stmp3xxx_dma_freeze(int ch) -{ - stmp3xxx_arch_dma_freeze(ch); -} - -static inline void stmp3xxx_dma_unfreeze(int ch) -{ - stmp3xxx_arch_dma_unfreeze(ch); -} - -static inline void stmp3xxx_dma_enable_interrupt(int ch) -{ - stmp3xxx_arch_dma_enable_interrupt(ch); -} - -static inline void stmp3xxx_dma_clear_interrupt(int ch) -{ - stmp3xxx_arch_dma_clear_interrupt(ch); -} - -static inline int stmp3xxx_dma_is_interrupt(int ch) -{ - return stmp3xxx_arch_dma_is_interrupt(ch); -} - -#endif /* __ASM_PLAT_STMP3XXX_DMA_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h deleted file mode 100644 index a8b5792..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X GPIO interface - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_GPIO_H -#define __ASM_PLAT_GPIO_H - -#define ARCH_NR_GPIOS (32 * 3) -#define gpio_to_irq(gpio) __gpio_to_irq(gpio) -#define gpio_get_value(gpio) __gpio_get_value(gpio) -#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value) - -#include - -#endif /* __ASM_PLAT_GPIO_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h deleted file mode 100644 index e166432..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __MACH_GPMI_H - -#include -#include - -struct gpmi_platform_data { - void *pins; - int nr_parts; - struct mtd_partition *parts; - const char *part_types[]; -}; -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h deleted file mode 100644 index 47b8978..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/hardware.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file contains the hardware definitions of the Freescale STMP3XXX - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define IO_BASE 0xF0000000 /* VA of IO */ -#define IO_SIZE 0x00100000 /* How much? */ -#define IO_START 0x80000000 /* PA of IO */ - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h deleted file mode 100644 index d08b1b7..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/io.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) -#define __mem_isa(a) (a) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h deleted file mode 100644 index 61fa548..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/memory.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0x40000000) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h deleted file mode 100644 index ba81e15..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/mmc.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _MACH_MMC_H -#define _MACH_MMC_H - -#include - -struct stmp3xxxmmc_platform_data { - int (*get_wp)(void); - unsigned long (*setclock)(void __iomem *base, unsigned long); - void (*cmd_pullup)(int); - int (*hw_init)(void); - void (*hw_release)(void); -}; - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h deleted file mode 100644 index cc5af82..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X Pin Multiplexing - * - * Author: Vladislav Buzov - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __PINMUX_H -#define __PINMUX_H - -#include -#include -#include -#include - -/* Pin definitions */ -#include "pins.h" -#include - -/* - * Each pin may be routed up to four different HW interfaces - * including GPIO - */ -enum pin_fun { - PIN_FUN1 = 0, - PIN_FUN2, - PIN_FUN3, - PIN_GPIO, -}; - -/* - * Each pin may have different output drive strength in range from - * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths. - */ -enum pin_strength { - PIN_4MA = 0, - PIN_8MA, - PIN_12MA, - PIN_16MA, - PIN_20MA, -}; - -/* - * Each pin can be programmed for 1.8V or 3.3V - */ -enum pin_voltage { - PIN_1_8V = 0, - PIN_3_3V, -}; - -/* - * Structure to define a group of pins and their parameters - */ -struct pin_desc { - unsigned id; - enum pin_fun fun; - enum pin_strength strength; - enum pin_voltage voltage; - unsigned pullup:1; -}; - -struct pin_group { - struct pin_desc *pins; - int nr_pins; -}; - -/* Set pin drive strength */ -void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, - const char *label); - -/* Set pin voltage */ -void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, - const char *label); - -/* Enable pull-up resistor for a pin */ -void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label); - -/* - * Request a pin ownership, only one module (identified by @label) - * may own a pin. - */ -int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label); - -/* Release pin */ -void stmp3xxx_release_pin(unsigned id, const char *label); - -void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun); - -/* - * Each bank is associated with a number of registers to control - * pin function, drive strength, voltage and pull-up reigster. The - * number of registers of a given type depends on the number of bits - * describin particular pin. - */ -#define HW_MUXSEL_NUM 2 /* registers per bank */ -#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */ -#define HW_MUXSEL_PIN_NUM 16 /* pins per register */ -#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */ -#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */ - -#define HW_DRIVE_NUM 4 /* registers per bank */ -#define HW_DRIVE_PIN_LEN 4 /* bits per pin */ -#define HW_DRIVE_PIN_NUM 8 /* pins per register */ -#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */ -#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */ -#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */ - - -struct stmp3xxx_pinmux_bank { - struct gpio_chip chip; - - /* Pins allocation map */ - unsigned long pin_map; - - /* Pin owner names */ - const char *pin_labels[32]; - - /* Bank registers */ - void __iomem *hw_muxsel[HW_MUXSEL_NUM]; - void __iomem *hw_drive[HW_DRIVE_NUM]; - void __iomem *hw_pull; - - void __iomem *pin2irq, - *irqlevel, - *irqpolarity, - *irqen, - *irqstat; - - /* HW MUXSEL register function bit values */ - u8 functions[HW_MUXSEL_PINFUN_NUM]; - - /* - * HW DRIVE register strength bit values: - * 0xff - requested strength is not supported for this bank - */ - u8 strengths[HW_DRIVE_PINDRV_NUM]; - - /* GPIO things */ - void __iomem *hw_gpio_in, - *hw_gpio_out, - *hw_gpio_doe; - int irq, virq; -}; - -int __init stmp3xxx_pinmux_init(int virtual_irq_start); - -#endif /* __PINMUX_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h deleted file mode 100644 index c573318..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions - * - * Author: Vladislav Buzov - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_PINS_H -#define __ASM_PLAT_PINS_H - -#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin) -#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32) -#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32) - -/* - * Special invalid pin identificator to show a pin doesn't exist - */ -#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF) - -#endif /* __ASM_PLAT_PINS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h deleted file mode 100644 index 7007dda..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/platform.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_PLATFORM_H -#define __ASM_PLAT_PLATFORM_H - -#ifndef __ASSEMBLER__ -#include -#endif -#include - -/* Virtual address where registers are mapped */ -#define STMP3XXX_REGS_PHBASE 0x80000000 -#ifdef __ASSEMBLER__ -#define STMP3XXX_REGS_BASE 0xF0000000 -#else -#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000 -#endif -#define STMP3XXX_REGS_SIZE SZ_1M - -/* Virtual address where OCRAM is mapped */ -#define STMP3XXX_OCRAM_PHBASE 0x00000000 -#ifdef __ASSEMBLER__ -#define STMP3XXX_OCRAM_BASE 0xf1000000 -#else -#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000 -#endif -#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K) - -#ifdef CONFIG_ARCH_STMP37XX -#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD -#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR -#endif - -#ifdef CONFIG_ARCH_STMP378X -#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD -#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR -#endif - -#define HW_STMP3XXX_SET 0x04 -#define HW_STMP3XXX_CLR 0x08 -#define HW_STMP3XXX_TOG 0x0c - -#ifndef __ASSEMBLER__ -static inline void stmp3xxx_clearl(u32 v, void __iomem *r) -{ - __raw_writel(v, r + HW_STMP3XXX_CLR); -} - -static inline void stmp3xxx_setl(u32 v, void __iomem *r) -{ - __raw_writel(v, r + HW_STMP3XXX_SET); -} -#endif - -#define BF(value, field) (((value) << BP_##field) & BM_##field) - -#endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h deleted file mode 100644 index 2e300fe..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X core structure and function declarations - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_STMP3XXX_H -#define __ASM_PLAT_STMP3XXX_H - -#include - -extern struct sys_timer stmp3xxx_timer; - -void stmp3xxx_init_irq(struct irq_chip *chip); -void stmp3xxx_init(void); -int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable); -extern struct platform_device stmp3xxx_dbguart, - stmp3xxx_appuart, - stmp3xxx_watchdog, - stmp3xxx_touchscreen, - stmp3xxx_keyboard, - stmp3xxx_gpmi, - stmp3xxx_mmc, - stmp3xxx_udc, - stmp3xxx_ehci, - stmp3xxx_rtc, - stmp3xxx_spi1, - stmp3xxx_spi2, - stmp3xxx_backlight, - stmp3xxx_rotdec, - stmp3xxx_dcp, - stmp3xxx_dcp_bootstream, - stmp3xxx_persistent, - stmp3xxx_framebuffer, - stmp3xxx_battery; -int stmp3xxx_ssp1_device_register(void); -int stmp3xxx_ssp2_device_register(void); - -struct pin_group; -void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label); -int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label); - -#endif /* __ASM_PLAT_STMP3XXX_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h deleted file mode 100644 index 28a9888..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/system.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include -#include -#include -#include - -static inline void arch_idle(void) -{ - /* - * This should do all the clock switching - * and wait for interrupt tricks - */ - - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - /* Set BATTCHRG to default value */ - __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE); - - /* Set MINPWR to default value */ - __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR); - - /* Reset digital side of chip (but not power or RTC) */ - __raw_writel(BM_CLKCTRL_RESET_DIG, - REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET); - - /* Should not return */ -} - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h deleted file mode 100644 index 3373985..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/timex.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 1999 ARM Limited - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * System time clock is sourced from the 32k clock - */ -#define CLOCK_TICK_RATE (32768) diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h deleted file mode 100644 index f79f5ee..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_UNCOMPRESS_H -#define __ASM_PLAT_UNCOMPRESS_H - -/* - * Register includes are for when the MMU enabled; we need to define our - * own stuff here for pre-MMU use - */ -#define UARTDBG_BASE 0x80070000 -#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c]) - -/* - * This does not append a newline - */ -static void putc(char c) -{ - /* Wait for TX fifo empty */ - while ((UART(6) & (1<<7)) == 0) - continue; - - /* Write byte */ - UART(0) = c; - - /* Wait for last bit to exit the UART */ - while (UART(6) & (1<<3)) - continue; -} - -static void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() - -#define arch_decomp_wdog() - -#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h deleted file mode 100644 index 943c1a2..0000000 --- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define VMALLOC_END 0xf0000000UL diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c deleted file mode 100644 index 6fdf9ac..0000000 --- a/arch/arm/plat-stmp3xxx/irq.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X common interrupt handling code - * - * Author: Vladislav Buzov - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -void __init stmp3xxx_init_irq(struct irq_chip *chip) -{ - unsigned int i, lv; - - /* Reset the interrupt controller */ - stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true); - - /* Disable all interrupts initially */ - for (i = 0; i < NR_REAL_IRQS; i++) { - chip->irq_mask(irq_get_irq_data(i)); - irq_set_chip_and_handler(i, chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - - /* Ensure vector is cleared */ - for (lv = 0; lv < 4; lv++) - __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c deleted file mode 100644 index 3def03b..0000000 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Freescale STMP378X/STMP378X Pin Multiplexing - * - * Author: Vladislav Buzov - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define DEBUG -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define NR_BANKS ARRAY_SIZE(pinmux_banks) -static struct stmp3xxx_pinmux_bank pinmux_banks[] = { - [0] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0, - .irq = IRQ_GPIO0, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0, - }, - [1] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1, - .irq = IRQ_GPIO1, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1, - }, - [2] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2, - .irq = IRQ_GPIO2, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2, - }, - [3] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14, - NULL, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3, - .functions = {0x0, 0x1, 0x2, 0x3}, - .strengths = {0x0, 0x1, 0x2, 0x3, 0xff}, - }, -}; - -static inline struct stmp3xxx_pinmux_bank * -stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin) -{ - unsigned b, p; - - b = STMP3XXX_PINID_TO_BANK(id); - p = STMP3XXX_PINID_TO_PINNUM(id); - BUG_ON(b >= NR_BANKS); - if (bank) - *bank = b; - if (pin) - *pin = p; - return &pinmux_banks[b]; -} - -/* Check if requested pin is owned by caller */ -static int stmp3xxx_check_pin(unsigned id, const char *label) -{ - unsigned pin; - struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin); - - if (!test_bit(pin, &pm->pin_map)) { - printk(KERN_WARNING - "%s: Accessing free pin %x, caller %s\n", - __func__, id, label); - - return -EINVAL; - } - - if (label && pm->pin_labels[pin] && - strcmp(label, pm->pin_labels[pin])) { - printk(KERN_WARNING - "%s: Wrong pin owner %x, caller %s owner %s\n", - __func__, id, label, pm->pin_labels[pin]); - - return -EINVAL; - } - return 0; -} - -void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, - const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwdrive; - u32 shift, val; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label, - bank, pin, strength); - - hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM]; - shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN; - val = pbank->strengths[strength]; - if (val == 0xff) { - printk(KERN_WARNING - "%s: strength is not supported for bank %d, caller %s", - __func__, bank, label); - return; - } - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: writing 0x%x to 0x%p register\n", __func__, - val << shift, hwdrive); - stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive); - stmp3xxx_setl(val << shift, hwdrive); -} - -void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, - const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwdrive; - u32 shift; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label, - bank, pin, voltage); - - hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM]; - shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN; - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: changing 0x%x bit in 0x%p register\n", - __func__, HW_DRIVE_PINV_MASK << shift, hwdrive); - if (voltage == PIN_1_8V) - stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive); - else - stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive); -} - -void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwpull; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label, - bank, pin, enable); - - hwpull = pbank->hw_pull; - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: changing 0x%x bit in 0x%p register\n", - __func__, 1 << pin, hwpull); - if (enable) - stmp3xxx_setl(1 << pin, hwpull); - else - stmp3xxx_clearl(1 << pin, hwpull); -} - -int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - u32 bank, pin; - int ret = 0; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label, - bank, pin, fun); - - if (test_bit(pin, &pbank->pin_map)) { - printk(KERN_WARNING - "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n", - __func__, bank, pin, label, pbank->pin_labels[pin]); - return -EBUSY; - } - - set_bit(pin, &pbank->pin_map); - pbank->pin_labels[pin] = label; - - stmp3xxx_set_pin_type(id, fun); - - return ret; -} - -void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwmux; - u32 shift, val; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - - hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM]; - shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; - - val = pbank->functions[fun]; - shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; - pr_debug("%s: writing 0x%x to 0x%p register\n", - __func__, val << shift, hwmux); - stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux); - stmp3xxx_setl(val << shift, hwmux); -} - -void stmp3xxx_release_pin(unsigned id, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin); - - if (stmp3xxx_check_pin(id, label)) - return; - - clear_bit(pin, &pbank->pin_map); - pbank->pin_labels[pin] = NULL; -} - -int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label) -{ - struct pin_desc *pin; - int p; - int err = 0; - - /* Allocate and configure pins */ - for (p = 0; p < pin_group->nr_pins; p++) { - pr_debug("%s: #%d\n", __func__, p); - pin = &pin_group->pins[p]; - - err = stmp3xxx_request_pin(pin->id, pin->fun, label); - if (err) - goto out_err; - - stmp3xxx_pin_strength(pin->id, pin->strength, label); - stmp3xxx_pin_voltage(pin->id, pin->voltage, label); - stmp3xxx_pin_pullup(pin->id, pin->pullup, label); - } - - return 0; - -out_err: - /* Release allocated pins in case of error */ - while (--p >= 0) { - pr_debug("%s: releasing #%d\n", __func__, p); - stmp3xxx_release_pin(pin_group->pins[p].id, label); - } - return err; -} -EXPORT_SYMBOL(stmp3xxx_request_pin_group); - -void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label) -{ - struct pin_desc *pin; - int p; - - for (p = 0; p < pin_group->nr_pins; p++) { - pin = &pin_group->pins[p]; - stmp3xxx_release_pin(pin->id, label); - } -} -EXPORT_SYMBOL(stmp3xxx_release_pin_group); - -static int stmp3xxx_irq_data_to_gpio(struct irq_data *d, - struct stmp3xxx_pinmux_bank **bank, unsigned *gpio) -{ - struct stmp3xxx_pinmux_bank *pm; - - for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++) - if (pm->virq <= d->irq && d->irq < pm->virq + 32) { - *bank = pm; - *gpio = d->irq - pm->virq; - return 0; - } - return -ENOENT; -} - -static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - int l, p; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - switch (type) { - case IRQ_TYPE_EDGE_RISING: - l = 0; p = 1; break; - case IRQ_TYPE_EDGE_FALLING: - l = 0; p = 0; break; - case IRQ_TYPE_LEVEL_HIGH: - l = 1; p = 1; break; - case IRQ_TYPE_LEVEL_LOW: - l = 1; p = 0; break; - default: - pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", - __func__, type); - return -ENXIO; - } - - if (l) - stmp3xxx_setl(1 << gpio, pm->irqlevel); - else - stmp3xxx_clearl(1 << gpio, pm->irqlevel); - if (p) - stmp3xxx_setl(1 << gpio, pm->irqpolarity); - else - stmp3xxx_clearl(1 << gpio, pm->irqpolarity); - return 0; -} - -static void stmp3xxx_pin_ack_irq(struct irq_data *d) -{ - u32 stat; - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stat = __raw_readl(pm->irqstat) & (1 << gpio); - stmp3xxx_clearl(stat, pm->irqstat); -} - -static void stmp3xxx_pin_mask_irq(struct irq_data *d) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stmp3xxx_clearl(1 << gpio, pm->irqen); - stmp3xxx_clearl(1 << gpio, pm->pin2irq); -} - -static void stmp3xxx_pin_unmask_irq(struct irq_data *d) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stmp3xxx_setl(1 << gpio, pm->irqen); - stmp3xxx_setl(1 << gpio, pm->pin2irq); -} - -static inline -struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip) -{ - return container_of(chip, struct stmp3xxx_pinmux_bank, chip); -} - -static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - return pm->virq + offset; -} - -static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - unsigned v; - - v = __raw_readl(pm->hw_gpio_in) & (1 << offset); - return v ? 1 : 0; -} - -static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - if (v) - stmp3xxx_setl(1 << offset, pm->hw_gpio_out); - else - stmp3xxx_clearl(1 << offset, pm->hw_gpio_out); -} - -static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - stmp3xxx_setl(1 << offset, pm->hw_gpio_doe); - stmp3xxx_gpio_set(chip, offset, v); - return 0; -} - -static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe); - return 0; -} - -static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio"); -} - -static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - stmp3xxx_release_pin(chip->base + offset, "gpio"); -} - -static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) -{ - struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq); - int gpio_irq = pm->virq; - u32 stat = __raw_readl(pm->irqstat); - - while (stat) { - if (stat & 1) - generic_handle_irq(gpio_irq); - gpio_irq++; - stat >>= 1; - } -} - -static struct irq_chip gpio_irq_chip = { - .irq_ack = stmp3xxx_pin_ack_irq, - .irq_mask = stmp3xxx_pin_mask_irq, - .irq_unmask = stmp3xxx_pin_unmask_irq, - .irq_set_type = stmp3xxx_set_irqtype, -}; - -int __init stmp3xxx_pinmux_init(int virtual_irq_start) -{ - int b, r = 0; - struct stmp3xxx_pinmux_bank *pm; - int virq; - - for (b = 0; b < 3; b++) { - /* only banks 0,1,2 are allowed to GPIO */ - pm = pinmux_banks + b; - pm->chip.base = 32 * b; - pm->chip.ngpio = 32; - pm->chip.owner = THIS_MODULE; - pm->chip.can_sleep = 1; - pm->chip.exported = 1; - pm->chip.to_irq = stmp3xxx_gpio_to_irq; - pm->chip.direction_input = stmp3xxx_gpio_input; - pm->chip.direction_output = stmp3xxx_gpio_output; - pm->chip.get = stmp3xxx_gpio_get; - pm->chip.set = stmp3xxx_gpio_set; - pm->chip.request = stmp3xxx_gpio_request; - pm->chip.free = stmp3xxx_gpio_free; - pm->virq = virtual_irq_start + b * 32; - - for (virq = pm->virq; virq < pm->virq; virq++) { - gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); - irq_set_chip_and_handler(virq, &gpio_irq_chip, - handle_level_irq); - set_irq_flags(virq, IRQF_VALID); - } - r = gpiochip_add(&pm->chip); - if (r < 0) - break; - irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq); - irq_set_handler_data(pm->irq, pm); - } - return r; -} - -MODULE_AUTHOR("Vladislav Buzov"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c deleted file mode 100644 index c395630..0000000 --- a/arch/arm/plat-stmp3xxx/timer.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * System timer for Freescale STMP37XX/STMP378X - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static irqreturn_t -stmp3xxx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *c = dev_id; - - /* timer 0 */ - if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) & - BM_TIMROT_TIMCTRLn_IRQ) { - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - c->event_handler(c); - } - - /* timer 1 */ - else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1) - & BM_TIMROT_TIMCTRLn_IRQ) { - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - } - - return IRQ_HANDLED; -} - -static cycle_t stmp3xxx_clock_read(struct clocksource *cs) -{ - return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1) - & 0xFFFF0000) >> 16); -} - -static int -stmp3xxx_timrot_set_next_event(unsigned long delta, - struct clock_event_device *dev) -{ - /* reload the timer */ - __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - return 0; -} - -static void -stmp3xxx_timrot_set_mode(enum clock_event_mode mode, - struct clock_event_device *dev) -{ -} - -static struct clock_event_device ckevt_timrot = { - .name = "timrot", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .set_next_event = stmp3xxx_timrot_set_next_event, - .set_mode = stmp3xxx_timrot_set_mode, -}; - -static struct clocksource cksrc_stmp3xxx = { - .name = "cksrc_stmp3xxx", - .rating = 250, - .read = stmp3xxx_clock_read, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static struct irqaction stmp3xxx_timer_irq = { - .name = "stmp3xxx_timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = stmp3xxx_timer_interrupt, - .dev_id = &ckevt_timrot, -}; - - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -static void __init stmp3xxx_init_timer(void) -{ - ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, - ckevt_timrot.shift); - ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); - ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); - ckevt_timrot.cpumask = cpumask_of(0); - - stmp3xxx_reset_block(REGS_TIMROT_BASE, false); - - /* clear two timers */ - __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - - /* configure them */ - __raw_writel( - (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - __raw_writel( - (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - - __raw_writel(CLOCK_TICK_RATE / HZ - 1, - REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - - setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); - - clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE); - clockevents_register_device(&ckevt_timrot); -} - -#ifdef CONFIG_PM - -void stmp3xxx_suspend_timer(void) -{ - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE, - REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL); -} - -void stmp3xxx_resume_timer(void) -{ - stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE, - REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL); - __raw_writel( - 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - __raw_writel( - 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - __raw_writel(CLOCK_TICK_RATE / HZ - 1, - REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); -} - -#else - -#define stmp3xxx_suspend_timer NULL -#define stmp3xxx_resume_timer NULL - -#endif /* CONFIG_PM */ - -struct sys_timer stmp3xxx_timer = { - .init = stmp3xxx_init_timer, - .suspend = stmp3xxx_suspend_timer, - .resume = stmp3xxx_resume_timer, -}; -- cgit v0.10.2 From 7b769bb3e859b0de65999468dd1660e3364f8994 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 7 Apr 2011 13:49:41 +0300 Subject: ARM: Moving Marvell Dove platform defaults to ARMv7 Disabled legacy support for ARMv6 architecture on Dove platform. Latest Dove HW uses only ARMv7 model. Signed-off-by: Konstantin Porotchkin Signed-off-by: Nicolas Pitre diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 377a7a5..44c16f0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -468,7 +468,7 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" - select CPU_V6K + select CPU_V7 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 54bf5ee..d7c3cfa 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_DOVE=y CONFIG_MACH_DOVE_DB=y -CONFIG_CPU_V6=y -CONFIG_CPU_32v6K=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_AEABI=y -- cgit v0.10.2 From 0ffd3c4805446dc00a042140443fd7342a35d0b4 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 7 Apr 2011 13:49:42 +0300 Subject: ARM: Sync Marvell Dove defconfig with latest kernel Re-generate defconfig for Marvell Dove platform Signed-off-by: Konstantin Porotchkin Signed-off-by: Nicolas Pitre diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index d7c3cfa..40db34c 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -42,7 +42,6 @@ CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 -# CONFIG_MISC_DEVICES is not set # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set @@ -57,12 +56,12 @@ CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set # CONFIG_MOUSE_PS2 is not set # CONFIG_SERIO is not set +CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_DEVKMEM is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_PCI is not set CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y @@ -70,12 +69,10 @@ CONFIG_I2C_MV64XXX=y CONFIG_SPI=y CONFIG_SPI_ORION=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set CONFIG_USB=y CONFIG_USB_DEVICEFS=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_STORAGE=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_MV=y @@ -84,7 +81,6 @@ CONFIG_MV_XOR=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_UDF_FS=m @@ -108,23 +104,19 @@ CONFIG_DEBUG_KERNEL=y CONFIG_TIMER_STATS=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_TEA=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_DEFLATE=y -- cgit v0.10.2 From f5178ddd2f09de8b1cfc5e19043892e8b24666cb Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 3 May 2011 15:30:34 -0400 Subject: ARM: PJ4: remove the ARMv6 compatible cache method entries The Marvell PJ4 is ARMv7 capable, so we don't support it in ARMv6 mode anymore. Signed-off-by: Nicolas Pitre Acked-by: Saeed Bishara Acked-by: Haojian Zhuang diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index adf583c..a36f452 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -735,12 +735,6 @@ proc_types: W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush - .word 0x560f5810 @ Marvell PJ4 ARMv6 - .word 0xff0ffff0 - W(b) __armv4_mmu_cache_on - W(b) __armv4_mmu_cache_off - W(b) __armv6_mmu_cache_flush - .word 0x000f0000 @ new CPU Id .word 0x000f0000 W(b) __armv7_mmu_cache_on diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 7c99cb4..ab17cc0 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -175,11 +175,6 @@ cpu_v6_name: .asciz "ARMv6-compatible processor" .size cpu_v6_name, . - cpu_v6_name - .type cpu_pj4_name, #object -cpu_pj4_name: - .asciz "Marvell PJ4 processor" - .size cpu_pj4_name, . - cpu_pj4_name - .align __CPUINIT @@ -305,32 +300,3 @@ __v6_proc_info: .long v6_user_fns .long v6_cache_fns .size __v6_proc_info, . - __v6_proc_info - - .type __pj4_v6_proc_info, #object -__pj4_v6_proc_info: - .long 0x560f5810 - .long 0xff0ffff0 - ALT_SMP(.long \ - PMD_TYPE_SECT | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ | \ - PMD_FLAGS_SMP) - ALT_UP(.long \ - PMD_TYPE_SECT | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ | \ - PMD_FLAGS_UP) - .long PMD_TYPE_SECT | \ - PMD_SECT_XN | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ - b __v6_setup - .long cpu_arch_name - .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS - .long cpu_pj4_name - .long v6_processor_functions - .long v6wbi_tlb_fns - .long v6_user_fns - .long v6_cache_fns - .size __pj4_v6_proc_info, . - __pj4_v6_proc_info -- cgit v0.10.2 From 34cc1a8fe0d3f89f3602b49f1121a99d2bfc5efc Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 19 Apr 2011 15:42:43 -0400 Subject: ARM: zImage: no need to get the decompressed size from the filesystem In commit d239b1dc093d the hardcoded 4x estimate for the decompressed kernel size was replaced by the exact Image file size and passed to the linker as a symbol value. Turns out that this is unneeded as the size is already included at the end of the compressed piggy data. For those compressed formats that don't include this data, the build system already takes care of appending it using size_append in scripts/Makefile.lib. So let's use that instead. Signed-off-by: Nicolas Pitre Tested-by: Shawn Guo Tested-by: Tony Lindgren diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 0c6852d..79b5c62 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -98,8 +98,6 @@ endif ccflags-y := -fpic -fno-builtin asflags-y := -Wa,-march=all -# Provide size of uncompressed kernel to the decompressor via a linker symbol. -LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image) # Supply ZRELADDR to the decompressor via a linker symbol. ifneq ($(CONFIG_AUTO_ZRELADDR),y) LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index d1fd1cf..b541217 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -187,7 +187,7 @@ not_angel: bl cache_on restart: adr r0, LC0 - ldmia r0, {r1, r2, r3, r6, r9, r11, r12} + ldmia r0, {r1, r2, r3, r6, r10, r11, r12} ldr sp, [r0, #28] /* @@ -196,6 +196,20 @@ restart: adr r0, LC0 */ sub r0, r0, r1 @ calculate the delta offset add r6, r6, r0 @ _edata + add r10, r10, r0 @ inflated kernel size location + + /* + * The kernel build system appends the size of the + * decompressed kernel at the end of the compressed data + * in little-endian form. + */ + ldrb r9, [r10, #0] + ldrb lr, [r10, #1] + orr r9, r9, lr, lsl #8 + ldrb lr, [r10, #2] + ldrb r10, [r10, #3] + orr r9, r9, lr, lsl #16 + orr r9, r9, r10, lsl #24 #ifndef CONFIG_ZBOOT_ROM /* malloc space is above the relocated stack (64k max) */ @@ -355,7 +369,7 @@ LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 .word _edata @ r6 - .word _image_size @ r9 + .word input_data_end - 4 @ r10 (inflated size location) .word _got_start @ r11 .word _got_end @ ip .word user_stack_end @ sp -- cgit v0.10.2 From e40f1e9fb342a2e38fae164861a8cff248ceb87b Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 19 Apr 2011 16:13:23 -0400 Subject: ARM: zImage: simplify decompress_kernel() The return value for decompress_kernel() is no longer used. Furthermore, this was obtained and stored in a variable called output_ptr which is a complete misnomer for what is actually the size of the decompressed kernel image. Let's get rid of it. Signed-off-by: Nicolas Pitre Tested-by: Shawn Guo Tested-by: Tony Lindgren diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 4657e87..51b87b5 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -26,8 +26,6 @@ unsigned int __machine_arch_type; #include #include -#include - static void putstr(const char *ptr); extern void error(char *x); @@ -149,13 +147,12 @@ void *memcpy(void *__dest, __const void *__src, size_t __n) } /* - * gzip delarations + * gzip declarations */ extern char input_data[]; extern char input_data_end[]; unsigned char *output_data; -unsigned long output_ptr; unsigned long free_mem_ptr; unsigned long free_mem_end_ptr; @@ -183,13 +180,11 @@ asmlinkage void __div0(void) extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); -unsigned long +void decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, unsigned long free_mem_ptr_end_p, int arch_id) { - unsigned char *tmp; - output_data = (unsigned char *)output_start; free_mem_ptr = free_mem_ptr_p; free_mem_end_ptr = free_mem_ptr_end_p; @@ -197,12 +192,8 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, arch_decomp_setup(); - tmp = (unsigned char *) (((unsigned long)input_data_end) - 4); - output_ptr = get_unaligned_le32(tmp); - putstr("Uncompressing Linux..."); do_decompress(input_data, input_data_end - input_data, output_data, error); putstr(" done, booting the kernel.\n"); - return output_ptr; } -- cgit v0.10.2 From ccc1c7c6c25661f0071a7ebe997abcbf529df3e9 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 21 Apr 2011 21:59:49 -0400 Subject: ARM: zImage: don't ignore error returned from decompress() If decompress() returns an error without calling error(), we must not attempt to boot the resulting kernel. Signed-off-by: Nicolas Pitre Tested-by: Shawn Guo Tested-by: Tony Lindgren diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index 4c72a97..07be5a2 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -44,7 +44,7 @@ extern void error(char *); #include "../../../../lib/decompress_unlzma.c" #endif -void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) +int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) { - decompress(input, len, NULL, NULL, output, NULL, error); + return decompress(input, len, NULL, NULL, output, NULL, error); } diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 51b87b5..65871a7 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -177,7 +177,7 @@ asmlinkage void __div0(void) error("Attempting division by 0!"); } -extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); +extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); void @@ -185,6 +185,8 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, unsigned long free_mem_ptr_end_p, int arch_id) { + int ret; + output_data = (unsigned char *)output_start; free_mem_ptr = free_mem_ptr_p; free_mem_end_ptr = free_mem_ptr_end_p; @@ -193,7 +195,10 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, arch_decomp_setup(); putstr("Uncompressing Linux..."); - do_decompress(input_data, input_data_end - input_data, - output_data, error); - putstr(" done, booting the kernel.\n"); + ret = do_decompress(input_data, input_data_end - input_data, + output_data, error); + if (ret) + error("decompressor returned an error"); + else + putstr(" done, booting the kernel.\n"); } -- cgit v0.10.2 From 8ea0de4b8831513924e3ec6a17bb721fabf97055 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 28 Apr 2011 17:00:17 -0400 Subject: ARM: zImage: remove the static qualifier from global data variables To be able to relocate the .bss section at run time independently from the rest of the code, we must make sure that no GOTOFF relocations are used with .bss symbols. This usually means that no global variables can be marked static unless they're also const. Let's remove the static qualifier from current offenders, or turn them into const variables when possible. Next commit will ensure the build fails if one of those is reintroduced due to otherwise enforced coding standards for the kernel. Signed-off-by: Nicolas Pitre Tested-by: Tony Lindgren diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 47723e8..78d8068 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -25,8 +25,7 @@ #include -static u32 *uart; -static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO); +u32 *uart; /* PORT_16C550A, in polled non-fifo mode */ static void putc(char c) @@ -44,6 +43,8 @@ static inline void flush(void) static inline void set_uart_info(u32 phys, void * __iomem virt) { + u32 *uart_info = (u32 *)(DAVINCI_UART_INFO); + uart = (u32 *)phys; uart_info[0] = phys; uart_info[1] = (u32)virt; diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h index 5483f61..0efa262 100644 --- a/arch/arm/mach-gemini/include/mach/uncompress.h +++ b/arch/arm/mach-gemini/include/mach/uncompress.h @@ -16,7 +16,7 @@ #include #include -static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE; +static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE; /* * The following code assumes the serial port has already been diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h index b247551..4fd7154 100644 --- a/arch/arm/mach-iop32x/include/mach/uncompress.h +++ b/arch/arm/mach-iop32x/include/mach/uncompress.h @@ -7,7 +7,7 @@ #include #include -static volatile u8 *uart_base; +volatile u8 *uart_base; #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h index b42423f..f99bb84 100644 --- a/arch/arm/mach-iop33x/include/mach/uncompress.h +++ b/arch/arm/mach-iop33x/include/mach/uncompress.h @@ -7,7 +7,7 @@ #include #include -static volatile u32 *uart_base; +volatile u32 *uart_base; #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h index 2db0078..219d7c1 100644 --- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h +++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h @@ -19,7 +19,7 @@ #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) -static volatile u32* uart_base; +volatile u32* uart_base; static inline void putc(int c) { diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h index 85bd8a2..d6daeb7 100644 --- a/arch/arm/mach-mmp/include/mach/uncompress.h +++ b/arch/arm/mach-mmp/include/mach/uncompress.h @@ -14,7 +14,7 @@ #define UART2_BASE (APB_PHYS_BASE + 0x17000) #define UART3_BASE (APB_PHYS_BASE + 0x18000) -static volatile unsigned long *UART; +volatile unsigned long *UART; static inline void putc(char c) { diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h index f12a173..7f8bf65 100644 --- a/arch/arm/mach-mxs/include/mach/uncompress.h +++ b/arch/arm/mach-mxs/include/mach/uncompress.h @@ -20,7 +20,7 @@ #include -static unsigned long mxs_duart_base; +unsigned long mxs_duart_base; #define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x))) diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h index 770a68c..00ef4a6 100644 --- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h +++ b/arch/arm/mach-ns9xxx/include/mach/uncompress.h @@ -20,7 +20,7 @@ static void putc_dummy(char c, void __iomem *base) /* nothing */ } -static int timeout; +int timeout; static void putc_ns9360(char c, void __iomem *base) { diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h index 73082cd..381cb9b 100644 --- a/arch/arm/mach-nuc93x/include/mach/uncompress.h +++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h @@ -27,7 +27,7 @@ #define arch_decomp_wdog() #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) -static u32 * uart_base = (u32 *)UART0_PA; +static u32 * const uart_base = (u32 *)UART0_PA; static void putc(int ch) { diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 759b851..5519a34 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -16,9 +16,9 @@ #define BTUART_BASE (0x40200000) #define STUART_BASE (0x40700000) -static unsigned long uart_base; -static unsigned int uart_shift; -static unsigned int uart_is_pxa; +unsigned long uart_base; +unsigned int uart_shift; +unsigned int uart_is_pxa; static inline unsigned char uart_read(int offset) { diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h index 8c9e2c7..9cd9bcd 100644 --- a/arch/arm/mach-rpc/include/mach/uncompress.h +++ b/arch/arm/mach-rpc/include/mach/uncompress.h @@ -66,12 +66,12 @@ extern __attribute__((pure)) struct param_struct *params(void); #define params (params()) #ifndef STANDALONE_DEBUG -static unsigned long video_num_cols; -static unsigned long video_num_rows; -static unsigned long video_x; -static unsigned long video_y; -static unsigned char bytes_per_char_v; -static int white; +unsigned long video_num_cols; +unsigned long video_num_rows; +unsigned long video_x; +unsigned long video_y; +unsigned char bytes_per_char_v; +int white; /* * This does not append a newline diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h index c65b229..1608faf 100644 --- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h +++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h @@ -24,8 +24,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ /* uart setup */ -static unsigned int fifo_mask; -static unsigned int fifo_max; +unsigned int fifo_mask; +unsigned int fifo_max; /* forward declerations */ @@ -43,7 +43,7 @@ static void arch_detect_cpu(void); /* how many bytes we allow into the FIFO at a time in FIFO mode */ #define FIFO_MAX (14) -static unsigned long uart_base; +unsigned long uart_base; static __inline__ void get_uart_base(void) { diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index ab0fe14..088b550 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -24,7 +24,7 @@ #include #include -static u32 ux500_uart_base; +u32 ux500_uart_base; static void putc(const char c) { diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h index 56f1a74..0313021 100644 --- a/arch/arm/mach-w90x900/include/mach/uncompress.h +++ b/arch/arm/mach-w90x900/include/mach/uncompress.h @@ -27,7 +27,7 @@ #define arch_decomp_wdog() #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) -static volatile u32 * uart_base = (u32 *)UART0_PA; +static volatile u32 * const uart_base = (u32 *)UART0_PA; static void putc(int ch) { diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 4864b0a..d85e2d1 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -21,7 +21,7 @@ #include -static unsigned long uart_base; +unsigned long uart_base; #define UART(x) (*(volatile unsigned long *)(uart_base + (x))) diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 30b891c..565d266 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -27,8 +27,8 @@ #define MDR1_MODE_MASK 0x07 -static volatile u8 *uart_base; -static int uart_shift; +volatile u8 *uart_base; +int uart_shift; /* * Store the DEBUG_LL uart number into memory. diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 7d6ed72..ee48e12 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -18,8 +18,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ /* uart setup */ -static unsigned int fifo_mask; -static unsigned int fifo_max; +unsigned int fifo_mask; +unsigned int fifo_max; /* forward declerations */ -- cgit v0.10.2 From 8d7e4cc2c8ea1d180d32d902eb899f27d3ee53d7 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 27 Apr 2011 14:54:39 -0400 Subject: ARM: zImage: make sure no GOTOFF relocs are used with .bss symbols To be able to relocate the .bss section at run time independently from the rest of the code, we must make sure that no GOTOFF relocations are used with .bss symbols. This usually means that no global variables can be marked static unless they're also const. To enforce this, suffice to fail the build whenever a private symbol is allocated to .bss and list those symbols for convenience. The user_stack and user_stack_end labels in head.S were converted into non exported symbols to remove false positives. Signed-off-by: Nicolas Pitre Tested-by: Tony Lindgren diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 79b5c62..23aad07 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -120,10 +120,23 @@ lib1funcs = $(obj)/lib1funcs.o $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE $(call cmd,shipped) +# We need to prevent any GOTOFF relocs being used with references +# to symbols in the .bss section since we cannot relocate them +# independently from the rest at run time. This can be achieved by +# ensuring that no private .bss symbols exist, as global symbols +# always have a GOT entry which is what we need. +# The .data section is already discarded by the linker script so no need +# to bother about it here. +check_for_bad_syms = \ +bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \ +[ -z "$$bad_syms" ] || \ + ( echo "following symbols must have non local/private scope:" >&2; \ + echo "$$bad_syms" >&2; rm -f $@; false ) + $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE $(call if_changed,ld) - @: + @$(check_for_bad_syms) $(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE $(call if_changed,$(suffix_y)) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b541217..8d5d91a 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -372,7 +372,7 @@ LC0: .word LC0 @ r1 .word input_data_end - 4 @ r10 (inflated size location) .word _got_start @ r11 .word _got_end @ ip - .word user_stack_end @ sp + .word .L_user_stack_end @ sp .size LC0, . - LC0 #ifdef CONFIG_ARCH_RPC @@ -1100,5 +1100,5 @@ reloc_code_end: .align .section ".stack", "aw", %nobits -user_stack: .space 4096 -user_stack_end: +.L_user_stack: .space 4096 +.L_user_stack_end: -- cgit v0.10.2 From ad739dcff27435dfb3674c7549ec1b4955b050ec Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 9 May 2011 10:08:00 +0200 Subject: ARM: SAMSUNG: S5P: Convert irq-gpioint to generic irq chip Signed-off-by: Thomas Gleixner Acked-by: Kukjin Kim Signed-off-by: Mark Brown diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index cd6d67c..135abda 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -41,72 +41,11 @@ struct s5p_gpioint_bank { LIST_HEAD(banks); -static int s5p_gpioint_get_offset(struct irq_data *data) +static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type) { - struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); - return data->irq - chip->irq_base; -} - -static void s5p_gpioint_ack(struct irq_data *data) -{ - struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); - int group, offset, pend_offset; - unsigned int value; - - group = chip->group; - offset = s5p_gpioint_get_offset(data); - pend_offset = REG_OFFSET(group); - - value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset); - value |= BIT(offset); - __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset); -} - -static void s5p_gpioint_mask(struct irq_data *data) -{ - struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); - int group, offset, mask_offset; - unsigned int value; - - group = chip->group; - offset = s5p_gpioint_get_offset(data); - mask_offset = REG_OFFSET(group); - - value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset); - value |= BIT(offset); - __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset); -} - -static void s5p_gpioint_unmask(struct irq_data *data) -{ - struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); - int group, offset, mask_offset; - unsigned int value; - - group = chip->group; - offset = s5p_gpioint_get_offset(data); - mask_offset = REG_OFFSET(group); - - value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset); - value &= ~BIT(offset); - __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset); -} - -static void s5p_gpioint_mask_ack(struct irq_data *data) -{ - s5p_gpioint_mask(data); - s5p_gpioint_ack(data); -} - -static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) -{ - struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); - int group, offset, con_offset; - unsigned int value; - - group = chip->group; - offset = s5p_gpioint_get_offset(data); - con_offset = REG_OFFSET(group); + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = gc->chip_types; + unsigned int shift = (d->irq - gc->irq_base) << 2; switch (type) { case IRQ_TYPE_EDGE_RISING: @@ -130,23 +69,12 @@ static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) return -EINVAL; } - value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset); - value &= ~(0x7 << (offset * 0x4)); - value |= (type << (offset * 0x4)); - __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset); - + gc->type_cache &= ~(0x7 << shift); + gc->type_cache |= type << shift; + writel(gc->type_cache, gc->reg_base + ct->regs.type); return 0; } -static struct irq_chip s5p_gpioint = { - .name = "s5p_gpioint", - .irq_ack = s5p_gpioint_ack, - .irq_mask = s5p_gpioint_mask, - .irq_mask_ack = s5p_gpioint_mask_ack, - .irq_unmask = s5p_gpioint_unmask, - .irq_set_type = s5p_gpioint_set_type, -}; - static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) { struct s5p_gpioint_bank *bank = irq_get_handler_data(irq); @@ -179,9 +107,10 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) { static int used_gpioint_groups = 0; - int irq, group = chip->group; - int i; + int group = chip->group; struct s5p_gpioint_bank *bank = NULL; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT) return -ENOMEM; @@ -211,19 +140,28 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) * chained GPIO irq has been successfully registered, allocate new gpio * int group and assign irq nubmers */ - chip->irq_base = S5P_GPIOINT_BASE + used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE; used_gpioint_groups++; bank->chips[group - bank->start] = chip; - for (i = 0; i < chip->chip.ngpio; i++) { - irq = chip->irq_base + i; - irq_set_chip(irq, &s5p_gpioint); - irq_set_handler_data(irq, chip); - irq_set_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } + + gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base, + (void __iomem *)GPIO_BASE(chip), + handle_level_irq); + if (!gc) + return -ENOMEM; + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->chip.irq_set_type = s5p_gpioint_set_type, + ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group); + ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group); + ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group); + irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio), + IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); return 0; } -- cgit v0.10.2 From 2d2e1d3c404d7e5bd20d6e1ad910e440eaf6c14d Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 9 May 2011 10:09:26 +0200 Subject: ARM: SAMSUNG: Convert irq-vic-timer to generic irq chip Signed-off-by: Thomas Gleixner Acked-by: Kukjin Kim Signed-off-by: Mark Brown diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c index 67a145d..97660c8 100644 --- a/arch/arm/mach-s3c64xx/irq.c +++ b/arch/arm/mach-s3c64xx/irq.c @@ -58,12 +58,7 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); /* add the timer sub-irqs */ - - s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); - s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); - s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); - s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); - s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); + s3c_init_vic_timer_irq(5, IRQ_TIMER0); s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c index 5560b12..a97c089 100644 --- a/arch/arm/plat-s5p/irq.c +++ b/arch/arm/plat-s5p/irq.c @@ -64,11 +64,7 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); #endif - s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); - s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); - s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); - s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); - s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); + s3c_init_vic_timer_irq(5, IRQ_TIMER0); s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h index a90b534..5b9c42f 100644 --- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h +++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h @@ -10,4 +10,4 @@ * published by the Free Software Foundation. */ -extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer); +extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq); diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index d6ad66a..a607546 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -28,60 +28,43 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) } /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ - -static void s3c_irq_timer_mask(struct irq_data *data) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; - - reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~mask; - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_unmask(struct irq_data *data) +static void s3c_irq_timer_ack(struct irq_data *d) { - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + u32 mask = (1 << 5) << (d->irq - gc->irq_base); - reg &= 0x1f; /* mask out pending interrupts */ - reg |= mask; - __raw_writel(reg, S3C64XX_TINT_CSTAT); + irq_reg_writel(mask | gc->mask_cache, gc->reg_base); } -static void s3c_irq_timer_ack(struct irq_data *data) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; - - reg &= 0x1f; - reg |= mask << 5; - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static struct irq_chip s3c_irq_timer = { - .name = "s3c-timer", - .irq_mask = s3c_irq_timer_mask, - .irq_unmask = s3c_irq_timer_unmask, - .irq_ack = s3c_irq_timer_ack, -}; - /** * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ - * @parent_irq: The parent IRQ on the VIC for the timer. - * @timer_irq: The IRQ to be used for the timer. + * @num: Number of timers to initialize + * @timer_irq: Base IRQ number to be used for the timers. * * Register the necessary IRQ chaining and support for the timer IRQs * chained of the VIC. */ -void __init s3c_init_vic_timer_irq(unsigned int parent_irq, - unsigned int timer_irq) +void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq) { + unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC }; + struct irq_chip_generic *s3c_tgc; + struct irq_chip_type *ct; + unsigned int i; - irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer); - irq_set_handler_data(parent_irq, (void *)timer_irq); + s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, + S3C64XX_TINT_CSTAT, handle_level_irq); + ct = s3c_tgc->chip_types; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_ack = s3c_irq_timer_ack; + irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + /* Clear the upper bits of the mask_cache*/ + s3c_tgc->mask_cache &= 0x1f; - irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq); - irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); - set_irq_flags(timer_irq, IRQF_VALID); + for (i = 0; i < num; i++, timer_irq++) { + irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer); + irq_set_handler_data(pirq[i], (void *)timer_irq); + } } -- cgit v0.10.2 From bd7e388035d3c80aab360f18d123eb2e06eda8d1 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 9 May 2011 10:10:22 +0200 Subject: ARM: SAMSUNG: Convert irq-uart to generic irq chip Signed-off-by: Thomas Gleixner Acked-by: Kukjin Kim Signed-off-by: Mark Brown diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 4d4e571..32582c0 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c @@ -27,60 +27,6 @@ /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] * are consecutive when looking up the interrupt in the demux routines. */ - -static inline void __iomem *s3c_irq_uart_base(struct irq_data *data) -{ - struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data); - return uirq->regs; -} - -static inline unsigned int s3c_irq_uart_bit(unsigned int irq) -{ - return irq & 3; -} - -static void s3c_irq_uart_mask(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_maskack(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_uart_unmask(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg &= ~(1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_ack(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) { struct s3c_uart_irq *uirq = desc->irq_data.handler_data; @@ -97,30 +43,25 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) generic_handle_irq(base + 3); } -static struct irq_chip s3c_irq_uart = { - .name = "s3c-uart", - .irq_mask = s3c_irq_uart_mask, - .irq_unmask = s3c_irq_uart_unmask, - .irq_mask_ack = s3c_irq_uart_maskack, - .irq_ack = s3c_irq_uart_ack, -}; - static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) { void __iomem *reg_base = uirq->regs; - unsigned int irq; - int offs; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; /* mask all interrupts at the start. */ __raw_writel(0xf, reg_base + S3C64XX_UINTM); - for (offs = 0; offs < 3; offs++) { - irq = uirq->base_irq + offs; - - irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq); - irq_set_chip_data(irq, uirq); - set_irq_flags(irq, IRQF_VALID); - } + gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->regs.ack = S3C64XX_UINTP; + ct->regs.mask = S3C64XX_UINTM; + irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); irq_set_handler_data(uirq->parent_irq, uirq); irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); -- cgit v0.10.2 From b0ec5cf191eeca7fd885ef2860e9a586d29bff00 Mon Sep 17 00:00:00 2001 From: Ryan Mallon Date: Tue, 29 Mar 2011 01:04:57 +0100 Subject: ARM: 6852/1: EP93xx: Remove ep93xx_gpio_dbg_show function The interrupt printing functionality in the ep93xx gpio debugfs function does not behave as expected. It prints [interrupt] beside all pins which are capable of being interrupts, not just those which are currently configured as interrupts. The best solution is just to remove the custom ep93xx gpio debugfs function all together. The generic gpiolib one is good enough. Signed-off-by: Ryan Mallon Acked-by: H Hartley Sweeten Signed-off-by: Russell King diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index a5a9ff7..415dce3 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -356,29 +356,6 @@ static int ep93xx_gpio_set_debounce(struct gpio_chip *chip, return 0; } -static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); - u8 data_reg, data_dir_reg; - int gpio, i; - - data_reg = __raw_readb(ep93xx_chip->data_reg); - data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg); - - gpio = ep93xx_chip->chip.base; - for (i = 0; i < chip->ngpio; i++, gpio++) { - int is_out = data_dir_reg & (1 << i); - int irq = gpio_to_irq(gpio); - - seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n", - chip->label, i, gpio, - gpiochip_is_requested(chip, i) ? : "", - is_out ? "out" : "in ", - (data_reg & (1<< i)) ? "hi" : "lo", - (!is_out && irq>= 0) ? "(interrupt)" : ""); - } -} - #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ { \ .chip = { \ @@ -387,7 +364,6 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) .direction_output = ep93xx_gpio_direction_output, \ .get = ep93xx_gpio_get, \ .set = ep93xx_gpio_set, \ - .dbg_show = ep93xx_gpio_dbg_show, \ .base = base_gpio, \ .ngpio = 8, \ }, \ -- cgit v0.10.2 From 49ac215e071234b2bf2cff7b8bf4f4f3d0e8cd6e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 4 Mar 2011 14:54:16 +0100 Subject: ARM: 6785/1: mmci: separate out ST Micro register defines The mmci.h header contained a few registers not clearly marked as ST Micro only, rectify this and remove the HWFC magic in the process. The idea is to make the mmci.h header file more ordered so other vendors with PL180 derivates can see where to put in their custom register defines. Includes portions of an earlier patch from Sebastian Rasmussen. Acked-by: Sebastian Rasmussen Signed-off-by: Linus Walleij Signed-off-by: Russell King diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index b4a7e4f..92061f8 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -77,7 +77,7 @@ static struct variant_data variant_arm_extended_fifo = { static struct variant_data variant_u300 = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, - .clkreg_enable = 1 << 13, /* HWFCEN */ + .clkreg_enable = MCI_ST_U300_HWFCEN, .datalength_bits = 16, .sdio = true, }; @@ -86,7 +86,7 @@ static struct variant_data variant_ux500 = { .fifosize = 30 * 4, .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, - .clkreg_enable = 1 << 14, /* HWFCEN */ + .clkreg_enable = MCI_ST_UX500_HWFCEN, .datalength_bits = 24, .sdio = true, .st_clkdiv = true, diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index ec9a7bc6..bb32e21 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -11,23 +11,33 @@ #define MCI_PWR_OFF 0x00 #define MCI_PWR_UP 0x02 #define MCI_PWR_ON 0x03 -#define MCI_DATA2DIREN (1 << 2) -#define MCI_CMDDIREN (1 << 3) -#define MCI_DATA0DIREN (1 << 4) -#define MCI_DATA31DIREN (1 << 5) #define MCI_OD (1 << 6) #define MCI_ROD (1 << 7) -/* The ST Micro version does not have ROD */ -#define MCI_FBCLKEN (1 << 7) -#define MCI_DATA74DIREN (1 << 8) +/* + * The ST Micro version does not have ROD and reuse the voltage registers + * for direction settings + */ +#define MCI_ST_DATA2DIREN (1 << 2) +#define MCI_ST_CMDDIREN (1 << 3) +#define MCI_ST_DATA0DIREN (1 << 4) +#define MCI_ST_DATA31DIREN (1 << 5) +#define MCI_ST_FBCLKEN (1 << 7) +#define MCI_ST_DATA74DIREN (1 << 8) #define MMCICLOCK 0x004 #define MCI_CLK_ENABLE (1 << 8) #define MCI_CLK_PWRSAVE (1 << 9) #define MCI_CLK_BYPASS (1 << 10) #define MCI_4BIT_BUS (1 << 11) -/* 8bit wide buses supported in ST Micro versions */ +/* + * 8bit wide buses, hardware flow contronl, negative edges and clock inversion + * supported in ST Micro U300 and Ux500 versions + */ #define MCI_ST_8BIT_BUS (1 << 12) +#define MCI_ST_U300_HWFCEN (1 << 13) +#define MCI_ST_UX500_NEG_EDGE (1 << 13) +#define MCI_ST_UX500_HWFCEN (1 << 14) +#define MCI_ST_UX500_CLK_INV (1 << 15) #define MMCIARGUMENT 0x008 #define MMCICOMMAND 0x00c @@ -88,8 +98,9 @@ #define MCI_RXFIFOEMPTY (1 << 19) #define MCI_TXDATAAVLBL (1 << 20) #define MCI_RXDATAAVLBL (1 << 21) -#define MCI_SDIOIT (1 << 22) -#define MCI_CEATAEND (1 << 23) +/* Extended status bits for the ST Micro variants */ +#define MCI_ST_SDIOIT (1 << 22) +#define MCI_ST_CEATAEND (1 << 23) #define MMCICLEAR 0x038 #define MCI_CMDCRCFAILCLR (1 << 0) @@ -102,8 +113,9 @@ #define MCI_CMDSENTCLR (1 << 7) #define MCI_DATAENDCLR (1 << 8) #define MCI_DATABLOCKENDCLR (1 << 10) -#define MCI_SDIOITC (1 << 22) -#define MCI_CEATAENDC (1 << 23) +/* Extended status bits for the ST Micro variants */ +#define MCI_ST_SDIOITC (1 << 22) +#define MCI_ST_CEATAENDC (1 << 23) #define MMCIMASK0 0x03c #define MCI_CMDCRCFAILMASK (1 << 0) @@ -127,8 +139,9 @@ #define MCI_RXFIFOEMPTYMASK (1 << 19) #define MCI_TXDATAAVLBLMASK (1 << 20) #define MCI_RXDATAAVLBLMASK (1 << 21) -#define MCI_SDIOITMASK (1 << 22) -#define MCI_CEATAENDMASK (1 << 23) +/* Extended status bits for the ST Micro variants */ +#define MCI_ST_SDIOITMASK (1 << 22) +#define MCI_ST_CEATAENDMASK (1 << 23) #define MMCIMASK1 0x040 #define MMCIFIFOCNT 0x048 -- cgit v0.10.2 From ee144182590a6bd9ed1481cb09d15b92e6b5c348 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 21 Feb 2011 13:46:08 +0000 Subject: ARM: omap: update GPIO chained IRQ handler to use entry/exit functions This patch updates the OMAP gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Cc: Colin Cross Cc: Tony Lindgren Tested-and-acked-by: Santosh Shilimkar Signed-off-by: Will Deacon diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d2adcdd..a2478eb 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -1137,8 +1137,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) struct gpio_bank *bank; u32 retrigger = 0; int unmasked = 0; + struct irq_chip *chip = irq_desc_get_chip(desc); - desc->irq_data.chip->irq_ack(&desc->irq_data); + chained_irq_enter(chip, desc); bank = irq_get_handler_data(irq); #ifdef CONFIG_ARCH_OMAP1 @@ -1195,7 +1196,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) configured, we could unmask GPIO bank interrupt immediately */ if (!level_mask && !unmasked) { unmasked = 1; - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } isr |= retrigger; @@ -1231,7 +1232,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) interrupt */ exit: if (!unmasked) - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } static void gpio_irq_shutdown(struct irq_data *d) -- cgit v0.10.2 From 0f43563f2d9d8f6f9e0727e4eedb7f557ed2fb4c Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 21 Feb 2011 14:37:43 +0000 Subject: ARM: s5pv310: update IRQ combiner to use chained entry/exit functions This patch updates the IRQ combiner chained IRQ handler code to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. This is required for the GIC to move to fasteoi interrupt handling. Cc: Kyungmin Park Signed-off-by: Will Deacon diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c index f488b66..5a2758a 100644 --- a/arch/arm/mach-exynos4/irq-combiner.c +++ b/arch/arm/mach-exynos4/irq-combiner.c @@ -59,8 +59,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) unsigned int cascade_irq, combiner_irq; unsigned long status; - /* primary controller ack'ing */ - chip->irq_ack(&desc->irq_data); + chained_irq_enter(chip, desc); spin_lock(&irq_controller_lock); status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); @@ -79,8 +78,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) generic_handle_irq(cascade_irq); out: - /* primary controller unmasking */ - chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } static struct irq_chip combiner_chip = { -- cgit v0.10.2 From 03dd765fe4dd9420ac430d2a7c19498afa4431b3 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 21 Feb 2011 14:54:57 +0000 Subject: ARM: msm: update GPIO chained IRQ handler to use entry/exit functions This patch updates the MSM gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Tested-and-reviewed-by: Abhijeet Dharmapurikar Acked-by: David Brown Signed-off-by: Will Deacon diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c index 56a964e..cc9c4fd 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/arch/arm/mach-msm/gpio-v2.c @@ -27,6 +27,9 @@ #include #include #include + +#include + #include #include "gpiomux.h" @@ -309,8 +312,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) */ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct irq_data *data = irq_desc_get_irq_data(desc); unsigned long i; + struct irq_chip *chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); i < NR_GPIO_IRQS; @@ -319,7 +324,8 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, i)); } - data->chip->irq_ack(data); + + chained_irq_exit(chip, desc); } static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) -- cgit v0.10.2 From adfed159ab71bff53ccac3013776580bc866d2ba Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 28 Feb 2011 10:12:29 +0000 Subject: ARM: nmk: update GPIO chained IRQ handler to entry/exit functions This patch updates the Nomadik gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Cc: Rabin Vincent Cc: Grant Likely Acked-by: Linus Walleij Signed-off-by: Will Deacon diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index f49748e..307b813 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -23,6 +23,8 @@ #include #include +#include + #include #include #include @@ -681,13 +683,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, struct irq_chip *host_chip = irq_get_chip(irq); unsigned int first_irq; - if (host_chip->irq_mask_ack) - host_chip->irq_mask_ack(&desc->irq_data); - else { - host_chip->irq_mask(&desc->irq_data); - if (host_chip->irq_ack) - host_chip->irq_ack(&desc->irq_data); - } + chained_irq_enter(host_chip, desc); nmk_chip = irq_get_handler_data(irq); first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); @@ -698,7 +694,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, status &= ~BIT(bit); } - host_chip->irq_unmask(&desc->irq_data); + chained_irq_exit(host_chip, desc); } static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -- cgit v0.10.2 From 98022940c2431025be3c95e50035d762c40f539d Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 21 Feb 2011 13:58:10 +0000 Subject: ARM: tegra: update GPIO chained IRQ handler to use entry/exit functions This patch updates the Tegra gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. This is required for the GIC to move to fasteoi interrupt handling. Acked-by: Colin Cross Signed-off-by: Will Deacon diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index 65a1aba..919d638 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c @@ -24,6 +24,8 @@ #include #include +#include + #include #include @@ -221,8 +223,9 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) int port; int pin; int unmasked = 0; + struct irq_chip *chip = irq_desc_get_chip(desc); - desc->irq_data.chip->irq_ack(&desc->irq_data); + chained_irq_enter(chip, desc); bank = irq_get_handler_data(irq); @@ -241,7 +244,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) */ if (lvl & (0x100 << pin)) { unmasked = 1; - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } generic_handle_irq(gpio_to_irq(gpio + pin)); @@ -249,7 +252,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) } if (!unmasked) - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } -- cgit v0.10.2 From 938fa349fbc16880feae4b65e56691ca12ede9ab Mon Sep 17 00:00:00 2001 From: Colin Cross Date: Sun, 1 May 2011 14:10:10 -0700 Subject: ARM: tegra: irq: convert to gic arch extensions Replace the ugly hack that inserts legacy irq controller calls into the irq call paths by reading and replacing the gic irq chip with the new gic arch extensions. Signed-off-by: Colin Cross diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 4330d89..567b75c 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -1,8 +1,8 @@ /* - * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2011 Google, Inc. * * Author: - * Colin Cross + * Colin Cross * * Copyright (C) 2010, NVIDIA Corporation * @@ -46,10 +46,6 @@ static u32 tegra_lp0_wake_enb; static u32 tegra_lp0_wake_level; static u32 tegra_lp0_wake_level_any; -static void (*tegra_gic_mask_irq)(struct irq_data *d); -static void (*tegra_gic_unmask_irq)(struct irq_data *d); -static void (*tegra_gic_ack_irq)(struct irq_data *d); - /* ensures that sufficient time is passed for a register write to * serialize into the 32KHz domain */ static void pmc_32kwritel(u32 val, unsigned long offs) @@ -103,58 +99,40 @@ void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any) static void tegra_mask(struct irq_data *d) { - tegra_gic_mask_irq(d); - tegra_legacy_mask_irq(d->irq); + if (d->irq >= 32) + tegra_legacy_mask_irq(d->irq); } static void tegra_unmask(struct irq_data *d) { - tegra_gic_unmask_irq(d); - tegra_legacy_unmask_irq(d->irq); + if (d->irq >= 32) + tegra_legacy_unmask_irq(d->irq); } static void tegra_ack(struct irq_data *d) { - tegra_legacy_force_irq_clr(d->irq); - tegra_gic_ack_irq(d); + if (d->irq >= 32) + tegra_legacy_force_irq_clr(d->irq); } static int tegra_retrigger(struct irq_data *d) { + if (d->irq < 32) + return 0; + tegra_legacy_force_irq_set(d->irq); return 1; } -static struct irq_chip tegra_irq = { - .name = "PPI", - .irq_ack = tegra_ack, - .irq_mask = tegra_mask, - .irq_unmask = tegra_unmask, - .irq_retrigger = tegra_retrigger, -}; - void __init tegra_init_irq(void) { - struct irq_chip *gic; - unsigned int i; - int irq; - tegra_init_legacy_irq(); + gic_arch_extn.irq_ack = tegra_ack; + gic_arch_extn.irq_mask = tegra_mask; + gic_arch_extn.irq_unmask = tegra_unmask; + gic_arch_extn.irq_retrigger = tegra_retrigger; + gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - - gic = irq_get_chip(29); - tegra_gic_unmask_irq = gic->irq_unmask; - tegra_gic_mask_irq = gic->irq_mask; - tegra_gic_ack_irq = gic->irq_ack; -#ifdef CONFIG_SMP - tegra_irq.irq_set_affinity = gic->irq_set_affinity; -#endif - - for (i = 0; i < INT_MAIN_NR; i++) { - irq = INT_PRI_BASE + i; - irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } } -- cgit v0.10.2 From 4dda2d384bc69de260647c3b419967734a4de496 Mon Sep 17 00:00:00 2001 From: Colin Cross Date: Sun, 1 May 2011 14:10:11 -0700 Subject: ARM: tegra: irq: Remove PM support Tegra PM irq support is being improved, remove it for now until the rest of the platform gets PM support. Signed-off-by: Colin Cross diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h index d898c0e..4c1f535 100644 --- a/arch/arm/mach-tegra/include/mach/legacy_irq.h +++ b/arch/arm/mach-tegra/include/mach/legacy_irq.h @@ -27,9 +27,6 @@ int tegra_legacy_force_irq_status(unsigned int irq); void tegra_legacy_select_fiq(unsigned int irq, bool fiq); unsigned long tegra_legacy_vfiq(int nr); unsigned long tegra_legacy_class(int nr); -int tegra_legacy_irq_set_wake(int irq, int enable); -void tegra_legacy_irq_set_lp1_wake_mask(void); -void tegra_legacy_irq_restore_mask(void); void tegra_init_legacy_irq(void); #endif diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 567b75c..4fa7a37 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -28,75 +28,9 @@ #include #include -#include #include "board.h" -#define PMC_CTRL 0x0 -#define PMC_CTRL_LATCH_WAKEUPS (1 << 5) -#define PMC_WAKE_MASK 0xc -#define PMC_WAKE_LEVEL 0x10 -#define PMC_WAKE_STATUS 0x14 -#define PMC_SW_WAKE_STATUS 0x18 -#define PMC_DPD_SAMPLE 0x20 - -static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); - -static u32 tegra_lp0_wake_enb; -static u32 tegra_lp0_wake_level; -static u32 tegra_lp0_wake_level_any; - -/* ensures that sufficient time is passed for a register write to - * serialize into the 32KHz domain */ -static void pmc_32kwritel(u32 val, unsigned long offs) -{ - writel(val, pmc + offs); - udelay(130); -} - -int tegra_set_lp1_wake(int irq, int enable) -{ - return tegra_legacy_irq_set_wake(irq, enable); -} - -void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any) -{ - u32 temp; - u32 status; - u32 lvl; - - wake_level &= wake_enb; - wake_any &= wake_enb; - - wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb); - wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb); - - wake_enb |= tegra_lp0_wake_enb; - - pmc_32kwritel(0, PMC_SW_WAKE_STATUS); - temp = readl(pmc + PMC_CTRL); - temp |= PMC_CTRL_LATCH_WAKEUPS; - pmc_32kwritel(temp, PMC_CTRL); - temp &= ~PMC_CTRL_LATCH_WAKEUPS; - pmc_32kwritel(temp, PMC_CTRL); - status = readl(pmc + PMC_SW_WAKE_STATUS); - lvl = readl(pmc + PMC_WAKE_LEVEL); - - /* flip the wakeup trigger for any-edge triggered pads - * which are currently asserting as wakeups */ - lvl ^= status; - lvl &= wake_any; - - wake_level |= lvl; - - writel(wake_level, pmc + PMC_WAKE_LEVEL); - /* Enable DPD sample to trigger sampling pads data and direction - * in which pad will be driven during lp0 mode*/ - writel(0x1, pmc + PMC_DPD_SAMPLE); - - writel(wake_enb, pmc + PMC_WAKE_MASK); -} - static void tegra_mask(struct irq_data *d) { if (d->irq >= 32) diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c index 38eb719..cb31669 100644 --- a/arch/arm/mach-tegra/legacy_irq.c +++ b/arch/arm/mach-tegra/legacy_irq.c @@ -49,9 +49,6 @@ static void __iomem *ictlr_reg_base[] = { IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), }; -static u32 tegra_legacy_wake_mask[4]; -static u32 tegra_legacy_saved_mask[4]; - /* When going into deep sleep, the CPU is powered down, taking the GIC with it In order to wake, the wake interrupts need to be enabled in the legacy interrupt controller. */ @@ -129,40 +126,6 @@ unsigned long tegra_legacy_class(int nr) return readl(base + ICTLR_CPU_IEP_CLASS); } -int tegra_legacy_irq_set_wake(int irq, int enable) -{ - irq -= 32; - if (enable) - tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31); - else - tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31)); - - return 0; -} - -void tegra_legacy_irq_set_lp1_wake_mask(void) -{ - void __iomem *base; - int i; - - for (i = 0; i < NUM_ICTLRS; i++) { - base = ictlr_reg_base[i]; - tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER); - writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER); - } -} - -void tegra_legacy_irq_restore_mask(void) -{ - void __iomem *base; - int i; - - for (i = 0; i < NUM_ICTLRS; i++) { - base = ictlr_reg_base[i]; - writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER); - } -} - void tegra_init_legacy_irq(void) { int i; @@ -173,43 +136,3 @@ void tegra_init_legacy_irq(void) writel(0, ictlr + ICTLR_CPU_IEP_CLASS); } } - -#ifdef CONFIG_PM -static u32 cop_ier[NUM_ICTLRS]; -static u32 cpu_ier[NUM_ICTLRS]; -static u32 cpu_iep[NUM_ICTLRS]; - -void tegra_irq_suspend(void) -{ - unsigned long flags; - int i; - - local_irq_save(flags); - for (i = 0; i < NUM_ICTLRS; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER); - cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS); - cop_ier[i] = readl(ictlr + ICTLR_COP_IER); - writel(~0, ictlr + ICTLR_COP_IER_CLR); - } - local_irq_restore(flags); -} - -void tegra_irq_resume(void) -{ - unsigned long flags; - int i; - - local_irq_save(flags); - for (i = 0; i < NUM_ICTLRS; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS); - writel(~0ul, ictlr + ICTLR_CPU_IER_CLR); - writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET); - writel(0, ictlr + ICTLR_COP_IEP_CLASS); - writel(~0ul, ictlr + ICTLR_COP_IER_CLR); - writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET); - } - local_irq_restore(flags); -} -#endif -- cgit v0.10.2 From d1d8c666683cdbef18329ff8f3743ddaca8842ee Mon Sep 17 00:00:00 2001 From: Colin Cross Date: Sun, 1 May 2011 15:26:51 -0700 Subject: ARM: tegra: irq: Move legacy_irq.c into irq.c Now that irq.c is just an interface layer between the gic and legacy_irq.c, move the contents of legacy_irq.c into irq.c. Signed-off-by: Colin Cross diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 1afe050..823c703 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,7 +1,7 @@ obj-y += common.o obj-y += devices.o obj-y += io.o -obj-y += irq.o legacy_irq.o +obj-y += irq.o obj-y += clock.o obj-y += timer.o obj-y += gpio.o diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h deleted file mode 100644 index 4c1f535..0000000 --- a/arch/arm/mach-tegra/include/mach/legacy_irq.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/legacy_irq.h - * - * Copyright (C) 2010 Google, Inc. - * Author: Colin Cross - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H -#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H - -void tegra_legacy_mask_irq(unsigned int irq); -void tegra_legacy_unmask_irq(unsigned int irq); -void tegra_legacy_select_fiq(unsigned int irq, bool fiq); -void tegra_legacy_force_irq_set(unsigned int irq); -void tegra_legacy_force_irq_clr(unsigned int irq); -int tegra_legacy_force_irq_status(unsigned int irq); -void tegra_legacy_select_fiq(unsigned int irq, bool fiq); -unsigned long tegra_legacy_vfiq(int nr); -unsigned long tegra_legacy_class(int nr); -void tegra_init_legacy_irq(void); - -#endif diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 4fa7a37..da17491 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -18,8 +18,6 @@ */ #include -#include -#include #include #include #include @@ -27,40 +25,95 @@ #include #include -#include #include "board.h" +#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) +#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) +#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) + +#define ICTLR_CPU_IEP_VFIQ 0x08 +#define ICTLR_CPU_IEP_FIR 0x14 +#define ICTLR_CPU_IEP_FIR_SET 0x18 +#define ICTLR_CPU_IEP_FIR_CLR 0x1c + +#define ICTLR_CPU_IER 0x20 +#define ICTLR_CPU_IER_SET 0x24 +#define ICTLR_CPU_IER_CLR 0x28 +#define ICTLR_CPU_IEP_CLASS 0x2C + +#define ICTLR_COP_IER 0x30 +#define ICTLR_COP_IER_SET 0x34 +#define ICTLR_COP_IER_CLR 0x38 +#define ICTLR_COP_IEP_CLASS 0x3c + +#define NUM_ICTLRS 4 +#define FIRST_LEGACY_IRQ 32 + +static void __iomem *ictlr_reg_base[] = { + IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), +}; + +static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) +{ + void __iomem *base; + u32 mask; + + BUG_ON(irq < FIRST_LEGACY_IRQ || + irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32); + + base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32]; + mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); + + __raw_writel(mask, base + reg); +} + static void tegra_mask(struct irq_data *d) { - if (d->irq >= 32) - tegra_legacy_mask_irq(d->irq); + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR); } static void tegra_unmask(struct irq_data *d) { - if (d->irq >= 32) - tegra_legacy_unmask_irq(d->irq); + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET); } static void tegra_ack(struct irq_data *d) { - if (d->irq >= 32) - tegra_legacy_force_irq_clr(d->irq); + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); } static int tegra_retrigger(struct irq_data *d) { - if (d->irq < 32) + if (d->irq < FIRST_LEGACY_IRQ) return 0; - tegra_legacy_force_irq_set(d->irq); + tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET); + return 1; } void __init tegra_init_irq(void) { - tegra_init_legacy_irq(); + int i; + + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + writel(~0, ictlr + ICTLR_CPU_IER_CLR); + writel(0, ictlr + ICTLR_CPU_IEP_CLASS); + } gic_arch_extn.irq_ack = tegra_ack; gic_arch_extn.irq_mask = tegra_mask; diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c deleted file mode 100644 index cb31669..0000000 --- a/arch/arm/mach-tegra/legacy_irq.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * arch/arm/mach-tegra/legacy_irq.c - * - * Copyright (C) 2010 Google, Inc. - * Author: Colin Cross - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include - -#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) -#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) -#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) - -#define ICTLR_CPU_IEP_VFIQ 0x08 -#define ICTLR_CPU_IEP_FIR 0x14 -#define ICTLR_CPU_IEP_FIR_SET 0x18 -#define ICTLR_CPU_IEP_FIR_CLR 0x1c - -#define ICTLR_CPU_IER 0x20 -#define ICTLR_CPU_IER_SET 0x24 -#define ICTLR_CPU_IER_CLR 0x28 -#define ICTLR_CPU_IEP_CLASS 0x2C - -#define ICTLR_COP_IER 0x30 -#define ICTLR_COP_IER_SET 0x34 -#define ICTLR_COP_IER_CLR 0x38 -#define ICTLR_COP_IEP_CLASS 0x3c - -#define NUM_ICTLRS 4 - -static void __iomem *ictlr_reg_base[] = { - IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), -}; - -/* When going into deep sleep, the CPU is powered down, taking the GIC with it - In order to wake, the wake interrupts need to be enabled in the legacy - interrupt controller. */ -void tegra_legacy_unmask_irq(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET); -} - -void tegra_legacy_mask_irq(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR); -} - -void tegra_legacy_force_irq_set(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET); -} - -void tegra_legacy_force_irq_clr(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR); -} - -int tegra_legacy_force_irq_status(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31))); -} - -void tegra_legacy_select_fiq(unsigned int irq, bool fiq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS); -} - -unsigned long tegra_legacy_vfiq(int nr) -{ - void __iomem *base; - base = ictlr_reg_base[nr]; - return readl(base + ICTLR_CPU_IEP_VFIQ); -} - -unsigned long tegra_legacy_class(int nr) -{ - void __iomem *base; - base = ictlr_reg_base[nr]; - return readl(base + ICTLR_CPU_IEP_CLASS); -} - -void tegra_init_legacy_irq(void) -{ - int i; - - for (i = 0; i < NUM_ICTLRS; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - writel(~0, ictlr + ICTLR_CPU_IER_CLR); - writel(0, ictlr + ICTLR_CPU_IEP_CLASS); - } -} -- cgit v0.10.2 From 4bd66cfde5c3b6eced0da483c6357ae46d3adbb5 Mon Sep 17 00:00:00 2001 From: Colin Cross Date: Sun, 1 May 2011 15:27:34 -0700 Subject: ARM: tegra: irq: Add tegra_eoi Implement irq_eoi to allow the GIC irq chip flow controller to be changed to fasteoi. Signed-off-by: Colin Cross diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index da17491..4956c3c 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -95,6 +95,14 @@ static void tegra_ack(struct irq_data *d) tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); } +static void tegra_eoi(struct irq_data *d) +{ + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); +} + static int tegra_retrigger(struct irq_data *d) { if (d->irq < FIRST_LEGACY_IRQ) @@ -116,6 +124,7 @@ void __init tegra_init_irq(void) } gic_arch_extn.irq_ack = tegra_ack; + gic_arch_extn.irq_eoi = tegra_eoi; gic_arch_extn.irq_mask = tegra_mask; gic_arch_extn.irq_unmask = tegra_unmask; gic_arch_extn.irq_retrigger = tegra_retrigger; -- cgit v0.10.2 From 1a01753ed90a4fb84357b9b592e50564c07737f7 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 9 Feb 2011 12:01:12 +0000 Subject: ARM: gic: use handle_fasteoi_irq for SPIs Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling. On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux. This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip. Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary. Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs). Tested-and-reviewed-by: Abhijeet Dharmapurikar Tested-and-acked-by: Santosh Shilimkar Acked-by: Catalin Marinas Signed-off-by: Will Deacon diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index f70ec7d..e9c2ff8 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -49,7 +49,7 @@ struct gic_chip_data { * Default make them NULL. */ struct irq_chip gic_arch_extn = { - .irq_ack = NULL, + .irq_eoi = NULL, .irq_mask = NULL, .irq_unmask = NULL, .irq_retrigger = NULL, @@ -84,15 +84,6 @@ static inline unsigned int gic_irq(struct irq_data *d) /* * Routines to acknowledge, disable and enable interrupts */ -static void gic_ack_irq(struct irq_data *d) -{ - spin_lock(&irq_controller_lock); - if (gic_arch_extn.irq_ack) - gic_arch_extn.irq_ack(d); - writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); - spin_unlock(&irq_controller_lock); -} - static void gic_mask_irq(struct irq_data *d) { u32 mask = 1 << (d->irq % 32); @@ -115,6 +106,17 @@ static void gic_unmask_irq(struct irq_data *d) spin_unlock(&irq_controller_lock); } +static void gic_eoi_irq(struct irq_data *d) +{ + if (gic_arch_extn.irq_eoi) { + spin_lock(&irq_controller_lock); + gic_arch_extn.irq_eoi(d); + spin_unlock(&irq_controller_lock); + } + + writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); +} + static int gic_set_type(struct irq_data *d, unsigned int type) { void __iomem *base = gic_dist_base(d); @@ -218,8 +220,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) unsigned int cascade_irq, gic_irq; unsigned long status; - /* primary controller ack'ing */ - chip->irq_ack(&desc->irq_data); + chained_irq_enter(chip, desc); spin_lock(&irq_controller_lock); status = readl(chip_data->cpu_base + GIC_CPU_INTACK); @@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) generic_handle_irq(cascade_irq); out: - /* primary controller unmasking */ - chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } static struct irq_chip gic_chip = { .name = "GIC", - .irq_ack = gic_ack_irq, .irq_mask = gic_mask_irq, .irq_unmask = gic_unmask_irq, + .irq_eoi = gic_eoi_irq, .irq_set_type = gic_set_type, .irq_retrigger = gic_retrigger, #ifdef CONFIG_SMP @@ -319,7 +319,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic, * Setup the Linux IRQ subsystem. */ for (i = irq_start; i < irq_limit; i++) { - irq_set_chip_and_handler(i, &gic_chip, handle_level_irq); + irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq); irq_set_chip_data(i, gic); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } -- cgit v0.10.2 From 6ac77e469e991e9dd91b28e503fa24b5609eedba Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 28 Mar 2011 19:27:46 +0530 Subject: ARM: GIC: Convert GIC library to use the IO relaxed operations The GIC register accesses today make use of readl()/writel() which prove to be very expensive when used along with mandatory barriers. This mandatory barriers also introduces an un-necessary and expensive l2x0_sync() operation. On Cortex-A9 MP cores, GIC IO accesses from CPU are direct and doesn't go through L2X0 write buffer. A DSB before writel_relaxed() in gic_raise_softirq() is added to be compliant with the Barrier Litmus document - the mailbox scenario. Signed-off-by: Santosh Shilimkar Acked-by: Catalin Marinas Cc: Will Deacon diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index e9c2ff8..4ddd0a6 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -89,7 +89,7 @@ static void gic_mask_irq(struct irq_data *d) u32 mask = 1 << (d->irq % 32); spin_lock(&irq_controller_lock); - writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); + writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); if (gic_arch_extn.irq_mask) gic_arch_extn.irq_mask(d); spin_unlock(&irq_controller_lock); @@ -102,7 +102,7 @@ static void gic_unmask_irq(struct irq_data *d) spin_lock(&irq_controller_lock); if (gic_arch_extn.irq_unmask) gic_arch_extn.irq_unmask(d); - writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); + writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); spin_unlock(&irq_controller_lock); } @@ -114,7 +114,7 @@ static void gic_eoi_irq(struct irq_data *d) spin_unlock(&irq_controller_lock); } - writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); + writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); } static int gic_set_type(struct irq_data *d, unsigned int type) @@ -140,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) if (gic_arch_extn.irq_set_type) gic_arch_extn.irq_set_type(d, type); - val = readl(base + GIC_DIST_CONFIG + confoff); + val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); if (type == IRQ_TYPE_LEVEL_HIGH) val &= ~confmask; else if (type == IRQ_TYPE_EDGE_RISING) @@ -150,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type) * As recommended by the spec, disable the interrupt before changing * the configuration */ - if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { - writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); + if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { + writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); enabled = true; } - writel(val, base + GIC_DIST_CONFIG + confoff); + writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); if (enabled) - writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); + writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); spin_unlock(&irq_controller_lock); @@ -190,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, spin_lock(&irq_controller_lock); d->node = cpu; - val = readl(reg) & ~mask; - writel(val | bit, reg); + val = readl_relaxed(reg) & ~mask; + writel_relaxed(val | bit, reg); spin_unlock(&irq_controller_lock); return 0; @@ -223,7 +223,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) chained_irq_enter(chip, desc); spin_lock(&irq_controller_lock); - status = readl(chip_data->cpu_base + GIC_CPU_INTACK); + status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); spin_unlock(&irq_controller_lock); gic_irq = (status & 0x3ff); @@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic, cpumask |= cpumask << 8; cpumask |= cpumask << 16; - writel(0, base + GIC_DIST_CTRL); + writel_relaxed(0, base + GIC_DIST_CTRL); /* * Find out how many interrupts are supported. * The GIC only supports up to 1020 interrupt sources. */ - gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f; + gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f; gic_irqs = (gic_irqs + 1) * 32; if (gic_irqs > 1020) gic_irqs = 1020; @@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic, * Set all global interrupts to be level triggered, active low. */ for (i = 32; i < gic_irqs; i += 16) - writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); + writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); /* * Set all global interrupts to this CPU only. */ for (i = 32; i < gic_irqs; i += 4) - writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); + writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); /* * Set priority on all global interrupts. */ for (i = 32; i < gic_irqs; i += 4) - writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); + writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); /* * Disable all interrupts. Leave the PPI and SGIs alone * as these enables are banked registers. */ for (i = 32; i < gic_irqs; i += 32) - writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); + writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); /* * Limit number of interrupts registered to the platform maximum @@ -324,7 +324,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic, set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } - writel(1, base + GIC_DIST_CTRL); + writel_relaxed(1, base + GIC_DIST_CTRL); } static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) @@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) * Deal with the banked PPI and SGI interrupts - disable all * PPI interrupts, ensure all SGI interrupts are enabled. */ - writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); - writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); + writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); + writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); /* * Set priority on PPI and SGI interrupts */ for (i = 0; i < 32; i += 4) - writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); + writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); - writel(0xf0, base + GIC_CPU_PRIMASK); - writel(1, base + GIC_CPU_CTRL); + writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); + writel_relaxed(1, base + GIC_CPU_CTRL); } void __init gic_init(unsigned int gic_nr, unsigned int irq_start, @@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) { unsigned long map = *cpus_addr(*mask); + /* + * Ensure that stores to Normal memory are visible to the + * other CPUs before issuing the IPI. + */ + dsb(); + /* this always happens on GIC0 */ - writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); + writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); } #endif -- cgit v0.10.2 From aac4dd1dab8acfc244d697473d2a5f4424a5746c Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Fri, 15 Apr 2011 11:19:57 +0200 Subject: arm: davinci: Use generic irq chip Simple conversion which simply uses the fact that the second irq chip base address has offset 0x04 to the first one. Signed-off-by: Thomas Gleixner Reviewed-and-Tested-by: Kevin Hilman Tested-by: Sekhar Nori diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index e6269a6..bfe68ec 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -29,8 +29,6 @@ #include #include -#define IRQ_BIT(irq) ((irq) & 0x1f) - #define FIQ_REG0_OFFSET 0x0000 #define FIQ_REG1_OFFSET 0x0004 #define IRQ_REG0_OFFSET 0x0008 @@ -42,78 +40,33 @@ #define IRQ_INTPRI0_REG_OFFSET 0x0030 #define IRQ_INTPRI7_REG_OFFSET 0x004C -static inline unsigned int davinci_irq_readl(int offset) -{ - return __raw_readl(davinci_intc_base + offset); -} - static inline void davinci_irq_writel(unsigned long value, int offset) { __raw_writel(value, davinci_intc_base + offset); } -/* Disable interrupt */ -static void davinci_mask_irq(struct irq_data *d) +static __init void +davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) { - unsigned int mask; - u32 l; - - mask = 1 << IRQ_BIT(d->irq); - - if (d->irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } -} - -/* Enable interrupt */ -static void davinci_unmask_irq(struct irq_data *d) -{ - unsigned int mask; - u32 l; - - mask = 1 << IRQ_BIT(d->irq); - - if (d->irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq); + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + + ct->regs.ack = IRQ_REG0_OFFSET; + ct->regs.mask = IRQ_ENT_REG0_OFFSET; + irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); } -/* EOI interrupt */ -static void davinci_ack_irq(struct irq_data *d) -{ - unsigned int mask; - - mask = 1 << IRQ_BIT(d->irq); - - if (d->irq > 31) - davinci_irq_writel(mask, IRQ_REG1_OFFSET); - else - davinci_irq_writel(mask, IRQ_REG0_OFFSET); -} - -static struct irq_chip davinci_irq_chip_0 = { - .name = "AINTC", - .irq_ack = davinci_ack_irq, - .irq_mask = davinci_mask_irq, - .irq_unmask = davinci_unmask_irq, -}; - /* ARM Interrupt Controller Initialization */ void __init davinci_irq_init(void) { - unsigned i; + unsigned i, j; const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; davinci_intc_type = DAVINCI_INTC_TYPE_AINTC; @@ -144,7 +97,6 @@ void __init davinci_irq_init(void) davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { - unsigned j; u32 pri; for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++) @@ -152,13 +104,8 @@ void __init davinci_irq_init(void) davinci_irq_writel(pri, i); } - /* set up genirq dispatch for ARM INTC */ - for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { - irq_set_chip(i, &davinci_irq_chip_0); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - if (i != IRQ_TINT1_TINT34) - irq_set_handler(i, handle_edge_irq); - else - irq_set_handler(i, handle_level_irq); - } + for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04) + davinci_alloc_gc(davinci_intc_base + j, i, 32); + + irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); } -- cgit v0.10.2 From 2fb3ec5c9503ba8874e24170de2b40e8f1a58370 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 11 May 2011 16:06:29 +0100 Subject: ARM: Replace platform definition of ISA_DMA_THRESHOLD/MAX_DMA_ADDRESS The values of ISA_DMA_THRESHOLD and MAX_DMA_ADDRESS are related; one is the physical/bus address, the other is the virtual address. Both need to be kept in step, so rather than having platforms define both, allow them to define a single macro which sets both of these macros appropraitely. Acked-by: Nicolas Pitre Acked-by: Catalin Marinas Signed-off-by: Russell King diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index ca51143..4200554 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h @@ -6,8 +6,10 @@ /* * This is the maximum virtual address which can be DMA'd from. */ -#ifndef MAX_DMA_ADDRESS +#ifndef ARM_DMA_ZONE_SIZE #define MAX_DMA_ADDRESS 0xffffffff +#else +#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE) #endif #ifdef CONFIG_ISA_DMA_API diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 431077c..ee5ff41 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -209,8 +209,10 @@ static inline unsigned long __phys_to_virt(unsigned long x) * allocations. This must be the smallest DMA mask in the system, * so a successful GFP_DMA allocation will always satisfy this. */ -#ifndef ISA_DMA_THRESHOLD +#ifndef ARM_DMA_ZONE_SIZE #define ISA_DMA_THRESHOLD (0xffffffffULL) +#else +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1) #endif #ifndef arch_adjust_zones diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index 7882272..8d27246 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -59,8 +59,7 @@ __arch_adjust_zones(unsigned long *size, unsigned long *holes) #define arch_adjust_zones(zone_size, holes) \ if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes) -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20)) +#define ARM_DMA_ZONE_SIZE SZ_128M #endif diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h index 9d36876..b0b3bae 100644 --- a/arch/arm/mach-h720x/include/mach/memory.h +++ b/arch/arm/mach-h720x/include/mach/memory.h @@ -13,7 +13,6 @@ * There should not be more than (0xd0000000 - 0xc0000000) * bytes of RAM. */ -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) +#define ARM_DMA_ZONE_SIZE SZ_256M #endif diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index 6d388c9..a5c26f8 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -21,8 +21,7 @@ void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes); #define arch_adjust_zones(size, holes) \ ixp4xx_adjust_zones(size, holes) -#define ISA_DMA_THRESHOLD (SZ_64M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) +#define ARM_DMA_ZONE_SIZE SZ_64M #endif diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 7f68724..57a0b68 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -23,8 +23,7 @@ void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); #define arch_adjust_zones(size, holes) \ cmx2xx_pci_adjust_zones(size, holes) -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) +#define ARM_DMA_ZONE_SIZE SZ_64M #endif #endif diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h index e05fc2c..973428d 100644 --- a/arch/arm/mach-realview/include/mach/memory.h +++ b/arch/arm/mach-realview/include/mach/memory.h @@ -34,8 +34,7 @@ extern void realview_adjust_zones(unsigned long *size, unsigned long *hole); #define arch_adjust_zones(size, hole) \ realview_adjust_zones(size, hole) -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) +#define ARM_DMA_ZONE_SIZE SZ_256M #endif #ifdef CONFIG_SPARSEMEM diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index a44da6a..090b829 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -22,8 +22,7 @@ void sa1111_adjust_zones(unsigned long *size, unsigned long *holes); #define arch_adjust_zones(size, holes) \ sa1111_adjust_zones(size, holes) -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M) +#define ARM_DMA_ZONE_SIZE SZ_1M #endif #endif diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index 9afb170..48fe84b 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -32,8 +32,7 @@ static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long * #define arch_adjust_zones(size, holes) \ __arch_adjust_zones(size, holes) -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M) +#define ARM_DMA_ZONE_SIZE SZ_4M #endif -- cgit v0.10.2 From be20902ba67de70b38c995903321f4152dee57b7 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 11 May 2011 15:39:00 +0100 Subject: ARM: use ARM_DMA_ZONE_SIZE to adjust the zone sizes Rather than each platform providing its own function to adjust the zone sizes, use the new ARM_DMA_ZONE_SIZE definition to perform this adjustment. This ensures that the actual DMA zone size and the ISA_DMA_THRESHOLD/MAX_DMA_ADDRESS definitions are consistent with each other, and moves this complexity out of the platform code. Acked-by: Nicolas Pitre Acked-by: Catalin Marinas Signed-off-by: Russell King diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index a12b33c..9c49a46 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -185,14 +185,6 @@ static struct sa1111_dev_info sa1111_devices[] = { }, }; -void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes) -{ - unsigned int sz = SZ_1M >> PAGE_SHIFT; - - size[1] = size[0] - sz; - size[0] = sz; -} - /* * SA1111 interrupt support. Since clearing an IRQ while there are * active IRQs causes the interrupt output to pulse, the upper levels diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index ee5ff41..af44a8f 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -215,12 +215,6 @@ static inline unsigned long __phys_to_virt(unsigned long x) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1) #endif -#ifndef arch_adjust_zones -#define arch_adjust_zones(size,holes) do { } while (0) -#elif !defined(CONFIG_ZONE_DMA) -#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA" -#endif - /* * PFNs are used to describe any physical page; this means * PFN 0 == physical address 0. diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index 8d27246..491249e 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -41,26 +41,11 @@ */ #define CONSISTENT_DMA_SIZE (14<<20) -#ifndef __ASSEMBLY__ /* * Restrict DMA-able region to workaround silicon bug. The bug * restricts buffers available for DMA to video hardware to be * below 128M */ -static inline void -__arch_adjust_zones(unsigned long *size, unsigned long *holes) -{ - unsigned int sz = (128<<20) >> PAGE_SHIFT; - - size[1] = size[0] - sz; - size[0] = sz; -} - -#define arch_adjust_zones(zone_size, holes) \ - if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes) - #define ARM_DMA_ZONE_SIZE SZ_128M -#endif - #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index a54b3db..e9a5893 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -342,29 +342,6 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); } -/* - * Only first 64MB of memory can be accessed via PCI. - * We use GFP_DMA to allocate safe buffers to do map/unmap. - * This is really ugly and we need a better way of specifying - * DMA-capable regions of memory. - */ -void __init ixp4xx_adjust_zones(unsigned long *zone_size, - unsigned long *zhole_size) -{ - unsigned int sz = SZ_64M >> PAGE_SHIFT; - - /* - * Only adjust if > 64M on current system - */ - if (zone_size[0] <= sz) - return; - - zone_size[1] = zone_size[0] - sz; - zone_size[0] = sz; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; -} - void __init ixp4xx_pci_preinit(void) { unsigned long cpuid = read_cpuid_id(); diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index a5c26f8..34e7940 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -14,15 +14,8 @@ */ #define PLAT_PHYS_OFFSET UL(0x00000000) -#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) - -void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - ixp4xx_adjust_zones(size, holes) - +#ifdef CONFIG_PCI #define ARM_DMA_ZONE_SIZE SZ_64M - #endif #endif diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 8b1a309..1afc0fb 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -29,33 +29,6 @@ unsigned long it8152_base_address; static int cmx2xx_it8152_irq_gpio; -/* - * Only first 64MB of memory can be accessed via PCI. - * We use GFP_DMA to allocate safe buffers to do map/unmap. - * This is really ugly and we need a better way of specifying - * DMA-capable regions of memory. - */ -void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size, - unsigned long *zhole_size) -{ - unsigned int sz = SZ_64M >> PAGE_SHIFT; - - if (machine_is_armcore()) { - pr_info("Adjusting zones for CM-X2XX\n"); - - /* - * Only adjust if > 64M on current system - */ - if (zone_size[0] <= sz) - return; - - zone_size[1] = zone_size[0] - sz; - zone_size[0] = sz; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; - } -} - static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) { /* clear our parent irq */ diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 57a0b68..07734f3 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -17,12 +17,7 @@ */ #define PLAT_PHYS_OFFSET UL(0xa0000000) -#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) -void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - cmx2xx_pci_adjust_zones(size, holes) - +#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) #define ARM_DMA_ZONE_SIZE SZ_64M #endif diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 75dbc87..525ad17 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -56,25 +56,6 @@ #include "core.h" -#ifdef CONFIG_ZONE_DMA -/* - * Adjust the zones if there are restrictions for DMA access. - */ -void __init realview_adjust_zones(unsigned long *size, unsigned long *hole) -{ - unsigned long dma_size = SZ_256M >> PAGE_SHIFT; - - if (!machine_is_realview_pbx() || size[0] <= dma_size) - return; - - size[ZONE_NORMAL] = size[0] - dma_size; - size[ZONE_DMA] = dma_size; - hole[ZONE_NORMAL] = hole[0]; - hole[ZONE_DMA] = 0; -} -#endif - - #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) static int realview_flash_init(void) diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h index 973428d..1759fa6 100644 --- a/arch/arm/mach-realview/include/mach/memory.h +++ b/arch/arm/mach-realview/include/mach/memory.h @@ -29,11 +29,7 @@ #define PLAT_PHYS_OFFSET UL(0x00000000) #endif -#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) -extern void realview_adjust_zones(unsigned long *size, unsigned long *hole); -#define arch_adjust_zones(size, hole) \ - realview_adjust_zones(size, hole) - +#ifdef CONFIG_ZONE_DMA #define ARM_DMA_ZONE_SIZE SZ_256M #endif diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index 090b829..cff31ee 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -14,17 +14,8 @@ */ #define PLAT_PHYS_OFFSET UL(0xc0000000) -#ifndef __ASSEMBLY__ - #ifdef CONFIG_SA1111 -void sa1111_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - sa1111_adjust_zones(size, holes) - #define ARM_DMA_ZONE_SIZE SZ_1M - -#endif #endif /* diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index 48fe84b..4c0831f8 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -17,25 +17,8 @@ */ #define PLAT_PHYS_OFFSET UL(0x08000000) -#ifndef __ASSEMBLY__ - -static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size) -{ - /* Only the first 4 MB (=1024 Pages) are usable for DMA */ - /* See dev / -> .properties in OpenFirmware. */ - zone_size[1] = zone_size[0] - 1024; - zone_size[0] = 1024; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; -} - -#define arch_adjust_zones(size, holes) \ - __arch_adjust_zones(size, holes) - #define ARM_DMA_ZONE_SIZE SZ_4M -#endif - /* * Cache flushing area */ diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index e5f6fc4..49eaad9 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -201,6 +201,20 @@ static void __init arm_bootmem_init(unsigned long start_pfn, } } +#ifdef CONFIG_ZONE_DMA +static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole, + unsigned long dma_size) +{ + if (size[0] <= dma_size) + return; + + size[ZONE_NORMAL] = size[0] - dma_size; + size[ZONE_DMA] = dma_size; + hole[ZONE_NORMAL] = hole[0]; + hole[ZONE_DMA] = 0; +} +#endif + static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, unsigned long max_high) { @@ -243,11 +257,18 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, #endif } +#ifdef ARM_DMA_ZONE_SIZE +#ifndef CONFIG_ZONE_DMA +#error ARM_DMA_ZONE_SIZE set but no DMA zone to limit allocations +#endif + /* * Adjust the sizes according to any special requirements for * this machine type. */ - arch_adjust_zones(zone_size, zhole_size); + arm_adjust_dma_zone(zone_size, zhole_size, + ARM_DMA_ZONE_SIZE >> PAGE_SHIFT); +#endif free_area_init_node(0, zone_size, min, zhole_size); } -- cgit v0.10.2 From bb2d8130dcc6d285b215b75d4ec2a9b2063efa4f Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 12 May 2011 09:52:02 +0100 Subject: ARM: SMP: drop experimental status SMP on ARM has been around for a while now, without any major issues being raised. So, drop the experimental status of this feature. Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 377a7a5..ac19a5a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1318,8 +1318,7 @@ menu "Kernel Features" source "kernel/time/Kconfig" config SMP - bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL + bool "Symmetric Multi-Processing" depends on CPU_V6K || CPU_V7 depends on GENERIC_CLOCKEVENTS depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ -- cgit v0.10.2 From e8db89a242f46820b622be48d65951879575efd1 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 12 May 2011 09:53:05 +0100 Subject: ARM: Highmem: drop experimental status Highmem on ARM has been around for a while now, without any major issues being raised. So, drop the experimental status of this feature. Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ac19a5a..a816a93 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1520,8 +1520,8 @@ config ARCH_SELECT_MEMORY_MODEL def_bool ARCH_SPARSEMEM_ENABLE config HIGHMEM - bool "High Memory Support (EXPERIMENTAL)" - depends on MMU && EXPERIMENTAL + bool "High Memory Support" + depends on MMU help The address space of ARM processors is only 4 Gigabytes large and it has to accommodate user address space, kernel address -- cgit v0.10.2 From 111e9a5ce66e64cbf9cf33a60982f29fd7e224da Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 12 May 2011 10:02:42 +0100 Subject: ARM: phys-to-virt: improve Kconfig help texts Improve the Kconfig help texts for the phys-to-virt patching feature. Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a816a93..3f3faaa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -197,15 +197,21 @@ config ARM_PATCH_PHYS_VIRT depends on !XIP_KERNEL && MMU depends on !ARCH_REALVIEW || !SPARSEMEM help - Patch phys-to-virt translation functions at runtime according to - the position of the kernel in system memory. + Patch phys-to-virt and virt-to-phys translation functions at + boot and module load time according to the position of the + kernel in system memory. - This can only be used with non-XIP with MMU kernels where - the base of physical memory is at a 16MB boundary. + This can only be used with non-XIP MMU kernels where the base + of physical memory is at a 16MB boundary, or theoretically 64K + for the MSM machine class. config ARM_PATCH_PHYS_VIRT_16BIT def_bool y depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM + help + This option extends the physical to virtual translation patching + to allow physical memory down to a theoretical minimum of 64K + boundaries. source "init/Kconfig" -- cgit v0.10.2 From af3e4fd37a18f2e5a00175bc96061541d1364a3b Mon Sep 17 00:00:00 2001 From: "Mark A. Greer" Date: Fri, 1 Apr 2011 15:41:26 +0100 Subject: ARM: 6859/1: Add writethrough dcache support for ARM926EJS processor The ARM kernel supports writethrough data cache via the CONFIG_CPU_DCACHE_WRITETHROUGH option. However, that functionality wasn't implemented in the arch/arm/boot/compressed code. It is now necessary due to a new ARM926EJS processor that has an issue with writeback data cache. Signed-off-by: Mark A. Greer Signed-off-by: Russell King diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index adf583c..ae7ecc2 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -447,7 +447,11 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size orr r1, r1, #3 << 10 add r2, r3, #16384 1: cmp r1, r9 @ if virt > start of RAM +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + orrhs r1, r1, #0x08 @ set cacheable +#else orrhs r1, r1, #0x0c @ set cacheable, bufferable +#endif cmp r1, r10 @ if virt > end of RAM bichs r1, r1, #0x0c @ clear cacheable, bufferable str r1, [r0], #4 @ 1:1 mapping @@ -472,6 +476,12 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size mov pc, lr ENDPROC(__setup_mmu) +__arm926ejs_mmu_cache_on: +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mov r0, #4 @ put dcache in WT mode + mcr p15, 7, r0, c15, c0, 0 +#endif + __armv4_mmu_cache_on: mov r12, lr #ifdef CONFIG_MMU @@ -653,6 +663,12 @@ proc_types: W(b) __armv4_mpu_cache_off W(b) __armv4_mpu_cache_flush + .word 0x41069260 @ ARM926EJ-S (v5TEJ) + .word 0xff0ffff0 + b __arm926ejs_mmu_cache_on + b __armv4_mmu_cache_off + b __armv5tej_mmu_cache_flush + .word 0x00007000 @ ARM7 IDs .word 0x0000f000 mov pc, lr -- cgit v0.10.2 From c1b0db56604b4ccc55a325104b14093aeedeb829 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 28 Apr 2011 18:43:01 +0100 Subject: ARM: 6889/1: futex: add SMP futex support when !CPU_USE_DOMAINS This patch uses the load/store exclusive instructions to add SMP futex support for ARM. Since the ARM architecture does not provide instructions for unprivileged exclusive memory accesses, we can only provide SMP futexes when CPU domain support is disabled. Cc: Nicolas Pitre Signed-off-by: Will Deacon Signed-off-by: Russell King diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h index 199a6b6..8c73900 100644 --- a/arch/arm/include/asm/futex.h +++ b/arch/arm/include/asm/futex.h @@ -3,16 +3,74 @@ #ifdef __KERNEL__ +#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP) +/* ARM doesn't provide unprivileged exclusive memory accessors */ +#include +#else + +#include +#include +#include + +#define __futex_atomic_ex_table(err_reg) \ + "3:\n" \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 4f, 2b, 4f\n" \ + " .popsection\n" \ + " .pushsection .fixup,\"ax\"\n" \ + "4: mov %0, " err_reg "\n" \ + " b 3b\n" \ + " .popsection" + #ifdef CONFIG_SMP -#include +#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ + smp_mb(); \ + __asm__ __volatile__( \ + "1: ldrex %1, [%2]\n" \ + " " insn "\n" \ + "2: strex %1, %0, [%2]\n" \ + " teq %1, #0\n" \ + " bne 1b\n" \ + " mov %0, #0\n" \ + __futex_atomic_ex_table("%4") \ + : "=&r" (ret), "=&r" (oldval) \ + : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ + : "cc", "memory") + +static inline int +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) +{ + int ret; + u32 val; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + return -EFAULT; + + smp_mb(); + __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" + "1: ldrex %1, [%4]\n" + " teq %1, %2\n" + " ite eq @ explicit IT needed for the 2b label\n" + "2: strexeq %0, %3, [%4]\n" + " movne %0, #0\n" + " teq %0, #0\n" + " bne 1b\n" + __futex_atomic_ex_table("%5") + : "=&r" (ret), "=&r" (val) + : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) + : "cc", "memory"); + smp_mb(); + + *uval = val; + return ret; +} #else /* !SMP, we can work around lack of atomic ops by disabling preemption */ -#include #include -#include -#include #include #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ @@ -21,20 +79,38 @@ " " insn "\n" \ "2: " T(str) " %0, [%2]\n" \ " mov %0, #0\n" \ - "3:\n" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 4f, 2b, 4f\n" \ - " .popsection\n" \ - " .pushsection .fixup,\"ax\"\n" \ - "4: mov %0, %4\n" \ - " b 3b\n" \ - " .popsection" \ + __futex_atomic_ex_table("%4") \ : "=&r" (ret), "=&r" (oldval) \ : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ : "cc", "memory") static inline int +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) +{ + int ret = 0; + u32 val; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + return -EFAULT; + + __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" + "1: " T(ldr) " %1, [%4]\n" + " teq %1, %2\n" + " it eq @ explicit IT needed for the 2b label\n" + "2: " T(streq) " %3, [%4]\n" + __futex_atomic_ex_table("%5") + : "+r" (ret), "=&r" (val) + : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) + : "cc", "memory"); + + *uval = val; + return ret; +} + +#endif /* !SMP */ + +static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; @@ -87,39 +163,6 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) return ret; } -static inline int -futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, - u32 oldval, u32 newval) -{ - int ret = 0; - u32 val; - - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) - return -EFAULT; - - __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" - "1: " T(ldr) " %1, [%4]\n" - " teq %1, %2\n" - " it eq @ explicit IT needed for the 2b label\n" - "2: " T(streq) " %3, [%4]\n" - "3:\n" - " .pushsection __ex_table,\"a\"\n" - " .align 3\n" - " .long 1b, 4f, 2b, 4f\n" - " .popsection\n" - " .pushsection .fixup,\"ax\"\n" - "4: mov %0, %5\n" - " b 3b\n" - " .popsection" - : "+r" (ret), "=&r" (val) - : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) - : "cc", "memory"); - - *uval = val; - return ret; -} - -#endif /* !SMP */ - +#endif /* !(CPU_USE_DOMAINS && SMP) */ #endif /* __KERNEL__ */ #endif /* _ASM_ARM_FUTEX_H */ -- cgit v0.10.2 From 4394c1244249198c6b85093d46935b761b36ae05 Mon Sep 17 00:00:00 2001 From: Victor Boivie Date: Wed, 4 May 2011 17:07:55 +0100 Subject: ARM: 6893/1: Allow for kernel command line concatenation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch allows the provided CONFIG_CMDLINE to be concatenated with the one provided by the boot loader. This is useful to merge the static values defined in CONFIG_CMDLINE with the boot loader's (possibly) more dynamic values, such as startup reasons and more. Signed-off-by: Victor Boivie Reviewed-by: Bjorn Andersson Signed-off-by: Oskar Andero Acked-by: Nicolas Pitre Acked-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3f3faaa..7fd33a3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1747,16 +1747,31 @@ config CMDLINE time by entering them here. As a minimum, you should specify the memory size and the root device (e.g., mem=64M root=/dev/nfs). +choice + prompt "Kernel command line type" if CMDLINE != "" + default CMDLINE_FROM_BOOTLOADER + +config CMDLINE_FROM_BOOTLOADER + bool "Use bootloader kernel arguments if available" + help + Uses the command-line options passed by the boot loader. If + the boot loader doesn't provide any, the default kernel command + string provided in CMDLINE will be used. + +config CMDLINE_EXTEND + bool "Extend bootloader kernel arguments" + help + The command-line arguments provided by the boot loader will be + appended to the default kernel command string. + config CMDLINE_FORCE bool "Always use the default kernel command string" - depends on CMDLINE != "" help Always use the default kernel command string, even if the boot loader passes other arguments to the kernel. This is useful if you cannot or don't want to change the command-line options your boot loader passes to the kernel. - - If unsure, say N. +endchoice config XIP_KERNEL bool "Kernel Execute-In-Place from ROM" diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 006c1e8..6dce209 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -672,11 +672,16 @@ __tagtable(ATAG_REVISION, parse_tag_revision); static int __init parse_tag_cmdline(const struct tag *tag) { -#ifndef CONFIG_CMDLINE_FORCE - strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); -#else +#if defined(CONFIG_CMDLINE_EXTEND) + strlcat(default_command_line, " ", COMMAND_LINE_SIZE); + strlcat(default_command_line, tag->u.cmdline.cmdline, + COMMAND_LINE_SIZE); +#elif defined(CONFIG_CMDLINE_FORCE) pr_warning("Ignoring tag cmdline (using the default kernel command line)\n"); -#endif /* CONFIG_CMDLINE_FORCE */ +#else + strlcpy(default_command_line, tag->u.cmdline.cmdline, + COMMAND_LINE_SIZE); +#endif return 0; } -- cgit v0.10.2 From 399bc4863e2a3b4b255ca22189820c81ca34f4e0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 1 Apr 2011 07:59:17 +0100 Subject: ARM: 6858/1: mmci: force negative edge on clock bypass for ux500 This fixes a regression on high clock speeds with the MMCI on ux500. We need to make sure we derive the passthru clock on the falling edge of the incoming clock if it shall work at high frequencies, and on the ux500's there is a special bit for this. Signed-off-by: Linus Walleij Signed-off-by: Russell King diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 92061f8..4941e06 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -103,6 +103,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) if (desired) { if (desired >= host->mclk) { clk = MCI_CLK_BYPASS; + if (variant->st_clkdiv) + clk |= MCI_ST_UX500_NEG_EDGE; host->cclk = host->mclk; } else if (variant->st_clkdiv) { /* -- cgit v0.10.2 From 4c3b512c6b054e8c0bf14b1d61b20d4569de0a21 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Mon, 18 Apr 2011 14:48:22 +0100 Subject: ARM: 6882/1: ELF: Define new core note type for VFP registers The VFP registers are not currently included in coredumps, and there's no existing note type where they can sensibly be included, so this patch defines a dedicated note type for them. Signed-off-by: Dave Martin Acked-by: Will Deacon Signed-off-by: Russell King diff --git a/include/linux/elf.h b/include/linux/elf.h index 4d60801..110821c 100644 --- a/include/linux/elf.h +++ b/include/linux/elf.h @@ -395,6 +395,7 @@ typedef struct elf64_shdr { #define NT_S390_CTRS 0x304 /* s390 control registers */ #define NT_S390_PREFIX 0x305 /* s390 prefix register */ #define NT_S390_LAST_BREAK 0x306 /* s390 breaking event address */ +#define NT_ARM_VFP 0x400 /* ARM VFP/NEON registers */ /* Note header in a PT_NOTE section */ -- cgit v0.10.2 From 5be6f62b0059a3344437b4c2877152c58cb3fdeb Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Mon, 18 Apr 2011 14:48:23 +0100 Subject: ARM: 6883/1: ptrace: Migrate to regsets framework This patch migrates the implementation of the ptrace interface for the core integer registers, legacy FPA registers and VFP registers to use the regsets framework. As an added bonus, all this stuff gets included in coredumps at no extra cost. Without this patch, coredumps contained no VFP state. Third-party extension register sets (iwmmx, crunch) are not migrated by this patch, and continue to use the old implementation; these should be migratable without much extra work. Signed-off-by: Dave Martin Acked-by: Will Deacon Signed-off-by: Russell King diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index c3cd875..0e9ce8d 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -108,6 +108,7 @@ struct task_struct; int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define ELF_CORE_COPY_TASK_REGS dump_task_regs +#define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index a8ff22b..312d108 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -128,6 +128,12 @@ struct pt_regs { #define ARM_r0 uregs[0] #define ARM_ORIG_r0 uregs[17] +/* + * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS + * and core dumps. + */ +#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ ) + #ifdef __KERNEL__ #define user_mode(regs) \ diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 8182f45..9726006 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -308,58 +309,6 @@ static int ptrace_write_user(struct task_struct *tsk, unsigned long off, return put_user_reg(tsk, off >> 2, val); } -/* - * Get all user integer registers. - */ -static int ptrace_getregs(struct task_struct *tsk, void __user *uregs) -{ - struct pt_regs *regs = task_pt_regs(tsk); - - return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0; -} - -/* - * Set all user integer registers. - */ -static int ptrace_setregs(struct task_struct *tsk, void __user *uregs) -{ - struct pt_regs newregs; - int ret; - - ret = -EFAULT; - if (copy_from_user(&newregs, uregs, sizeof(struct pt_regs)) == 0) { - struct pt_regs *regs = task_pt_regs(tsk); - - ret = -EINVAL; - if (valid_user_regs(&newregs)) { - *regs = newregs; - ret = 0; - } - } - - return ret; -} - -/* - * Get the child FPU state. - */ -static int ptrace_getfpregs(struct task_struct *tsk, void __user *ufp) -{ - return copy_to_user(ufp, &task_thread_info(tsk)->fpstate, - sizeof(struct user_fp)) ? -EFAULT : 0; -} - -/* - * Set the child FPU state. - */ -static int ptrace_setfpregs(struct task_struct *tsk, void __user *ufp) -{ - struct thread_info *thread = task_thread_info(tsk); - thread->used_cp[1] = thread->used_cp[2] = 1; - return copy_from_user(&thread->fpstate, ufp, - sizeof(struct user_fp)) ? -EFAULT : 0; -} - #ifdef CONFIG_IWMMXT /* @@ -418,56 +367,6 @@ static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp) } #endif -#ifdef CONFIG_VFP -/* - * Get the child VFP state. - */ -static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data) -{ - struct thread_info *thread = task_thread_info(tsk); - union vfp_state *vfp = &thread->vfpstate; - struct user_vfp __user *ufp = data; - - vfp_sync_hwstate(thread); - - /* copy the floating point registers */ - if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs, - sizeof(vfp->hard.fpregs))) - return -EFAULT; - - /* copy the status and control register */ - if (put_user(vfp->hard.fpscr, &ufp->fpscr)) - return -EFAULT; - - return 0; -} - -/* - * Set the child VFP state. - */ -static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data) -{ - struct thread_info *thread = task_thread_info(tsk); - union vfp_state *vfp = &thread->vfpstate; - struct user_vfp __user *ufp = data; - - vfp_sync_hwstate(thread); - - /* copy the floating point registers */ - if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs, - sizeof(vfp->hard.fpregs))) - return -EFAULT; - - /* copy the status and control register */ - if (get_user(vfp->hard.fpscr, &ufp->fpscr)) - return -EFAULT; - - vfp_flush_hwstate(thread); - - return 0; -} -#endif - #ifdef CONFIG_HAVE_HW_BREAKPOINT /* * Convert a virtual register number into an index for a thread_info @@ -694,6 +593,219 @@ out: } #endif +/* regset get/set implementations */ + +static int gpr_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + struct pt_regs *regs = task_pt_regs(target); + + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + regs, + 0, sizeof(*regs)); +} + +static int gpr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct pt_regs newregs; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &newregs, + 0, sizeof(newregs)); + if (ret) + return ret; + + if (!valid_user_regs(&newregs)) + return -EINVAL; + + *task_pt_regs(target) = newregs; + return 0; +} + +static int fpa_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &task_thread_info(target)->fpstate, + 0, sizeof(struct user_fp)); +} + +static int fpa_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct thread_info *thread = task_thread_info(target); + + thread->used_cp[1] = thread->used_cp[2] = 1; + + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &thread->fpstate, + 0, sizeof(struct user_fp)); +} + +#ifdef CONFIG_VFP +/* + * VFP register get/set implementations. + * + * With respect to the kernel, struct user_fp is divided into three chunks: + * 16 or 32 real VFP registers (d0-d15 or d0-31) + * These are transferred to/from the real registers in the task's + * vfp_hard_struct. The number of registers depends on the kernel + * configuration. + * + * 16 or 0 fake VFP registers (d16-d31 or empty) + * i.e., the user_vfp structure has space for 32 registers even if + * the kernel doesn't have them all. + * + * vfp_get() reads this chunk as zero where applicable + * vfp_set() ignores this chunk + * + * 1 word for the FPSCR + * + * The bounds-checking logic built into user_regset_copyout and friends + * means that we can make a simple sequence of calls to map the relevant data + * to/from the specified slice of the user regset structure. + */ +static int vfp_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + int ret; + struct thread_info *thread = task_thread_info(target); + struct vfp_hard_struct const *vfp = &thread->vfpstate.hard; + const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); + const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); + + vfp_sync_hwstate(thread); + + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &vfp->fpregs, + user_fpregs_offset, + user_fpregs_offset + sizeof(vfp->fpregs)); + if (ret) + return ret; + + ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, + user_fpregs_offset + sizeof(vfp->fpregs), + user_fpscr_offset); + if (ret) + return ret; + + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &vfp->fpscr, + user_fpscr_offset, + user_fpscr_offset + sizeof(vfp->fpscr)); +} + +/* + * For vfp_set() a read-modify-write is done on the VFP registers, + * in order to avoid writing back a half-modified set of registers on + * failure. + */ +static int vfp_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct thread_info *thread = task_thread_info(target); + struct vfp_hard_struct new_vfp = thread->vfpstate.hard; + const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); + const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &new_vfp.fpregs, + user_fpregs_offset, + user_fpregs_offset + sizeof(new_vfp.fpregs)); + if (ret) + return ret; + + ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, + user_fpregs_offset + sizeof(new_vfp.fpregs), + user_fpscr_offset); + if (ret) + return ret; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &new_vfp.fpscr, + user_fpscr_offset, + user_fpscr_offset + sizeof(new_vfp.fpscr)); + if (ret) + return ret; + + vfp_sync_hwstate(thread); + thread->vfpstate.hard = new_vfp; + vfp_flush_hwstate(thread); + + return 0; +} +#endif /* CONFIG_VFP */ + +enum arm_regset { + REGSET_GPR, + REGSET_FPR, +#ifdef CONFIG_VFP + REGSET_VFP, +#endif +}; + +static const struct user_regset arm_regsets[] = { + [REGSET_GPR] = { + .core_note_type = NT_PRSTATUS, + .n = ELF_NGREG, + .size = sizeof(u32), + .align = sizeof(u32), + .get = gpr_get, + .set = gpr_set + }, + [REGSET_FPR] = { + /* + * For the FPA regs in fpstate, the real fields are a mixture + * of sizes, so pretend that the registers are word-sized: + */ + .core_note_type = NT_PRFPREG, + .n = sizeof(struct user_fp) / sizeof(u32), + .size = sizeof(u32), + .align = sizeof(u32), + .get = fpa_get, + .set = fpa_set + }, +#ifdef CONFIG_VFP + [REGSET_VFP] = { + /* + * Pretend that the VFP regs are word-sized, since the FPSCR is + * a single word dangling at the end of struct user_vfp: + */ + .core_note_type = NT_ARM_VFP, + .n = ARM_VFPREGS_SIZE / sizeof(u32), + .size = sizeof(u32), + .align = sizeof(u32), + .get = vfp_get, + .set = vfp_set + }, +#endif /* CONFIG_VFP */ +}; + +static const struct user_regset_view user_arm_view = { + .name = "arm", .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, + .regsets = arm_regsets, .n = ARRAY_SIZE(arm_regsets) +}; + +const struct user_regset_view *task_user_regset_view(struct task_struct *task) +{ + return &user_arm_view; +} + long arch_ptrace(struct task_struct *child, long request, unsigned long addr, unsigned long data) { @@ -710,19 +822,31 @@ long arch_ptrace(struct task_struct *child, long request, break; case PTRACE_GETREGS: - ret = ptrace_getregs(child, datap); + ret = copy_regset_to_user(child, + &user_arm_view, REGSET_GPR, + 0, sizeof(struct pt_regs), + datap); break; case PTRACE_SETREGS: - ret = ptrace_setregs(child, datap); + ret = copy_regset_from_user(child, + &user_arm_view, REGSET_GPR, + 0, sizeof(struct pt_regs), + datap); break; case PTRACE_GETFPREGS: - ret = ptrace_getfpregs(child, datap); + ret = copy_regset_to_user(child, + &user_arm_view, REGSET_FPR, + 0, sizeof(union fp_state), + datap); break; - + case PTRACE_SETFPREGS: - ret = ptrace_setfpregs(child, datap); + ret = copy_regset_from_user(child, + &user_arm_view, REGSET_FPR, + 0, sizeof(union fp_state), + datap); break; #ifdef CONFIG_IWMMXT @@ -757,11 +881,17 @@ long arch_ptrace(struct task_struct *child, long request, #ifdef CONFIG_VFP case PTRACE_GETVFPREGS: - ret = ptrace_getvfpregs(child, datap); + ret = copy_regset_to_user(child, + &user_arm_view, REGSET_VFP, + 0, ARM_VFPREGS_SIZE, + datap); break; case PTRACE_SETVFPREGS: - ret = ptrace_setvfpregs(child, datap); + ret = copy_regset_from_user(child, + &user_arm_view, REGSET_VFP, + 0, ARM_VFPREGS_SIZE, + datap); break; #endif -- cgit v0.10.2 From 60ba5369135e05f040ea1f6b8130c7b082ed53c8 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 7 May 2011 08:48:24 +0100 Subject: ARM: Update mach-types Signed-off-by: Russell King diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 7ca41f0..3b3776d 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -17,7 +17,7 @@ # XXX: the last 12 months. If your entry is missing please email rmk at # XXX: # -# Last update: Sun Mar 20 18:06:11 2011 +# Last update: Sat May 7 08:48:24 2011 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -377,6 +377,8 @@ davinci_da850_evm MACH_DAVINCI_DA850_EVM DAVINCI_DA850_EVM 2157 at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159 omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 +btmavb101 MACH_BTMAVB101 BTMAVB101 2172 +btmawb101 MACH_BTMAWB101 BTMAWB101 2173 omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 anw6410 MACH_ANW6410 ANW6410 2183 imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187 @@ -400,6 +402,7 @@ d2net MACH_D2NET D2NET 2282 bigdisk MACH_BIGDISK BIGDISK 2283 at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 bcmring MACH_BCMRING BCMRING 2289 +dp6xx MACH_DP6XX DP6XX 2302 mahimahi MACH_MAHIMAHI MAHIMAHI 2304 smdk6442 MACH_SMDK6442 SMDK6442 2324 openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 @@ -424,6 +427,7 @@ smdkv210 MACH_SMDKV210 SMDKV210 2456 omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464 omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465 smartq7 MACH_SMARTQ7 SMARTQ7 2479 +watson_efm_plugin MACH_WATSON_EFM_PLUGIN WATSON_EFM_PLUGIN 2491 g4evm MACH_G4EVM G4EVM 2493 omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495 ts41x MACH_TS41X TS41X 2502 @@ -433,6 +437,8 @@ mx28evk MACH_MX28EVK MX28EVK 2531 smartq5 MACH_SMARTQ5 SMARTQ5 2534 davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548 mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 +riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576 +riot_x37 MACH_RIOT_X37 RIOT_X37 2578 capc7117 MACH_CAPC7117 CAPC7117 2612 icontrol MACH_ICONTROL ICONTROL 2624 qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627 @@ -445,6 +451,7 @@ spear320 MACH_SPEAR320 SPEAR320 2661 aquila MACH_AQUILA AQUILA 2676 sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678 msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679 +ea2478devkit MACH_EA2478DEVKIT EA2478DEVKIT 2683 terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697 msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703 msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704 @@ -463,75 +470,16 @@ wbd222 MACH_WBD222 WBD222 2753 msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755 msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756 tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758 -ap420 MACH_AP420 AP420 2765 -davinci_dm365_fc MACH_DAVINCI_DM365_FC DAVINCI_DM365_FC 2767 -msm8x55_surf MACH_MSM8X55_SURF MSM8X55_SURF 2768 -msm8x55_ffa MACH_MSM8X55_FFA MSM8X55_FFA 2769 -esl_vamana MACH_ESL_VAMANA ESL_VAMANA 2770 -sbc35 MACH_SBC35 SBC35 2771 -mpx6446 MACH_MPX6446 MPX6446 2772 -oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773 -kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774 -ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775 +nanos MACH_NANOS NANOS 2759 +stamp9g45 MACH_STAMP9G45 STAMP9G45 2761 cns3420vb MACH_CNS3420VB CNS3420VB 2776 -olympus MACH_OLYMPUS OLYMPUS 2778 -vortex MACH_VORTEX VORTEX 2779 -s5pc200 MACH_S5PC200 S5PC200 2780 -ecucore_9263 MACH_ECUCORE_9263 ECUCORE_9263 2781 -smdkc200 MACH_SMDKC200 SMDKC200 2782 -emsiso_sx27 MACH_EMSISO_SX27 EMSISO_SX27 2783 -apx_som9g45_ek MACH_APX_SOM9G45_EK APX_SOM9G45_EK 2784 -songshan MACH_SONGSHAN SONGSHAN 2785 -tianshan MACH_TIANSHAN TIANSHAN 2786 -vpx500 MACH_VPX500 VPX500 2787 -am3517sam MACH_AM3517SAM AM3517SAM 2788 -skat91_sim508 MACH_SKAT91_SIM508 SKAT91_SIM508 2789 -skat91_s3e MACH_SKAT91_S3E SKAT91_S3E 2790 omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791 -df7220 MACH_DF7220 DF7220 2792 -nemini MACH_NEMINI NEMINI 2793 -t8200 MACH_T8200 T8200 2794 -apf51 MACH_APF51 APF51 2795 -dr_rc_unit MACH_DR_RC_UNIT DR_RC_UNIT 2796 -bordeaux MACH_BORDEAUX BORDEAUX 2797 -catania_b MACH_CATANIA_B CATANIA_B 2798 -mx51_ocean MACH_MX51_OCEAN MX51_OCEAN 2799 ti8168evm MACH_TI8168EVM TI8168EVM 2800 -neocoreomap MACH_NEOCOREOMAP NEOCOREOMAP 2801 -withings_wbp MACH_WITHINGS_WBP WITHINGS_WBP 2802 -dbps MACH_DBPS DBPS 2803 -pcbfp0001 MACH_PCBFP0001 PCBFP0001 2805 -speedy MACH_SPEEDY SPEEDY 2806 -chrysaor MACH_CHRYSAOR CHRYSAOR 2807 -tango MACH_TANGO TANGO 2808 -synology_dsx11 MACH_SYNOLOGY_DSX11 SYNOLOGY_DSX11 2809 -hanlin_v3ext MACH_HANLIN_V3EXT HANLIN_V3EXT 2810 -hanlin_v5 MACH_HANLIN_V5 HANLIN_V5 2811 -hanlin_v3plus MACH_HANLIN_V3PLUS HANLIN_V3PLUS 2812 -iriver_story MACH_IRIVER_STORY IRIVER_STORY 2813 -irex_iliad MACH_IREX_ILIAD IREX_ILIAD 2814 -irex_dr1000 MACH_IREX_DR1000 IREX_DR1000 2815 teton_bga MACH_TETON_BGA TETON_BGA 2816 -snapper9g45 MACH_SNAPPER9G45 SNAPPER9G45 2817 -tam3517 MACH_TAM3517 TAM3517 2818 -pdc100 MACH_PDC100 PDC100 2819 eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820 eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821 eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822 eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823 -p565 MACH_P565 P565 2824 -acer_a4 MACH_ACER_A4 ACER_A4 2825 -davinci_dm368_bip MACH_DAVINCI_DM368_BIP DAVINCI_DM368_BIP 2826 -eshare MACH_ESHARE ESHARE 2827 -wlbargn MACH_WLBARGN WLBARGN 2829 -bm170 MACH_BM170 BM170 2830 -netspace_mini_v2 MACH_NETSPACE_MINI_V2 NETSPACE_MINI_V2 2831 -netspace_plug_v2 MACH_NETSPACE_PLUG_V2 NETSPACE_PLUG_V2 2832 -siemens_l1 MACH_SIEMENS_L1 SIEMENS_L1 2833 -elv_lcu1 MACH_ELV_LCU1 ELV_LCU1 2834 -mcu1 MACH_MCU1 MCU1 2835 -omap3_tao3530 MACH_OMAP3_TAO3530 OMAP3_TAO3530 2836 -omap3_pcutouch MACH_OMAP3_PCUTOUCH OMAP3_PCUTOUCH 2837 smdkc210 MACH_SMDKC210 SMDKC210 2838 omap3_braillo MACH_OMAP3_BRAILLO OMAP3_BRAILLO 2839 spyplug MACH_SPYPLUG SPYPLUG 2840 @@ -973,9 +921,7 @@ isc3 MACH_ISC3 ISC3 3291 rascal MACH_RASCAL RASCAL 3292 hrefv60 MACH_HREFV60 HREFV60 3293 tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294 -pyramid_td MACH_PYRAMID_TD PYRAMID_TD 3295 splendor MACH_SPLENDOR SPLENDOR 3296 -guf_planet MACH_GUF_PLANET GUF_PLANET 3297 msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298 htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299 athene MACH_ATHENE ATHENE 3300 @@ -1099,3 +1045,71 @@ ecuv5 MACH_ECUV5 ECUV5 3421 hsgx6d MACH_HSGX6D HSGX6D 3422 dawad7 MACH_DAWAD7 DAWAD7 3423 sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424 +gt_i5700 MACH_GT_I5700 GT_I5700 3425 +ctera_plug_c2 MACH_CTERA_PLUG_C2 CTERA_PLUG_C2 3426 +marvelct MACH_MARVELCT MARVELCT 3427 +ag11005 MACH_AG11005 AG11005 3428 +vangogh MACH_VANGOGH VANGOGH 3430 +matrix505 MACH_MATRIX505 MATRIX505 3431 +oce_nigma MACH_OCE_NIGMA OCE_NIGMA 3432 +t55 MACH_T55 T55 3433 +bio3k MACH_BIO3K BIO3K 3434 +expressct MACH_EXPRESSCT EXPRESSCT 3435 +cardhu MACH_CARDHU CARDHU 3436 +aruba MACH_ARUBA ARUBA 3437 +bonaire MACH_BONAIRE BONAIRE 3438 +nuc700evb MACH_NUC700EVB NUC700EVB 3439 +nuc710evb MACH_NUC710EVB NUC710EVB 3440 +nuc740evb MACH_NUC740EVB NUC740EVB 3441 +nuc745evb MACH_NUC745EVB NUC745EVB 3442 +transcede MACH_TRANSCEDE TRANSCEDE 3443 +mora MACH_MORA MORA 3444 +nda_evm MACH_NDA_EVM NDA_EVM 3445 +timu MACH_TIMU TIMU 3446 +expressh MACH_EXPRESSH EXPRESSH 3447 +veridis_a300 MACH_VERIDIS_A300 VERIDIS_A300 3448 +dm368_leopard MACH_DM368_LEOPARD DM368_LEOPARD 3449 +omap_mcop MACH_OMAP_MCOP OMAP_MCOP 3450 +tritip MACH_TRITIP TRITIP 3451 +sm1k MACH_SM1K SM1K 3452 +monch MACH_MONCH MONCH 3453 +curacao MACH_CURACAO CURACAO 3454 +origen MACH_ORIGEN ORIGEN 3455 +epc10 MACH_EPC10 EPC10 3456 +sgh_i740 MACH_SGH_I740 SGH_I740 3457 +tuna MACH_TUNA TUNA 3458 +mx51_tulip MACH_MX51_TULIP MX51_TULIP 3459 +mx51_aster7 MACH_MX51_ASTER7 MX51_ASTER7 3460 +acro37xbrd MACH_ACRO37XBRD ACRO37XBRD 3461 +elke MACH_ELKE ELKE 3462 +sbc6000x MACH_SBC6000X SBC6000X 3463 +r1801e MACH_R1801E R1801E 3464 +h1600 MACH_H1600 H1600 3465 +mini210 MACH_MINI210 MINI210 3466 +mini8168 MACH_MINI8168 MINI8168 3467 +pc7308 MACH_PC7308 PC7308 3468 +kmm2m01 MACH_KMM2M01 KMM2M01 3470 +mx51erebus MACH_MX51EREBUS MX51EREBUS 3471 +wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472 +tuxrail MACH_TUXRAIL TUXRAIL 3473 +arthur MACH_ARTHUR ARTHUR 3474 +doorboy MACH_DOORBOY DOORBOY 3475 +xarina MACH_XARINA XARINA 3476 +roverx7 MACH_ROVERX7 ROVERX7 3477 +sdvr MACH_SDVR SDVR 3478 +acer_maya MACH_ACER_MAYA ACER_MAYA 3479 +pico MACH_PICO PICO 3480 +cwmx233 MACH_CWMX233 CWMX233 3481 +cwam1808 MACH_CWAM1808 CWAM1808 3482 +cwdm365 MACH_CWDM365 CWDM365 3483 +mx51_moray MACH_MX51_MORAY MX51_MORAY 3484 +thales_cbc MACH_THALES_CBC THALES_CBC 3485 +bluepoint MACH_BLUEPOINT BLUEPOINT 3486 +dir665 MACH_DIR665 DIR665 3487 +acmerover1 MACH_ACMEROVER1 ACMEROVER1 3488 +shooter_ct MACH_SHOOTER_CT SHOOTER_CT 3489 +bliss MACH_BLISS BLISS 3490 +blissc MACH_BLISSC BLISSC 3491 +thales_adc MACH_THALES_ADC THALES_ADC 3492 +ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493 +atdgp318 MACH_ATDGP318 ATDGP318 3494 -- cgit v0.10.2 From 667a11facee70c0bd15cf07946fba71236490e07 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 May 2011 02:07:38 -0700 Subject: arm: omap2/3: Use generic irq chip Use generic irq chip for omap2 & 3. Note that this patch also leaves out the spurious IRQ warning for omap3. This warning should no longer be needed as the interrupt handlers for various devices have implemented the necessayr read-back of the posted write. Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 237e453..3af2b7a 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -73,83 +73,18 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) return __raw_readl(bank->base_reg + reg); } -static int previous_irq; - -/* - * On 34xx we can get occasional spurious interrupts if the ack from - * an interrupt handler does not get posted before we unmask. Warn about - * the interrupt handlers that need to flush posted writes. - */ -static int omap_check_spurious(unsigned int irq) -{ - u32 sir, spurious; - - sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR); - spurious = sir >> 7; - - if (spurious) { - printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush " - "posted write for irq %i\n", - irq, sir, previous_irq); - return spurious; - } - - return 0; -} - /* XXX: FIQ and additional INTC support (only MPU at the moment) */ static void omap_ack_irq(struct irq_data *d) { intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); } -static void omap_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq; - int offset = irq & (~(IRQ_BITS_PER_REG - 1)); - - if (cpu_is_omap34xx() && !cpu_is_ti816x()) { - int spurious = 0; - - /* - * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because - * it is the highest irq number? - */ - if (irq == INT_34XX_GPT12_IRQ) - spurious = omap_check_spurious(irq); - - if (!spurious) - previous_irq = irq; - } - - irq &= (IRQ_BITS_PER_REG - 1); - - intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset); -} - -static void omap_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq; - int offset = irq & (~(IRQ_BITS_PER_REG - 1)); - - irq &= (IRQ_BITS_PER_REG - 1); - - intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset); -} - static void omap_mask_ack_irq(struct irq_data *d) { - omap_mask_irq(d); + irq_gc_mask_disable_reg(d); omap_ack_irq(d); } -static struct irq_chip omap_irq_chip = { - .name = "INTC", - .irq_ack = omap_mask_ack_irq, - .irq_mask = omap_mask_irq, - .irq_unmask = omap_unmask_irq, -}; - static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) { unsigned long tmp; @@ -186,11 +121,31 @@ int omap_irq_pending(void) return 0; } +static __init void +omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_ack = omap_mask_ack_irq; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + + ct->regs.ack = INTC_CONTROL; + ct->regs.enable = INTC_MIR_CLEAR0; + ct->regs.disable = INTC_MIR_SET0; + irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); +} + void __init omap_init_irq(void) { unsigned long nr_of_irqs = 0; unsigned int nr_banks = 0; - int i; + int i, j; for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { unsigned long base = 0; @@ -215,17 +170,15 @@ void __init omap_init_irq(void) omap_irq_bank_init_one(bank); + for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20) + omap_alloc_gc(bank->base_reg + j, i, 32); + nr_of_irqs += bank->nr_irqs; nr_banks++; } printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n", nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); - - for (i = 0; i < nr_of_irqs; i++) { - irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } } #ifdef CONFIG_ARCH_OMAP3 -- cgit v0.10.2 From 5f23188e036aabfe9245f9e61adbb4ea27ed8f35 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Mon, 16 May 2011 11:43:55 +0100 Subject: ARM: 6900/1: Suspend: Fix build error on ARCH_S5PC100 The current mainline codes of ARCH_S5PC100 cannot support suspend to ram. So needs this for preventing build error. Cc: Russell King Signed-off-by: Kukjin Kim Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 377a7a5..96839d9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2010,7 +2010,7 @@ menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE - depends on !ARCH_S5P64X0 && !ARCH_S5P6442 + depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE def_bool y -- cgit v0.10.2 From 8373dc38ca8d4918210710807256a313cd111f0b Mon Sep 17 00:00:00 2001 From: saeed bishara Date: Mon, 16 May 2011 15:41:15 +0100 Subject: ARM: 6901/1: remove unneeded check of the cache_is_vipt_nonaliasing() when cache_is_vipt_nonaliasing(), we always have pte_exec() true at the end of this function, so no need for the additional check. Acked-by: Catalin Marinas Signed-off-by: Saeed Bishara Signed-off-by: Russell King diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 2b269c9..f1b7998 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -253,8 +253,8 @@ void __sync_icache_dcache(pte_t pteval) if (!test_and_set_bit(PG_dcache_clean, &page->flags)) __flush_dcache_page(mapping, page); - /* pte_exec() already checked above for non-aliasing VIPT cache */ - if (cache_is_vipt_nonaliasing() || pte_exec(pteval)) + + if (pte_exec(pteval)) __flush_icache_all(); } #endif -- cgit v0.10.2 From e59347a1d15c0b1d9fdc510520f8fa78d7d19a5b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 14 Apr 2011 19:17:57 +0200 Subject: arm: orion: Use generic irq chip The core interrupt chip is a straight forward conversion. The gpio chip is implemented with two instances of the irq_chip_type which can be switched with the irq_set_type function. That allows us to use the generic callbacks and avoids the conditionals in them. Signed-off-by: Thomas Gleixner Signed-off-by: Nicolas Pitre diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index a431a13..5b4fffa 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -321,59 +321,16 @@ EXPORT_SYMBOL(orion_gpio_set_blink); * polarity LEVEL mask * ****************************************************************************/ -static void gpio_irq_ack(struct irq_data *d) -{ - struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type = irqd_get_trigger_type(d); - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - int pin = d->irq - ochip->secondary_irq_base; - - writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip)); - } -} - -static void gpio_irq_mask(struct irq_data *d) -{ - struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type = irqd_get_trigger_type(d); - void __iomem *reg; - int pin; - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - reg = GPIO_EDGE_MASK(ochip); - else - reg = GPIO_LEVEL_MASK(ochip); - - pin = d->irq - ochip->secondary_irq_base; - - writel(readl(reg) & ~(1 << pin), reg); -} - -static void gpio_irq_unmask(struct irq_data *d) -{ - struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type = irqd_get_trigger_type(d); - void __iomem *reg; - int pin; - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - reg = GPIO_EDGE_MASK(ochip); - else - reg = GPIO_LEVEL_MASK(ochip); - - pin = d->irq - ochip->secondary_irq_base; - - writel(readl(reg) | (1 << pin), reg); -} static int gpio_irq_set_type(struct irq_data *d, u32 type) { - struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); + struct orion_gpio_chip *ochip = gc->private; int pin; u32 u; - pin = d->irq - ochip->secondary_irq_base; + pin = d->irq - gc->irq_base; u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); if (!u) { @@ -382,18 +339,14 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type) return -EINVAL; } - /* - * Set edge/level type. - */ - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - __irq_set_handler_locked(d->irq, handle_edge_irq); - } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - __irq_set_handler_locked(d->irq, handle_level_irq); - } else { - printk(KERN_ERR "failed to set irq=%d (type=%d)\n", - d->irq, type); + type &= IRQ_TYPE_SENSE_MASK; + if (type == IRQ_TYPE_NONE) return -EINVAL; - } + + /* Check if we need to change chip and handler */ + if (!(ct->type & type)) + if (irq_setup_alt_chip(d, type)) + return -EINVAL; /* * Configure interrupt polarity. @@ -425,19 +378,12 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type) return 0; } -struct irq_chip orion_gpio_irq_chip = { - .name = "orion_gpio_irq", - .irq_ack = gpio_irq_ack, - .irq_mask = gpio_irq_mask, - .irq_unmask = gpio_irq_unmask, - .irq_set_type = gpio_irq_set_type, -}; - void __init orion_gpio_init(int gpio_base, int ngpio, u32 base, int mask_offset, int secondary_irq_base) { struct orion_gpio_chip *ochip; - int i; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) return; @@ -471,15 +417,29 @@ void __init orion_gpio_init(int gpio_base, int ngpio, writel(0, GPIO_EDGE_MASK(ochip)); writel(0, GPIO_LEVEL_MASK(ochip)); - for (i = 0; i < ngpio; i++) { - unsigned int irq = secondary_irq_base + i; - - irq_set_chip_and_handler(irq, &orion_gpio_irq_chip, - handle_level_irq); - irq_set_chip_data(irq, ochip); - irq_set_status_flags(irq, IRQ_LEVEL); - set_irq_flags(irq, IRQF_VALID); - } + gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base, + ochip->base, handle_level_irq); + gc->private = ochip; + + ct = gc->chip_types; + ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; + ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_set_type = gpio_irq_set_type; + + ct++; + ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; + ct->regs.ack = GPIO_EDGE_CAUSE_OFF; + ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_set_type = gpio_irq_set_type; + ct->handler = handle_edge_irq; + + irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); } void orion_gpio_irq_handler(int pinoff) diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h index 5578b98..3075b9f 100644 --- a/arch/arm/plat-orion/include/plat/gpio.h +++ b/arch/arm/plat-orion/include/plat/gpio.h @@ -39,7 +39,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio, /* * GPIO interrupt handling. */ -extern struct irq_chip orion_gpio_irq_chip; void orion_gpio_irq_handler(int irqoff); diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index d8d638e..2d5b9c1 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -14,52 +14,21 @@ #include #include -static void orion_irq_mask(struct irq_data *d) -{ - void __iomem *maskaddr = irq_data_get_irq_chip_data(d); - u32 mask; - - mask = readl(maskaddr); - mask &= ~(1 << (d->irq & 31)); - writel(mask, maskaddr); -} - -static void orion_irq_unmask(struct irq_data *d) -{ - void __iomem *maskaddr = irq_data_get_irq_chip_data(d); - u32 mask; - - mask = readl(maskaddr); - mask |= 1 << (d->irq & 31); - writel(mask, maskaddr); -} - -static struct irq_chip orion_irq_chip = { - .name = "orion_irq", - .irq_mask = orion_irq_mask, - .irq_mask_ack = orion_irq_mask, - .irq_unmask = orion_irq_unmask, -}; - void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) { - unsigned int i; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; /* * Mask all interrupts initially. */ writel(0, maskaddr); - /* - * Register IRQ sources. - */ - for (i = 0; i < 32; i++) { - unsigned int irq = irq_start + i; - - irq_set_chip_and_handler(irq, &orion_irq_chip, - handle_level_irq); - irq_set_chip_data(irq, maskaddr); - irq_set_status_flags(irq, IRQ_LEVEL); - set_irq_flags(irq, IRQF_VALID); - } + gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); } -- cgit v0.10.2 From 5c60255149eece2a36ec9f5c99817b85f96fe8ec Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:40 +0200 Subject: ARM: orion: Rename some constants to macros to make code more identical Changing eg 0xffffffff to DMA_BIT_MASK(32) etc allows easier side by side comparision of identical code which can be consolidated. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index e06a88f..30c9518 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -281,7 +282,7 @@ static struct resource dove_uart0_resources[] = { static struct platform_device dove_uart0 = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = dove_uart0_data, }, @@ -324,7 +325,7 @@ static struct resource dove_uart1_resources[] = { static struct platform_device dove_uart1 = { .name = "serial8250", - .id = 1, + .id = PLAT8250_DEV_PLATFORM1, .dev = { .platform_data = dove_uart1_data, }, @@ -367,7 +368,7 @@ static struct resource dove_uart2_resources[] = { static struct platform_device dove_uart2 = { .name = "serial8250", - .id = 2, + .id = PLAT8250_DEV_PLATFORM2, .dev = { .platform_data = dove_uart2_data, }, diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 20e71df..4b89eed2 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -79,7 +79,7 @@ static struct orion_ehci_data kirkwood_ehci_data = { .phy_version = EHCI_PHY_NA, }; -static u64 ehci_dmamask = 0xffffffffUL; +static u64 ehci_dmamask = DMA_BIT_MASK(32); /***************************************************************************** @@ -88,7 +88,7 @@ static u64 ehci_dmamask = 0xffffffffUL; static struct resource kirkwood_ehci_resources[] = { { .start = USB_PHYS_BASE, - .end = USB_PHYS_BASE + 0x0fff, + .end = USB_PHYS_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { .start = IRQ_KIRKWOOD_USB, @@ -102,7 +102,7 @@ static struct platform_device kirkwood_ehci = { .id = 0, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &kirkwood_ehci_data, }, .resource = kirkwood_ehci_resources, @@ -127,7 +127,7 @@ static struct resource kirkwood_ge00_shared_resources[] = { { .name = "ge00 base", .start = GE00_PHYS_BASE + 0x2000, - .end = GE00_PHYS_BASE + 0x3fff, + .end = GE00_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { .name = "ge00 err irq", @@ -162,7 +162,7 @@ static struct platform_device kirkwood_ge00 = { .num_resources = 1, .resource = kirkwood_ge00_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; @@ -189,7 +189,7 @@ static struct resource kirkwood_ge01_shared_resources[] = { { .name = "ge01 base", .start = GE01_PHYS_BASE + 0x2000, - .end = GE01_PHYS_BASE + 0x3fff, + .end = GE01_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { .name = "ge01 err irq", @@ -224,7 +224,7 @@ static struct platform_device kirkwood_ge01 = { .num_resources = 1, .resource = kirkwood_ge01_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; @@ -358,7 +358,7 @@ static struct platform_device kirkwood_sata = { .name = "sata_mv", .id = 0, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(kirkwood_sata_resources), .resource = kirkwood_sata_resources, @@ -391,14 +391,14 @@ static struct resource mvsdio_resources[] = { }, }; -static u64 mvsdio_dmamask = 0xffffffffUL; +static u64 mvsdio_dmamask = DMA_BIT_MASK(32); static struct platform_device kirkwood_sdio = { .name = "mvsdio", .id = -1, .dev = { .dma_mask = &mvsdio_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(mvsdio_resources), .resource = mvsdio_resources, @@ -518,7 +518,7 @@ static struct resource kirkwood_uart0_resources[] = { static struct platform_device kirkwood_uart0 = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = kirkwood_uart0_data, }, @@ -562,7 +562,7 @@ static struct resource kirkwood_uart1_resources[] = { static struct platform_device kirkwood_uart1 = { .name = "serial8250", - .id = 1, + .id = PLAT8250_DEV_PLATFORM1, .dev = { .platform_data = kirkwood_uart1_data, }, @@ -620,8 +620,6 @@ static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = { .dram = &kirkwood_mbus_dram_info, }; -static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32); - /***************************************************************************** * XOR0 @@ -650,6 +648,8 @@ static struct platform_device kirkwood_xor0_shared = { .resource = kirkwood_xor0_shared_resources, }; +static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32); + static struct resource kirkwood_xor00_resources[] = { [0] = { .start = IRQ_KIRKWOOD_XOR_00, diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c index e41e909..4ff4c62 100644 --- a/arch/arm/mach-loki/common.c +++ b/arch/arm/mach-loki/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -54,7 +55,7 @@ static struct resource loki_ge0_shared_resources[] = { { .name = "ge0 base", .start = GE0_PHYS_BASE + 0x2000, - .end = GE0_PHYS_BASE + 0x3fff, + .end = GE0_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, }; @@ -84,7 +85,7 @@ static struct platform_device loki_ge0 = { .num_resources = 1, .resource = loki_ge0_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; @@ -111,7 +112,7 @@ static struct resource loki_ge1_shared_resources[] = { { .name = "ge1 base", .start = GE1_PHYS_BASE + 0x2000, - .end = GE1_PHYS_BASE + 0x3fff, + .end = GE1_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, }; @@ -141,7 +142,7 @@ static struct platform_device loki_ge1 = { .num_resources = 1, .resource = loki_ge1_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; @@ -187,7 +188,7 @@ static struct platform_device loki_sas = { .name = "mvsas", .id = 0, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(loki_sas_resources), .resource = loki_sas_resources, @@ -230,7 +231,7 @@ static struct resource loki_uart0_resources[] = { static struct platform_device loki_uart0 = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = loki_uart0_data, }, @@ -274,7 +275,7 @@ static struct resource loki_uart1_resources[] = { static struct platform_device loki_uart1 = { .name = "serial8250", - .id = 1, + .id = PLAT8250_DEV_PLATFORM1, .dev = { .platform_data = loki_uart1_data, }, diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 44fb4e5..c38250d 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -173,7 +173,7 @@ static struct orion_ehci_data mv78xx0_ehci_data = { .phy_version = EHCI_PHY_NA, }; -static u64 ehci_dmamask = 0xffffffffUL; +static u64 ehci_dmamask = DMA_BIT_MASK(32); /***************************************************************************** @@ -182,7 +182,7 @@ static u64 ehci_dmamask = 0xffffffffUL; static struct resource mv78xx0_ehci0_resources[] = { { .start = USB0_PHYS_BASE, - .end = USB0_PHYS_BASE + 0x0fff, + .end = USB0_PHYS_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { .start = IRQ_MV78XX0_USB_0, @@ -196,7 +196,7 @@ static struct platform_device mv78xx0_ehci0 = { .id = 0, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &mv78xx0_ehci_data, }, .resource = mv78xx0_ehci0_resources, @@ -215,7 +215,7 @@ void __init mv78xx0_ehci0_init(void) static struct resource mv78xx0_ehci1_resources[] = { { .start = USB1_PHYS_BASE, - .end = USB1_PHYS_BASE + 0x0fff, + .end = USB1_PHYS_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { .start = IRQ_MV78XX0_USB_1, @@ -229,7 +229,7 @@ static struct platform_device mv78xx0_ehci1 = { .id = 1, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &mv78xx0_ehci_data, }, .resource = mv78xx0_ehci1_resources, @@ -248,7 +248,7 @@ void __init mv78xx0_ehci1_init(void) static struct resource mv78xx0_ehci2_resources[] = { { .start = USB2_PHYS_BASE, - .end = USB2_PHYS_BASE + 0x0fff, + .end = USB2_PHYS_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { .start = IRQ_MV78XX0_USB_2, @@ -262,7 +262,7 @@ static struct platform_device mv78xx0_ehci2 = { .id = 2, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &mv78xx0_ehci_data, }, .resource = mv78xx0_ehci2_resources, @@ -287,7 +287,7 @@ static struct resource mv78xx0_ge00_shared_resources[] = { { .name = "ge00 base", .start = GE00_PHYS_BASE + 0x2000, - .end = GE00_PHYS_BASE + 0x3fff, + .end = GE00_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { .name = "ge err irq", @@ -322,7 +322,7 @@ static struct platform_device mv78xx0_ge00 = { .num_resources = 1, .resource = mv78xx0_ge00_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; @@ -349,7 +349,7 @@ static struct resource mv78xx0_ge01_shared_resources[] = { { .name = "ge01 base", .start = GE01_PHYS_BASE + 0x2000, - .end = GE01_PHYS_BASE + 0x3fff, + .end = GE01_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, }; @@ -379,7 +379,7 @@ static struct platform_device mv78xx0_ge01 = { .num_resources = 1, .resource = mv78xx0_ge01_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; @@ -406,7 +406,7 @@ static struct resource mv78xx0_ge10_shared_resources[] = { { .name = "ge10 base", .start = GE10_PHYS_BASE + 0x2000, - .end = GE10_PHYS_BASE + 0x3fff, + .end = GE10_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, }; @@ -436,7 +436,7 @@ static struct platform_device mv78xx0_ge10 = { .num_resources = 1, .resource = mv78xx0_ge10_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; @@ -476,7 +476,7 @@ static struct resource mv78xx0_ge11_shared_resources[] = { { .name = "ge11 base", .start = GE11_PHYS_BASE + 0x2000, - .end = GE11_PHYS_BASE + 0x3fff, + .end = GE11_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, }; @@ -506,7 +506,7 @@ static struct platform_device mv78xx0_ge11 = { .num_resources = 1, .resource = mv78xx0_ge11_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; @@ -625,7 +625,7 @@ static struct platform_device mv78xx0_sata = { .name = "sata_mv", .id = 0, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(mv78xx0_sata_resources), .resource = mv78xx0_sata_resources, @@ -669,7 +669,7 @@ static struct resource mv78xx0_uart0_resources[] = { static struct platform_device mv78xx0_uart0 = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = mv78xx0_uart0_data, }, @@ -713,7 +713,7 @@ static struct resource mv78xx0_uart1_resources[] = { static struct platform_device mv78xx0_uart1 = { .name = "serial8250", - .id = 1, + .id = PLAT8250_DEV_PLATFORM1, .dev = { .platform_data = mv78xx0_uart1_data, }, @@ -757,7 +757,7 @@ static struct resource mv78xx0_uart2_resources[] = { static struct platform_device mv78xx0_uart2 = { .name = "serial8250", - .id = 2, + .id = PLAT8250_DEV_PLATFORM2, .dev = { .platform_data = mv78xx0_uart2_data, }, diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 986c3bf..d281b19 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -77,7 +77,7 @@ static struct orion_ehci_data orion5x_ehci_data = { .phy_version = EHCI_PHY_ORION, }; -static u64 ehci_dmamask = 0xffffffffUL; +static u64 ehci_dmamask = DMA_BIT_MASK(32); /***************************************************************************** @@ -100,7 +100,7 @@ static struct platform_device orion5x_ehci0 = { .id = 0, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &orion5x_ehci_data, }, .resource = orion5x_ehci0_resources, @@ -133,7 +133,7 @@ static struct platform_device orion5x_ehci1 = { .id = 1, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &orion5x_ehci_data, }, .resource = orion5x_ehci1_resources, @@ -147,16 +147,16 @@ void __init orion5x_ehci1_init(void) /***************************************************************************** - * GigE + * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = { +struct mv643xx_eth_shared_platform_data orion5x_ge00_shared_data = { .dram = &orion5x_mbus_dram_info, }; -static struct resource orion5x_eth_shared_resources[] = { +static struct resource orion5x_ge00_shared_resources[] = { { .start = ORION5X_ETH_PHYS_BASE + 0x2000, - .end = ORION5X_ETH_PHYS_BASE + 0x3fff, + .end = ORION5X_ETH_PHYS_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { .start = IRQ_ORION5X_ETH_ERR, @@ -165,17 +165,17 @@ static struct resource orion5x_eth_shared_resources[] = { }, }; -static struct platform_device orion5x_eth_shared = { +static struct platform_device orion5x_ge00_shared = { .name = MV643XX_ETH_SHARED_NAME, .id = 0, .dev = { - .platform_data = &orion5x_eth_shared_data, + .platform_data = &orion5x_ge00_shared_data, }, - .num_resources = ARRAY_SIZE(orion5x_eth_shared_resources), - .resource = orion5x_eth_shared_resources, + .num_resources = ARRAY_SIZE(orion5x_ge00_shared_resources), + .resource = orion5x_ge00_shared_resources, }; -static struct resource orion5x_eth_resources[] = { +static struct resource orion5x_ge00_resources[] = { { .name = "eth irq", .start = IRQ_ORION5X_ETH_SUM, @@ -188,18 +188,18 @@ static struct platform_device orion5x_eth = { .name = MV643XX_ETH_NAME, .id = 0, .num_resources = 1, - .resource = orion5x_eth_resources, + .resource = orion5x_ge00_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &orion5x_eth_shared; + eth_data->shared = &orion5x_ge00_shared; orion5x_eth.dev.platform_data = eth_data; - platform_device_register(&orion5x_eth_shared); + platform_device_register(&orion5x_ge00_shared); platform_device_register(&orion5x_eth); } @@ -234,7 +234,7 @@ void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) d->netdev = &orion5x_eth.dev; for (i = 0; i < d->nr_chips; i++) - d->chip[i].mii_bus = &orion5x_eth_shared.dev; + d->chip[i].mii_bus = &orion5x_ge00_shared.dev; orion5x_switch_device.dev.platform_data = d; platform_device_register(&orion5x_switch_device); @@ -299,7 +299,7 @@ static struct platform_device orion5x_sata = { .name = "sata_mv", .id = 0, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(orion5x_sata_resources), .resource = orion5x_sata_resources, @@ -685,7 +685,7 @@ void __init orion5x_init(void) orion5x_id(&dev, &rev, &dev_name); printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); - orion5x_eth_shared_data.t_clk = orion5x_tclk; + orion5x_ge00_shared_data.t_clk = orion5x_tclk; orion5x_spi_plat_data.tclk = orion5x_tclk; orion5x_uart0_data[0].uartclk = orion5x_tclk; orion5x_uart1_data[0].uartclk = orion5x_tclk; -- cgit v0.10.2 From 28a2b45054f2e3f3671e36a6e9efc82756afa31a Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:41 +0200 Subject: ARM: orion: Consolidate the creation of the uart platform data. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 30c9518..fffa92e 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -36,8 +36,11 @@ #include #include #include +#include #include "common.h" +static int get_tclk(void); + /***************************************************************************** * I/O Address Mapping ****************************************************************************/ @@ -255,173 +258,37 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data) /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port dove_uart0_data[] = { - { - .mapbase = DOVE_UART0_PHYS_BASE, - .membase = (char *)DOVE_UART0_VIRT_BASE, - .irq = IRQ_DOVE_UART_0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource dove_uart0_resources[] = { - { - .start = DOVE_UART0_PHYS_BASE, - .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_UART_0, - .end = IRQ_DOVE_UART_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_uart0 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dove_uart0_data, - }, - .resource = dove_uart0_resources, - .num_resources = ARRAY_SIZE(dove_uart0_resources), -}; - void __init dove_uart0_init(void) { - platform_device_register(&dove_uart0); + orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, + IRQ_DOVE_UART_0, get_tclk()); } /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port dove_uart1_data[] = { - { - .mapbase = DOVE_UART1_PHYS_BASE, - .membase = (char *)DOVE_UART1_VIRT_BASE, - .irq = IRQ_DOVE_UART_1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource dove_uart1_resources[] = { - { - .start = DOVE_UART1_PHYS_BASE, - .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_UART_1, - .end = IRQ_DOVE_UART_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_uart1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = dove_uart1_data, - }, - .resource = dove_uart1_resources, - .num_resources = ARRAY_SIZE(dove_uart1_resources), -}; - void __init dove_uart1_init(void) { - platform_device_register(&dove_uart1); + orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, + IRQ_DOVE_UART_1, get_tclk()); } /***************************************************************************** * UART2 ****************************************************************************/ -static struct plat_serial8250_port dove_uart2_data[] = { - { - .mapbase = DOVE_UART2_PHYS_BASE, - .membase = (char *)DOVE_UART2_VIRT_BASE, - .irq = IRQ_DOVE_UART_2, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource dove_uart2_resources[] = { - { - .start = DOVE_UART2_PHYS_BASE, - .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_UART_2, - .end = IRQ_DOVE_UART_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_uart2 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = dove_uart2_data, - }, - .resource = dove_uart2_resources, - .num_resources = ARRAY_SIZE(dove_uart2_resources), -}; - void __init dove_uart2_init(void) { - platform_device_register(&dove_uart2); + orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, + IRQ_DOVE_UART_2, get_tclk()); } /***************************************************************************** * UART3 ****************************************************************************/ -static struct plat_serial8250_port dove_uart3_data[] = { - { - .mapbase = DOVE_UART3_PHYS_BASE, - .membase = (char *)DOVE_UART3_VIRT_BASE, - .irq = IRQ_DOVE_UART_3, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource dove_uart3_resources[] = { - { - .start = DOVE_UART3_PHYS_BASE, - .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_UART_3, - .end = IRQ_DOVE_UART_3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_uart3 = { - .name = "serial8250", - .id = 3, - .dev = { - .platform_data = dove_uart3_data, - }, - .resource = dove_uart3_resources, - .num_resources = ARRAY_SIZE(dove_uart3_resources), -}; - void __init dove_uart3_init(void) { - platform_device_register(&dove_uart3); + orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, + IRQ_DOVE_UART_3, get_tclk()); } /***************************************************************************** @@ -835,10 +702,6 @@ void __init dove_init(void) dove_setup_cpu_mbus(); dove_ge00_shared_data.t_clk = tclk; - dove_uart0_data[0].uartclk = tclk; - dove_uart1_data[0].uartclk = tclk; - dove_uart2_data[0].uartclk = tclk; - dove_uart3_data[0].uartclk = tclk; dove_spi0_data.tclk = tclk; dove_spi1_data.tclk = tclk; diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 4b89eed2..8cdf9f9 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "common.h" @@ -491,91 +492,23 @@ void __init kirkwood_i2c_init(void) /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port kirkwood_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_KIRKWOOD_UART_0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource kirkwood_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_KIRKWOOD_UART_0, - .end = IRQ_KIRKWOOD_UART_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_uart0 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = kirkwood_uart0_data, - }, - .resource = kirkwood_uart0_resources, - .num_resources = ARRAY_SIZE(kirkwood_uart0_resources), -}; void __init kirkwood_uart0_init(void) { - platform_device_register(&kirkwood_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_KIRKWOOD_UART_0, kirkwood_tclk); } /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port kirkwood_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_KIRKWOOD_UART_1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource kirkwood_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_KIRKWOOD_UART_1, - .end = IRQ_KIRKWOOD_UART_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_uart1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = kirkwood_uart1_data, - }, - .resource = kirkwood_uart1_resources, - .num_resources = ARRAY_SIZE(kirkwood_uart1_resources), -}; - void __init kirkwood_uart1_init(void) { - platform_device_register(&kirkwood_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_KIRKWOOD_UART_1, kirkwood_tclk); } - /***************************************************************************** * Cryptographic Engines and Security Accelerator (CESA) ****************************************************************************/ @@ -987,8 +920,6 @@ void __init kirkwood_init(void) kirkwood_ge00_shared_data.t_clk = kirkwood_tclk; kirkwood_ge01_shared_data.t_clk = kirkwood_tclk; kirkwood_spi_plat_data.tclk = kirkwood_tclk; - kirkwood_uart0_data[0].uartclk = kirkwood_tclk; - kirkwood_uart1_data[0].uartclk = kirkwood_tclk; kirkwood_i2s_data.tclk = kirkwood_tclk; /* diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c index 4ff4c62..c071804 100644 --- a/arch/arm/mach-loki/common.c +++ b/arch/arm/mach-loki/common.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "common.h" /***************************************************************************** @@ -204,88 +205,19 @@ void __init loki_sas_init(void) /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port loki_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_LOKI_UART0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = LOKI_TCLK, - }, { - }, -}; - -static struct resource loki_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_LOKI_UART0, - .end = IRQ_LOKI_UART0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device loki_uart0 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = loki_uart0_data, - }, - .resource = loki_uart0_resources, - .num_resources = ARRAY_SIZE(loki_uart0_resources), -}; - void __init loki_uart0_init(void) { - platform_device_register(&loki_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_LOKI_UART0, LOKI_TCLK); } - /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port loki_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_LOKI_UART1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = LOKI_TCLK, - }, { - }, -}; - -static struct resource loki_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_LOKI_UART1, - .end = IRQ_LOKI_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device loki_uart1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = loki_uart1_data, - }, - .resource = loki_uart1_resources, - .num_resources = ARRAY_SIZE(loki_uart1_resources), -}; - void __init loki_uart1_init(void) { - platform_device_register(&loki_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_LOKI_UART1, LOKI_TCLK); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index c38250d..5b474e4 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -25,8 +25,10 @@ #include #include #include +#include #include "common.h" +static int get_tclk(void); /***************************************************************************** * Common bits @@ -642,179 +644,41 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_0, - .end = IRQ_MV78XX0_UART_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart0 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = mv78xx0_uart0_data, - }, - .resource = mv78xx0_uart0_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources), -}; - void __init mv78xx0_uart0_init(void) { - platform_device_register(&mv78xx0_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_MV78XX0_UART_0, get_tclk()); } /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_1, - .end = IRQ_MV78XX0_UART_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = mv78xx0_uart1_data, - }, - .resource = mv78xx0_uart1_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources), -}; - void __init mv78xx0_uart1_init(void) { - platform_device_register(&mv78xx0_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_MV78XX0_UART_1, get_tclk()); } /***************************************************************************** * UART2 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart2_data[] = { - { - .mapbase = UART2_PHYS_BASE, - .membase = (char *)UART2_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_2, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart2_resources[] = { - { - .start = UART2_PHYS_BASE, - .end = UART2_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_2, - .end = IRQ_MV78XX0_UART_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart2 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = mv78xx0_uart2_data, - }, - .resource = mv78xx0_uart2_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources), -}; - void __init mv78xx0_uart2_init(void) { - platform_device_register(&mv78xx0_uart2); + orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, + IRQ_MV78XX0_UART_2, get_tclk()); } - /***************************************************************************** * UART3 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart3_data[] = { - { - .mapbase = UART3_PHYS_BASE, - .membase = (char *)UART3_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_3, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart3_resources[] = { - { - .start = UART3_PHYS_BASE, - .end = UART3_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_3, - .end = IRQ_MV78XX0_UART_3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart3 = { - .name = "serial8250", - .id = 3, - .dev = { - .platform_data = mv78xx0_uart3_data, - }, - .resource = mv78xx0_uart3_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources), -}; - void __init mv78xx0_uart3_init(void) { - platform_device_register(&mv78xx0_uart3); + orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, + IRQ_MV78XX0_UART_3, get_tclk()); } - /***************************************************************************** * Time handling ****************************************************************************/ @@ -900,8 +764,4 @@ void __init mv78xx0_init(void) mv78xx0_ge01_shared_data.t_clk = tclk; mv78xx0_ge10_shared_data.t_clk = tclk; mv78xx0_ge11_shared_data.t_clk = tclk; - mv78xx0_uart0_data[0].uartclk = tclk; - mv78xx0_uart1_data[0].uartclk = tclk; - mv78xx0_uart2_data[0].uartclk = tclk; - mv78xx0_uart3_data[0].uartclk = tclk; } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index d281b19..310de50 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "common.h" /***************************************************************************** @@ -349,91 +350,21 @@ void __init orion5x_spi_init() /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port orion5x_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_ORION5X_UART0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource orion5x_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_UART0, - .end = IRQ_ORION5X_UART0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_uart0 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = orion5x_uart0_data, - }, - .resource = orion5x_uart0_resources, - .num_resources = ARRAY_SIZE(orion5x_uart0_resources), -}; - void __init orion5x_uart0_init(void) { - platform_device_register(&orion5x_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_ORION5X_UART0, orion5x_tclk); } - /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port orion5x_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_ORION5X_UART1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource orion5x_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_UART1, - .end = IRQ_ORION5X_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_uart1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = orion5x_uart1_data, - }, - .resource = orion5x_uart1_resources, - .num_resources = ARRAY_SIZE(orion5x_uart1_resources), -}; - void __init orion5x_uart1_init(void) { - platform_device_register(&orion5x_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_ORION5X_UART1, orion5x_tclk); } - /***************************************************************************** * XOR engine ****************************************************************************/ @@ -687,8 +618,6 @@ void __init orion5x_init(void) orion5x_ge00_shared_data.t_clk = orion5x_tclk; orion5x_spi_plat_data.tclk = orion5x_tclk; - orion5x_uart0_data[0].uartclk = orion5x_tclk; - orion5x_uart1_data[0].uartclk = orion5x_tclk; /* * Setup Orion address map diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 56021a7..0f048c5 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o time.o +obj-y := irq.o pcie.o time.o common.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c new file mode 100644 index 0000000..4eac532 --- /dev/null +++ b/arch/arm/plat-orion/common.c @@ -0,0 +1,171 @@ +/* + * arch/arm/plat-orion/common.c + * + * Marvell Orion SoC common setup code used by multiple mach-/common.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include + +/* Fill in the resources structure and link it into the platform + device structure. There is always a memory region, and nearly + always an interrupt.*/ +static void fill_resources(struct platform_device *device, + struct resource *resources, + resource_size_t mapbase, + resource_size_t size, + unsigned int irq) +{ + device->resource = resources; + device->num_resources = 1; + resources[0].flags = IORESOURCE_MEM; + resources[0].start = mapbase; + resources[0].end = mapbase + size; + + if (irq != NO_IRQ) { + device->num_resources++; + resources[1].flags = IORESOURCE_IRQ; + resources[1].start = irq; + resources[1].end = irq; + } +} + +/***************************************************************************** + * UART + ****************************************************************************/ +static void __init uart_complete( + struct platform_device *orion_uart, + struct plat_serial8250_port *data, + struct resource *resources, + unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + data->mapbase = mapbase; + data->membase = (void __iomem *)membase; + data->irq = irq; + data->uartclk = uartclk; + orion_uart->dev.platform_data = data; + + fill_resources(orion_uart, resources, mapbase, 0xff, irq); + platform_device_register(orion_uart); +} + +/***************************************************************************** + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port orion_uart0_data[] = { + { + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + }, { + }, +}; + +static struct resource orion_uart0_resources[2]; + +static struct platform_device orion_uart0 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, +}; + +void __init orion_uart0_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources, + membase, mapbase, irq, uartclk); +} + +/***************************************************************************** + * UART1 + ****************************************************************************/ +static struct plat_serial8250_port orion_uart1_data[] = { + { + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + }, { + }, +}; + +static struct resource orion_uart1_resources[2]; + +static struct platform_device orion_uart1 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, +}; + +void __init orion_uart1_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources, + membase, mapbase, irq, uartclk); +} + +/***************************************************************************** + * UART2 + ****************************************************************************/ +static struct plat_serial8250_port orion_uart2_data[] = { + { + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + }, { + }, +}; + +static struct resource orion_uart2_resources[2]; + +static struct platform_device orion_uart2 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, +}; + +void __init orion_uart2_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources, + membase, mapbase, irq, uartclk); +} + +/***************************************************************************** + * UART3 + ****************************************************************************/ +static struct plat_serial8250_port orion_uart3_data[] = { + { + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + }, { + }, +}; + +static struct resource orion_uart3_resources[2]; + +static struct platform_device orion_uart3 = { + .name = "serial8250", + .id = 3, +}; + +void __init orion_uart3_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources, + membase, mapbase, irq, uartclk); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h new file mode 100644 index 0000000..92ff991 --- /dev/null +++ b/arch/arm/plat-orion/include/plat/common.h @@ -0,0 +1,33 @@ +/* + * arch/arm/plat-orion/include/plat/common.h + * + * Marvell Orion SoC common setup code used by different mach-/common.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_COMMON_H + + +void __init orion_uart0_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk); + +void __init orion_uart1_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk); + +void __init orion_uart2_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk); + +void __init orion_uart3_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk); +#endif -- cgit v0.10.2 From f6eaccb30fb4381da05e1e04f7fb9b956ab22826 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:42 +0200 Subject: ARM: orion: Consolidate the creation of the RTC platform data. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index fffa92e..8a414cb 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -205,20 +205,9 @@ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) /***************************************************************************** * SoC RTC ****************************************************************************/ -static struct resource dove_rtc_resource[] = { - { - .start = DOVE_RTC_PHYS_BASE, - .end = DOVE_RTC_PHYS_BASE + 32 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_RTC, - .flags = IORESOURCE_IRQ, - } -}; - void __init dove_rtc_init(void) { - platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); + orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); } /***************************************************************************** diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 8cdf9f9..b77050e 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -326,15 +326,9 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, /***************************************************************************** * SoC RTC ****************************************************************************/ -static struct resource kirkwood_rtc_resource = { - .start = RTC_PHYS_BASE, - .end = RTC_PHYS_BASE + SZ_16 - 1, - .flags = IORESOURCE_MEM, -}; - static void __init kirkwood_rtc_init(void) { - platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); + orion_rtc_init(RTC_PHYS_BASE, NO_IRQ); } diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 4eac532..d065591 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -169,3 +169,21 @@ void __init orion_uart3_init(unsigned int membase, uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources, membase, mapbase, irq, uartclk); } + +/***************************************************************************** + * SoC RTC + ****************************************************************************/ +static struct resource orion_rtc_resource[2]; + +void __init orion_rtc_init(unsigned long mapbase, + unsigned long irq) +{ + orion_rtc_resource[0].start = mapbase; + orion_rtc_resource[0].end = mapbase + SZ_32 - 1; + orion_rtc_resource[0].flags = IORESOURCE_MEM; + orion_rtc_resource[1].start = irq; + orion_rtc_resource[1].end = irq; + orion_rtc_resource[1].flags = IORESOURCE_IRQ; + + platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 92ff991..016b95e 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -30,4 +30,7 @@ void __init orion_uart3_init(unsigned int membase, resource_size_t mapbase, unsigned int irq, unsigned int uartclk); + +void __init orion_rtc_init(unsigned long mapbase, + unsigned long irq); #endif -- cgit v0.10.2 From 4748058c5cbf70b3adfa37204c047fcb29f335c0 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:43 +0200 Subject: ARM: kirkwood: Add support for RTC interrupts which allows RTC alarms. Tested using the test program in Documentation/rtc.txt Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index b77050e..f6868fc 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -328,7 +328,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, ****************************************************************************/ static void __init kirkwood_rtc_init(void) { - orion_rtc_init(RTC_PHYS_BASE, NO_IRQ); + orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC); } diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h index 9da2eb5..2bf8161 100644 --- a/arch/arm/mach-kirkwood/include/mach/irqs.h +++ b/arch/arm/mach-kirkwood/include/mach/irqs.h @@ -51,6 +51,7 @@ #define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41 #define IRQ_KIRKWOOD_GE00_ERR 46 #define IRQ_KIRKWOOD_GE01_ERR 47 +#define IRQ_KIRKWOOD_RTC 53 /* * KIRKWOOD General Purpose Pins -- cgit v0.10.2 From 7e3819d820c9aa3536d15fe7310c054bef1f5f04 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:44 +0200 Subject: ARM: orion: Consolidate ethernet platform data Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 8a414cb..1d878ce 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -150,56 +149,11 @@ void __init dove_ehci1_init(void) /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = { - .t_clk = 0, - .dram = &dove_mbus_dram_info, -}; - -static struct resource dove_ge00_shared_resources[] = { - { - .name = "ge00 base", - .start = DOVE_GE00_PHYS_BASE + 0x2000, - .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dove_ge00_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &dove_ge00_shared_data, - }, - .num_resources = 1, - .resource = dove_ge00_shared_resources, -}; - -static struct resource dove_ge00_resources[] = { - { - .name = "ge00 irq", - .start = IRQ_DOVE_GE00_SUM, - .end = IRQ_DOVE_GE00_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_ge00 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = dove_ge00_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &dove_ge00_shared; - dove_ge00.dev.platform_data = eth_data; - - platform_device_register(&dove_ge00_shared); - platform_device_register(&dove_ge00); + orion_ge00_init(eth_data, &dove_mbus_dram_info, + DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, + 0, get_tclk()); } /***************************************************************************** @@ -690,7 +644,6 @@ void __init dove_init(void) #endif dove_setup_cpu_mbus(); - dove_ge00_shared_data.t_clk = tclk; dove_spi0_data.tclk = tclk; dove_spi1_data.tclk = tclk; diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f6868fc..485f3b9 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -70,7 +69,7 @@ void __init kirkwood_map_io(void) * registered. Some reserved bits must be set to 1. */ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; - + /***************************************************************************** * EHCI @@ -120,160 +119,36 @@ void __init kirkwood_ehci_init(void) /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = { - .dram = &kirkwood_mbus_dram_info, -}; - -static struct resource kirkwood_ge00_shared_resources[] = { - { - .name = "ge00 base", - .start = GE00_PHYS_BASE + 0x2000, - .end = GE00_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "ge00 err irq", - .start = IRQ_KIRKWOOD_GE00_ERR, - .end = IRQ_KIRKWOOD_GE00_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ge00_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &kirkwood_ge00_shared_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources), - .resource = kirkwood_ge00_shared_resources, -}; - -static struct resource kirkwood_ge00_resources[] = { - { - .name = "ge00 irq", - .start = IRQ_KIRKWOOD_GE00_SUM, - .end = IRQ_KIRKWOOD_GE00_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ge00 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = kirkwood_ge00_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { kirkwood_clk_ctrl |= CGC_GE0; - eth_data->shared = &kirkwood_ge00_shared; - kirkwood_ge00.dev.platform_data = eth_data; - platform_device_register(&kirkwood_ge00_shared); - platform_device_register(&kirkwood_ge00); + orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, + GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, + IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); } /***************************************************************************** * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = { - .dram = &kirkwood_mbus_dram_info, - .shared_smi = &kirkwood_ge00_shared, -}; - -static struct resource kirkwood_ge01_shared_resources[] = { - { - .name = "ge01 base", - .start = GE01_PHYS_BASE + 0x2000, - .end = GE01_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "ge01 err irq", - .start = IRQ_KIRKWOOD_GE01_ERR, - .end = IRQ_KIRKWOOD_GE01_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ge01_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &kirkwood_ge01_shared_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources), - .resource = kirkwood_ge01_shared_resources, -}; - -static struct resource kirkwood_ge01_resources[] = { - { - .name = "ge01 irq", - .start = IRQ_KIRKWOOD_GE01_SUM, - .end = IRQ_KIRKWOOD_GE01_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ge01 = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 1, - .resource = kirkwood_ge01_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) { + kirkwood_clk_ctrl |= CGC_GE1; - eth_data->shared = &kirkwood_ge01_shared; - kirkwood_ge01.dev.platform_data = eth_data; - platform_device_register(&kirkwood_ge01_shared); - platform_device_register(&kirkwood_ge01); + orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, + GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, + IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); } /***************************************************************************** * Ethernet switch ****************************************************************************/ -static struct resource kirkwood_switch_resources[] = { - { - .start = 0, - .end = 0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_switch_device = { - .name = "dsa", - .id = 0, - .num_resources = 0, - .resource = kirkwood_switch_resources, -}; - void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) { - int i; - - if (irq != NO_IRQ) { - kirkwood_switch_resources[0].start = irq; - kirkwood_switch_resources[0].end = irq; - kirkwood_switch_device.num_resources = 1; - } - - d->netdev = &kirkwood_ge00.dev; - for (i = 0; i < d->nr_chips; i++) - d->chip[i].mii_bus = &kirkwood_ge00_shared.dev; - kirkwood_switch_device.dev.platform_data = d; - - platform_device_register(&kirkwood_switch_device); + orion_ge00_switch_init(d, irq); } @@ -911,8 +786,6 @@ void __init kirkwood_init(void) { printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk); - kirkwood_ge00_shared_data.t_clk = kirkwood_tclk; - kirkwood_ge01_shared_data.t_clk = kirkwood_tclk; kirkwood_spi_plat_data.tclk = kirkwood_tclk; kirkwood_i2s_data.tclk = kirkwood_tclk; diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c index c071804..5f02664 100644 --- a/arch/arm/mach-loki/common.c +++ b/arch/arm/mach-loki/common.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -45,116 +44,28 @@ void __init loki_map_io(void) /***************************************************************************** - * GE0 + * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = { - .t_clk = LOKI_TCLK, - .dram = &loki_mbus_dram_info, -}; - -static struct resource loki_ge0_shared_resources[] = { - { - .name = "ge0 base", - .start = GE0_PHYS_BASE + 0x2000, - .end = GE0_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device loki_ge0_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &loki_ge0_shared_data, - }, - .num_resources = 1, - .resource = loki_ge0_shared_resources, -}; - -static struct resource loki_ge0_resources[] = { - { - .name = "ge0 irq", - .start = IRQ_LOKI_GBE_A_INT, - .end = IRQ_LOKI_GBE_A_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device loki_ge0 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = loki_ge0_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &loki_ge0_shared; - loki_ge0.dev.platform_data = eth_data; - writel(0x00079220, GE0_VIRT_BASE + 0x20b0); - platform_device_register(&loki_ge0_shared); - platform_device_register(&loki_ge0); + + orion_ge00_init(eth_data, &loki_mbus_dram_info, + GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT, + 0, LOKI_TCLK); } /***************************************************************************** - * GE1 + * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = { - .t_clk = LOKI_TCLK, - .dram = &loki_mbus_dram_info, -}; - -static struct resource loki_ge1_shared_resources[] = { - { - .name = "ge1 base", - .start = GE1_PHYS_BASE + 0x2000, - .end = GE1_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device loki_ge1_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &loki_ge1_shared_data, - }, - .num_resources = 1, - .resource = loki_ge1_shared_resources, -}; - -static struct resource loki_ge1_resources[] = { - { - .name = "ge1 irq", - .start = IRQ_LOKI_GBE_B_INT, - .end = IRQ_LOKI_GBE_B_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device loki_ge1 = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 1, - .resource = loki_ge1_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &loki_ge1_shared; - loki_ge1.dev.platform_data = eth_data; - writel(0x00079220, GE1_VIRT_BASE + 0x20b0); - platform_device_register(&loki_ge1_shared); - platform_device_register(&loki_ge1); + + orion_ge01_init(eth_data, &loki_mbus_dram_info, + GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT, + 0, LOKI_TCLK); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 5b474e4..0fd9a83 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -280,175 +279,32 @@ void __init mv78xx0_ehci2_init(void) /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, -}; - -static struct resource mv78xx0_ge00_shared_resources[] = { - { - .name = "ge00 base", - .start = GE00_PHYS_BASE + 0x2000, - .end = GE00_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "ge err irq", - .start = IRQ_MV78XX0_GE_ERR, - .end = IRQ_MV78XX0_GE_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge00_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &mv78xx0_ge00_shared_data, - }, - .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources), - .resource = mv78xx0_ge00_shared_resources, -}; - -static struct resource mv78xx0_ge00_resources[] = { - { - .name = "ge00 irq", - .start = IRQ_MV78XX0_GE00_SUM, - .end = IRQ_MV78XX0_GE00_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge00 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = mv78xx0_ge00_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &mv78xx0_ge00_shared; - mv78xx0_ge00.dev.platform_data = eth_data; - - platform_device_register(&mv78xx0_ge00_shared); - platform_device_register(&mv78xx0_ge00); + orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, + GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, + IRQ_MV78XX0_GE_ERR, get_tclk()); } /***************************************************************************** * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge01_shared_resources[] = { - { - .name = "ge01 base", - .start = GE01_PHYS_BASE + 0x2000, - .end = GE01_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge01_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &mv78xx0_ge01_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge01_shared_resources, -}; - -static struct resource mv78xx0_ge01_resources[] = { - { - .name = "ge01 irq", - .start = IRQ_MV78XX0_GE01_SUM, - .end = IRQ_MV78XX0_GE01_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge01 = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 1, - .resource = mv78xx0_ge01_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &mv78xx0_ge01_shared; - mv78xx0_ge01.dev.platform_data = eth_data; - - platform_device_register(&mv78xx0_ge01_shared); - platform_device_register(&mv78xx0_ge01); + orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, + GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, + NO_IRQ, get_tclk()); } /***************************************************************************** * GE10 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge10_shared_resources[] = { - { - .name = "ge10 base", - .start = GE10_PHYS_BASE + 0x2000, - .end = GE10_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge10_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 2, - .dev = { - .platform_data = &mv78xx0_ge10_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge10_shared_resources, -}; - -static struct resource mv78xx0_ge10_resources[] = { - { - .name = "ge10 irq", - .start = IRQ_MV78XX0_GE10_SUM, - .end = IRQ_MV78XX0_GE10_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge10 = { - .name = MV643XX_ETH_NAME, - .id = 2, - .num_resources = 1, - .resource = mv78xx0_ge10_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) { u32 dev, rev; - eth_data->shared = &mv78xx0_ge10_shared; - mv78xx0_ge10.dev.platform_data = eth_data; - /* * On the Z0, ge10 and ge11 are internally connected back * to back, and not brought out. @@ -460,65 +316,19 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - platform_device_register(&mv78xx0_ge10_shared); - platform_device_register(&mv78xx0_ge10); + orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, + GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, + NO_IRQ, get_tclk()); } /***************************************************************************** * GE11 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge11_shared_resources[] = { - { - .name = "ge11 base", - .start = GE11_PHYS_BASE + 0x2000, - .end = GE11_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge11_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 3, - .dev = { - .platform_data = &mv78xx0_ge11_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge11_shared_resources, -}; - -static struct resource mv78xx0_ge11_resources[] = { - { - .name = "ge11 irq", - .start = IRQ_MV78XX0_GE11_SUM, - .end = IRQ_MV78XX0_GE11_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge11 = { - .name = MV643XX_ETH_NAME, - .id = 3, - .num_resources = 1, - .resource = mv78xx0_ge11_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) { u32 dev, rev; - eth_data->shared = &mv78xx0_ge11_shared; - mv78xx0_ge11.dev.platform_data = eth_data; - /* * On the Z0, ge10 and ge11 are internally connected back * to back, and not brought out. @@ -530,8 +340,9 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - platform_device_register(&mv78xx0_ge11_shared); - platform_device_register(&mv78xx0_ge11); + orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, + GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, + NO_IRQ, get_tclk()); } /***************************************************************************** @@ -759,9 +570,4 @@ void __init mv78xx0_init(void) #ifdef CONFIG_CACHE_FEROCEON_L2 feroceon_l2_init(is_l2_writethrough()); #endif - - mv78xx0_ge00_shared_data.t_clk = tclk; - mv78xx0_ge01_shared_data.t_clk = tclk; - mv78xx0_ge10_shared_data.t_clk = tclk; - mv78xx0_ge11_shared_data.t_clk = tclk; } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 310de50..0a1c760 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -150,95 +149,20 @@ void __init orion5x_ehci1_init(void) /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion5x_ge00_shared_data = { - .dram = &orion5x_mbus_dram_info, -}; - -static struct resource orion5x_ge00_shared_resources[] = { - { - .start = ORION5X_ETH_PHYS_BASE + 0x2000, - .end = ORION5X_ETH_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_ETH_ERR, - .end = IRQ_ORION5X_ETH_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_ge00_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &orion5x_ge00_shared_data, - }, - .num_resources = ARRAY_SIZE(orion5x_ge00_shared_resources), - .resource = orion5x_ge00_shared_resources, -}; - -static struct resource orion5x_ge00_resources[] = { - { - .name = "eth irq", - .start = IRQ_ORION5X_ETH_SUM, - .end = IRQ_ORION5X_ETH_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_eth = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = orion5x_ge00_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &orion5x_ge00_shared; - orion5x_eth.dev.platform_data = eth_data; - - platform_device_register(&orion5x_ge00_shared); - platform_device_register(&orion5x_eth); + orion_ge00_init(eth_data, &orion5x_mbus_dram_info, + ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, + IRQ_ORION5X_ETH_ERR, orion5x_tclk); } /***************************************************************************** * Ethernet switch ****************************************************************************/ -static struct resource orion5x_switch_resources[] = { - { - .start = 0, - .end = 0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_switch_device = { - .name = "dsa", - .id = 0, - .num_resources = 0, - .resource = orion5x_switch_resources, -}; - void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) { - int i; - - if (irq != NO_IRQ) { - orion5x_switch_resources[0].start = irq; - orion5x_switch_resources[0].end = irq; - orion5x_switch_device.num_resources = 1; - } - - d->netdev = &orion5x_eth.dev; - for (i = 0; i < d->nr_chips; i++) - d->chip[i].mii_bus = &orion5x_ge00_shared.dev; - orion5x_switch_device.dev.platform_data = d; - - platform_device_register(&orion5x_switch_device); + orion_ge00_switch_init(d, irq); } @@ -616,7 +540,6 @@ void __init orion5x_init(void) orion5x_id(&dev, &rev, &dev_name); printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); - orion5x_ge00_shared_data.t_clk = orion5x_tclk; orion5x_spi_plat_data.tclk = orion5x_tclk; /* diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index d065591..15c3f35 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -11,7 +11,11 @@ #include #include #include +#include #include +#include +#include +#include /* Fill in the resources structure and link it into the platform device structure. There is always a memory region, and nearly @@ -187,3 +191,275 @@ void __init orion_rtc_init(unsigned long mapbase, platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2); } + +/***************************************************************************** + * GE + ****************************************************************************/ +static __init void ge_complete( + struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, + struct mbus_dram_target_info *mbus_dram_info, int tclk, + struct resource *orion_ge_resource, unsigned long irq, + struct platform_device *orion_ge_shared, + struct mv643xx_eth_platform_data *eth_data, + struct platform_device *orion_ge) +{ + orion_ge_shared_data->dram = mbus_dram_info; + orion_ge_shared_data->t_clk = tclk; + orion_ge_resource->start = irq; + orion_ge_resource->end = irq; + eth_data->shared = orion_ge_shared; + orion_ge->dev.platform_data = eth_data; + + platform_device_register(orion_ge_shared); + platform_device_register(orion_ge); +} + +/***************************************************************************** + * GE00 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data orion_ge00_shared_data; + +static struct resource orion_ge00_shared_resources[] = { + { + .name = "ge00 base", + }, { + .name = "ge00 err irq", + }, +}; + +static struct platform_device orion_ge00_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &orion_ge00_shared_data, + }, +}; + +static struct resource orion_ge00_resources[] = { + { + .name = "ge00 irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_ge00 = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = orion_ge00_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk) +{ + fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, + mapbase + 0x2000, SZ_16K - 1, irq_err); + ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk, + orion_ge00_resources, irq, &orion_ge00_shared, + eth_data, &orion_ge00); +} + +/***************************************************************************** + * GE01 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = { + .shared_smi = &orion_ge00_shared, +}; + +static struct resource orion_ge01_shared_resources[] = { + { + .name = "ge01 base", + }, { + .name = "ge01 err irq", + }, +}; + +static struct platform_device orion_ge01_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &orion_ge01_shared_data, + }, +}; + +static struct resource orion_ge01_resources[] = { + { + .name = "ge01 irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_ge01 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 1, + .resource = orion_ge01_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk) +{ + fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, + mapbase + 0x2000, SZ_16K - 1, irq_err); + ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk, + orion_ge01_resources, irq, &orion_ge01_shared, + eth_data, &orion_ge01); +} + +/***************************************************************************** + * GE10 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = { + .shared_smi = &orion_ge00_shared, +}; + +static struct resource orion_ge10_shared_resources[] = { + { + .name = "ge10 base", + }, { + .name = "ge10 err irq", + }, +}; + +static struct platform_device orion_ge10_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &orion_ge10_shared_data, + }, +}; + +static struct resource orion_ge10_resources[] = { + { + .name = "ge10 irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_ge10 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 2, + .resource = orion_ge10_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk) +{ + fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, + mapbase + 0x2000, SZ_16K - 1, irq_err); + ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk, + orion_ge10_resources, irq, &orion_ge10_shared, + eth_data, &orion_ge10); +} + +/***************************************************************************** + * GE11 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = { + .shared_smi = &orion_ge00_shared, +}; + +static struct resource orion_ge11_shared_resources[] = { + { + .name = "ge11 base", + }, { + .name = "ge11 err irq", + }, +}; + +static struct platform_device orion_ge11_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &orion_ge11_shared_data, + }, +}; + +static struct resource orion_ge11_resources[] = { + { + .name = "ge11 irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_ge11 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 2, + .resource = orion_ge11_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk) +{ + fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, + mapbase + 0x2000, SZ_16K - 1, irq_err); + ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk, + orion_ge11_resources, irq, &orion_ge11_shared, + eth_data, &orion_ge11); +} + +/***************************************************************************** + * Ethernet switch + ****************************************************************************/ +static struct resource orion_switch_resources[] = { + { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_switch_device = { + .name = "dsa", + .id = 0, + .num_resources = 0, + .resource = orion_switch_resources, +}; + +void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq) +{ + int i; + + if (irq != NO_IRQ) { + orion_switch_resources[0].start = irq; + orion_switch_resources[0].end = irq; + orion_switch_device.num_resources = 1; + } + + d->netdev = &orion_ge00.dev; + for (i = 0; i < d->nr_chips; i++) + d->chip[i].mii_bus = &orion_ge00_shared.dev; + orion_switch_device.dev.platform_data = d; + + platform_device_register(&orion_switch_device); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 016b95e..3f23258 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -9,7 +9,9 @@ */ #ifndef __PLAT_COMMON_H +#include +struct dsa_platform_data; void __init orion_uart0_init(unsigned int membase, resource_size_t mapbase, @@ -33,4 +35,36 @@ void __init orion_uart3_init(unsigned int membase, void __init orion_rtc_init(unsigned long mapbase, unsigned long irq); + +void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk); + +void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk); + +void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk); + +void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk); + +void __init orion_ge00_switch_init(struct dsa_platform_data *d, + int irq); + #endif -- cgit v0.10.2 From aac7ffa3ed121846b61347028828617c5dd1ce46 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:45 +0200 Subject: ARM: orion: Consolidate I2C initialization. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 1d878ce..198760b 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -305,39 +304,9 @@ void __init dove_spi1_init(void) /***************************************************************************** * I2C ****************************************************************************/ -static struct mv64xxx_i2c_pdata dove_i2c_data = { - .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource dove_i2c_resources[] = { - { - .name = "i2c base", - .start = DOVE_I2C_PHYS_BASE, - .end = DOVE_I2C_PHYS_BASE + 0x20 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "i2c irq", - .start = IRQ_DOVE_I2C, - .end = IRQ_DOVE_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_i2c = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(dove_i2c_resources), - .resource = dove_i2c_resources, - .dev = { - .platform_data = &dove_i2c_data, - }, -}; - void __init dove_i2c_init(void) { - platform_device_register(&dove_i2c); + orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); } /***************************************************************************** diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 485f3b9..fc86a80 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -324,37 +323,9 @@ void __init kirkwood_spi_init() /***************************************************************************** * I2C ****************************************************************************/ -static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource kirkwood_i2c_resources[] = { - { - .start = I2C_PHYS_BASE, - .end = I2C_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_KIRKWOOD_TWSI, - .end = IRQ_KIRKWOOD_TWSI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_i2c = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(kirkwood_i2c_resources), - .resource = kirkwood_i2c_resources, - .dev = { - .platform_data = &kirkwood_i2c_pdata, - }, -}; - void __init kirkwood_i2c_init(void) { - platform_device_register(&kirkwood_i2c); + orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 0fd9a83..aa27c15 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -346,75 +345,12 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) } /***************************************************************************** - * I2C bus 0 + * I2C ****************************************************************************/ - -static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource mv78xx0_i2c_0_resources[] = { - { - .start = I2C_0_PHYS_BASE, - .end = I2C_0_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_I2C_0, - .end = IRQ_MV78XX0_I2C_0, - .flags = IORESOURCE_IRQ, - }, -}; - - -static struct platform_device mv78xx0_i2c_0 = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources), - .resource = mv78xx0_i2c_0_resources, - .dev = { - .platform_data = &mv78xx0_i2c_0_pdata, - }, -}; - -/***************************************************************************** - * I2C bus 1 - ****************************************************************************/ - -static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource mv78xx0_i2c_1_resources[] = { - { - .start = I2C_1_PHYS_BASE, - .end = I2C_1_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_I2C_1, - .end = IRQ_MV78XX0_I2C_1, - .flags = IORESOURCE_IRQ, - }, -}; - - -static struct platform_device mv78xx0_i2c_1 = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources), - .resource = mv78xx0_i2c_1_resources, - .dev = { - .platform_data = &mv78xx0_i2c_1_pdata, - }, -}; - void __init mv78xx0_i2c_init(void) { - platform_device_register(&mv78xx0_i2c_0); - platform_device_register(&mv78xx0_i2c_1); + orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); + orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); } /***************************************************************************** diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 0a1c760..9af0b88 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -169,37 +169,10 @@ void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) /***************************************************************************** * I2C ****************************************************************************/ -static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource orion5x_i2c_resources[] = { - { - .start = I2C_PHYS_BASE, - .end = I2C_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_I2C, - .end = IRQ_ORION5X_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_i2c = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(orion5x_i2c_resources), - .resource = orion5x_i2c_resources, - .dev = { - .platform_data = &orion5x_i2c_pdata, - }, -}; - void __init orion5x_i2c_init(void) { - platform_device_register(&orion5x_i2c); + orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); + } diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 15c3f35..bcc1734 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -15,6 +15,7 @@ #include #include #include +#include #include /* Fill in the resources structure and link it into the platform @@ -463,3 +464,56 @@ void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq) platform_device_register(&orion_switch_device); } + +/***************************************************************************** + * I2C + ****************************************************************************/ +static struct mv64xxx_i2c_pdata orion_i2c_pdata = { + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource orion_i2c_resources[2]; + +static struct platform_device orion_i2c = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 0, + .dev = { + .platform_data = &orion_i2c_pdata, + }, +}; + +static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = { + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource orion_i2c_1_resources[2]; + +static struct platform_device orion_i2c_1 = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 1, + .dev = { + .platform_data = &orion_i2c_1_pdata, + }, +}; + +void __init orion_i2c_init(unsigned long mapbase, + unsigned long irq, + unsigned long freq_m) +{ + orion_i2c_pdata.freq_m = freq_m; + fill_resources(&orion_i2c, orion_i2c_resources, mapbase, + SZ_32 - 1, irq); + platform_device_register(&orion_i2c); +} + +void __init orion_i2c_1_init(unsigned long mapbase, + unsigned long irq, + unsigned long freq_m) +{ + orion_i2c_1_pdata.freq_m = freq_m; + fill_resources(&orion_i2c_1, orion_i2c_1_resources, mapbase, + SZ_32 - 1, irq); + platform_device_register(&orion_i2c_1); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 3f23258..d107c62 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -66,5 +66,11 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq); +void __init orion_i2c_init(unsigned long mapbase, + unsigned long irq, + unsigned long freq_m); +void __init orion_i2c_1_init(unsigned long mapbase, + unsigned long irq, + unsigned long freq_m); #endif -- cgit v0.10.2 From 980f9f601ad456dc5a699bf526b6bd894957bad3 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:46 +0200 Subject: ARM: orion: Consolidate SPI initialization. This change removes the interrupt resource. The driver does not use it. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 198760b..e3e043c 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -234,71 +233,16 @@ void __init dove_uart3_init(void) } /***************************************************************************** - * SPI0 + * SPI ****************************************************************************/ -static struct orion_spi_info dove_spi0_data = { - .tclk = 0, -}; - -static struct resource dove_spi0_resources[] = { - { - .start = DOVE_SPI0_PHYS_BASE, - .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_SPI0, - .end = IRQ_DOVE_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_spi0 = { - .name = "orion_spi", - .id = 0, - .resource = dove_spi0_resources, - .dev = { - .platform_data = &dove_spi0_data, - }, - .num_resources = ARRAY_SIZE(dove_spi0_resources), -}; - void __init dove_spi0_init(void) { - platform_device_register(&dove_spi0); + orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk()); } -/***************************************************************************** - * SPI1 - ****************************************************************************/ -static struct orion_spi_info dove_spi1_data = { - .tclk = 0, -}; - -static struct resource dove_spi1_resources[] = { - { - .start = DOVE_SPI1_PHYS_BASE, - .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_SPI1, - .end = IRQ_DOVE_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_spi1 = { - .name = "orion_spi", - .id = 1, - .resource = dove_spi1_resources, - .dev = { - .platform_data = &dove_spi1_data, - }, - .num_resources = ARRAY_SIZE(dove_spi1_resources), -}; - void __init dove_spi1_init(void) { - platform_device_register(&dove_spi1); + orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk()); } /***************************************************************************** @@ -613,9 +557,6 @@ void __init dove_init(void) #endif dove_setup_cpu_mbus(); - dove_spi0_data.tclk = tclk; - dove_spi1_data.tclk = tclk; - /* internal devices that every board has */ dove_rtc_init(); dove_xor0_init(); diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index fc86a80..af864fc 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -292,31 +291,10 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) /***************************************************************************** * SPI ****************************************************************************/ -static struct orion_spi_info kirkwood_spi_plat_data = { -}; - -static struct resource kirkwood_spi_resources[] = { - { - .start = SPI_PHYS_BASE, - .end = SPI_PHYS_BASE + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device kirkwood_spi = { - .name = "orion_spi", - .id = 0, - .resource = kirkwood_spi_resources, - .dev = { - .platform_data = &kirkwood_spi_plat_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_spi_resources), -}; - void __init kirkwood_spi_init() { kirkwood_clk_ctrl |= CGC_RUNIT; - platform_device_register(&kirkwood_spi); + orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk); } @@ -757,7 +735,6 @@ void __init kirkwood_init(void) { printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk); - kirkwood_spi_plat_data.tclk = kirkwood_tclk; kirkwood_i2s_data.tclk = kirkwood_tclk; /* diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 9af0b88..d2dee43 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -214,33 +213,9 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) /***************************************************************************** * SPI ****************************************************************************/ -static struct orion_spi_info orion5x_spi_plat_data = { - .tclk = 0, - .enable_clock_fix = 1, -}; - -static struct resource orion5x_spi_resources[] = { - { - .name = "spi base", - .start = SPI_PHYS_BASE, - .end = SPI_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device orion5x_spi = { - .name = "orion_spi", - .id = 0, - .dev = { - .platform_data = &orion5x_spi_plat_data, - }, - .num_resources = ARRAY_SIZE(orion5x_spi_resources), - .resource = orion5x_spi_resources, -}; - void __init orion5x_spi_init() { - platform_device_register(&orion5x_spi); + orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); } @@ -513,8 +488,6 @@ void __init orion5x_init(void) orion5x_id(&dev, &rev, &dev_name); printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); - orion5x_spi_plat_data.tclk = orion5x_tclk; - /* * Setup Orion address map */ diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index bcc1734..2afe79d 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -17,6 +17,7 @@ #include #include #include +#include /* Fill in the resources structure and link it into the platform device structure. There is always a memory region, and nearly @@ -517,3 +518,49 @@ void __init orion_i2c_1_init(unsigned long mapbase, SZ_32 - 1, irq); platform_device_register(&orion_i2c_1); } + +/***************************************************************************** + * SPI + ****************************************************************************/ +static struct orion_spi_info orion_spi_plat_data; +static struct resource orion_spi_resources; + +static struct platform_device orion_spi = { + .name = "orion_spi", + .id = 0, + .dev = { + .platform_data = &orion_spi_plat_data, + }, +}; + +static struct orion_spi_info orion_spi_1_plat_data; +static struct resource orion_spi_1_resources; + +static struct platform_device orion_spi_1 = { + .name = "orion_spi", + .id = 1, + .dev = { + .platform_data = &orion_spi_1_plat_data, + }, +}; + +/* Note: The SPI silicon core does have interrupts. However the + * current Linux software driver does not use interrupts. */ + +void __init orion_spi_init(unsigned long mapbase, + unsigned long tclk) +{ + orion_spi_plat_data.tclk = tclk; + fill_resources(&orion_spi, &orion_spi_resources, + mapbase, SZ_512 - 1, NO_IRQ); + platform_device_register(&orion_spi); +} + +void __init orion_spi_1_init(unsigned long mapbase, + unsigned long tclk) +{ + orion_spi_1_plat_data.tclk = tclk; + fill_resources(&orion_spi_1, &orion_spi_1_resources, + mapbase, SZ_512 - 1, NO_IRQ); + platform_device_register(&orion_spi_1); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index d107c62..e72c146 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -73,4 +73,10 @@ void __init orion_i2c_init(unsigned long mapbase, void __init orion_i2c_1_init(unsigned long mapbase, unsigned long irq, unsigned long freq_m); + +void __init orion_spi_init(unsigned long mapbase, + unsigned long tclk); + +void __init orion_spi_1_init(unsigned long mapbase, + unsigned long tclk); #endif -- cgit v0.10.2 From 5e00d3783dd362a34c9816bb582103c9833e4643 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:47 +0200 Subject: ARM: orion: Consolidate the platform data setup for the watchdog. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index af864fc..08847a6 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include "common.h" @@ -575,23 +574,9 @@ static void __init kirkwood_xor1_init(void) /***************************************************************************** * Watchdog ****************************************************************************/ -static struct orion_wdt_platform_data kirkwood_wdt_data = { - .tclk = 0, -}; - -static struct platform_device kirkwood_wdt_device = { - .name = "orion_wdt", - .id = -1, - .dev = { - .platform_data = &kirkwood_wdt_data, - }, - .num_resources = 0, -}; - static void __init kirkwood_wdt_init(void) { - kirkwood_wdt_data.tclk = kirkwood_tclk; - platform_device_register(&kirkwood_wdt_device); + orion_wdt_init(kirkwood_tclk); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index d2dee43..c26e6db 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include "common.h" @@ -380,23 +379,9 @@ static int __init orion5x_crypto_init(void) /***************************************************************************** * Watchdog ****************************************************************************/ -static struct orion_wdt_platform_data orion5x_wdt_data = { - .tclk = 0, -}; - -static struct platform_device orion5x_wdt_device = { - .name = "orion_wdt", - .id = -1, - .dev = { - .platform_data = &orion5x_wdt_data, - }, - .num_resources = 0, -}; - void __init orion5x_wdt_init(void) { - orion5x_wdt_data.tclk = orion5x_tclk; - platform_device_register(&orion5x_wdt_device); + orion_wdt_init(orion5x_tclk); } diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 2afe79d..6502209 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -18,6 +18,7 @@ #include #include #include +#include /* Fill in the resources structure and link it into the platform device structure. There is always a memory region, and nearly @@ -564,3 +565,23 @@ void __init orion_spi_1_init(unsigned long mapbase, mapbase, SZ_512 - 1, NO_IRQ); platform_device_register(&orion_spi_1); } + +/***************************************************************************** + * Watchdog + ****************************************************************************/ +static struct orion_wdt_platform_data orion_wdt_data; + +static struct platform_device orion_wdt_device = { + .name = "orion_wdt", + .id = -1, + .dev = { + .platform_data = &orion_wdt_data, + }, + .num_resources = 0, +}; + +void __init orion_wdt_init(unsigned long tclk) +{ + orion_wdt_data.tclk = tclk; + platform_device_register(&orion_wdt_device); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index e72c146..38ae4bf 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -79,4 +79,6 @@ void __init orion_spi_init(unsigned long mapbase, void __init orion_spi_1_init(unsigned long mapbase, unsigned long tclk); + +void __init orion_wdt_init(unsigned long tclk); #endif -- cgit v0.10.2 From ee9627234dae8d1b8059b2ac39c961ee0932b803 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:48 +0200 Subject: ARM: orion: Consolidate the XOR platform setup code. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index e3e043c..6703bf3 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -278,208 +277,22 @@ struct sys_timer dove_timer = { }; /***************************************************************************** - * XOR - ****************************************************************************/ -static struct mv_xor_platform_shared_data dove_xor_shared_data = { - .dram = &dove_mbus_dram_info, -}; - -/***************************************************************************** * XOR 0 ****************************************************************************/ -static u64 dove_xor0_dmamask = DMA_BIT_MASK(32); - -static struct resource dove_xor0_shared_resources[] = { - { - .name = "xor 0 low", - .start = DOVE_XOR0_PHYS_BASE, - .end = DOVE_XOR0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor 0 high", - .start = DOVE_XOR0_HIGH_PHYS_BASE, - .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dove_xor0_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &dove_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(dove_xor0_shared_resources), - .resource = dove_xor0_shared_resources, -}; - -static struct resource dove_xor00_resources[] = { - [0] = { - .start = IRQ_DOVE_XOR_00, - .end = IRQ_DOVE_XOR_00, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data dove_xor00_data = { - .shared = &dove_xor0_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device dove_xor00_channel = { - .name = MV_XOR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(dove_xor00_resources), - .resource = dove_xor00_resources, - .dev = { - .dma_mask = &dove_xor0_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &dove_xor00_data, - }, -}; - -static struct resource dove_xor01_resources[] = { - [0] = { - .start = IRQ_DOVE_XOR_01, - .end = IRQ_DOVE_XOR_01, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data dove_xor01_data = { - .shared = &dove_xor0_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device dove_xor01_channel = { - .name = MV_XOR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(dove_xor01_resources), - .resource = dove_xor01_resources, - .dev = { - .dma_mask = &dove_xor0_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &dove_xor01_data, - }, -}; - void __init dove_xor0_init(void) { - platform_device_register(&dove_xor0_shared); - - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask); - dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask); - platform_device_register(&dove_xor00_channel); - - dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask); - dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask); - dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask); - platform_device_register(&dove_xor01_channel); + orion_xor0_init(&dove_mbus_dram_info, + DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, + IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); } /***************************************************************************** * XOR 1 ****************************************************************************/ -static u64 dove_xor1_dmamask = DMA_BIT_MASK(32); - -static struct resource dove_xor1_shared_resources[] = { - { - .name = "xor 0 low", - .start = DOVE_XOR1_PHYS_BASE, - .end = DOVE_XOR1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor 0 high", - .start = DOVE_XOR1_HIGH_PHYS_BASE, - .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dove_xor1_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &dove_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(dove_xor1_shared_resources), - .resource = dove_xor1_shared_resources, -}; - -static struct resource dove_xor10_resources[] = { - [0] = { - .start = IRQ_DOVE_XOR_10, - .end = IRQ_DOVE_XOR_10, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data dove_xor10_data = { - .shared = &dove_xor1_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device dove_xor10_channel = { - .name = MV_XOR_NAME, - .id = 2, - .num_resources = ARRAY_SIZE(dove_xor10_resources), - .resource = dove_xor10_resources, - .dev = { - .dma_mask = &dove_xor1_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &dove_xor10_data, - }, -}; - -static struct resource dove_xor11_resources[] = { - [0] = { - .start = IRQ_DOVE_XOR_11, - .end = IRQ_DOVE_XOR_11, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data dove_xor11_data = { - .shared = &dove_xor1_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device dove_xor11_channel = { - .name = MV_XOR_NAME, - .id = 3, - .num_resources = ARRAY_SIZE(dove_xor11_resources), - .resource = dove_xor11_resources, - .dev = { - .dma_mask = &dove_xor1_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &dove_xor11_data, - }, -}; - void __init dove_xor1_init(void) { - platform_device_register(&dove_xor1_shared); - - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask); - dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask); - platform_device_register(&dove_xor10_channel); - - dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask); - dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask); - dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask); - platform_device_register(&dove_xor11_channel); + orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, + IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); } /***************************************************************************** diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 08847a6..7c2b5df 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -364,210 +364,27 @@ void __init kirkwood_crypto_init(void) /***************************************************************************** - * XOR - ****************************************************************************/ -static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = { - .dram = &kirkwood_mbus_dram_info, -}; - - -/***************************************************************************** * XOR0 ****************************************************************************/ -static struct resource kirkwood_xor0_shared_resources[] = { - { - .name = "xor 0 low", - .start = XOR0_PHYS_BASE, - .end = XOR0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor 0 high", - .start = XOR0_HIGH_PHYS_BASE, - .end = XOR0_HIGH_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device kirkwood_xor0_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &kirkwood_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources), - .resource = kirkwood_xor0_shared_resources, -}; - -static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32); - -static struct resource kirkwood_xor00_resources[] = { - [0] = { - .start = IRQ_KIRKWOOD_XOR_00, - .end = IRQ_KIRKWOOD_XOR_00, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data kirkwood_xor00_data = { - .shared = &kirkwood_xor0_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device kirkwood_xor00_channel = { - .name = MV_XOR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(kirkwood_xor00_resources), - .resource = kirkwood_xor00_resources, - .dev = { - .dma_mask = &kirkwood_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &kirkwood_xor00_data, - }, -}; - -static struct resource kirkwood_xor01_resources[] = { - [0] = { - .start = IRQ_KIRKWOOD_XOR_01, - .end = IRQ_KIRKWOOD_XOR_01, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data kirkwood_xor01_data = { - .shared = &kirkwood_xor0_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device kirkwood_xor01_channel = { - .name = MV_XOR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(kirkwood_xor01_resources), - .resource = kirkwood_xor01_resources, - .dev = { - .dma_mask = &kirkwood_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &kirkwood_xor01_data, - }, -}; - static void __init kirkwood_xor0_init(void) { kirkwood_clk_ctrl |= CGC_XOR0; - platform_device_register(&kirkwood_xor0_shared); - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask); - dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask); - platform_device_register(&kirkwood_xor00_channel); - - dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask); - dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask); - dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask); - platform_device_register(&kirkwood_xor01_channel); + orion_xor0_init(&kirkwood_mbus_dram_info, + XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, + IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); } /***************************************************************************** * XOR1 ****************************************************************************/ -static struct resource kirkwood_xor1_shared_resources[] = { - { - .name = "xor 1 low", - .start = XOR1_PHYS_BASE, - .end = XOR1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor 1 high", - .start = XOR1_HIGH_PHYS_BASE, - .end = XOR1_HIGH_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device kirkwood_xor1_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &kirkwood_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources), - .resource = kirkwood_xor1_shared_resources, -}; - -static struct resource kirkwood_xor10_resources[] = { - [0] = { - .start = IRQ_KIRKWOOD_XOR_10, - .end = IRQ_KIRKWOOD_XOR_10, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data kirkwood_xor10_data = { - .shared = &kirkwood_xor1_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device kirkwood_xor10_channel = { - .name = MV_XOR_NAME, - .id = 2, - .num_resources = ARRAY_SIZE(kirkwood_xor10_resources), - .resource = kirkwood_xor10_resources, - .dev = { - .dma_mask = &kirkwood_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &kirkwood_xor10_data, - }, -}; - -static struct resource kirkwood_xor11_resources[] = { - [0] = { - .start = IRQ_KIRKWOOD_XOR_11, - .end = IRQ_KIRKWOOD_XOR_11, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data kirkwood_xor11_data = { - .shared = &kirkwood_xor1_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device kirkwood_xor11_channel = { - .name = MV_XOR_NAME, - .id = 3, - .num_resources = ARRAY_SIZE(kirkwood_xor11_resources), - .resource = kirkwood_xor11_resources, - .dev = { - .dma_mask = &kirkwood_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &kirkwood_xor11_data, - }, -}; - static void __init kirkwood_xor1_init(void) { kirkwood_clk_ctrl |= CGC_XOR1; - platform_device_register(&kirkwood_xor1_shared); - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask); - dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask); - platform_device_register(&kirkwood_xor10_channel); - - dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask); - dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask); - dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask); - platform_device_register(&kirkwood_xor11_channel); + orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE, + IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index c26e6db..5c7e391 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -28,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -239,104 +239,12 @@ void __init orion5x_uart1_init(void) /***************************************************************************** * XOR engine ****************************************************************************/ -struct mv_xor_platform_shared_data orion5x_xor_shared_data = { - .dram = &orion5x_mbus_dram_info, -}; - -static struct resource orion5x_xor_shared_resources[] = { - { - .name = "xor low", - .start = ORION5X_XOR_PHYS_BASE, - .end = ORION5X_XOR_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor high", - .start = ORION5X_XOR_PHYS_BASE + 0x200, - .end = ORION5X_XOR_PHYS_BASE + 0x2ff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device orion5x_xor_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &orion5x_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources), - .resource = orion5x_xor_shared_resources, -}; - -static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32); - -static struct resource orion5x_xor0_resources[] = { - [0] = { - .start = IRQ_ORION5X_XOR0, - .end = IRQ_ORION5X_XOR0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data orion5x_xor0_data = { - .shared = &orion5x_xor_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device orion5x_xor0_channel = { - .name = MV_XOR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(orion5x_xor0_resources), - .resource = orion5x_xor0_resources, - .dev = { - .dma_mask = &orion5x_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &orion5x_xor0_data, - }, -}; - -static struct resource orion5x_xor1_resources[] = { - [0] = { - .start = IRQ_ORION5X_XOR1, - .end = IRQ_ORION5X_XOR1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data orion5x_xor1_data = { - .shared = &orion5x_xor_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device orion5x_xor1_channel = { - .name = MV_XOR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(orion5x_xor1_resources), - .resource = orion5x_xor1_resources, - .dev = { - .dma_mask = &orion5x_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &orion5x_xor1_data, - }, -}; - void __init orion5x_xor_init(void) { - platform_device_register(&orion5x_xor_shared); - - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask); - dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask); - platform_device_register(&orion5x_xor0_channel); - - dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask); - dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask); - dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask); - platform_device_register(&orion5x_xor1_channel); + orion_xor0_init(&orion5x_mbus_dram_info, + ORION5X_XOR_PHYS_BASE, + ORION5X_XOR_PHYS_BASE + 0x200, + IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); } static struct resource orion5x_crypto_res[] = { diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 6502209..0a2face 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -19,6 +19,7 @@ #include #include #include +#include /* Fill in the resources structure and link it into the platform device structure. There is always a memory region, and nearly @@ -585,3 +586,217 @@ void __init orion_wdt_init(unsigned long tclk) orion_wdt_data.tclk = tclk; platform_device_register(&orion_wdt_device); } + +/***************************************************************************** + * XOR + ****************************************************************************/ +static struct mv_xor_platform_shared_data orion_xor_shared_data; + +static u64 orion_xor_dmamask = DMA_BIT_MASK(32); + +void __init orion_xor_init_channels( + struct mv_xor_platform_data *orion_xor0_data, + struct platform_device *orion_xor0_channel, + struct mv_xor_platform_data *orion_xor1_data, + struct platform_device *orion_xor1_channel) +{ + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask); + dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask); + platform_device_register(orion_xor0_channel); + + dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask); + dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask); + dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask); + platform_device_register(orion_xor1_channel); +} + +/***************************************************************************** + * XOR0 + ****************************************************************************/ +static struct resource orion_xor0_shared_resources[] = { + { + .name = "xor 0 low", + .flags = IORESOURCE_MEM, + }, { + .name = "xor 0 high", + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion_xor0_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &orion_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), + .resource = orion_xor0_shared_resources, +}; + +static struct resource orion_xor00_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion_xor00_data = { + .shared = &orion_xor0_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion_xor00_channel = { + .name = MV_XOR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(orion_xor00_resources), + .resource = orion_xor00_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor00_data, + }, +}; + +static struct resource orion_xor01_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion_xor01_data = { + .shared = &orion_xor0_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion_xor01_channel = { + .name = MV_XOR_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(orion_xor01_resources), + .resource = orion_xor01_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor01_data, + }, +}; + +void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase_low, + unsigned long mapbase_high, + unsigned long irq_0, + unsigned long irq_1) +{ + orion_xor_shared_data.dram = mbus_dram_info; + + orion_xor0_shared_resources[0].start = mapbase_low; + orion_xor0_shared_resources[0].end = mapbase_low + 0xff; + orion_xor0_shared_resources[1].start = mapbase_high; + orion_xor0_shared_resources[1].end = mapbase_high + 0xff; + + orion_xor00_resources[0].start = irq_0; + orion_xor00_resources[0].end = irq_0; + orion_xor01_resources[0].start = irq_1; + orion_xor01_resources[0].end = irq_1; + + platform_device_register(&orion_xor0_shared); + + orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel, + &orion_xor01_data, &orion_xor01_channel); +} + +/***************************************************************************** + * XOR1 + ****************************************************************************/ +static struct resource orion_xor1_shared_resources[] = { + { + .name = "xor 1 low", + .flags = IORESOURCE_MEM, + }, { + .name = "xor 1 high", + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion_xor1_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &orion_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), + .resource = orion_xor1_shared_resources, +}; + +static struct resource orion_xor10_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion_xor10_data = { + .shared = &orion_xor1_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion_xor10_channel = { + .name = MV_XOR_NAME, + .id = 2, + .num_resources = ARRAY_SIZE(orion_xor10_resources), + .resource = orion_xor10_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor10_data, + }, +}; + +static struct resource orion_xor11_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion_xor11_data = { + .shared = &orion_xor1_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion_xor11_channel = { + .name = MV_XOR_NAME, + .id = 3, + .num_resources = ARRAY_SIZE(orion_xor11_resources), + .resource = orion_xor11_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor11_data, + }, +}; + +void __init orion_xor1_init(unsigned long mapbase_low, + unsigned long mapbase_high, + unsigned long irq_0, + unsigned long irq_1) +{ + orion_xor1_shared_resources[0].start = mapbase_low; + orion_xor1_shared_resources[0].end = mapbase_low + 0xff; + orion_xor1_shared_resources[1].start = mapbase_high; + orion_xor1_shared_resources[1].end = mapbase_high + 0xff; + + orion_xor10_resources[0].start = irq_0; + orion_xor10_resources[0].end = irq_0; + orion_xor11_resources[0].start = irq_1; + orion_xor11_resources[0].end = irq_1; + + platform_device_register(&orion_xor1_shared); + + orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel, + &orion_xor11_data, &orion_xor11_channel); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 38ae4bf..0e11ca5 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -81,4 +81,15 @@ void __init orion_spi_1_init(unsigned long mapbase, unsigned long tclk); void __init orion_wdt_init(unsigned long tclk); + +void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase_low, + unsigned long mapbase_high, + unsigned long irq_0, + unsigned long irq_1); + +void __init orion_xor1_init(unsigned long mapbase_low, + unsigned long mapbase_high, + unsigned long irq_0, + unsigned long irq_1); #endif -- cgit v0.10.2 From 4fcd3f374a928081d391cd9a570afe3b2c692fdc Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:49 +0200 Subject: ARM: orion: Consolidate USB platform setup code. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 6703bf3..1412592 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include "common.h" @@ -70,77 +69,21 @@ void __init dove_map_io(void) } /***************************************************************************** - * EHCI - ****************************************************************************/ -static struct orion_ehci_data dove_ehci_data = { - .dram = &dove_mbus_dram_info, - .phy_version = EHCI_PHY_NA, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - -/***************************************************************************** * EHCI0 ****************************************************************************/ -static struct resource dove_ehci0_resources[] = { - { - .start = DOVE_USB0_PHYS_BASE, - .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_USB0, - .end = IRQ_DOVE_USB0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_ehci0 = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dove_ehci_data, - }, - .resource = dove_ehci0_resources, - .num_resources = ARRAY_SIZE(dove_ehci0_resources), -}; - void __init dove_ehci0_init(void) { - platform_device_register(&dove_ehci0); + orion_ehci_init(&dove_mbus_dram_info, + DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); } /***************************************************************************** * EHCI1 ****************************************************************************/ -static struct resource dove_ehci1_resources[] = { - { - .start = DOVE_USB1_PHYS_BASE, - .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_USB1, - .end = IRQ_DOVE_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_ehci1 = { - .name = "orion-ehci", - .id = 1, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dove_ehci_data, - }, - .resource = dove_ehci1_resources, - .num_resources = ARRAY_SIZE(dove_ehci1_resources), -}; - void __init dove_ehci1_init(void) { - platform_device_register(&dove_ehci1); + orion_ehci_1_init(&dove_mbus_dram_info, + DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); } /***************************************************************************** diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 7c2b5df..9e56cbb 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -69,47 +68,13 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; /***************************************************************************** - * EHCI - ****************************************************************************/ -static struct orion_ehci_data kirkwood_ehci_data = { - .dram = &kirkwood_mbus_dram_info, - .phy_version = EHCI_PHY_NA, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - - -/***************************************************************************** * EHCI0 ****************************************************************************/ -static struct resource kirkwood_ehci_resources[] = { - { - .start = USB_PHYS_BASE, - .end = USB_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_KIRKWOOD_USB, - .end = IRQ_KIRKWOOD_USB, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ehci = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &kirkwood_ehci_data, - }, - .resource = kirkwood_ehci_resources, - .num_resources = ARRAY_SIZE(kirkwood_ehci_resources), -}; - void __init kirkwood_ehci_init(void) { kirkwood_clk_ctrl |= CGC_USB0; - platform_device_register(&kirkwood_ehci); + orion_ehci_init(&kirkwood_mbus_dram_info, + USB_PHYS_BASE, IRQ_KIRKWOOD_USB); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index aa27c15..f250196 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -168,110 +167,30 @@ void __init mv78xx0_map_io(void) /***************************************************************************** * EHCI ****************************************************************************/ -static struct orion_ehci_data mv78xx0_ehci_data = { - .dram = &mv78xx0_mbus_dram_info, - .phy_version = EHCI_PHY_NA, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - - -/***************************************************************************** - * EHCI0 - ****************************************************************************/ -static struct resource mv78xx0_ehci0_resources[] = { - { - .start = USB0_PHYS_BASE, - .end = USB0_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_0, - .end = IRQ_MV78XX0_USB_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci0 = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci0_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources), -}; - void __init mv78xx0_ehci0_init(void) { - platform_device_register(&mv78xx0_ehci0); + orion_ehci_init(&mv78xx0_mbus_dram_info, + USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); } /***************************************************************************** * EHCI1 ****************************************************************************/ -static struct resource mv78xx0_ehci1_resources[] = { - { - .start = USB1_PHYS_BASE, - .end = USB1_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_1, - .end = IRQ_MV78XX0_USB_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci1 = { - .name = "orion-ehci", - .id = 1, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci1_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources), -}; - void __init mv78xx0_ehci1_init(void) { - platform_device_register(&mv78xx0_ehci1); + orion_ehci_1_init(&mv78xx0_mbus_dram_info, + USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); } /***************************************************************************** * EHCI2 ****************************************************************************/ -static struct resource mv78xx0_ehci2_resources[] = { - { - .start = USB2_PHYS_BASE, - .end = USB2_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_2, - .end = IRQ_MV78XX0_USB_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci2 = { - .name = "orion-ehci", - .id = 2, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci2_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources), -}; - void __init mv78xx0_ehci2_init(void) { - platform_device_register(&mv78xx0_ehci2); + orion_ehci_2_init(&mv78xx0_mbus_dram_info, + USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 5c7e391..2132eaf 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -68,79 +67,22 @@ void __init orion5x_map_io(void) /***************************************************************************** - * EHCI - ****************************************************************************/ -static struct orion_ehci_data orion5x_ehci_data = { - .dram = &orion5x_mbus_dram_info, - .phy_version = EHCI_PHY_ORION, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - - -/***************************************************************************** * EHCI0 ****************************************************************************/ -static struct resource orion5x_ehci0_resources[] = { - { - .start = ORION5X_USB0_PHYS_BASE, - .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_USB0_CTRL, - .end = IRQ_ORION5X_USB0_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_ehci0 = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &orion5x_ehci_data, - }, - .resource = orion5x_ehci0_resources, - .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), -}; - void __init orion5x_ehci0_init(void) { - platform_device_register(&orion5x_ehci0); + orion_ehci_init(&orion5x_mbus_dram_info, + ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); } /***************************************************************************** * EHCI1 ****************************************************************************/ -static struct resource orion5x_ehci1_resources[] = { - { - .start = ORION5X_USB1_PHYS_BASE, - .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_USB1_CTRL, - .end = IRQ_ORION5X_USB1_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_ehci1 = { - .name = "orion-ehci", - .id = 1, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &orion5x_ehci_data, - }, - .resource = orion5x_ehci1_resources, - .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), -}; - void __init orion5x_ehci1_init(void) { - platform_device_register(&orion5x_ehci1); + orion_ehci_1_init(&orion5x_mbus_dram_info, + ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); } diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 0a2face..802cbf4 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -20,6 +20,7 @@ #include #include #include +#include /* Fill in the resources structure and link it into the platform device structure. There is always a memory region, and nearly @@ -800,3 +801,91 @@ void __init orion_xor1_init(unsigned long mapbase_low, orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel, &orion_xor11_data, &orion_xor11_channel); } + +/***************************************************************************** + * EHCI + ****************************************************************************/ +static struct orion_ehci_data orion_ehci_data = { + .phy_version = EHCI_PHY_NA, +}; + +static u64 ehci_dmamask = DMA_BIT_MASK(32); + + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +static struct resource orion_ehci_resources[2]; + +static struct platform_device orion_ehci = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &orion_ehci_data, + }, +}; + +void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq) +{ + orion_ehci_data.dram = mbus_dram_info; + fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, + irq); + + platform_device_register(&orion_ehci); +} + +/***************************************************************************** + * EHCI1 + ****************************************************************************/ +static struct resource orion_ehci_1_resources[2]; + +static struct platform_device orion_ehci_1 = { + .name = "orion-ehci", + .id = 1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &orion_ehci_data, + }, +}; + +void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq) +{ + orion_ehci_data.dram = mbus_dram_info; + fill_resources(&orion_ehci_1, orion_ehci_1_resources, + mapbase, SZ_4K - 1, irq); + + platform_device_register(&orion_ehci_1); +} + +/***************************************************************************** + * EHCI2 + ****************************************************************************/ +static struct resource orion_ehci_2_resources[2]; + +static struct platform_device orion_ehci_2 = { + .name = "orion-ehci", + .id = 2, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &orion_ehci_data, + }, +}; + +void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq) +{ + orion_ehci_data.dram = mbus_dram_info; + fill_resources(&orion_ehci_2, orion_ehci_2_resources, + mapbase, SZ_4K - 1, irq); + + platform_device_register(&orion_ehci_2); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 0e11ca5..6386f8e 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -92,4 +92,16 @@ void __init orion_xor1_init(unsigned long mapbase_low, unsigned long mapbase_high, unsigned long irq_0, unsigned long irq_1); + +void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq); + +void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq); + +void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq); #endif -- cgit v0.10.2 From 9e613f8a7904f2b7516eed08f413463c579325bd Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:50 +0200 Subject: ARM: orion: Consolidate SATA platform setup. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 1412592..5ed51b8 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -107,35 +107,11 @@ void __init dove_rtc_init(void) /***************************************************************************** * SATA ****************************************************************************/ -static struct resource dove_sata_resources[] = { - { - .name = "sata base", - .start = DOVE_SATA_PHYS_BASE, - .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_DOVE_SATA, - .end = IRQ_DOVE_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(dove_sata_resources), - .resource = dove_sata_resources, -}; - void __init dove_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &dove_mbus_dram_info; - dove_sata.dev.platform_data = sata_data; - platform_device_register(&dove_sata); + orion_sata_init(sata_data, &dove_mbus_dram_info, + DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); + } /***************************************************************************** diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 9e56cbb..e96ec4e 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -172,38 +172,14 @@ static void __init kirkwood_rtc_init(void) /***************************************************************************** * SATA ****************************************************************************/ -static struct resource kirkwood_sata_resources[] = { - { - .name = "sata base", - .start = SATA_PHYS_BASE, - .end = SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_KIRKWOOD_SATA, - .end = IRQ_KIRKWOOD_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(kirkwood_sata_resources), - .resource = kirkwood_sata_resources, -}; - void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) { kirkwood_clk_ctrl |= CGC_SATA0; if (sata_data->n_ports > 1) kirkwood_clk_ctrl |= CGC_SATA1; - sata_data->dram = &kirkwood_mbus_dram_info; - kirkwood_sata.dev.platform_data = sata_data; - platform_device_register(&kirkwood_sata); + + orion_sata_init(sata_data, &kirkwood_mbus_dram_info, + SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index f250196..23d3980 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -275,35 +275,10 @@ void __init mv78xx0_i2c_init(void) /***************************************************************************** * SATA ****************************************************************************/ -static struct resource mv78xx0_sata_resources[] = { - { - .name = "sata base", - .start = SATA_PHYS_BASE, - .end = SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_MV78XX0_SATA, - .end = IRQ_MV78XX0_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mv78xx0_sata_resources), - .resource = mv78xx0_sata_resources, -}; - void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &mv78xx0_mbus_dram_info; - mv78xx0_sata.dev.platform_data = sata_data; - platform_device_register(&mv78xx0_sata); + orion_sata_init(sata_data, &mv78xx0_mbus_dram_info, + SATA_PHYS_BASE, IRQ_MV78XX0_SATA); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 2132eaf..8bbf497c 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -119,35 +119,10 @@ void __init orion5x_i2c_init(void) /***************************************************************************** * SATA ****************************************************************************/ -static struct resource orion5x_sata_resources[] = { - { - .name = "sata base", - .start = ORION5X_SATA_PHYS_BASE, - .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_ORION5X_SATA, - .end = IRQ_ORION5X_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(orion5x_sata_resources), - .resource = orion5x_sata_resources, -}; - void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &orion5x_mbus_dram_info; - orion5x_sata.dev.platform_data = sata_data; - platform_device_register(&orion5x_sata); + orion_sata_init(sata_data, &orion5x_mbus_dram_info, + ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); } diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 802cbf4..d1cf7c3 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -889,3 +890,37 @@ void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, platform_device_register(&orion_ehci_2); } + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct resource orion_sata_resources[2] = { + { + .name = "sata base", + }, { + .name = "sata irq", + }, +}; + +static struct platform_device orion_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_sata_init(struct mv_sata_platform_data *sata_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq) +{ + sata_data->dram = mbus_dram_info; + orion_sata.dev.platform_data = sata_data; + fill_resources(&orion_sata, orion_sata_resources, + mapbase, 0x5000 - 1, irq); + + platform_device_register(&orion_sata); +} + + diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 6386f8e..0ec6b66 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -104,4 +104,9 @@ void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq); + +void __init orion_sata_init(struct mv_sata_platform_data *sata_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq); #endif -- cgit v0.10.2 From 44350061905b2a502579d3827eacaf8efa393aad Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:51 +0200 Subject: ARM: orion: Consolidate setup of the crypto engine. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index e96ec4e..f3248cf 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -270,37 +270,11 @@ void __init kirkwood_uart1_init(void) /***************************************************************************** * Cryptographic Engines and Security Accelerator (CESA) ****************************************************************************/ - -static struct resource kirkwood_crypto_res[] = { - { - .name = "regs", - .start = CRYPTO_PHYS_BASE, - .end = CRYPTO_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, - }, { - .name = "sram", - .start = KIRKWOOD_SRAM_PHYS_BASE, - .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "crypto interrupt", - .start = IRQ_KIRKWOOD_CRYPTO, - .end = IRQ_KIRKWOOD_CRYPTO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_crypto_device = { - .name = "mv_crypto", - .id = -1, - .num_resources = ARRAY_SIZE(kirkwood_crypto_res), - .resource = kirkwood_crypto_res, -}; - void __init kirkwood_crypto_init(void) { kirkwood_clk_ctrl |= CGC_CRYPTO; - platform_device_register(&kirkwood_crypto_device); + orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE, + KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 8bbf497c..0ab531d 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -164,41 +164,19 @@ void __init orion5x_xor_init(void) IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); } -static struct resource orion5x_crypto_res[] = { - { - .name = "regs", - .start = ORION5X_CRYPTO_PHYS_BASE, - .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, - }, { - .name = "sram", - .start = ORION5X_SRAM_PHYS_BASE, - .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "crypto interrupt", - .start = IRQ_ORION5X_CESA, - .end = IRQ_ORION5X_CESA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_crypto_device = { - .name = "mv_crypto", - .id = -1, - .num_resources = ARRAY_SIZE(orion5x_crypto_res), - .resource = orion5x_crypto_res, -}; - -static int __init orion5x_crypto_init(void) +/***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ +static void __init orion5x_crypto_init(void) { int ret; ret = orion5x_setup_sram_win(); if (ret) - return ret; + return; - return platform_device_register(&orion5x_crypto_device); + orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, + SZ_8K, IRQ_ORION5X_CESA); } /***************************************************************************** diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index d1cf7c3..9e5451b 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -923,4 +923,35 @@ void __init orion_sata_init(struct mv_sata_platform_data *sata_data, platform_device_register(&orion_sata); } +/***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ +static struct resource orion_crypto_resources[] = { + { + .name = "regs", + }, { + .name = "crypto interrupt", + }, { + .name = "sram", + .flags = IORESOURCE_MEM, + }, +}; +static struct platform_device orion_crypto = { + .name = "mv_crypto", + .id = -1, +}; + +void __init orion_crypto_init(unsigned long mapbase, + unsigned long srambase, + unsigned long sram_size, + unsigned long irq) +{ + fill_resources(&orion_crypto, orion_crypto_resources, + mapbase, 0xffff, irq); + orion_crypto.num_resources = 3; + orion_crypto_resources[2].start = srambase; + orion_crypto_resources[2].end = srambase + sram_size - 1; + + platform_device_register(&orion_crypto); +} diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 0ec6b66..a63c357 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -109,4 +109,9 @@ void __init orion_sata_init(struct mv_sata_platform_data *sata_data, struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq); + +void __init orion_crypto_init(unsigned long mapbase, + unsigned long srambase, + unsigned long sram_size, + unsigned long irq); #endif -- cgit v0.10.2 From b2f427a1088a9ad4f86855f4df1fc059bebb441f Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:52 +0200 Subject: ARM: orion: Refactor the MPP code common in the orion platform mv78xx0 and kirkwood use identical mpp code. It should also be possible to rewrite the orion5x mpp to use this platform code. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 7ce2018..b0a7d97 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "common.h" #include "mpp.h" @@ -36,61 +37,8 @@ static unsigned int __init kirkwood_variant(void) return 0; } -#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) -#define MPP_NR_REGS (1 + MPP_MAX/8) - void __init kirkwood_mpp_conf(unsigned int *mpp_list) { - u32 mpp_ctrl[MPP_NR_REGS]; - unsigned int variant_mask; - int i; - - variant_mask = kirkwood_variant(); - if (!variant_mask) - return; - - printk(KERN_DEBUG "initial MPP regs:"); - for (i = 0; i < MPP_NR_REGS; i++) { - mpp_ctrl[i] = readl(MPP_CTRL(i)); - printk(" %08x", mpp_ctrl[i]); - } - printk("\n"); - - for ( ; *mpp_list; mpp_list++) { - unsigned int num = MPP_NUM(*mpp_list); - unsigned int sel = MPP_SEL(*mpp_list); - int shift, gpio_mode; - - if (num > MPP_MAX) { - printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP " - "number (%u)\n", num); - continue; - } - if (!(*mpp_list & variant_mask)) { - printk(KERN_WARNING - "kirkwood_mpp_conf: requested MPP%u config " - "unavailable on this hardware\n", num); - continue; - } - - shift = (num & 7) << 2; - mpp_ctrl[num / 8] &= ~(0xf << shift); - mpp_ctrl[num / 8] |= sel << shift; - - gpio_mode = 0; - if (*mpp_list & MPP_INPUT_MASK) - gpio_mode |= GPIO_INPUT_OK; - if (*mpp_list & MPP_OUTPUT_MASK) - gpio_mode |= GPIO_OUTPUT_OK; - if (sel != 0) - gpio_mode = 0; - orion_gpio_set_valid(num, gpio_mode); - } - - printk(KERN_DEBUG " final MPP regs:"); - for (i = 0; i < MPP_NR_REGS; i++) { - writel(mpp_ctrl[i], MPP_CTRL(i)); - printk(" %08x", mpp_ctrl[i]); - } - printk("\n"); + orion_mpp_conf(mpp_list, kirkwood_variant(), + MPP_MAX, DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h index 9b0a94d..ac78795 100644 --- a/arch/arm/mach-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/mpp.h @@ -22,14 +22,8 @@ /* available on F6281 */ ((!!(_F6281)) << 17) | \ /* available on F6282 */ ((!!(_F6282)) << 18)) -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - /* num sel i o 6180 6190 6192 6281 6282 */ -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 ) -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 ) - #define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 ) #define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 ) #define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 ) diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index 65b72c4..59b7686 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include "common.h" @@ -31,61 +32,8 @@ static unsigned int __init mv78xx0_variant(void) return 0; } -#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) -#define MPP_NR_REGS (1 + MPP_MAX/8) - void __init mv78xx0_mpp_conf(unsigned int *mpp_list) { - u32 mpp_ctrl[MPP_NR_REGS]; - unsigned int variant_mask; - int i; - - variant_mask = mv78xx0_variant(); - if (!variant_mask) - return; - - printk(KERN_DEBUG "initial MPP regs:"); - for (i = 0; i < MPP_NR_REGS; i++) { - mpp_ctrl[i] = readl(MPP_CTRL(i)); - printk(" %08x", mpp_ctrl[i]); - } - printk("\n"); - - for ( ; *mpp_list; mpp_list++) { - unsigned int num = MPP_NUM(*mpp_list); - unsigned int sel = MPP_SEL(*mpp_list); - int shift, gpio_mode; - - if (num > MPP_MAX) { - printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP " - "number (%u)\n", num); - continue; - } - if (!(*mpp_list & variant_mask)) { - printk(KERN_WARNING - "mv78xx0_mpp_conf: requested MPP%u config " - "unavailable on this hardware\n", num); - continue; - } - - shift = (num & 7) << 2; - mpp_ctrl[num / 8] &= ~(0xf << shift); - mpp_ctrl[num / 8] |= sel << shift; - - gpio_mode = 0; - if (*mpp_list & MPP_INPUT_MASK) - gpio_mode |= GPIO_INPUT_OK; - if (*mpp_list & MPP_OUTPUT_MASK) - gpio_mode |= GPIO_OUTPUT_OK; - if (sel != 0) - gpio_mode = 0; - orion_gpio_set_valid(num, gpio_mode); - } - - printk(KERN_DEBUG " final MPP regs:"); - for (i = 0; i < MPP_NR_REGS; i++) { - writel(mpp_ctrl[i], MPP_CTRL(i)); - printk(" %08x", mpp_ctrl[i]); - } - printk("\n"); + orion_mpp_conf(mpp_list, mv78xx0_variant(), + MPP_MAX, DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h index 80840b7..b61b509 100644 --- a/arch/arm/mach-mv78xx0/mpp.h +++ b/arch/arm/mach-mv78xx0/mpp.h @@ -19,14 +19,8 @@ /* may be output signal */ ((!!(_out)) << 13) | \ /* available on A0 */ ((!!(_78100_A0)) << 14)) -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - /* num sel i o 78100_A0 */ -#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0) -#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0) - #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 0f048c5..95a5fc5 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o time.o common.o +obj-y := irq.o pcie.o time.o common.o mpp.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h new file mode 100644 index 0000000..723adce --- /dev/null +++ b/arch/arm/plat-orion/include/plat/mpp.h @@ -0,0 +1,34 @@ +/* + * arch/arm/plat-orion/include/plat/mpp.h + * + * Marvell Orion SoC MPP handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_MPP_H +#define __PLAT_MPP_H + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + +/* This is the generic MPP macro, without any variant information. + Each machine architecture is expected to extend this with further + bit fields indicating which MPP configurations are valid for a + specific variant. */ + +#define GENERIC_MPP(_num, _sel, _in, _out) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13)) + +#define MPP_INPUT_MASK GENERIC_MPP(0, 0x0, 1, 0) +#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1) + +void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, + unsigned int mpp_max, unsigned int dev_bus); + +#endif diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c new file mode 100644 index 0000000..248c022 --- /dev/null +++ b/arch/arm/plat-orion/mpp.c @@ -0,0 +1,81 @@ +/* + * arch/arm/plat-orion/mpp.c + * + * MPP functions for Marvell orion SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Address of the ith MPP control register */ +static __init unsigned long mpp_ctrl_addr(unsigned int i, + unsigned long dev_bus) +{ + return dev_bus + (i) * 4; +} + + +void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, + unsigned int mpp_max, unsigned int dev_bus) +{ + unsigned int mpp_nr_regs = (1 + mpp_max/8); + u32 mpp_ctrl[mpp_nr_regs]; + int i; + + if (!variant_mask) + return; + + printk(KERN_DEBUG "initial MPP regs:"); + for (i = 0; i < mpp_nr_regs; i++) { + mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus)); + printk(" %08x", mpp_ctrl[i]); + } + printk("\n"); + + for ( ; *mpp_list; mpp_list++) { + unsigned int num = MPP_NUM(*mpp_list); + unsigned int sel = MPP_SEL(*mpp_list); + int shift, gpio_mode; + + if (num > mpp_max) { + printk(KERN_ERR "orion_mpp_conf: invalid MPP " + "number (%u)\n", num); + continue; + } + if (!(*mpp_list & variant_mask)) { + printk(KERN_WARNING + "orion_mpp_conf: requested MPP%u config " + "unavailable on this hardware\n", num); + continue; + } + + shift = (num & 7) << 2; + mpp_ctrl[num / 8] &= ~(0xf << shift); + mpp_ctrl[num / 8] |= sel << shift; + + gpio_mode = 0; + if (*mpp_list & MPP_INPUT_MASK) + gpio_mode |= GPIO_INPUT_OK; + if (*mpp_list & MPP_OUTPUT_MASK) + gpio_mode |= GPIO_OUTPUT_OK; + if (sel != 0) + gpio_mode = 0; + orion_gpio_set_valid(num, gpio_mode); + } + + printk(KERN_DEBUG " final MPP regs:"); + for (i = 0; i < mpp_nr_regs; i++) { + writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus)); + printk(" %08x", mpp_ctrl[i]); + } + printk("\n"); +} -- cgit v0.10.2 From 554cdaefd1cf7bb54b209c4e68c7cec87ce442a9 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:53 +0200 Subject: ARM: orion5x: Refactor mpp code to use common orion platform mpp. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 42580757..19cf5bf 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c @@ -267,28 +267,28 @@ static struct platform_device d2net_gpio_buttons = { * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Board ID (bit 0) */ - { 1, MPP_GPIO }, /* Board ID (bit 1) */ - { 2, MPP_GPIO }, /* Board ID (bit 2) */ - { 3, MPP_GPIO }, /* SATA 0 power */ - { 4, MPP_UNUSED }, - { 5, MPP_GPIO }, /* Fan fail detection */ - { 6, MPP_GPIO }, /* Red front LED */ - { 7, MPP_UNUSED }, - { 8, MPP_GPIO }, /* Rear power switch (on|auto) */ - { 9, MPP_GPIO }, /* Rear power switch (auto|off) */ - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_GPIO }, /* SATA 1 power */ - { 13, MPP_UNUSED }, - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_GPIO }, /* Blue front LED blink control */ - { 17, MPP_UNUSED }, - { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ - { 19, MPP_UNUSED }, - { -1 } +static unsigned int d2net_mpp_modes[] __initdata = { + MPP0_GPIO, /* Board ID (bit 0) */ + MPP1_GPIO, /* Board ID (bit 1) */ + MPP2_GPIO, /* Board ID (bit 2) */ + MPP3_GPIO, /* SATA 0 power */ + MPP4_UNUSED, + MPP5_GPIO, /* Fan fail detection */ + MPP6_GPIO, /* Red front LED */ + MPP7_UNUSED, + MPP8_GPIO, /* Rear power switch (on|auto) */ + MPP9_GPIO, /* Rear power switch (auto|off) */ + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_GPIO, /* SATA 1 power */ + MPP13_UNUSED, + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_GPIO, /* Blue front LED blink control */ + MPP17_UNUSED, + MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */ + MPP19_UNUSED, + 0, /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ /* 23: Blue front LED off */ /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */ diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index b7d4591..f95d3cb 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -298,28 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* USB Over Current */ - { 1, MPP_GPIO }, /* USB Vbat input */ - { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */ - { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */ - { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */ - { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */ - { 6, MPP_GPIO }, /* JP0, CON17.2 */ - { 7, MPP_GPIO }, /* JP1, CON17.1 */ - { 8, MPP_GPIO }, /* JP2, CON11.2 */ - { 9, MPP_GPIO }, /* JP3, CON11.3 */ - { 10, MPP_GPIO }, /* RTC int */ - { 11, MPP_GPIO }, /* Baud Rate Generator */ - { 12, MPP_GPIO }, /* PCI int 1 */ - { 13, MPP_GPIO }, /* PCI int 2 */ - { 14, MPP_NAND }, /* NAND_REn[2] */ - { 15, MPP_NAND }, /* NAND_WEn[2] */ - { 16, MPP_UART }, /* UART1_RX */ - { 17, MPP_UART }, /* UART1_TX */ - { 18, MPP_UART }, /* UART1_CTSn */ - { 19, MPP_UART }, /* UART1_RTSn */ - { -1 }, +static unsigned int db88f5281_mpp_modes[] __initdata = { + MPP0_GPIO, /* USB Over Current */ + MPP1_GPIO, /* USB Vbat input */ + MPP2_PCI_ARB, /* PCI_REQn[2] */ + MPP3_PCI_ARB, /* PCI_GNTn[2] */ + MPP4_PCI_ARB, /* PCI_REQn[3] */ + MPP5_PCI_ARB, /* PCI_GNTn[3] */ + MPP6_GPIO, /* JP0, CON17.2 */ + MPP7_GPIO, /* JP1, CON17.1 */ + MPP8_GPIO, /* JP2, CON11.2 */ + MPP9_GPIO, /* JP3, CON11.3 */ + MPP10_GPIO, /* RTC int */ + MPP11_GPIO, /* Baud Rate Generator */ + MPP12_GPIO, /* PCI int 1 */ + MPP13_GPIO, /* PCI int 2 */ + MPP14_NAND, /* NAND_REn[2] */ + MPP15_NAND, /* NAND_WEn[2] */ + MPP16_UART, /* UART1_RX */ + MPP17_UART, /* UART1_TX */ + MPP18_UART, /* UART1_CTSn */ + MPP19_UART, /* UART1_RTSn */ + 0, }; static void __init db88f5281_init(void) diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 90ab022..855e0e7 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -385,76 +385,76 @@ static struct mv_sata_platform_data dns323_sata_data = { /**************************************************************************** * General Setup */ -static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = { - { 0, MPP_PCIE_RST_OUTn }, - { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ - { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ - { 3, MPP_UNUSED }, - { 4, MPP_GPIO }, /* power button LED */ - { 5, MPP_GPIO }, /* power button LED */ - { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ - { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ - { 8, MPP_GPIO }, /* triggers power off */ - { 9, MPP_GPIO }, /* power button switch */ - { 10, MPP_GPIO }, /* reset button switch */ - { 11, MPP_UNUSED }, - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_UNUSED }, - { 15, MPP_UNUSED }, - { 16, MPP_UNUSED }, - { 17, MPP_UNUSED }, - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int dns323a_mpp_modes[] __initdata = { + MPP0_PCIE_RST_OUTn, + MPP1_GPIO, /* right amber LED (sata ch0) */ + MPP2_GPIO, /* left amber LED (sata ch1) */ + MPP3_UNUSED, + MPP4_GPIO, /* power button LED */ + MPP5_GPIO, /* power button LED */ + MPP6_GPIO, /* GMT G751-2f overtemp */ + MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */ + MPP8_GPIO, /* triggers power off */ + MPP9_GPIO, /* power button switch */ + MPP10_GPIO, /* reset button switch */ + MPP11_UNUSED, + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_UNUSED, + MPP15_UNUSED, + MPP16_UNUSED, + MPP17_UNUSED, + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; -static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ - { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ - { 3, MPP_GPIO }, /* system up flag */ - { 4, MPP_GPIO }, /* power button LED */ - { 5, MPP_GPIO }, /* power button LED */ - { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ - { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ - { 8, MPP_GPIO }, /* triggers power off */ - { 9, MPP_GPIO }, /* power button switch */ - { 10, MPP_GPIO }, /* reset button switch */ - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, - { 13, MPP_SATA_LED }, - { 14, MPP_SATA_LED }, - { 15, MPP_SATA_LED }, - { 16, MPP_UNUSED }, - { 17, MPP_UNUSED }, - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int dns323b_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_GPIO, /* right amber LED (sata ch0) */ + MPP2_GPIO, /* left amber LED (sata ch1) */ + MPP3_GPIO, /* system up flag */ + MPP4_GPIO, /* power button LED */ + MPP5_GPIO, /* power button LED */ + MPP6_GPIO, /* GMT G751-2f overtemp */ + MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */ + MPP8_GPIO, /* triggers power off */ + MPP9_GPIO, /* power button switch */ + MPP10_GPIO, /* reset button switch */ + MPP11_UNUSED, + MPP12_SATA_LED, + MPP13_SATA_LED, + MPP14_SATA_LED, + MPP15_SATA_LED, + MPP16_UNUSED, + MPP17_UNUSED, + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; -static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* ? input */ - { 1, MPP_GPIO }, /* input power switch (0 = pressed) */ - { 2, MPP_GPIO }, /* output power off */ - { 3, MPP_UNUSED }, /* ? output */ - { 4, MPP_UNUSED }, /* ? output */ - { 5, MPP_UNUSED }, /* ? output */ - { 6, MPP_UNUSED }, /* ? output */ - { 7, MPP_UNUSED }, /* ? output */ - { 8, MPP_GPIO }, /* i/o right amber LED */ - { 9, MPP_GPIO }, /* i/o left amber LED */ - { 10, MPP_GPIO }, /* input */ - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, - { 13, MPP_SATA_LED }, - { 14, MPP_SATA_LED }, - { 15, MPP_SATA_LED }, - { 16, MPP_UNUSED }, - { 17, MPP_GPIO }, /* power button LED */ - { 18, MPP_GPIO }, /* fan speed bit 0 */ - { 19, MPP_GPIO }, /* fan speed bit 1 */ - { -1 }, +static unsigned int dns323c_mpp_modes[] __initdata = { + MPP0_GPIO, /* ? input */ + MPP1_GPIO, /* input power switch (0 = pressed) */ + MPP2_GPIO, /* output power off */ + MPP3_UNUSED, /* ? output */ + MPP4_UNUSED, /* ? output */ + MPP5_UNUSED, /* ? output */ + MPP6_UNUSED, /* ? output */ + MPP7_UNUSED, /* ? output */ + MPP8_GPIO, /* i/o right amber LED */ + MPP9_GPIO, /* i/o left amber LED */ + MPP10_GPIO, /* input */ + MPP11_UNUSED, + MPP12_SATA_LED, + MPP13_SATA_LED, + MPP14_SATA_LED, + MPP15_SATA_LED, + MPP16_UNUSED, + MPP17_GPIO, /* power button LED */ + MPP18_GPIO, /* fan speed bit 0 */ + MPP19_GPIO, /* fan speed bit 1 */ + 0, }; /* Rev C1 Fan speed notes: diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index d037a90..b67cff0 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -180,31 +180,31 @@ static struct platform_device edmini_v2_gpio_buttons = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_UNUSED }, - { 2, MPP_UNUSED }, - { 3, MPP_GPIO }, /* RTC interrupt */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_UNUSED }, - { 7, MPP_UNUSED }, - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ +static unsigned int edminiv2_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_UNUSED, + MPP2_UNUSED, + MPP3_GPIO, /* RTC interrupt */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_UNUSED, + MPP7_UNUSED, + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ /* 16: Power LED control (0 = On, 1 = Off) */ - { 16, MPP_GPIO }, + MPP16_GPIO, /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */ - { 17, MPP_GPIO }, + MPP17_GPIO, /* 18: Power button status (0 = Released, 1 = Pressed) */ - { 18, MPP_GPIO }, - { 19, MPP_UNUSED }, - { -1 } + MPP18_GPIO, + MPP19_UNUSED, + 0, }; static void __init edmini_v2_init(void) diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index 47497c7..c0eb646 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -315,28 +315,28 @@ static void kurobox_pro_power_off(void) /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_UNUSED }, - { 2, MPP_GPIO }, /* GPIO Micon */ - { 3, MPP_GPIO }, /* GPIO Rtc */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_NAND }, /* NAND Flash REn */ - { 7, MPP_NAND }, /* NAND Flash WEn */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UART }, /* UART1 RXD */ - { 17, MPP_UART }, /* UART1 TXD */ - { 18, MPP_UART }, /* UART1 CTSn */ - { 19, MPP_UART }, /* UART1 RTSn */ - { -1 }, +static unsigned int kurobox_pro_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_UNUSED, + MPP2_GPIO, /* GPIO Micon */ + MPP3_GPIO, /* GPIO Rtc */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_NAND, /* NAND Flash REn */ + MPP7_NAND, /* NAND Flash WEn */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UART, /* UART1 RXD */ + MPP17_UART, /* UART1 TXD */ + MPP18_UART, /* UART1 CTSn */ + MPP19_UART, /* UART1 RTSn */ + 0, }; static void __init kurobox_pro_init(void) diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 6ae12aa..5065803 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -251,28 +251,28 @@ static struct platform_device lschl_fan_device = { * GPIO Data ****************************************************************************/ -static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* LED POWER */ - { 1, MPP_GPIO }, /* HDD POWER */ - { 2, MPP_GPIO }, /* LED ALARM */ - { 3, MPP_GPIO }, /* LED INFO */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_GPIO }, /* FAN LOCK */ - { 7, MPP_GPIO }, /* SW INIT */ - { 8, MPP_GPIO }, /* SW POWER */ - { 9, MPP_GPIO }, /* USB POWER */ - { 10, MPP_GPIO }, /* SW AUTO POWER */ - { 11, MPP_UNUSED }, - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_GPIO }, /* FAN HIGH */ - { 15, MPP_GPIO }, /* SW FUNC */ - { 16, MPP_GPIO }, /* FAN LOW */ - { 17, MPP_GPIO }, /* LED FUNC */ - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int lschl_mpp_modes[] __initdata = { + MPP0_GPIO, /* LED POWER */ + MPP1_GPIO, /* HDD POWER */ + MPP2_GPIO, /* LED ALARM */ + MPP3_GPIO, /* LED INFO */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_GPIO, /* FAN LOCK */ + MPP7_GPIO, /* SW INIT */ + MPP8_GPIO, /* SW POWER */ + MPP9_GPIO, /* USB POWER */ + MPP10_GPIO, /* SW AUTO POWER */ + MPP11_UNUSED, + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_GPIO, /* FAN HIGH */ + MPP15_GPIO, /* SW FUNC */ + MPP16_GPIO, /* FAN LOW */ + MPP17_GPIO, /* LED FUNC */ + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init lschl_init(void) diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index 7adafd7..8503d0a 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -200,28 +200,28 @@ static void ls_hgl_power_off(void) #define LS_HGL_GPIO_HDD_POWER 1 -static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* LED_PWR */ - { 1, MPP_GPIO }, /* HDD_PWR */ - { 2, MPP_GPIO }, /* LED_ALARM */ - { 3, MPP_GPIO }, /* LED_INFO */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_GPIO }, /* FAN_LCK */ - { 7, MPP_GPIO }, /* INIT */ - { 8, MPP_GPIO }, /* POWER */ - { 9, MPP_GPIO }, /* USB_PWR */ - { 10, MPP_GPIO }, /* AUTO_POWER */ - { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_UNUSED }, - { 15, MPP_GPIO }, /* FUNC */ - { 16, MPP_UNUSED }, - { 17, MPP_GPIO }, /* LED_FUNC */ - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int ls_hgl_mpp_modes[] __initdata = { + MPP0_GPIO, /* LED_PWR */ + MPP1_GPIO, /* HDD_PWR */ + MPP2_GPIO, /* LED_ALARM */ + MPP3_GPIO, /* LED_INFO */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_GPIO, /* FAN_LCK */ + MPP7_GPIO, /* INIT */ + MPP8_GPIO, /* POWER */ + MPP9_GPIO, /* USB_PWR */ + MPP10_GPIO, /* AUTO_POWER */ + MPP11_UNUSED, /* LED_ETH (dummy) */ + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_UNUSED, + MPP15_GPIO, /* FUNC */ + MPP16_UNUSED, + MPP17_GPIO, /* LED_FUNC */ + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init ls_hgl_init(void) diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index 869958f..9c82723 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -201,28 +201,28 @@ static void lsmini_power_off(void) #define LSMINI_GPIO_HDD_POWER0 1 #define LSMINI_GPIO_HDD_POWER1 19 -static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */ - { 1, MPP_GPIO }, /* HDD_PWR */ - { 2, MPP_GPIO }, /* LED_ALARM */ - { 3, MPP_GPIO }, /* LED_INFO */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_UNUSED }, - { 7, MPP_UNUSED }, - { 8, MPP_UNUSED }, - { 9, MPP_GPIO }, /* LED_FUNC */ - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_GPIO }, /* LED_PWR */ - { 15, MPP_GPIO }, /* FUNC */ - { 16, MPP_GPIO }, /* USB_PWR */ - { 17, MPP_GPIO }, /* AUTO_POWER */ - { 18, MPP_GPIO }, /* POWER */ - { 19, MPP_GPIO }, /* HDD_PWR1 */ - { -1 }, +static unsigned int lsmini_mpp_modes[] __initdata = { + MPP0_UNUSED, /* LED_RESERVE1 (unused) */ + MPP1_GPIO, /* HDD_PWR */ + MPP2_GPIO, /* LED_ALARM */ + MPP3_GPIO, /* LED_INFO */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_UNUSED, + MPP7_UNUSED, + MPP8_UNUSED, + MPP9_GPIO, /* LED_FUNC */ + MPP10_UNUSED, + MPP11_UNUSED, /* LED_ETH (dummy) */ + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_GPIO, /* LED_PWR */ + MPP15_GPIO, /* FUNC */ + MPP16_GPIO, /* USB_PWR */ + MPP17_GPIO, /* AUTO_POWER */ + MPP18_GPIO, /* POWER */ + MPP19_GPIO, /* HDD_PWR1 */ + 0, }; static void __init lsmini_init(void) diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 2288207..f12c41b 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -12,154 +12,34 @@ #include #include #include -#include #include -#include "common.h" +#include #include "mpp.h" +#include "common.h" -static int is_5181l(void) -{ - u32 dev; - u32 rev; - - orion5x_pcie_id(&dev, &rev); - - return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0); -} - -static int is_5182(void) +static unsigned int __init orion5x_variant(void) { u32 dev; u32 rev; orion5x_pcie_id(&dev, &rev); - return !!(dev == MV88F5182_DEV_ID); -} + if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) + return MPP_F5181_MASK; -static int is_5281(void) -{ - u32 dev; - u32 rev; + if (dev == MV88F5182_DEV_ID) + return MPP_F5182_MASK; - orion5x_pcie_id(&dev, &rev); + if (dev == MV88F5281_DEV_ID) + return MPP_F5281_MASK; - return !!(dev == MV88F5281_DEV_ID); + printk(KERN_ERR "MPP setup: unknown orion5x variant " + "(dev %#x rev %#x)\n", dev, rev); + return 0; } -static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type) +void __init orion5x_mpp_conf(unsigned int *mpp_list) { - switch (type) { - case MPP_UNUSED: - case MPP_GPIO: - if (mpp == 0) - return 3; - if (mpp >= 1 && mpp <= 15) - return 0; - if (mpp >= 16 && mpp <= 19) { - if (is_5182()) - return 5; - if (type == MPP_UNUSED) - return 0; - } - return -1; - - case MPP_PCIE_RST_OUTn: - if (mpp == 0) - return 0; - return -1; - - case MPP_PCI_ARB: - if (mpp >= 0 && mpp <= 7) - return 2; - return -1; - - case MPP_PCI_PMEn: - if (mpp == 2) - return 3; - return -1; - - case MPP_GIGE: - if (mpp >= 8 && mpp <= 19) - return 1; - return -1; - - case MPP_NAND: - if (is_5182() || is_5281()) { - if (mpp >= 4 && mpp <= 7) - return 4; - if (mpp >= 12 && mpp <= 17) - return 4; - } - return -1; - - case MPP_PCI_CLK: - if (is_5181l() && mpp >= 6 && mpp <= 7) - return 5; - return -1; - - case MPP_SATA_LED: - if (is_5182()) { - if (mpp >= 4 && mpp <= 7) - return 5; - if (mpp >= 12 && mpp <= 15) - return 5; - } - return -1; - - case MPP_UART: - if (mpp >= 16 && mpp <= 19) - return 0; - return -1; - } - - printk(KERN_INFO "unknown MPP type %d\n", type); - - return -1; -} - -void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode) -{ - u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL); - u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL); - u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL); - - for ( ; mode->mpp >= 0; mode++) { - u32 *reg; - int num_type; - int shift; - - if (mode->mpp >= 0 && mode->mpp <= 7) - reg = &mpp_0_7_ctrl; - else if (mode->mpp >= 8 && mode->mpp <= 15) - reg = &mpp_8_15_ctrl; - else if (mode->mpp >= 16 && mode->mpp <= 19) - reg = &mpp_16_19_ctrl; - else { - printk(KERN_ERR "orion5x_mpp_conf: invalid MPP " - "(%d)\n", mode->mpp); - continue; - } - - num_type = determine_type_encoding(mode->mpp, mode->type); - if (num_type < 0) { - printk(KERN_ERR "orion5x_mpp_conf: invalid MPP " - "combination (%d, %d)\n", mode->mpp, - mode->type); - continue; - } - - shift = (mode->mpp & 7) << 2; - *reg &= ~(0xf << shift); - *reg |= (num_type & 0xf) << shift; - - if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182())) - orion_gpio_set_unused(mode->mpp); - - orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); - } - - writel(mpp_0_7_ctrl, MPP_0_7_CTRL); - writel(mpp_8_15_ctrl, MPP_8_15_CTRL); - writel(mpp_16_19_ctrl, MPP_16_19_CTRL); + orion_mpp_conf(mpp_list, orion5x_variant(), + MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h index 290e610..eac6897 100644 --- a/arch/arm/mach-orion5x/mpp.h +++ b/arch/arm/mach-orion5x/mpp.h @@ -1,74 +1,129 @@ #ifndef __ARCH_ORION5X_MPP_H #define __ARCH_ORION5X_MPP_H -enum orion5x_mpp_type { - /* - * This MPP is unused. - */ - MPP_UNUSED, - - /* - * This MPP pin is used as a generic GPIO pin. Valid for - * MPPs 0-15 and device bus data pins 16-31. On 5182, also - * valid for MPPs 16-19. - */ - MPP_GPIO, - - /* - * This MPP is used as PCIe_RST_OUTn pin. Valid for - * MPP 0 only. - */ - MPP_PCIE_RST_OUTn, - - /* - * This MPP is used as PCI arbiter pin (REQn/GNTn). - * Valid for MPPs 0-7 only. - */ - MPP_PCI_ARB, - - /* - * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only. - */ - MPP_PCI_PMEn, - - /* - * This MPP is used as GigE half-duplex (COL, CRS) or GMII - * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for - * MPPs 8-19 only. - */ - MPP_GIGE, - - /* - * This MPP is used as NAND REn/WEn pin. Valid for MPPs - * 4-7 and 12-17 only, and only on the 5181l/5182/5281. - */ - MPP_NAND, - - /* - * This MPP is used as a PCI clock output pin. Valid for - * MPPs 6-7 only, and only on the 5181l. - */ - MPP_PCI_CLK, - - /* - * This MPP is used as a SATA presence/activity LED. - * Valid for MPPs 4-7 and 12-15 only, and only on the 5182. - */ - MPP_SATA_LED, - - /* - * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin. - * Valid for MPPs 16-19 only. - */ - MPP_UART, -}; - -struct orion5x_mpp_mode { - int mpp; - enum orion5x_mpp_type type; -}; - -void orion5x_mpp_conf(struct orion5x_mpp_mode *mode); +#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on F5181l */ ((!!(_F5181l)) << 14) | \ + /* available on F5182 */ ((!!(_F5182)) << 15) | \ + /* available on F5281 */ ((!!(_F5281)) << 16)) + /* num sel i o 5181 5182 5281 */ + +#define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0) +#define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0) +#define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1) + +#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1) +#define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1) +#define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1) +#define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1) + +#define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1) +#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1) +#define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1) + +#define MPP2_UNUSED MPP(2, 0x0, 0, 0, 1, 1, 1) +#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1, 1) +#define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1) +#define MPP2_PCI_PMEn MPP(2, 0x3, 0, 0, 1, 1, 1) + +#define MPP3_UNUSED MPP(3, 0x0, 0, 0, 1, 1, 1) +#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1, 1) +#define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1) + +#define MPP4_UNUSED MPP(4, 0x0, 0, 0, 1, 1, 1) +#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1, 1) +#define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1) +#define MPP4_NAND MPP(4, 0x4, 0, 0, 0, 1, 1) +#define MPP4_SATA_LED MPP(4, 0x5, 0, 0, 0, 1, 0) + +#define MPP5_UNUSED MPP(5, 0x0, 0, 0, 1, 1, 1) +#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1, 1) +#define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1) +#define MPP5_NAND MPP(5, 0x4, 0, 0, 0, 1, 1) +#define MPP5_SATA_LED MPP(5, 0x5, 0, 0, 0, 1, 0) + +#define MPP6_UNUSED MPP(6, 0x0, 0, 0, 1, 1, 1) +#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1, 1) +#define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1) +#define MPP6_NAND MPP(6, 0x4, 0, 0, 0, 1, 1) +#define MPP6_PCI_CLK MPP(6, 0x5, 0, 0, 1, 0, 0) +#define MPP6_SATA_LED MPP(6, 0x5, 0, 0, 0, 1, 0) + +#define MPP7_UNUSED MPP(7, 0x0, 0, 0, 1, 1, 1) +#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1, 1) +#define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1) +#define MPP7_NAND MPP(7, 0x4, 0, 0, 0, 1, 1) +#define MPP7_PCI_CLK MPP(7, 0x5, 0, 0, 1, 0, 0) +#define MPP7_SATA_LED MPP(7, 0x5, 0, 0, 0, 1, 0) + +#define MPP8_UNUSED MPP(8, 0x0, 0, 0, 1, 1, 1) +#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1, 1) +#define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1) + +#define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1) +#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1) +#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1) + +#define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1) +#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1) +#define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1) + +#define MPP11_UNUSED MPP(11, 0x0, 0, 0, 1, 1, 1) +#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1, 1) +#define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1) + +#define MPP12_UNUSED MPP(12, 0x0, 0, 0, 1, 1, 1) +#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1, 1) +#define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1) +#define MPP12_NAND MPP(12, 0x4, 0, 0, 0, 1, 1) +#define MPP12_SATA_LED MPP(12, 0x5, 0, 0, 0, 1, 0) + +#define MPP13_UNUSED MPP(13, 0x0, 0, 0, 1, 1, 1) +#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1, 1) +#define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1) +#define MPP13_NAND MPP(13, 0x4, 0, 0, 0, 1, 1) +#define MPP13_SATA_LED MPP(13, 0x5, 0, 0, 0, 1, 0) + +#define MPP14_UNUSED MPP(14, 0x0, 0, 0, 1, 1, 1) +#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1, 1) +#define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1) +#define MPP14_NAND MPP(14, 0x4, 0, 0, 0, 1, 1) +#define MPP14_SATA_LED MPP(14, 0x5, 0, 0, 0, 1, 0) + +#define MPP15_UNUSED MPP(15, 0x0, 0, 0, 1, 1, 1) +#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1, 1) +#define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1) +#define MPP15_NAND MPP(15, 0x4, 0, 0, 0, 1, 1) +#define MPP15_SATA_LED MPP(15, 0x5, 0, 0, 0, 1, 0) + +#define MPP16_UNUSED MPP(16, 0x0, 0, 0, 1, 1, 1) +#define MPP16_GPIO MPP(16, 0x5, 1, 1, 0, 1, 0) +#define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1) +#define MPP16_NAND MPP(16, 0x4, 0, 0, 0, 1, 1) +#define MPP16_UART MPP(16, 0x0, 0, 0, 0, 1, 1) + +#define MPP17_UNUSED MPP(17, 0x0, 0, 0, 1, 1, 1) +#define MPP17_GPIO MPP(17, 0x5, 1, 1, 0, 1, 0) +#define MPP17_GIGE MPP(17, 0x1, 0, 0, 1, 1, 1) +#define MPP17_NAND MPP(17, 0x4, 0, 0, 0, 1, 1) +#define MPP17_UART MPP(17, 0x0, 0, 0, 0, 1, 1) + +#define MPP18_UNUSED MPP(18, 0x0, 0, 0, 1, 1, 1) +#define MPP18_GPIO MPP(18, 0x5, 1, 1, 0, 1, 0) +#define MPP18_GIGE MPP(18, 0x1, 0, 0, 1, 1, 1) +#define MPP18_UART MPP(18, 0x0, 0, 0, 0, 1, 1) + +#define MPP19_UNUSED MPP(19, 0x0, 0, 0, 1, 1, 1) +#define MPP19_GPIO MPP(19, 0x5, 1, 1, 0, 1, 0) +#define MPP19_GIGE MPP(19, 0x1, 0, 0, 1, 1, 1) +#define MPP19_UART MPP(19, 0x0, 0, 0, 0, 1, 1) + +#define MPP_MAX 19 + +void orion5x_mpp_conf(unsigned int *mpp_list); #endif diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index b43b208..59263b7 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -193,28 +193,28 @@ static void mss2_power_off(void) /**************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Power LED */ - { 1, MPP_GPIO }, /* Error LED */ - { 2, MPP_UNUSED }, - { 3, MPP_GPIO }, /* RTC interrupt */ - { 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/ - { 5, MPP_GPIO }, /* HD0 5V control */ - { 6, MPP_GPIO }, /* HD0 12V control */ - { 7, MPP_GPIO }, /* HD1 5V control */ - { 8, MPP_GPIO }, /* HD1 12V control */ - { 9, MPP_UNUSED }, - { 10, MPP_GPIO }, /* Fan control */ - { 11, MPP_GPIO }, /* Power button */ - { 12, MPP_GPIO }, /* Reset button */ - { 13, MPP_UNUSED }, - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UNUSED }, - { 17, MPP_UNUSED }, - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int mss2_mpp_modes[] __initdata = { + MPP0_GPIO, /* Power LED */ + MPP1_GPIO, /* Error LED */ + MPP2_UNUSED, + MPP3_GPIO, /* RTC interrupt */ + MPP4_GPIO, /* HDD ind. (Single/Dual)*/ + MPP5_GPIO, /* HD0 5V control */ + MPP6_GPIO, /* HD0 12V control */ + MPP7_GPIO, /* HD1 5V control */ + MPP8_GPIO, /* HD1 12V control */ + MPP9_UNUSED, + MPP10_GPIO, /* Fan control */ + MPP11_GPIO, /* Power button */ + MPP12_GPIO, /* Reset button */ + MPP13_UNUSED, + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UNUSED, + MPP17_UNUSED, + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init mss2_init(void) diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index c55d071..63ff10c 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -108,28 +108,28 @@ static struct platform_device mv2120_button_device = { /**************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Sys status LED */ - { 1, MPP_GPIO }, /* Sys error LED */ - { 2, MPP_GPIO }, /* OverTemp interrupt */ - { 3, MPP_GPIO }, /* RTC interrupt */ - { 4, MPP_GPIO }, /* V_LED 5V */ - { 5, MPP_GPIO }, /* V_LED 3.3V */ - { 6, MPP_UNUSED }, - { 7, MPP_UNUSED }, - { 8, MPP_GPIO }, /* SATA 0 fail LED */ - { 9, MPP_GPIO }, /* SATA 1 fail LED */ - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UNUSED }, - { 17, MPP_GPIO }, /* Reset button */ - { 18, MPP_GPIO }, /* Power button */ - { 19, MPP_GPIO }, /* Power off */ - { -1 }, +static unsigned int mv2120_mpp_modes[] __initdata = { + MPP0_GPIO, /* Sys status LED */ + MPP1_GPIO, /* Sys error LED */ + MPP2_GPIO, /* OverTemp interrupt */ + MPP3_GPIO, /* RTC interrupt */ + MPP4_GPIO, /* V_LED 5V */ + MPP5_GPIO, /* V_LED 3.3V */ + MPP6_UNUSED, + MPP7_UNUSED, + MPP8_GPIO, /* SATA 0 fail LED */ + MPP9_GPIO, /* SATA 1 fail LED */ + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UNUSED, + MPP17_GPIO, /* Reset button */ + MPP18_GPIO, /* Power button */ + MPP19_GPIO, /* Power off */ + 0, }; static struct i2c_board_info __initdata mv2120_i2c_rtc = { diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index a5930f8..e43b39c 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -339,28 +339,28 @@ static struct platform_device net2big_gpio_buttons = { * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Raid mode (bit 0) */ - { 1, MPP_GPIO }, /* USB port 2 fuse (0 = Fail, 1 = Ok) */ - { 2, MPP_GPIO }, /* Raid mode (bit 1) */ - { 3, MPP_GPIO }, /* Board ID (bit 0) */ - { 4, MPP_GPIO }, /* Fan activity (0 = Off, 1 = On) */ - { 5, MPP_GPIO }, /* Fan fail detection */ - { 6, MPP_GPIO }, /* Red front LED (0 = Off, 1 = On) */ - { 7, MPP_GPIO }, /* Disable initial blinking on front LED */ - { 8, MPP_GPIO }, /* Rear power switch (on|auto) */ - { 9, MPP_GPIO }, /* Rear power switch (auto|off) */ - { 10, MPP_GPIO }, /* SATA 1 red LED (0 = Off, 1 = On) */ - { 11, MPP_GPIO }, /* SATA 0 red LED (0 = Off, 1 = On) */ - { 12, MPP_GPIO }, /* Board ID (bit 1) */ - { 13, MPP_GPIO }, /* SATA 1 blue LED blink control */ - { 14, MPP_SATA_LED }, - { 15, MPP_SATA_LED }, - { 16, MPP_GPIO }, /* Blue front LED control */ - { 17, MPP_GPIO }, /* SATA 0 blue LED blink control */ - { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ - { 19, MPP_GPIO }, /* SATA{0,1} power On/Off request */ - { -1 } +static unsigned int net2big_mpp_modes[] __initdata = { + MPP0_GPIO, /* Raid mode (bit 0) */ + MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */ + MPP2_GPIO, /* Raid mode (bit 1) */ + MPP3_GPIO, /* Board ID (bit 0) */ + MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */ + MPP5_GPIO, /* Fan fail detection */ + MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */ + MPP7_GPIO, /* Disable initial blinking on front LED */ + MPP8_GPIO, /* Rear power switch (on|auto) */ + MPP9_GPIO, /* Rear power switch (auto|off) */ + MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */ + MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */ + MPP12_GPIO, /* Board ID (bit 1) */ + MPP13_GPIO, /* SATA 1 blue LED blink control */ + MPP14_SATA_LED, + MPP15_SATA_LED, + MPP16_GPIO, /* Blue front LED control */ + MPP17_GPIO, /* SATA 0 blue LED blink control */ + MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */ + MPP19_GPIO, /* SATA{0,1} power On/Off request */ + 0, /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ /* 23: SATA 0 power status */ /* 24: Board power off */ diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 34310ab..9eec7c2 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -64,28 +64,28 @@ static struct platform_device rd88f5181l_fxo_nor_boot_flash = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */ - { 1, MPP_GPIO }, /* PCI_intA */ - { 2, MPP_GPIO }, /* Hard Reset / Factory Init*/ - { 3, MPP_GPIO }, /* FXS or DAA select */ - { 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */ - { 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */ - { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ - { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ - { 8, MPP_GPIO }, /* CardBus reset */ - { 9, MPP_GPIO }, /* GE_RXERR */ - { 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */ - { 11, MPP_GPIO }, /* Lifeline control */ - { 12, MPP_GIGE }, /* GE_TXD[4] */ - { 13, MPP_GIGE }, /* GE_TXD[5] */ - { 14, MPP_GIGE }, /* GE_TXD[6] */ - { 15, MPP_GIGE }, /* GE_TXD[7] */ - { 16, MPP_GIGE }, /* GE_RXD[4] */ - { 17, MPP_GIGE }, /* GE_RXD[5] */ - { 18, MPP_GIGE }, /* GE_RXD[6] */ - { 19, MPP_GIGE }, /* GE_RXD[7] */ - { -1 }, +static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = { + MPP0_GPIO, /* LED1 CardBus LED (front panel) */ + MPP1_GPIO, /* PCI_intA */ + MPP2_GPIO, /* Hard Reset / Factory Init*/ + MPP3_GPIO, /* FXS or DAA select */ + MPP4_GPIO, /* LED6 - phone LED (front panel) */ + MPP5_GPIO, /* LED5 - phone LED (front panel) */ + MPP6_PCI_CLK, /* CPU PCI refclk */ + MPP7_PCI_CLK, /* PCI/PCIe refclk */ + MPP8_GPIO, /* CardBus reset */ + MPP9_GPIO, /* GE_RXERR */ + MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */ + MPP11_GPIO, /* Lifeline control */ + MPP12_GIGE, /* GE_TXD[4] */ + MPP13_GIGE, /* GE_TXD[5] */ + MPP14_GIGE, /* GE_TXD[6] */ + MPP15_GIGE, /* GE_TXD[7] */ + MPP16_GIGE, /* GE_RXD[4] */ + MPP17_GIGE, /* GE_RXD[5] */ + MPP18_GIGE, /* GE_RXD[6] */ + MPP19_GIGE, /* GE_RXD[7] */ + 0, }; static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index c1f79fa..0cc90bbf 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -65,28 +65,28 @@ static struct platform_device rd88f5181l_ge_nor_boot_flash = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* LED1 */ - { 1, MPP_GPIO }, /* LED5 */ - { 2, MPP_GPIO }, /* LED4 */ - { 3, MPP_GPIO }, /* LED3 */ - { 4, MPP_GPIO }, /* PCI_intA */ - { 5, MPP_GPIO }, /* RTC interrupt */ - { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ - { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ - { 8, MPP_GPIO }, /* 88e6131 interrupt */ - { 9, MPP_GPIO }, /* GE_RXERR */ - { 10, MPP_GPIO }, /* PCI_intB */ - { 11, MPP_GPIO }, /* LED2 */ - { 12, MPP_GIGE }, /* GE_TXD[4] */ - { 13, MPP_GIGE }, /* GE_TXD[5] */ - { 14, MPP_GIGE }, /* GE_TXD[6] */ - { 15, MPP_GIGE }, /* GE_TXD[7] */ - { 16, MPP_GIGE }, /* GE_RXD[4] */ - { 17, MPP_GIGE }, /* GE_RXD[5] */ - { 18, MPP_GIGE }, /* GE_RXD[6] */ - { 19, MPP_GIGE }, /* GE_RXD[7] */ - { -1 }, +static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = { + MPP0_GPIO, /* LED1 */ + MPP1_GPIO, /* LED5 */ + MPP2_GPIO, /* LED4 */ + MPP3_GPIO, /* LED3 */ + MPP4_GPIO, /* PCI_intA */ + MPP5_GPIO, /* RTC interrupt */ + MPP6_PCI_CLK, /* CPU PCI refclk */ + MPP7_PCI_CLK, /* PCI/PCIe refclk */ + MPP8_GPIO, /* 88e6131 interrupt */ + MPP9_GPIO, /* GE_RXERR */ + MPP10_GPIO, /* PCI_intB */ + MPP11_GPIO, /* LED2 */ + MPP12_GIGE, /* GE_TXD[4] */ + MPP13_GIGE, /* GE_TXD[5] */ + MPP14_GIGE, /* GE_TXD[6] */ + MPP15_GIGE, /* GE_TXD[7] */ + MPP16_GIGE, /* GE_RXD[4] */ + MPP17_GIGE, /* GE_RXD[5] */ + MPP18_GIGE, /* GE_RXD[6] */ + MPP19_GIGE, /* GE_RXD[7] */ + 0, }; static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = { diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 4fc4677..48da39b 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -241,28 +241,28 @@ static struct mv_sata_platform_data rd88f5182_sata_data = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Debug Led */ - { 1, MPP_GPIO }, /* Reset Switch */ - { 2, MPP_UNUSED }, - { 3, MPP_GPIO }, /* RTC Int */ - { 4, MPP_GPIO }, - { 5, MPP_GPIO }, - { 6, MPP_GPIO }, /* PCI_intA */ - { 7, MPP_GPIO }, /* PCI_intB */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UNUSED }, - { 17, MPP_UNUSED }, - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int rd88f5182_mpp_modes[] __initdata = { + MPP0_GPIO, /* Debug Led */ + MPP1_GPIO, /* Reset Switch */ + MPP2_UNUSED, + MPP3_GPIO, /* RTC Int */ + MPP4_GPIO, + MPP5_GPIO, + MPP6_GPIO, /* PCI_intA */ + MPP7_GPIO, /* PCI_intB */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UNUSED, + MPP17_UNUSED, + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init rd88f5182_init(void) diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c index b080c69..ad2eba9 100644 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -27,7 +27,6 @@ #include #include #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = { .phy_addr = -1, diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 6160041..29ce826 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -295,28 +295,28 @@ static void tsp2_power_off(void) /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = { - { 0, MPP_PCIE_RST_OUTn }, - { 1, MPP_UNUSED }, - { 2, MPP_UNUSED }, - { 3, MPP_UNUSED }, - { 4, MPP_NAND }, /* BOOT NAND Flash REn */ - { 5, MPP_NAND }, /* BOOT NAND Flash WEn */ - { 6, MPP_NAND }, /* BOOT NAND Flash HREn[0] */ - { 7, MPP_NAND }, /* BOOT NAND Flash WEn[0] */ - { 8, MPP_GPIO }, /* MICON int */ - { 9, MPP_GPIO }, /* RTC int */ - { 10, MPP_UNUSED }, - { 11, MPP_GPIO }, /* PCI Int A */ - { 12, MPP_UNUSED }, - { 13, MPP_GPIO }, /* UPS on UART0 enable */ - { 14, MPP_GPIO }, /* UPS low battery detection */ - { 15, MPP_UNUSED }, - { 16, MPP_UART }, /* UART1 RXD */ - { 17, MPP_UART }, /* UART1 TXD */ - { 18, MPP_UART }, /* UART1 CTSn */ - { 19, MPP_UART }, /* UART1 RTSn */ - { -1 }, +static unsigned int tsp2_mpp_modes[] __initdata = { + MPP0_PCIE_RST_OUTn, + MPP1_UNUSED, + MPP2_UNUSED, + MPP3_UNUSED, + MPP4_NAND, /* BOOT NAND Flash REn */ + MPP5_NAND, /* BOOT NAND Flash WEn */ + MPP6_NAND, /* BOOT NAND Flash HREn[0] */ + MPP7_NAND, /* BOOT NAND Flash WEn[0] */ + MPP8_GPIO, /* MICON int */ + MPP9_GPIO, /* RTC int */ + MPP10_UNUSED, + MPP11_GPIO, /* PCI Int A */ + MPP12_UNUSED, + MPP13_GPIO, /* UPS on UART0 enable */ + MPP14_GPIO, /* UPS low battery detection */ + MPP15_UNUSED, + MPP16_UART, /* UART1 RXD */ + MPP17_UART, /* UART1 TXD */ + MPP18_UART, /* UART1 CTSn */ + MPP19_UART, /* UART1 RTSn */ + 0, }; static void __init tsp2_init(void) diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index e6d6449..47162fd 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -244,28 +244,28 @@ static struct mv_sata_platform_data qnap_ts209_sata_data = { * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_GPIO }, /* USB copy button */ - { 2, MPP_GPIO }, /* Load defaults button */ - { 3, MPP_GPIO }, /* GPIO RTC */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_GPIO }, /* PCI Int A */ - { 7, MPP_GPIO }, /* PCI Int B */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UART }, /* UART1 RXD */ - { 17, MPP_UART }, /* UART1 TXD */ - { 18, MPP_GPIO }, /* SW_RST */ - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int ts209_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_GPIO, /* USB copy button */ + MPP2_GPIO, /* Load defaults button */ + MPP3_GPIO, /* GPIO RTC */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_GPIO, /* PCI Int A */ + MPP7_GPIO, /* PCI Int B */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UART, /* UART1 RXD */ + MPP17_UART, /* UART1 TXD */ + MPP18_GPIO, /* SW_RST */ + MPP19_UNUSED, + 0, }; static void __init qnap_ts209_init(void) diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 9eac819..5aacc7a 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -242,28 +242,28 @@ static struct platform_device qnap_ts409_button_device = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_UNUSED }, - { 2, MPP_UNUSED }, - { 3, MPP_UNUSED }, - { 4, MPP_GPIO }, /* HDD 1 status */ - { 5, MPP_GPIO }, /* HDD 2 status */ - { 6, MPP_GPIO }, /* HDD 3 status */ - { 7, MPP_GPIO }, /* HDD 4 status */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_GPIO }, /* RTC int */ - { 11, MPP_UNUSED }, - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_GPIO }, /* SW_RST */ - { 15, MPP_GPIO }, /* USB copy button */ - { 16, MPP_UART }, /* UART1 RXD */ - { 17, MPP_UART }, /* UART1 TXD */ - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int ts409_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_UNUSED, + MPP2_UNUSED, + MPP3_UNUSED, + MPP4_GPIO, /* HDD 1 status */ + MPP5_GPIO, /* HDD 2 status */ + MPP6_GPIO, /* HDD 3 status */ + MPP7_GPIO, /* HDD 4 status */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_GPIO, /* RTC int */ + MPP11_UNUSED, + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_GPIO, /* SW_RST */ + MPP15_GPIO, /* USB copy button */ + MPP16_UART, /* UART1 RXD */ + MPP17_UART, /* UART1 TXD */ + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init qnap_ts409_init(void) diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index edb1dd2..6b7b541 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -557,27 +557,27 @@ static struct kobj_attribute ts78xx_fpga_attr = /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_GPIO }, /* JTAG Clock */ - { 2, MPP_GPIO }, /* JTAG Data In */ - { 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */ - { 4, MPP_GPIO }, /* JTAG Data Out */ - { 5, MPP_GPIO }, /* JTAG TMS */ - { 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */ - { 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_UNUSED }, - { 15, MPP_UNUSED }, - { 16, MPP_UART }, - { 17, MPP_UART }, - { 18, MPP_UART }, - { 19, MPP_UART }, +static unsigned int ts78xx_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_GPIO, /* JTAG Clock */ + MPP2_GPIO, /* JTAG Data In */ + MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */ + MPP4_GPIO, /* JTAG Data Out */ + MPP5_GPIO, /* JTAG TMS */ + MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */ + MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_UNUSED, + MPP15_UNUSED, + MPP16_UART, + MPP17_UART, + MPP18_UART, + MPP19_UART, /* * MPP[20] PCI Clock Out 1 * MPP[21] PCI Clock Out 0 @@ -586,7 +586,7 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { * MPP[24] Unused * MPP[25] Unused */ - { -1 }, + 0, }; static void __init ts78xx_init(void) diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 4e5216b..444a1c7 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -24,28 +24,28 @@ #include "common.h" #include "mpp.h" -static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Power LED green (0=on) */ - { 1, MPP_GPIO }, /* Reset Button (0=off) */ - { 2, MPP_GPIO }, /* Power LED blink (0=off) */ - { 3, MPP_GPIO }, /* WAN Status LED amber (0=off) */ - { 4, MPP_GPIO }, /* PCI int */ - { 5, MPP_GPIO }, /* ??? */ - { 6, MPP_GPIO }, /* ??? */ - { 7, MPP_GPIO }, /* ??? */ - { 8, MPP_UNUSED }, /* ??? */ - { 9, MPP_GIGE }, /* GE_RXERR */ - { 10, MPP_UNUSED }, /* ??? */ - { 11, MPP_UNUSED }, /* ??? */ - { 12, MPP_GIGE }, /* GE_TXD[4] */ - { 13, MPP_GIGE }, /* GE_TXD[5] */ - { 14, MPP_GIGE }, /* GE_TXD[6] */ - { 15, MPP_GIGE }, /* GE_TXD[7] */ - { 16, MPP_GIGE }, /* GE_RXD[4] */ - { 17, MPP_GIGE }, /* GE_RXD[5] */ - { 18, MPP_GIGE }, /* GE_RXD[6] */ - { 19, MPP_GIGE }, /* GE_RXD[7] */ - { -1 }, +static unsigned int wnr854t_mpp_modes[] __initdata = { + MPP0_GPIO, /* Power LED green (0=on) */ + MPP1_GPIO, /* Reset Button (0=off) */ + MPP2_GPIO, /* Power LED blink (0=off) */ + MPP3_GPIO, /* WAN Status LED amber (0=off) */ + MPP4_GPIO, /* PCI int */ + MPP5_GPIO, /* ??? */ + MPP6_GPIO, /* ??? */ + MPP7_GPIO, /* ??? */ + MPP8_UNUSED, /* ??? */ + MPP9_GIGE, /* GE_RXERR */ + MPP10_UNUSED, /* ??? */ + MPP11_UNUSED, /* ??? */ + MPP12_GIGE, /* GE_TXD[4] */ + MPP13_GIGE, /* GE_TXD[5] */ + MPP14_GIGE, /* GE_TXD[6] */ + MPP15_GIGE, /* GE_TXD[7] */ + MPP16_GIGE, /* GE_RXD[4] */ + MPP17_GIGE, /* GE_RXD[5] */ + MPP18_GIGE, /* GE_RXD[6] */ + MPP19_GIGE, /* GE_RXD[7] */ + 0, }; /* diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index fab79d0..d1952be 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -101,28 +101,28 @@ static struct platform_device wrt350n_v2_button_device = { /* * General setup */ -static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Power LED green (0=on) */ - { 1, MPP_GPIO }, /* Security LED (0=on) */ - { 2, MPP_GPIO }, /* Internal Button (0=on) */ - { 3, MPP_GPIO }, /* Reset Button (0=on) */ - { 4, MPP_GPIO }, /* PCI int */ - { 5, MPP_GPIO }, /* Power LED orange (0=on) */ - { 6, MPP_GPIO }, /* USB LED (0=on) */ - { 7, MPP_GPIO }, /* Wireless LED (0=on) */ - { 8, MPP_UNUSED }, /* ??? */ - { 9, MPP_GIGE }, /* GE_RXERR */ - { 10, MPP_UNUSED }, /* ??? */ - { 11, MPP_UNUSED }, /* ??? */ - { 12, MPP_GIGE }, /* GE_TXD[4] */ - { 13, MPP_GIGE }, /* GE_TXD[5] */ - { 14, MPP_GIGE }, /* GE_TXD[6] */ - { 15, MPP_GIGE }, /* GE_TXD[7] */ - { 16, MPP_GIGE }, /* GE_RXD[4] */ - { 17, MPP_GIGE }, /* GE_RXD[5] */ - { 18, MPP_GIGE }, /* GE_RXD[6] */ - { 19, MPP_GIGE }, /* GE_RXD[7] */ - { -1 }, +static unsigned int wrt350n_v2_mpp_modes[] __initdata = { + MPP0_GPIO, /* Power LED green (0=on) */ + MPP1_GPIO, /* Security LED (0=on) */ + MPP2_GPIO, /* Internal Button (0=on) */ + MPP3_GPIO, /* Reset Button (0=on) */ + MPP4_GPIO, /* PCI int */ + MPP5_GPIO, /* Power LED orange (0=on) */ + MPP6_GPIO, /* USB LED (0=on) */ + MPP7_GPIO, /* Wireless LED (0=on) */ + MPP8_UNUSED, /* ??? */ + MPP9_GIGE, /* GE_RXERR */ + MPP10_UNUSED, /* ??? */ + MPP11_UNUSED, /* ??? */ + MPP12_GIGE, /* GE_TXD[4] */ + MPP13_GIGE, /* GE_TXD[5] */ + MPP14_GIGE, /* GE_TXD[6] */ + MPP15_GIGE, /* GE_TXD[7] */ + MPP16_GIGE, /* GE_RXD[4] */ + MPP17_GIGE, /* GE_RXD[5] */ + MPP18_GIGE, /* GE_RXD[6] */ + MPP19_GIGE, /* GE_RXD[7] */ + 0, }; /* -- cgit v0.10.2 From 3cff484d4b264ff467a3b45c544cbbbab69f0bf8 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 15 May 2011 13:32:54 +0200 Subject: ARM: dove: Consolidate mpp code with platform mpp. Signed-off-by: Andrew Lunn Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index c66c763..51e0e41 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -11,24 +11,17 @@ #include #include #include - +#include #include - #include "mpp.h" -#define MPP_NR_REGS 4 -#define MPP_CTRL(i) ((i) == 3 ? \ - DOVE_MPP_CTRL4_VIRT_BASE : \ - DOVE_MPP_VIRT_BASE + (i) * 4) -#define PMU_SIG_REGS 2 -#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4) - struct dove_mpp_grp { int start; int end; }; -static struct dove_mpp_grp dove_mpp_grp[] = { +/* Map a group to a range of GPIO pins in that group */ +static const struct dove_mpp_grp dove_mpp_grp[] = { [MPP_24_39] = { .start = 24, .end = 39, @@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = { .end = 45, }, [MPP_46_51] = { - .start = 40, - .end = 45, + .start = 46, + .end = 51, }, [MPP_58_61] = { .start = 58, @@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = { }, }; +/* Enable gpio for a range of pins. mode should be a combination of + GPIO_OUTPUT_OK | GPIO_INPUT_OK */ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) { int i; @@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) orion_gpio_set_valid(i, gpio_mode); } +/* Dump all the extra MPP registers. The platform code will dump the + registers for pins 0-23. */ static void dove_mpp_dump_regs(void) { -#ifdef DEBUG - int i; + pr_debug("PMU_CTRL4_CTRL: %08x\n", + readl(DOVE_MPP_CTRL4_VIRT_BASE)); - pr_debug("MPP_CTRL regs:"); - for (i = 0; i < MPP_NR_REGS; i++) - printk(" %08x", readl(MPP_CTRL(i))); - printk("\n"); + pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", + readl(DOVE_PMU_MPP_GENERAL_CTRL)); - pr_debug("PMU_SIG_CTRL regs:"); - for (i = 0; i < PMU_SIG_REGS; i++) - printk(" %08x", readl(PMU_SIG_CTRL(i))); - printk("\n"); - - pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL)); pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); -#endif } static void dove_mpp_cfg_nfc(int sel) @@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel) static void dove_mpp_cfg_au1(int sel) { - u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); @@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel) writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); } -static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl) -{ - int start = dove_mpp_grp[num].start; - int end = dove_mpp_grp[num].end; - int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0; - - *mpp_ctrl &= ~(0x1 << num); - *mpp_ctrl |= sel << num; - - dove_mpp_gpio_mode(start, end, gpio_mode); -} - -void __init dove_mpp_conf(unsigned int *mpp_list) +/* Configure the group registers, enabling GPIO if sel indicates the + pin is to be used for GPIO */ +static void dove_mpp_conf_grp(unsigned int *mpp_grp_list) { - u32 mpp_ctrl[MPP_NR_REGS]; - u32 pmu_mpp_ctrl = 0; - u32 pmu_sig_ctrl[PMU_SIG_REGS]; - int i; - - for (i = 0; i < MPP_NR_REGS; i++) - mpp_ctrl[i] = readl(MPP_CTRL(i)); - - for (i = 0; i < PMU_SIG_REGS; i++) - pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i)); - - pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL); + u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + int gpio_mode; - dove_mpp_dump_regs(); - - for ( ; *mpp_list != MPP_END; mpp_list++) { - unsigned int num = MPP_NUM(*mpp_list); - unsigned int sel = MPP_SEL(*mpp_list); - int shift, gpio_mode; - - if (num > MPP_MAX) { - pr_err("dove: invalid MPP number (%u)\n", num); - continue; - } - - if (*mpp_list & MPP_NFC_MASK) { - dove_mpp_cfg_nfc(sel); - continue; - } + for ( ; *mpp_grp_list; mpp_grp_list++) { + unsigned int num = MPP_NUM(*mpp_grp_list); + unsigned int sel = MPP_SEL(*mpp_grp_list); - if (*mpp_list & MPP_AU1_MASK) { - dove_mpp_cfg_au1(sel); + if (num > MPP_GRP_MAX) { + pr_err("dove: invalid MPP GRP number (%u)\n", num); continue; } - if (*mpp_list & MPP_GRP_MASK) { - dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]); - continue; - } - - shift = (num & 7) << 2; - if (*mpp_list & MPP_PMU_MASK) { - pmu_mpp_ctrl |= (0x1 << num); - pmu_sig_ctrl[num / 8] &= ~(0xf << shift); - pmu_sig_ctrl[num / 8] |= 0xf << shift; - gpio_mode = 0; - } else { - mpp_ctrl[num / 8] &= ~(0xf << shift); - mpp_ctrl[num / 8] |= sel << shift; - gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK; - } + mpp_ctrl4 &= ~(0x1 << num); + mpp_ctrl4 |= sel << num; - orion_gpio_set_valid(num, gpio_mode); + gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0; + dove_mpp_gpio_mode(dove_mpp_grp[num].start, + dove_mpp_grp[num].end, gpio_mode); } + writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); +} - for (i = 0; i < MPP_NR_REGS; i++) - writel(mpp_ctrl[i], MPP_CTRL(i)); +/* Configure the various MPP pins on Dove */ +void __init dove_mpp_conf(unsigned int *mpp_list, + unsigned int *mpp_grp_list, + unsigned int grp_au1_52_57, + unsigned int grp_nfc_64_71) +{ + dove_mpp_dump_regs(); - for (i = 0; i < PMU_SIG_REGS; i++) - writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i)); + /* Use platform code for pins 0-23 */ + orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE); - writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL); + dove_mpp_conf_grp(mpp_grp_list); + dove_mpp_cfg_au1(grp_au1_52_57); + dove_mpp_cfg_nfc(grp_nfc_64_71); dove_mpp_dump_regs(); } diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h index 2a43ce4..fbec7c5 100644 --- a/arch/arm/mach-dove/mpp.h +++ b/arch/arm/mach-dove/mpp.h @@ -1,178 +1,150 @@ #ifndef __ARCH_DOVE_MPP_CODED_H #define __ARCH_DOVE_MPP_CODED_H -#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \ -/* MPP/group number */ ((_num) & 0xff) | \ -/* MPP select value */ (((_mode) & 0xf) << 8) | \ -/* MPP PMU */ ((!!(_pmu)) << 12) | \ -/* group flag */ ((!!(_grp)) << 13) | \ -/* AU1 flag */ ((!!(_au1)) << 14) | \ -/* NFCE flag */ ((!!(_nfc)) << 15)) - -#define MPP_MAX 71 - -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - -#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0) -#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0) -#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0) -#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1) - -#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1) - -#define MPP_PMU_DRIVE_0 0x1 -#define MPP_PMU_DRIVE_1 0x2 -#define MPP_PMU_SDI 0x3 -#define MPP_PMU_CPU_PWRDWN 0x4 -#define MPP_PMU_STBY_PWRDWN 0x5 -#define MPP_PMU_CORE_PWR_GOOD 0x8 -#define MPP_PMU_BAT_FAULT 0xa -#define MPP_PMU_EXT0_WU 0xb -#define MPP_PMU_EXT1_WU 0xc -#define MPP_PMU_EXT2_WU 0xd -#define MPP_PMU_BLINK 0xe -#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0) - -#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0) -#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0) -#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0) -#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1) - -#define MPP0_GPIO0 MPP_PIN(0, 0x0) -#define MPP0_UA2_RTSn MPP_PIN(0, 0x2) -#define MPP0_SDIO0_CD MPP_PIN(0, 0x3) -#define MPP0_LCD0_PWM MPP_PIN(0, 0xf) - -#define MPP1_GPIO1 MPP_PIN(1, 0x0) -#define MPP1_UA2_CTSn MPP_PIN(1, 0x2) -#define MPP1_SDIO0_WP MPP_PIN(1, 0x3) -#define MPP1_LCD1_PWM MPP_PIN(1, 0xf) - -#define MPP2_GPIO2 MPP_PIN(2, 0x0) -#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1) -#define MPP2_UA2_TXD MPP_PIN(2, 0x2) -#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3) -#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4) - -#define MPP3_GPIO3 MPP_PIN(3, 0x0) -#define MPP3_SATA_ACT MPP_PIN(3, 0x1) -#define MPP3_UA2_RXD MPP_PIN(3, 0x2) -#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3) -#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4) -#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf) - -#define MPP4_GPIO4 MPP_PIN(4, 0x0) -#define MPP4_UA3_RTSn MPP_PIN(4, 0x2) -#define MPP4_SDIO1_CD MPP_PIN(4, 0x3) -#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4) - -#define MPP5_GPIO5 MPP_PIN(5, 0x0) -#define MPP5_UA3_CTSn MPP_PIN(5, 0x2) -#define MPP5_SDIO1_WP MPP_PIN(5, 0x3) -#define MPP5_SPI_1_CS MPP_PIN(5, 0x4) - -#define MPP6_GPIO6 MPP_PIN(6, 0x0) -#define MPP6_UA3_TXD MPP_PIN(6, 0x2) -#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3) -#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4) - -#define MPP7_GPIO7 MPP_PIN(7, 0x0) -#define MPP7_UA3_RXD MPP_PIN(7, 0x2) -#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3) -#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4) - -#define MPP8_GPIO8 MPP_PIN(8, 0x0) -#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1) - -#define MPP9_GPIO9 MPP_PIN(9, 0x0) -#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5) - -#define MPP10_GPIO10 MPP_PIN(10, 0x0) -#define MPP10_SSP_SCLK MPP_PIN(10, 0x5) - -#define MPP11_GPIO11 MPP_PIN(11, 0x0) -#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1) -#define MPP11_SATA_ACT MPP_PIN(11, 0x2) -#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3) -#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4) -#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5) - -#define MPP12_GPIO12 MPP_PIN(12, 0x0) -#define MPP12_SATA_ACT MPP_PIN(12, 0x1) -#define MPP12_UA2_RTSn MPP_PIN(12, 0x2) -#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3) -#define MPP12_SDIO1_CD MPP_PIN(12, 0x4) - -#define MPP13_GPIO13 MPP_PIN(13, 0x0) -#define MPP13_UA2_CTSn MPP_PIN(13, 0x2) -#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3) -#define MPP13_SDIO1WP MPP_PIN(13, 0x4) -#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5) - -#define MPP14_GPIO14 MPP_PIN(14, 0x0) -#define MPP14_UA2_TXD MPP_PIN(14, 0x2) -#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4) -#define MPP14_SSP_RXD MPP_PIN(14, 0x5) - -#define MPP15_GPIO15 MPP_PIN(15, 0x0) -#define MPP15_UA2_RXD MPP_PIN(15, 0x2) -#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4) -#define MPP15_SSP_SFRM MPP_PIN(15, 0x5) - -#define MPP16_GPIO16 MPP_PIN(16, 0x0) -#define MPP16_UA3_RTSn MPP_PIN(16, 0x2) -#define MPP16_SDIO0_CD MPP_PIN(16, 0x3) -#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4) -#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5) - -#define MPP17_GPIO17 MPP_PIN(17, 0x0) -#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1) -#define MPP17_UA3_CTSn MPP_PIN(17, 0x2) -#define MPP17_SDIO0_WP MPP_PIN(17, 0x3) -#define MPP17_TW_SDA2 MPP_PIN(17, 0x4) -#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5) - -#define MPP18_GPIO18 MPP_PIN(18, 0x0) -#define MPP18_UA3_TXD MPP_PIN(18, 0x2) -#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3) -#define MPP18_LCD0_PWM MPP_PIN(18, 0x4) -#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5) - -#define MPP19_GPIO19 MPP_PIN(19, 0x0) -#define MPP19_UA3_RXD MPP_PIN(19, 0x2) -#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3) -#define MPP19_TW_SCK2 MPP_PIN(19, 0x4) - -#define MPP20_GPIO20 MPP_PIN(20, 0x0) -#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1) -#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2) -#define MPP20_SDIO1_CD MPP_PIN(20, 0x3) -#define MPP20_SDIO0_CD MPP_PIN(20, 0x5) -#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6) - -#define MPP21_GPIO21 MPP_PIN(21, 0x0) -#define MPP21_UA1_RTSn MPP_PIN(21, 0x1) -#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2) -#define MPP21_SDIO1_WP MPP_PIN(21, 0x3) -#define MPP21_SSP_SFRM MPP_PIN(21, 0x4) -#define MPP21_SDIO0_WP MPP_PIN(21, 0x5) -#define MPP21_SPI_1_CS MPP_PIN(21, 0x6) - -#define MPP22_GPIO22 MPP_PIN(22, 0x0) -#define MPP22_UA1_CTSn MPP_PIN(22, 0x1) -#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2) -#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3) -#define MPP22_SSP_TXD MPP_PIN(22, 0x4) -#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5) -#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6) - -#define MPP23_GPIO23 MPP_PIN(23, 0x0) -#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2) -#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3) -#define MPP23_SSP_SCLK MPP_PIN(23, 0x4) -#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5) -#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6) +#define MPP(_num, _sel, _in, _out) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13)) + +#define MPP0_GPIO0 MPP(0, 0x0, 1, 1) +#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0) +#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0) +#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0) + +#define MPP1_GPIO1 MPP(1, 0x0, 1, 1) +#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0) +#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0) +#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0) + +#define MPP2_GPIO2 MPP(2, 0x0, 1, 1) +#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0) +#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0) +#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0) +#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0) + +#define MPP3_GPIO3 MPP(3, 0x0, 1, 1) +#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0) +#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0) +#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0) +#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0) +#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0) + +#define MPP4_GPIO4 MPP(4, 0x0, 1, 1) +#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0) +#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0) +#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0) + +#define MPP5_GPIO5 MPP(5, 0x0, 1, 1) +#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0) +#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0) +#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0) + +#define MPP6_GPIO6 MPP(6, 0x0, 1, 1) +#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0) +#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0) +#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0) + +#define MPP7_GPIO7 MPP(7, 0x0, 1, 1) +#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0) +#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0) +#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0) + +#define MPP8_GPIO8 MPP(8, 0x0, 1, 1) +#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0) + +#define MPP9_GPIO9 MPP(9, 0x0, 1, 1) +#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0) + +#define MPP10_GPIO10 MPP(10, 0x0, 1, 1) +#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0) + +#define MPP11_GPIO11 MPP(11, 0x0, 1, 1) +#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0) +#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0) +#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0) +#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0) +#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0) + +#define MPP12_GPIO12 MPP(12, 0x0, 1, 1) +#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0) +#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0) +#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0) +#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0) + +#define MPP13_GPIO13 MPP(13, 0x0, 1, 1) +#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0) +#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0) +#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0) +#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0) + +#define MPP14_GPIO14 MPP(14, 0x0, 1, 1) +#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0) +#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0) +#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0) + +#define MPP15_GPIO15 MPP(15, 0x0, 1, 1) +#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0) +#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0) +#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0) + +#define MPP16_GPIO16 MPP(16, 0x0, 1, 1) +#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0) +#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0) +#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0) +#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0) + +#define MPP17_GPIO17 MPP(17, 0x0, 1, 1) +#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0) +#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0) +#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0) +#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0) +#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0) + +#define MPP18_GPIO18 MPP(18, 0x0, 1, 1) +#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0) +#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0) +#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0) +#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0) + +#define MPP19_GPIO19 MPP(19, 0x0, 1, 1) +#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0) +#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0) +#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0) + +#define MPP20_GPIO20 MPP(20, 0x0, 1, 1) +#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0) +#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0) +#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0) +#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0) +#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0) + +#define MPP21_GPIO21 MPP(21, 0x0, 1, 1) +#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0) +#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0) +#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0) +#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0) +#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0) +#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0) + +#define MPP22_GPIO22 MPP(22, 0x0, 1, 1) +#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0) +#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0) +#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0) +#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0) +#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0) +#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0) + +#define MPP23_GPIO23 MPP(23, 0x0, 1, 1) +#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0) +#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0) +#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0) +#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0) +#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0) + +#define MPP_MAX 23 + +#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0) /* for MPP groups _num is a group index */ enum dove_mpp_grp_idx { @@ -181,40 +153,44 @@ enum dove_mpp_grp_idx { MPP_46_51 = 1, MPP_58_61 = 5, MPP_62_63 = 4, + MPP_GRP_MAX = 5, }; -#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1) -#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0) +#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1) +#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0) -#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1) -#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0) +#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1) +#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0) -#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1) -#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0) +#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1) +#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0) -#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1) -#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0) +#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1) +#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0) -#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1) -#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0) +#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1) +#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0) /* The MPP[64:71] control differs from other groups */ -#define MPP64_71_GPO MPP_GRP_NFC(0x1) -#define MPP64_71_NFC MPP_GRP_NFC(0x0) +#define MPP_GRP_NFC_64_71_GPO 0x1 +#define MPP_GRP_NFC_64_71_NFC 0x0 /* * The MPP[52:57] functionality is encoded by 4 bits in different * registers. The _num field in this case encodes those bits in * correspodence with Table 135 of 88AP510 Functional specification */ -#define MPP52_57_AU1 MPP_GRP_AU1(0x0) -#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2) -#define MPP52_57_GPIO MPP_GRP_AU1(0xa) -#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb) -#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc) -#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe) -#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf) - -void dove_mpp_conf(unsigned int *mpp_list); +#define MPP_GRP_AU1_52_57_AU1 0x0 +#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2 +#define MPP_GRP_AU1_52_57_GPIO 0xa +#define MPP_GRP_AU1_52_57_TW_GPIO 0xb +#define MPP_GRP_AU1_52_57_AU1_SSP 0xc +#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe +#define MPP_GRP_AU1_52_57_SSP_TW 0xf + +void dove_mpp_conf(unsigned int *mpp_list, + unsigned int *mpp_grp_list, + unsigned int grp_au1_52_57, + unsigned int grp_nfc_64_71); #endif /* __ARCH_DOVE_MPP_CODED_H */ diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index 248c022..9155343 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -31,9 +31,6 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, u32 mpp_ctrl[mpp_nr_regs]; int i; - if (!variant_mask) - return; - printk(KERN_DEBUG "initial MPP regs:"); for (i = 0; i < mpp_nr_regs; i++) { mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus)); @@ -51,7 +48,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, "number (%u)\n", num); continue; } - if (!(*mpp_list & variant_mask)) { + if (variant_mask & !(*mpp_list & variant_mask)) { printk(KERN_WARNING "orion_mpp_conf: requested MPP%u config " "unavailable on this hardware\n", num); -- cgit v0.10.2 From 2d95378b043f082192a11f8476e3f63291c3477b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 25 Mar 2011 12:52:47 -0300 Subject: ARM: mx53: Print silicon revision on boot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having the silicon revision to appear on the boot log is a useful information. MX31, MX35 and MX51 already show the silicon revision on boot. Add support for displaying such information for MX53 as well. Tested on a mx53loco board, where it shows: CPU identified as i.MX53, silicon rev 2.0 Signed-off-by: Fabio Estevam LAKML-Reference: 1301068367-18937-1-git-send-email-fabio.estevam@freescale.com Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index fdbc05e..6b89c1b 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1563,6 +1563,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&iim_clk); mx53_revision(); clk_disable(&iim_clk); + mx53_display_revision(); /* Set SDHC parents to be PLL2 */ clk_set_parent(&esdhc1_clk, &pll2_sw_clk); diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 472bdfa..86f87da 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -166,6 +166,29 @@ int mx50_revision(void) } EXPORT_SYMBOL(mx50_revision); +void mx53_display_revision(void) +{ + int rev; + char *srev; + rev = mx53_revision(); + + switch (rev) { + case IMX_CHIP_REVISION_1_0: + srev = IMX_CHIP_REVISION_1_0_STRING; + break; + case IMX_CHIP_REVISION_2_0: + srev = IMX_CHIP_REVISION_2_0_STRING; + break; + case IMX_CHIP_REVISION_2_1: + srev = IMX_CHIP_REVISION_2_1_STRING; + break; + default: + srev = IMX_CHIP_REVISION_UNKNOWN_STRING; + } + printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev); +} +EXPORT_SYMBOL(mx53_display_revision); + static int __init post_cpu_init(void) { unsigned int reg; diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index a22ebe1..bfa1ffc 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -68,4 +68,5 @@ extern void mxc91231_arch_reset(int, const char *); extern void mxc91231_prepare_idle(void); extern void mx51_efikamx_reset(void); extern int mx53_revision(void); +extern int mx53_display_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index ace1786..9d2a1ef 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -337,17 +337,4 @@ #define MX53_INT_GPIO7_LOW 107 #define MX53_INT_GPIO7_HIGH 108 -/* silicon revisions specific to i.MX53 */ -#define MX53_CHIP_REV_1_0 0x10 -#define MX53_CHIP_REV_1_1 0x11 -#define MX53_CHIP_REV_1_2 0x12 -#define MX53_CHIP_REV_1_3 0x13 -#define MX53_CHIP_REV_2_0 0x20 -#define MX53_CHIP_REV_2_1 0x21 -#define MX53_CHIP_REV_2_2 0x22 -#define MX53_CHIP_REV_2_3 0x23 -#define MX53_CHIP_REV_3_0 0x30 -#define MX53_CHIP_REV_3_1 0x31 -#define MX53_CHIP_REV_3_2 0x32 - #endif /* ifndef __MACH_MX53_H__ */ -- cgit v0.10.2 From 6f9ec442a07701e0ef241854862fdf2540be1bdb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 17 Mar 2011 12:55:57 -0300 Subject: ARM: mx5/babbage: Use gpio_request_one in babbage_usbhub_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Current code inside babbage_usbhub_reset uses gpio_direction_output with initial value of the GPIO and also sets the GPIO value via gpio_set_value to the same level right after. This is not needed. By using gpio_request_one it is possible to set the direction and initial value in one shot. Signed-off-by: Fabio Estevam LAKML-Reference: 1300377359-23212-2-git-send-email-fabio.estevam@freescale.com Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index bea4e41..ab50aa9 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -208,18 +208,16 @@ static inline void babbage_usbhub_reset(void) { int ret; - /* Bring USB hub out of reset */ - ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7"); + /* Reset USB hub */ + ret = gpio_request_one(BABBAGE_USB_HUB_RESET, + GPIOF_OUT_INIT_LOW, "GPIO1_7"); if (ret) { printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret); return; } - gpio_direction_output(BABBAGE_USB_HUB_RESET, 0); - /* USB HUB RESET - De-assert USB HUB RESET_N */ - msleep(1); - gpio_set_value(BABBAGE_USB_HUB_RESET, 0); - msleep(1); + msleep(2); + /* Deassert reset */ gpio_set_value(BABBAGE_USB_HUB_RESET, 1); } -- cgit v0.10.2 From 9c97f66271a09dedfe26a145fceb74c6efd83571 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 26 Feb 2011 23:19:04 +0800 Subject: ARM: mach-imx: mx25_3ds: add write-protect and card-detect for SD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Shawn Guo LAKML-Reference: 1298733544-24659-1-git-send-email-shawn.guo@freescale.com Acked-by: Wolfram Sang [ukl: fixup conflict with ff86452 (ARM: mx25_3ds: Add I2C support) and drop #inclusion of ] Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index 06da438..378f433 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -103,6 +103,8 @@ static iomux_v3_cfg_t mx25pdk_pads[] = { MX25_PAD_SD1_DATA1__SD1_DATA1, MX25_PAD_SD1_DATA2__SD1_DATA2, MX25_PAD_SD1_DATA3__SD1_DATA3, + MX25_PAD_A14__GPIO_2_0, /* WriteProtect */ + MX25_PAD_A15__GPIO_2_1, /* CardDetect */ /* I2C1 */ MX25_PAD_I2C1_CLK__I2C1_CLK, @@ -208,6 +210,14 @@ static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = { .bitrate = 100000, }; +#define SD1_GPIO_WP IMX_GPIO_NR(2, 0) +#define SD1_GPIO_CD IMX_GPIO_NR(2, 1) + +static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = { + .wp_gpio = SD1_GPIO_WP, + .cd_gpio = SD1_GPIO_CD, +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, @@ -225,7 +235,7 @@ static void __init mx25pdk_init(void) imx25_add_fec(&mx25_fec_pdata); imx25_add_imx_keypad(&mx25pdk_keymap_data); - imx25_add_sdhci_esdhc_imx(0, NULL); + imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata); imx25_add_imx_i2c0(&mx25_3ds_i2c0_data); } -- cgit v0.10.2 From 5309498a56842d0acb723196b7bc57bfb9aee918 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 28 Feb 2011 18:04:33 +0100 Subject: ARM: imx: use imx_add_gpio_keys to register "gpio-keys" devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LAKML-Reference: 1302207841-12450-1-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 56b930a..4ac00e9 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -129,6 +129,7 @@ choice config MACH_EUKREA_MBIMXSD25_BASEBOARD bool "Eukrea MBIMXSD development board" + select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX_SSI help This adds board specific devices that can be found on Eukrea's @@ -254,6 +255,7 @@ config MACH_MX27_3DS config MACH_IMX27_VISSTRIM_M10 bool "Vista Silicon i.MX27 Visstrim_m10" select SOC_IMX27 + select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index 6269053..176e61b 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include