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authorSantan Kumar <santan.kumar@nxp.com>2017-04-13 10:01:09 (GMT)
committerYork Sun <york.sun@nxp.com>2017-04-24 16:02:46 (GMT)
commit99fe76d02313473f97892eab3e6fa564f1acfea4 (patch)
tree2a76a826c472049fc62c98ad09a0b6d80ca470eb
parent5d267ec67901d9e5fd6e535eec84bd9176501403 (diff)
downloadu-boot-99fe76d02313473f97892eab3e6fa564f1acfea4.tar.xz
armv8: ls2080ardb: Add phy number for serdes1 protocol 0x4b
Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
-rw-r--r--board/freescale/ls2080ardb/eth_ls2080rdb.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 799799c..ba584c8 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -62,6 +62,13 @@ int board_eth_init(bd_t *bis)
wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
break;
+ case 0x4B:
+ wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+
+ break;
default:
printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
srds_s1);