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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-08-10 06:00:20 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-23 04:12:21 (GMT) |
| commit | 75f98d57107a571de852d0d383833ac2b1bda0cd (patch) | |
| tree | 83c71ca2759098f662e8a57110eb0eef3dc9525d /README | |
| parent | 8e34f1023816f7b864a5dde8be10221892acb86f (diff) | |
| download | u-boot-75f98d57107a571de852d0d383833ac2b1bda0cd.tar.xz | |
armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters.
This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and
moves existing register space definaton of CCI-400 bus
from immap_lsch2 to fsl_immap, so that it can be used
for both chasis 2 and chasis 3.
"CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET
is introduced in Kconfig
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 9 |
1 files changed, 9 insertions, 0 deletions
@@ -312,6 +312,15 @@ Many of the options are named exactly as the corresponding Linux kernel configuration options. The intention is to make it easier to build a config tool - later. +- ARM Platform Bus Type(CCI): + CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which + provides full cache coherency between two clusters of multi-core + CPUs and I/O coherency for devices and I/O masters + + CONFIG_SYS_FSL_HAS_CCI400 + + Defined For SoC that has cache coherent interconnect + CCN-400 The following options need to be configured: |