diff options
author | Simon Glass <sjg@chromium.org> | 2017-04-06 18:47:05 (GMT) |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2017-04-13 13:40:57 (GMT) |
commit | f1683aa73c31db0a025e0254e6ce1ee7e56aad3e (patch) | |
tree | e60233acce1fb476d8d79cecd6252d50ed456b32 /arch/powerpc/cpu/ppc4xx | |
parent | 3eace37e5098c7f020a45a3672c062cd4ea199a0 (diff) | |
download | u-boot-f1683aa73c31db0a025e0254e6ce1ee7e56aad3e.tar.xz |
board_f: Rename initdram() to dram_init()
This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx')
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 10 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c | 8 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/sdram.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/spl_boot.c | 2 |
4 files changed, 12 insertions, 12 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 87fd5e6..ffc62a5 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -403,20 +403,20 @@ static unsigned char spd_read(uchar chip, uint addr) } /*-----------------------------------------------------------------------------+ - * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller. + * dram_init. Initializes the 440SP Memory Queue and DDR SDRAM controller. * Note: This routine runs from flash with a stack set up in the chip's * sram space. It is important that the routine does not require .sbss, .bss or * .data sections. It also cannot call routines that require these sections. *-----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- - * Function: initdram + * Function: dram_init * Description: Configures SDRAM memory banks for DDR operation. * Auto Memory Configuration option reads the DDR SDRAM EEPROMs * via the IIC bus and then configures the DDR SDRAM memory * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ -int initdram(void) +int dram_init(void) { unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE}; @@ -2855,13 +2855,13 @@ static void test(void) #else /* CONFIG_SPD_EEPROM */ /*----------------------------------------------------------------------------- - * Function: initdram + * Function: dram_init * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller. * The configuration is performed using static, compile- * time parameters. * Configures the PPC405EX(r) and PPC460EX/GT *---------------------------------------------------------------------------*/ -int initdram(void) +int dram_init(void) { unsigned long val; diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index 14d0fd9..c477853 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -987,20 +987,20 @@ static void program_ddr0_44(unsigned long dimm_ranks[], } /*-----------------------------------------------------------------------------+ - * initdram. Initializes the 440EPx/GPx DDR SDRAM controller. + * dram_init. Initializes the 440EPx/GPx DDR SDRAM controller. * Note: This routine runs from flash with a stack set up in the chip's * sram space. It is important that the routine does not require .sbss, .bss or * .data sections. It also cannot call routines that require these sections. *-----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- - * Function: initdram + * Function: dram_init * Description: Configures SDRAM memory banks for DDR operation. * Auto Memory Configuration option reads the DDR SDRAM EEPROMs * via the IIC bus and then configures the DDR SDRAM memory * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ -int initdram(void) +int dram_init(void) { unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned long dimm_ranks[MAXDIMMS]; @@ -1014,7 +1014,7 @@ int initdram(void) unsigned long cas_latency = 0; /* to quiet initialization warning */ unsigned long dram_size; - debug("\nEntering initdram()\n"); + debug("\nEntering dram_init()\n"); /*------------------------------------------------------------------ * Stop the DDR-SDRAM controller. diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c index a49bd69..c416bce 100644 --- a/arch/powerpc/cpu/ppc4xx/sdram.c +++ b/arch/powerpc/cpu/ppc4xx/sdram.c @@ -150,7 +150,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) /* * Autodetect onboard SDRAM on 405 platforms */ -int initdram(void) +int dram_init(void) { ulong speed; ulong sdtr1; @@ -353,7 +353,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) * so this should be extended for other future boards * using this routine! */ -int initdram(void) +int dram_init(void) { int i; int tr1_bank1; diff --git a/arch/powerpc/cpu/ppc4xx/spl_boot.c b/arch/powerpc/cpu/ppc4xx/spl_boot.c index f3aa46c..b30f169 100644 --- a/arch/powerpc/cpu/ppc4xx/spl_boot.c +++ b/arch/powerpc/cpu/ppc4xx/spl_boot.c @@ -26,7 +26,7 @@ void board_init_f(ulong bootflag) * First we need to initialize the SDRAM, so that the real * U-Boot or the OS (Linux) can be loaded */ - initdram(); + dram_init(); /* Clear bss */ memset(__bss_start, '\0', __bss_end - __bss_start); |