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| author | York Sun <yorksun@freescale.com> | 2013-09-16 19:49:31 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 23:15:17 (GMT) |
| commit | 133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a (patch) | |
| tree | 8310923265a2fd56d900bc4b973cfbb2f95dfc75 /arch/powerpc/include | |
| parent | e512c50bc9e3ef0bcf209620cabfc6ef35f22ff3 (diff) | |
| download | u-boot-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.tar.xz | |
powerpc/mpc85xx: Add workaround for erratum A006379
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.
Erratum A006379 applies to
T4240 rev 1.0
B4860 rev 1.0, 2.0
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_errata.h | 25 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 1 |
3 files changed, 28 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b51d383..946ea97 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -599,6 +599,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -624,6 +625,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h new file mode 100644 index 0000000..3cac2d4 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_FSL_ERRATA_H +#define _ASM_FSL_ERRATA_H + +#include <common.h> +#include <asm/processor.h> + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2)) + return true; + + return false; +} +#endif + +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 00f17b6..e516e07 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1671,6 +1671,7 @@ typedef struct cpc_corenet { #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 +#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ |