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| author | Bin Meng <bmeng.cn@gmail.com> | 2016-02-01 09:40:45 (GMT) |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-02-05 04:47:21 (GMT) |
| commit | 79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7 (patch) | |
| tree | 10b2756494ba0b3d3a0967f1ef82380689612e51 /arch/x86/dts/chromebook_link.dts | |
| parent | ec2af6f82d4ee07fa19877e2bb2e5c80d8d6962b (diff) | |
| download | u-boot-79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7.tar.xz | |
dm: pch: Add get_io_base op
On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/chromebook_link.dts')
0 files changed, 0 insertions, 0 deletions