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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-08-16 13:50:31 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-23 04:12:21 (GMT) |
| commit | 5ca57bcdc7573e39015ee181f19e9dcbbd72199c (patch) | |
| tree | a2c811fd9dc93cec96afbe6b4bbc4f990dc0beab /arch | |
| parent | aca7df320f4a01bea8c7cf045b274d83273ecf00 (diff) | |
| download | u-boot-5ca57bcdc7573e39015ee181f19e9dcbbd72199c.tar.xz | |
armv8: fsl-lsch3: Make CCN-504 related code conditional
LS2080 family has CCN-504 cache coherent interconnet.
Other SoCs from LSCH3 may have differnt interconnect like
LS1088.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 8 |
2 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index c44b2c3..2f8d9da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -72,6 +72,7 @@ config ARCH_LS2080A select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_CCN504 select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC select SYS_FSL_HAS_DDR4 @@ -289,6 +290,9 @@ config SYS_FSL_IFC_BANK_COUNT config SYS_FSL_HAS_CCI400 bool +config SYS_FSL_HAS_CCN504 + bool + config SYS_FSL_HAS_DP_DDR bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 619d9b7..e91be19 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -76,7 +76,7 @@ ENTRY(lowlevel_init) switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ 1: -#ifdef CONFIG_FSL_LSCH3 +#if defined (CONFIG_SYS_FSL_HAS_CCN504) /* Set Wuo bit for RN-I 20 */ #ifdef CONFIG_ARCH_LS2080A @@ -171,7 +171,7 @@ ENTRY(lowlevel_init) ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) ldr x1, =0x00FF000C bl ccn504_set_qos -#endif +#endif /* CONFIG_SYS_FSL_HAS_CCN504 */ #ifdef SMMU_BASE /* Set the SMMU page size in the sACR register */ @@ -338,7 +338,9 @@ get_svr: ldr x1, =FSL_LSCH3_SVR ldr w0, [x1] ret +#endif +#ifdef CONFIG_SYS_FSL_HAS_CCN504 hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 @@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache) mov lr, x29 ret ENDPROC(__asm_flush_l3_dcache) -#endif +#endif /* CONFIG_SYS_FSL_HAS_CCN504 */ #ifdef CONFIG_MP /* Keep literals not used by the secondary boot code outside it */ |