diff options
| author | Andy Yan <andy.yan@rock-chips.com> | 2017-06-01 10:00:55 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-06-07 13:29:25 (GMT) |
| commit | 2c1e11dd52e7d1db79b33e3e4c2fded573b70a9d (patch) | |
| tree | a9455228f9398503057b848850b5ec2303e99895 /include/configs | |
| parent | bae2f282a96e400a2bbcc8a545598289f36e1c32 (diff) | |
| download | u-boot-2c1e11dd52e7d1db79b33e3e4c2fded573b70a9d.tar.xz | |
rockchip: Add core Soc start-up code for rv1108
RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core
from Rockchip. It is designed for varies application scenario such
as car DVR, sports DV, secure camera and UAV camera.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/rv1108_common.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h new file mode 100644 index 0000000..52750cb --- /dev/null +++ b/include/configs/rv1108_common.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RV1108_COMMON_H +#define __CONFIG_RV1108_COMMON_H + +#include <asm/arch/hardware.h> +#include "rockchip-common.h" + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +/* TIMER1,initialized by ddr initialize code */ +#define CONFIG_SYS_TIMER_BASE 0x10350020 +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) + +#endif |