diff options
Diffstat (limited to 'arch')
30 files changed, 452 insertions, 178 deletions
diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index 93c9085..257fc7f 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -6,5 +6,5 @@ # extra-y := start.o -obj-y += cpu.o cache.o +obj-y += cpu.o cache.o mpu.o obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c index 162cfe3..e8f8642 100644 --- a/arch/arm/cpu/armv7m/cache.c +++ b/arch/arm/cpu/armv7m/cache.c @@ -253,6 +253,21 @@ void flush_dcache_range(unsigned long start, unsigned long stop) return; } } +void flush_dcache_all(void) +{ + if (action_dcache_all(FLUSH_SET_WAY)) { + printf("ERR: D-cache not flushed\n"); + return; + } +} + +void invalidate_dcache_all(void) +{ + if (action_dcache_all(INVALIDATE_SET_WAY)) { + printf("ERR: D-cache not invalidated\n"); + return; + } +} #else void dcache_enable(void) { @@ -268,6 +283,14 @@ int dcache_status(void) { return 0; } + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_all(void) +{ +} #endif #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index 58cde93..a424bab 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -18,6 +18,25 @@ */ int cleanup_before_linux(void) { + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * disable interrupt and turn off caches etc ... + */ + disable_interrupts(); + /* + * turn off D-cache + * dcache_disable() in turn flushes the d-cache + * MPU is still enabled & can't be disabled as the u-boot + * code might be running in sdram which by default is not + * executable area. + */ + dcache_disable(); + /* invalidate to make sure no cache line gets dirty between + * dcache flushing and disabling dcache */ + invalidate_dcache_all(); + return 0; } diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c new file mode 100644 index 0000000..31a243b --- /dev/null +++ b/arch/arm/cpu/armv7m/mpu.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/bitops.h> +#include <asm/armv7m.h> +#include <asm/armv7m_mpu.h> +#include <asm/io.h> + +#define V7M_MPU_CTRL_ENABLE (1 << 0) +#define V7M_MPU_CTRL_DISABLE (0 << 0) +#define V7M_MPU_CTRL_HFNMIENA (1 << 1) +#define VALID_REGION (1 << 4) + +#define ENABLE_REGION (1 << 0) + +#define AP_SHIFT 24 +#define XN_SHIFT 28 +#define TEX_SHIFT 19 +#define S_SHIFT 18 +#define C_SHIFT 17 +#define B_SHIFT 16 +#define REGION_SIZE_SHIFT 1 + +#define CACHEABLE (1 << C_SHIFT) +#define BUFFERABLE (1 << B_SHIFT) +#define SHAREABLE (1 << S_SHIFT) + +void disable_mpu(void) +{ + writel(0, &V7M_MPU->ctrl); +} + +void enable_mpu(void) +{ + writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + + /* Make sure new mpu config is effective for next memory access */ + dsb(); + isb(); /* Make sure instruction stream sees it */ +} + +void mpu_config(struct mpu_region_config *reg_config) +{ + uint32_t attr; + + switch (reg_config->mr_attr) { + case STRONG_ORDER: + attr = SHAREABLE; + break; + case SHARED_WRITE_BUFFERED: + attr = BUFFERABLE; + break; + case O_I_WT_NO_WR_ALLOC: + attr = CACHEABLE; + break; + case O_I_WB_NO_WR_ALLOC: + attr = CACHEABLE | BUFFERABLE; + break; + case O_I_NON_CACHEABLE: + attr = 1 << TEX_SHIFT; + break; + case O_I_WB_RD_WR_ALLOC: + attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; + break; + case DEVICE_NON_SHARED: + attr = (2 << TEX_SHIFT) | BUFFERABLE; + default: + attr = 0; /* strongly ordered */ + break; + }; + + writel(reg_config->start_addr | VALID_REGION | reg_config->region_no, + &V7M_MPU->rbar); + + writel(reg_config->xn << XN_SHIFT | reg_config->ap << AP_SHIFT | attr + | reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION + , &V7M_MPU->rasr); +} diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index f1deaa7..7cba308 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -138,6 +138,30 @@ ENTRY(__asm_flush_dcache_range) dsb sy ret ENDPROC(__asm_flush_dcache_range) +/* + * void __asm_invalidate_dcache_range(start, end) + * + * invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +ENTRY(__asm_invalidate_dcache_range) + mrs x3, ctr_el0 + ubfm x3, x3, #16, #19 + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc ivac, x0 /* invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__asm_invalidate_dcache_range) /* * void __asm_invalidate_icache_all(void) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index bd1c3e0..adc7e17 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -446,7 +446,7 @@ inline void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - __asm_flush_dcache_range(start, stop); + __asm_invalidate_dcache_range(start, stop); } /* diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index cd92b2c..a2dda33 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -43,7 +43,7 @@ unsigned long timer_read_counter(void) return cntpct; } -unsigned long long get_ticks(void) +uint64_t get_ticks(void) { unsigned long ticks = timer_read_counter(); diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index acf3fd5..19ccf5c 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -12,6 +12,7 @@ #define _CLOCKS_H_ #include <asm/arch/clocks_am33xx.h> +#include <asm/arch/hardware.h> #ifdef CONFIG_TI81XX #include <asm/arch/clock_ti81xx.h> @@ -103,6 +104,12 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; +extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; +extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ]; extern struct cm_wkuppll *const cmwkup; diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 4c9352a..653ec1b 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -16,14 +16,9 @@ #define MPUPLL_M_800 800 #define MPUPLL_M_720 720 #define MPUPLL_M_600 600 -#define MPUPLL_M_550 550 +#define MPUPLL_M_500 500 #define MPUPLL_M_300 300 -/* MAIN PLL Fdll = 550 MHz, by default */ -#ifndef CONFIG_SYS_MPUCLK -#define CONFIG_SYS_MPUCLK MPUPLL_M_550 -#endif - #define UART_RESET (0x1 << 1) #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) @@ -31,6 +26,8 @@ #define CM_DLL_CTRL_NO_OVERRIDE 0x0 #define CM_DLL_READYST 0x4 +#define NUM_OPPS 6 + extern void enable_dmm_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 54f449f..8cae291 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -49,6 +49,14 @@ #define TI81XX 0xB81E #define DEVICE_ID (CTRL_BASE + 0x0600) #define DEVICE_ID_MASK 0x1FFF +#define PACKAGE_TYPE_SHIFT 16 +#define PACKAGE_TYPE_MASK (3 << 16) + +/* Package Type */ +#define PACKAGE_TYPE_UNDEFINED 0x0 +#define PACKAGE_TYPE_ZCZ 0x1 +#define PACKAGE_TYPE_ZCE 0x2 +#define PACKAGE_TYPE_RESERVED 0x3 /* MPU max frequencies */ #define AM335X_ZCZ_300 0x1FEF diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index dd950e5..3437e61 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -61,5 +61,18 @@ /* CPSW Config space */ #define CPSW_BASE 0x4A100000 +/* Control status register */ +#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 +#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) +#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 +#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) +#define CTRL_SYSBOOT_15_14_SHIFT 22 + +#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 +#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 + +#define NUM_CRYSTAL_FREQ 0x4 + int clk_get(int clk); #endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index a7da6b5..af69ac6 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -85,19 +85,6 @@ #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) #define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) -/* Control status register */ -#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) -#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 -#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) -#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 -#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) -#define CTRL_SYSBOOT_15_14_SHIFT 22 - -#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 -#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 - -#define NUM_CRYSTAL_FREQ 0x4 - /* EDMA3 Base Address */ #define EDMA3_BASE 0x49000000 diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 903398f..4e78aaf 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -46,3 +46,4 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); void enable_usb_clocks(int index); void disable_usb_clocks(int index); void do_board_detect(void); +u32 get_sys_clk_index(void); diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index ebf0f17..af8a97e 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -70,24 +70,5 @@ struct v7m_mpu { }; #define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE) -#define V7M_MPU_CTRL_ENABLE (1 << 0) -#define V7M_MPU_CTRL_HFNMIENA (1 << 1) - -#define V7M_MPU_CTRL_ENABLE (1 << 0) -#define V7M_MPU_CTRL_DISABLE (0 << 0) -#define V7M_MPU_CTRL_HFNMIENA (1 << 1) - -#define V7M_MPU_RASR_EN (1 << 0) -#define V7M_MPU_RASR_SIZE_BITS 1 -#define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS) -#define V7M_MPU_RASR_SIZE_8MB (24 << V7M_MPU_RASR_SIZE_BITS) -#define V7M_MPU_RASR_TEX_SHIFT 19 -#define V7M_MPU_RASR_S_SHIFT 18 -#define V7M_MPU_RASR_C_SHIFT 17 -#define V7M_MPU_RASR_B_SHIFT 16 -#define V7M_MPU_RASR_AP_RW_RW (3 << 24) -#define V7M_MPU_RASR_XN_ENABLE (0 << 28) -#define V7M_MPU_RASR_XN_DISABLE (1 << 28) - #endif /* !defined(__ASSEMBLY__) */ #endif /* ARMV7M_H */ diff --git a/arch/arm/include/asm/armv7m_mpu.h b/arch/arm/include/asm/armv7m_mpu.h new file mode 100644 index 0000000..d7e99b4 --- /dev/null +++ b/arch/arm/include/asm/armv7m_mpu.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +enum region_number { + REGION_0 = 0, + REGION_1, + REGION_2, + REGION_3, + REGION_4, + REGION_5, + REGION_6, + REGION_7, +}; + +enum ap { + NO_ACCESS = 0, + PRIV_RW_USR_NO, + PRIV_RW_USR_RO, + PRIV_RW_USR_RW, + UNPREDICTABLE, + PRIV_RO_USR_NO, + PRIV_RO_USR_RO, +}; + +enum mr_attr { + STRONG_ORDER = 0, + SHARED_WRITE_BUFFERED, + O_I_WT_NO_WR_ALLOC, + O_I_WB_NO_WR_ALLOC, + O_I_NON_CACHEABLE, + O_I_WB_RD_WR_ALLOC, + DEVICE_NON_SHARED, +}; +enum size { + REGION_8MB = 22, + REGION_16MB, + REGION_32MB, + REGION_64MB, + REGION_128MB, + REGION_256MB, + REGION_512MB, + REGION_1GB, + REGION_2GB, + REGION_4GB, +}; + +enum xn { + XN_DIS = 0, + XN_EN, +}; + +struct mpu_region_config { + uint32_t start_addr; + enum region_number region_no; + enum xn xn; + enum ap ap; + enum mr_attr mr_attr; + enum size reg_size; +}; + +void disable_mpu(void); +void enable_mpu(void); +void mpu_config(struct mpu_region_config *reg_config); diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 1aab629..3cc0e5f 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -32,8 +32,8 @@ struct arch_global_data { #endif /* "static data" needed by most of timer.c on ARM platforms */ unsigned long timer_rate_hz; - unsigned long tbu; - unsigned long tbl; + unsigned int tbu; + unsigned int tbl; unsigned long lastinc; unsigned long long timer_reset_value; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 93e003a..f6eb51e 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -25,6 +25,8 @@ #ifndef OMAP_MMC_H_ #define OMAP_MMC_H_ +#include <mmc.h> + struct hsmmc { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ @@ -49,6 +51,13 @@ struct hsmmc { unsigned int capa; /* 0x140 */ }; +struct omap_hsmmc_plat { + struct mmc_config cfg; + struct hsmmc *base_addr; + struct mmc mmc; + bool cd_inverted; +}; + /* * OMAP HS MMC Bit definitions */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9c3261c..79bd19a 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -180,6 +180,21 @@ static inline unsigned long read_mpidr(void) void __asm_flush_dcache_all(void); void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); + +/** + * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses + * + * This performance an invalidate from @start to @end - 1. Both addresses + * should be cache-aligned, otherwise this function will align the start + * address and may continue past the end address. + * + * Data in the address range is evicted from the cache and is not written back + * to memory. + * + * @start: Start address to invalidate + * @end: End address to invalidate up to (exclusive) + */ +void __asm_invalidate_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); int __asm_invalidate_l3_dcache(void); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 6e96cfb..53d4ed2 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o else obj-$(CONFIG_SPL_FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o +obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o endif obj-$(CONFIG_$(SPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_)USE_ARCH_MEMCPY) += memcpy.o diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index d84789c..eaa817b 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -27,8 +27,10 @@ DECLARE_GLOBAL_DATA_PTR; int arch_fixup_fdt(void *blob) { + int ret = 0; +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT) bd_t *bd = gd->bd; - int bank, ret; + int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -42,9 +44,11 @@ int arch_fixup_fdt(void *blob) #endif } +#ifdef CONFIG_OF_LIBFDT ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); if (ret) return ret; +#endif #ifdef CONFIG_ARMV8_SPIN_TABLE ret = spin_table_update_dt(blob); @@ -58,6 +62,7 @@ int arch_fixup_fdt(void *blob) if (ret) return ret; #endif +#endif return 0; } diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 6d8c3e4..408b62c 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -135,6 +135,7 @@ config AM43XX config AM33XX bool "AM33XX SoC" imply SYS_THUMB_BUILD + imply USE_TINY_PRINTF help Support for AM335x SOC from Texas Instruments. The AM335x high performance SOC features a Cortex-A8 @@ -147,6 +148,11 @@ config TARGET_CM_T43 endchoice +config SYS_MPUCLK + int "MPU CLK speed" + default 500 + help + Defines the MPU clock speed (in MHz). config TI_SECURE_DEVICE bool "HS Device Type Support" diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index db3c70f..5c4168f 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -29,6 +29,11 @@ config TARGET_AM335X_EVM imply SPL_SERIAL_SUPPORT imply SPL_WATCHDOG_SUPPORT imply SPL_YMODEM_SUPPORT + imply SPL_SYS_MALLOC_SIMPLE + imply SPL_SEPARATE_BSS + imply SPL_DM + imply SPL_DM_SEQ_ALIAS + imply SPL_OF_LIBFDT help This option specifies support for the AM335x GP and HS EVM development platforms. The AM335x diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 2bfc864..a8b5d13 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -10,6 +10,7 @@ #include <common.h> #include <dm.h> +#include <debug_uart.h> #include <errno.h> #include <ns16550.h> #include <spl.h> @@ -242,8 +243,6 @@ int board_early_init_f(void) */ __weak void am33xx_spl_board_init(void) { - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); } #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) @@ -312,6 +311,9 @@ void early_system_init(void) set_uart_mux_conf(); setup_early_clocks(); uart_soft_reset(); +#ifdef CONFIG_DEBUG_UART_OMAP + debug_uart_init(); +#endif #ifdef CONFIG_TI_I2C_BOARD_DETECT do_board_detect(); #endif @@ -327,6 +329,10 @@ void board_init_f(ulong dummy) early_system_init(); board_early_init_f(); sdram_init(); + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); } #endif diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index 7b841b2..1780bbd 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> #include <asm/io.h> @@ -55,26 +56,94 @@ struct dpll_params dpll_mpu_opp100 = { CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; const struct dpll_params dpll_core_opp100 = { 1000, OSC-1, -1, -1, 10, 8, 4}; -const struct dpll_params dpll_mpu = { - MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { - 50, OSC-1, -1, -1, 1, 1, 1}; -const struct dpll_params dpll_per = { - 960, OSC-1, 5, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_mpu_params(void) + +const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ + {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ + {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ + {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */ + {30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */ + {100, 3, 1, -1, -1, -1, -1}, /* OPP TB */ + {125, 2, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */ + {144, 4, 1, -1, -1, -1, -1}, /* OPP 120 */ + {32, 0, 1, -1, -1, -1, -1}, /* OPP TB */ + {40, 0, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */ + {360, 12, 1, -1, -1, -1, -1}, /* OPP 120 */ + {400, 12, 1, -1, -1, -1, -1}, /* OPP TB */ + {500, 12, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = { + {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ + {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */ + {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */ + {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = { + {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ + {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ + {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = { + {505, 15, 2, -1, -1, -1, -1}, /*19.2*/ + {101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */ + {303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {303, 12, 2, -1, 4, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = { + {125, 5, 1, -1, -1, -1, -1}, /*19.2*/ + {50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */ + {16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */ + {200, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = { + {665, 47, 1, -1, -1, -1, -1}, /*19.2*/ + {133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */ + {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +}; + +__weak const struct dpll_params *get_dpll_mpu_params(void) { - return &dpll_mpu; + return &dpll_mpu_opp100; } const struct dpll_params *get_dpll_core_params(void) { - return &dpll_core; + int ind = get_sys_clk_index(); + + return &dpll_core_1000MHz[ind]; } const struct dpll_params *get_dpll_per_params(void) { - return &dpll_per; + int ind = get_sys_clk_index(); + + return &dpll_per_192MHz[ind]; } void setup_clocks_for_console(void) diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index e4fc461..564bae6 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -68,6 +68,24 @@ u32 get_sysboot_value(void) return readl(&cstat->statusreg) & SYSBOOT_MASK; } +u32 get_sys_clk_index(void) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + u32 ind = readl(&ctrl->statusreg); + +#ifdef CONFIG_AM43XX + u32 src; + src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; + if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ + return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> + CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); + else /* Value read from SYS BOOT pins */ +#endif + return ((ind & CTRL_SYSBOOT_15_14_MASK) >> + CTRL_SYSBOOT_15_14_SHIFT); +} + + #ifdef CONFIG_DISPLAY_CPUINFO static char *cpu_revs[] = { "1.0", @@ -132,13 +150,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev) sil_rev = readl(&cdev->deviceid) >> 28; - if (sil_rev == 1) - /* PG 2.0, efuse may not be set. */ - return MPUPLL_M_800; - else if (sil_rev >= 2) { + if (sil_rev == 0) { + /* No efuse in PG 1.0. Use max speed */ + return MPUPLL_M_720; + } else if (sil_rev >= 1) { /* Check what the efuse says our max speed is. */ - int efuse_arm_mpu_max_freq; + int efuse_arm_mpu_max_freq, package_type; efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma); + package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >> + PACKAGE_TYPE_SHIFT; + + /* PG 2.0, efuse may not be set. */ + if (package_type == PACKAGE_TYPE_UNDEFINED || package_type == + PACKAGE_TYPE_RESERVED) + return MPUPLL_M_800; + switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) { case AM335X_ZCZ_1000: return MPUPLL_M_1000; @@ -155,14 +181,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev) } } - /* PG 1.0 or otherwise unknown, use the PG1.0 max */ + /* unknown, use the PG1.0 max */ return MPUPLL_M_720; } int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) { - /* For PG2.1 and later, we have one set of values. */ - if (sil_rev >= 2) { + /* For PG2.0 and later, we have one set of values. */ + if (sil_rev >= 1) { switch (frequency) { case MPUPLL_M_1000: return TPS65910_OP_REG_SEL_1_3_2_5; @@ -171,12 +197,13 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) case MPUPLL_M_720: return TPS65910_OP_REG_SEL_1_2_0; case MPUPLL_M_600: + case MPUPLL_M_500: case MPUPLL_M_300: - return TPS65910_OP_REG_SEL_1_1_3; + return TPS65910_OP_REG_SEL_1_1_0; } } - /* Default to PG1.0/PG2.0 values. */ - return TPS65910_OP_REG_SEL_1_1_3; + /* Default to PG1.0 values. */ + return TPS65910_OP_REG_SEL_1_2_6; } #endif diff --git a/arch/arm/mach-omap2/am33xx/u-boot-spl.lds b/arch/arm/mach-omap2/am33xx/u-boot-spl.lds deleted file mode 100644 index 07cf267..0000000 --- a/arch/arm/mach-omap2/am33xx/u-boot-spl.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - *(.vectors) - arch/arm/cpu/armv7/start.o (.text) - *(.text*) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index f317293..c090442 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -12,6 +12,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <debug_uart.h> #include <spl.h> #include <asm/arch/sys_proto.h> #include <linux/sizes.h> @@ -159,6 +160,9 @@ void early_system_init(void) setup_early_clocks(); do_board_detect(); vcores_init(); +#ifdef CONFIG_DEBUG_UART_OMAP + debug_uart_init(); +#endif prcm_init(); } @@ -171,6 +175,7 @@ void board_init_f(ulong dummy) #endif /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); + gd->ram_size = omap_sdram_size(); } #endif diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 0522d65..7b8d0ee 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -17,13 +17,13 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0x20008000 -static struct rk3036_grf * const grf = (void *)GRF_BASE; #define DEBUG_UART_BASE 0x20068000 void board_init_f(ulong dummy) { #ifdef EARLY_DEBUG + struct rk3036_grf * const grf = (void *)GRF_BASE; /* * NOTE: sd card and debug uart use same iomux in rk3036, * so if you enable uart, diff --git a/arch/arm/mach-stm32/stm32f4/soc.c b/arch/arm/mach-stm32/stm32f4/soc.c index b5d06db..3f45a25 100644 --- a/arch/arm/mach-stm32/stm32f4/soc.c +++ b/arch/arm/mach-stm32/stm32f4/soc.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/armv7m.h> +#include <asm/armv7m_mpu.h> #include <asm/arch/stm32.h> u32 get_cpu_rev(void) @@ -17,17 +17,19 @@ u32 get_cpu_rev(void) int arch_cpu_init(void) { + struct mpu_region_config stm32_region_config[] = { + { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_4GB }, + }; configure_clocks(); - /* * Configure the memory protection unit (MPU) to allow full access to * the whole 4GB address space. */ - writel(0, &V7M_MPU->rnr); - writel(0, &V7M_MPU->rbar); - writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB - | V7M_MPU_RASR_EN), &V7M_MPU->rasr); - writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + disable_mpu(); + for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++) + mpu_config(&stm32_region_config[i]); + enable_mpu(); return 0; } diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c index 6f9704a..74a9350 100644 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ b/arch/arm/mach-stm32/stm32f7/soc.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/armv7m.h> +#include <asm/armv7m_mpu.h> #include <asm/arch/stm32.h> u32 get_cpu_rev(void) @@ -17,56 +17,27 @@ u32 get_cpu_rev(void) int arch_cpu_init(void) { - /* - * Configure the memory protection unit (MPU) - * 0x00000000 - 0xffffffff: Strong-order, Shareable - * 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable - */ + struct mpu_region_config stm32_region_config[] = { + { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_4GB }, - /* Disable MPU */ - writel(0, &V7M_MPU->ctrl); + { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_512MB }, - writel( - 0x00000000 /* address */ - | 1 << 4 /* VALID */ - | 0 << 0 /* REGION */ - , &V7M_MPU->rbar - ); + { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, + DEVICE_NON_SHARED, REGION_512MB }, - /* Strong-order, Shareable */ - /* TEX=000, S=1, C=0, B=0*/ - writel( - (V7M_MPU_RASR_XN_ENABLE - | V7M_MPU_RASR_AP_RW_RW - | 0x01 << V7M_MPU_RASR_S_SHIFT - | 0x00 << V7M_MPU_RASR_TEX_SHIFT - | V7M_MPU_RASR_SIZE_4GB - | V7M_MPU_RASR_EN) - , &V7M_MPU->rasr - ); + { 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, + DEVICE_NON_SHARED, REGION_512MB }, - writel( - 0xC0000000 /* address */ - | 1 << 4 /* VALID */ - | 1 << 0 /* REGION */ - , &V7M_MPU->rbar - ); + { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_512MB }, + }; - /* Normal, Outer and inner Non-cacheable */ - /* TEX=001, S=0, C=0, B=0*/ - writel( - (V7M_MPU_RASR_XN_ENABLE - | V7M_MPU_RASR_AP_RW_RW - | 0x01 << V7M_MPU_RASR_TEX_SHIFT - | 0x01 << V7M_MPU_RASR_B_SHIFT - | 0x01 << V7M_MPU_RASR_C_SHIFT - | V7M_MPU_RASR_SIZE_8MB - | V7M_MPU_RASR_EN) - , &V7M_MPU->rasr - ); - - /* Enable MPU */ - writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + disable_mpu(); + for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++) + mpu_config(&stm32_region_config[i]); + enable_mpu(); return 0; } |