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-rw-r--r--board/espt/lowlevel_init.S10
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c6
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c5
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c5
-rw-r--r--board/freescale/p1_p2_rdb/pci.c4
-rw-r--r--board/freescale/p2020ds/p2020ds.c6
-rw-r--r--board/renesas/sh7785lcr/lowlevel_init.S107
-rw-r--r--board/sbc8548/sbc8548.c4
-rw-r--r--board/sbc8641d/sbc8641d.c5
9 files changed, 64 insertions, 88 deletions
diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S
index 7d5d72e..7f0686c 100644
--- a/board/espt/lowlevel_init.S
+++ b/board/espt/lowlevel_init.S
@@ -72,15 +72,7 @@ lowlevel_init:
/* set DDR-SDRAM dummy read */
write32 MMSEL_A, MMSEL_D
- mov.l MMSEL_A, r0
- synco
- mov.l @r0, r1
- synco
-
- mov.l CS0_A, r0
- synco
- mov.l @r0, r1
- synco
+ write32 MMSEL_A, CS0_A
/* set DDR-SDRAM bus/endian etc */
write32 MIM_U_A, MIM_U_D
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 2b32234..933dd12 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -199,7 +199,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno, pcie_ep);
+ &pcie3_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
@@ -231,7 +231,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
@@ -251,7 +251,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 358148f..f42c316 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -127,11 +127,6 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- puts(" DDR: ");
- return dram_size;
-#endif
-
puts(" DDR: ");
return dram_size;
}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 1a08afa..c521527 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -74,11 +74,6 @@ initdram(int board_type)
dram_size = fixed_sdram();
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- puts(" DDR: ");
- return dram_size;
-#endif
-
puts(" DDR: ");
return dram_size;
}
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index 7736596..4c08f9e 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -71,7 +71,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
@@ -90,7 +90,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 9878fba..e38c014 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -227,7 +227,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
/*
* The workaround doesn't work on p2020 because the location
@@ -267,7 +267,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno, pcie_ep);
+ &pcie3_hose, first_free_busno);
} else {
printf(" PCIE3: disabled\n");
}
@@ -286,7 +286,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf(" PCIE1: disabled\n");
}
diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S
index 7faad95..40d9b08 100644
--- a/board/renesas/sh7785lcr/lowlevel_init.S
+++ b/board/renesas/sh7785lcr/lowlevel_init.S
@@ -178,60 +178,6 @@ lbsc_end:
.align 4
-/*------- LBSC -------*/
-MMSELR_A: .long 0xfc400020
-#if defined(CONFIG_SH_32BIT)
-MMSELR_D: .long 0xa5a50005
-#else
-MMSELR_D: .long 0xa5a50002
-#endif
-
-/*------- DBSC2 -------*/
-#define DBSC2_BASE 0xfe800000
-DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
-DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
-DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
-DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
-DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
-DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
-DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
-DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
-DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
-DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
-DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
-DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
-DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54
-DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
-DDR_DUMMY_ACCESS_A: .long 0x40000000
-
-DBSC2_DBCONF_D: .long 0x00630002
-DBSC2_DBTR0_D: .long 0x050b1f04
-DBSC2_DBTR1_D: .long 0x00040204
-DBSC2_DBTR2_D: .long 0x02100308
-DBSC2_DBFREQ_D1: .long 0x00000000
-DBSC2_DBFREQ_D2: .long 0x00000100
-DBSC2_DBDICODTOCD_D: .long 0x000f0907
-
-DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
-DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
-DBSC2_DBCMDCNT_D_REF: .long 0x00000004
-
-DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
-DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
-DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
-DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
-DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
-DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
-
-DBSC2_DBEN_D: .long 0x00000001
-
-DBSC2_DBPDCNT0_D3: .long 0x00000080
-DBSC2_DBRFCNT1_D: .long 0x00000926
-DBSC2_DBRFCNT2_D: .long 0x00fe00fe
-DBSC2_DBRFCNT0_D: .long 0x00010000
-
-WAIT_200US: .long 33333
-
/*------- GPIO -------*/
PACR_D: .long 0x0000
PBCR_D: .long 0x0000
@@ -291,6 +237,59 @@ PPUPR2_A: .long GPIO_BASE + 0x62
P1MSELR_A: .long GPIO_BASE + 0x80
P2MSELR_A: .long GPIO_BASE + 0x82
+MMSELR_A: .long 0xfc400020
+#if defined(CONFIG_SH_32BIT)
+MMSELR_D: .long 0xa5a50005
+#else
+MMSELR_D: .long 0xa5a50002
+#endif
+
+/*------- DBSC2 -------*/
+#define DBSC2_BASE 0xfe800000
+DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
+DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
+DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
+DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
+DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
+DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
+DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
+DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
+DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
+DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
+DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
+DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
+DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
+DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
+DDR_DUMMY_ACCESS_A: .long 0x40000000
+
+DBSC2_DBCONF_D: .long 0x00630002
+DBSC2_DBTR0_D: .long 0x050b1f04
+DBSC2_DBTR1_D: .long 0x00040204
+DBSC2_DBTR2_D: .long 0x02100308
+DBSC2_DBFREQ_D1: .long 0x00000000
+DBSC2_DBFREQ_D2: .long 0x00000100
+DBSC2_DBDICODTOCD_D:.long 0x000f0907
+
+DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
+DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
+DBSC2_DBCMDCNT_D_REF: .long 0x00000004
+
+DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
+DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
+DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
+DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
+DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
+DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
+
+DBSC2_DBEN_D: .long 0x00000001
+
+DBSC2_DBPDCNT0_D3: .long 0x00000080
+DBSC2_DBRFCNT1_D: .long 0x00000926
+DBSC2_DBRFCNT2_D: .long 0x00fe00fe
+DBSC2_DBRFCNT0_D: .long 0x00010000
+
+WAIT_200US: .long 33333
+
/*------- LBSC -------*/
PASCR_A: .long 0xff000070
PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 5e3e176..194f6ab 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -359,7 +359,7 @@ pci_init_board(void)
SET_STD_PCI_INFO(pci_info[num], 1);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pci1_hose, first_free_busno, 0);
+ &pci1_hose, first_free_busno);
} else {
printf (" PCI: disabled\n");
}
@@ -378,7 +378,7 @@ pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE at base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, 0);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE: disabled\n");
}
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index aabefa9..c4e9875 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -62,11 +62,6 @@ phys_size_t initdram (int board_type)
dram_size = fixed_sdram ();
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- puts (" DDR: ");
- return dram_size;
-#endif
-
puts (" DDR: ");
return dram_size;
}
generated by cgit v0.10.2 at 2024-11-20 11:32:45 (GMT)