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-rw-r--r--include/configs/apalis_imx6.h337
-rw-r--r--include/configs/colibri_imx6.h305
-rw-r--r--include/configs/colibri_vf.h7
-rw-r--r--include/configs/imx6qdl_icore.h14
-rw-r--r--include/configs/imx6qdl_icore_rqs.h135
-rw-r--r--include/configs/imx6ul_geam.h165
-rw-r--r--include/configs/liteboard.h171
-rw-r--r--include/configs/mx53cx9020.h198
-rw-r--r--include/configs/mx6_common.h3
-rw-r--r--include/configs/mx6sllevk.h152
-rw-r--r--include/configs/udoo_neo.h35
-rw-r--r--include/dt-bindings/clock/imx5-clock.h219
-rw-r--r--include/dt-bindings/clock/imx6sll-clock.h204
-rw-r--r--include/dt-bindings/clock/imx6ul-clock.h1
-rw-r--r--include/power/pfuze3000_pmic.h5
15 files changed, 1943 insertions, 8 deletions
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
new file mode 100644
index 0000000..d3af2da
--- /dev/null
+++ b/include/configs/apalis_imx6.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright 2013-2015 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex Apalis iMX6
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_SYS_THUMB_BUILD
+
+#undef CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
+
+#define CONFIG_MACH_TYPE 4886
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */
+#endif
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* Make the HW version stuff available in U-Boot env */
+#define CONFIG_VERSION_VARIABLE /* ver environment variable */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* OCOTP Configs */
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+
+#ifdef CONFIG_MX6Q
+#define CONFIG_CMD_SATA
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE 4096
+#define CONFIG_TFTP_TSIZE
+
+/* USB Configs */
+/* Host */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_KEYBOARD
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#endif /* CONFIG_USB_KEYBOARD */
+/* Client */
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_G_DNL_MANUFACTURER "Toradex"
+/* USB DFU */
+#define CONFIG_DFU_MMC
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_MXC_GPIO
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_CMD_BMP
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FLASH
+
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR 192.168.10.2
+#define CONFIG_NETMASK 255.255.255.0
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP 192.168.10.1
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DRIVE_SATA "sata "
+#else
+#define CONFIG_DRIVE_SATA
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_DRIVE_MMC "mmc "
+#else
+#define CONFIG_DRIVE_MMC
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
+
+#define DFU_ALT_EMMC_INFO \
+ "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "uImage fat 0 1;" \
+ "imx6q-colibri-eval-v3.dtb fat 0 1;" \
+ "imx6q-colibri-cam-eval-v3.dtb fat 0 1"
+
+#define EMMC_BOOTCMD \
+ "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "emmcboot=run setup; " \
+ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
+ "${vidargs}; echo Booting from internal eMMC chip...; " \
+ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x12000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "kernel_addr_r=0x11000000\0" \
+ "ramdisk_addr_r=0x12100000\0"
+
+#define NFS_BOOTCMD \
+ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
+ "nfsboot=run setup; " \
+ "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
+ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+ "run nfsdtbload; dhcp ${kernel_addr_r} " \
+ "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
+ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define SD_BOOTCMD \
+ "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "sdboot=run setup; " \
+ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
+ "${vidargs}; echo Booting from SD card; " \
+ "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define USB_BOOTCMD \
+ "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
+ "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+#define FDT_FILE "imx6q-apalis-eval.dtb"
+#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb"
+#else
+#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb"
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
+ "run nfsboot ; echo ; echo nfsboot failed ; " \
+ "usb start ;" \
+ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
+ "boot_file=uImage\0" \
+ "console=ttymxc0\0" \
+ "defargs=enable_wait_mode=off vmalloc=400M\0" \
+ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
+ EMMC_BOOTCMD \
+ "fdt_file=" FDT_FILE "\0" \
+ "fdt_fixup=;\0" \
+ MEM_LAYOUT_ENV_SETTINGS \
+ NFS_BOOTCMD \
+ SD_BOOTCMD \
+ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+ "flash_eth.img && source ${loadaddr}\0" \
+ "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
+ "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+ "source ${loadaddr}\0" \
+ "setup=setenv setupargs fec_mac=${ethaddr} " \
+ "consoleblank=0 no_console_suspend=1 console=tty1 " \
+ "console=${console},${baudrate}n8\0 " \
+ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
+ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+ "source ${loadaddr}\0" \
+ "splashpos=m,m\0" \
+ "vidargs=mxc_hdmi.only_cea=1 " \
+ "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \
+ "video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
+ "fbmem=32M\0 "
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 48
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
+ CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 1
+#endif
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#define CONFIG_CMD_TIME
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_CRC32_VERIFY
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
new file mode 100644
index 0000000..86ed4d2
--- /dev/null
+++ b/include/configs/colibri_imx6.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2013-2015 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex Colibri iMX6
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_SYS_THUMB_BUILD
+
+#undef CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */
+#endif
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* Make the HW version stuff available in U-Boot env */
+#define CONFIG_VERSION_VARIABLE /* ver environment variable */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* OCOTP Configs */
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE 16352
+#define CONFIG_TFTP_TSIZE
+
+/* USB Configs */
+/* Host */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_KEYBOARD
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#endif /* CONFIG_USB_KEYBOARD */
+/* Client */
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_G_DNL_MANUFACTURER "Toradex"
+/* USB DFU */
+#define CONFIG_DFU_MMC
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_MXC_GPIO
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_CMD_BMP
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FLASH
+
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR 192.168.10.2
+#define CONFIG_NETMASK 255.255.255.0
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP 192.168.10.1
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_DRIVE_MMC "mmc "
+#else
+#define CONFIG_DRIVE_MMC
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC
+
+#define DFU_ALT_EMMC_INFO \
+ "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "uImage fat 0 1;" \
+ "imx6q-colibri-eval-v3.dtb fat 0 1;" \
+ "imx6q-colibri-cam-eval-v3.dtb fat 0 1"
+
+#define EMMC_BOOTCMD \
+ "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "emmcboot=run setup; " \
+ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
+ "${vidargs}; echo Booting from internal eMMC chip...; " \
+ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x12000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "kernel_addr_r=0x11000000\0" \
+ "ramdisk_addr_r=0x12100000\0"
+
+#define NFS_BOOTCMD \
+ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
+ "nfsboot=run setup; " \
+ "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
+ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+ "run nfsdtbload; dhcp ${kernel_addr_r} " \
+ "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
+ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define SD_BOOTCMD \
+ "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "sdboot=run setup; " \
+ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
+ "${vidargs}; echo Booting from SD card; " \
+ "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define USB_BOOTCMD \
+ "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
+ "rootwait\0" \
+ "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
+ "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootm ${kernel_addr_r} ${dtbparam}\0" \
+ "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
+ "run nfsboot ; echo ; echo nfsboot failed ; " \
+ "usb start ;" \
+ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
+ "boot_file=uImage\0" \
+ "console=ttymxc0\0" \
+ "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
+ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
+ EMMC_BOOTCMD \
+ "fdt_file=" FDT_FILE "\0" \
+ "fdt_fixup=;\0" \
+ MEM_LAYOUT_ENV_SETTINGS \
+ NFS_BOOTCMD \
+ SD_BOOTCMD \
+ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+ "flash_eth.img && source ${loadaddr}\0" \
+ "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
+ "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+ "source ${loadaddr}\0" \
+ "setup=setenv setupargs fec_mac=${ethaddr} " \
+ "consoleblank=0 no_console_suspend=1 console=tty1 " \
+ "console=${console},${baudrate}n8\0 " \
+ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
+ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+ "source ${loadaddr}\0" \
+ "splashpos=m,m\0" \
+ "vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \
+ "video=mxcfb1:off fbmem=8M\0 "
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 48
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
+ CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 1
+#endif
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#define CONFIG_CMD_TIME
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_CRC32_VERIFY
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 47dea62..62131c7 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -97,7 +97,7 @@
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
"load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
"load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
@@ -106,7 +106,7 @@
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
"dhcp ${kernel_addr_r} && " \
"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
@@ -117,7 +117,7 @@
"ubi part ubi && " \
"ubi read ${kernel_addr_r} kernel && " \
"ubi read ${fdt_addr_r} dtb && " \
- "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
@@ -129,6 +129,7 @@
"kernel_file=zImage\0" \
"fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
"fdt_board=eval-v3\0" \
+ "fdt_fixup=;\0" \
"defargs=\0" \
"console=ttyLP0\0" \
"setup=setenv setupargs " \
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
index f8a1263..204e96e 100644
--- a/include/configs/imx6qdl_icore.h
+++ b/include/configs/imx6qdl_icore.h
@@ -37,6 +37,7 @@
/* Default environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
+ "splashpos=m,m\0" \
"image=zImage\0" \
"console=ttymxc3\0" \
"fdt_high=0xffffffff\0" \
@@ -149,6 +150,19 @@
# define CONFIG_PHY_SMSC
#endif
+/* Framebuffer */
+#ifdef CONFIG_VIDEO_IPUV3
+# define CONFIG_IPUV3_CLK 260000000
+# define CONFIG_IMX_VIDEO_SKIP
+
+# define CONFIG_SPLASH_SCREEN
+# define CONFIG_SPLASH_SCREEN_ALIGN
+# define CONFIG_BMP_16BPP
+# define CONFIG_VIDEO_BMP_RLE8
+# define CONFIG_VIDEO_LOGO
+# define CONFIG_VIDEO_BMP_LOGO
+#endif
+
/* SPL */
#ifdef CONFIG_SPL
# ifdef CONFIG_NAND_MXS
diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h
new file mode 100644
index 0000000..0121563
--- /dev/null
+++ b/include/configs/imx6qdl_icore_rqs.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam i.CoreM6 QDL RQS Starter Kits.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX6QLD_ICORE_RQS_CONFIG_H
+#define __IMX6QLD_ICORE_RQS_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+# define CONFIG_ENV_OFFSET 0x100000
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc3\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x18000000\0" \
+ "boot_fdt=try\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE UART4_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV 0
+# define CONFIG_SYS_FSL_USDHC_NUM 1
+# define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#endif
+
+/* Ethernet */
+#ifdef CONFIG_FEC_MXC
+# define CONFIG_FEC_MXC_PHYADDR 3
+# define CONFIG_FEC_XCV_TYPE RGMII
+
+# define CONFIG_MII
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_MICREL
+# define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# define CONFIG_SPL_MMC_SUPPORT
+# include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+# undef CONFIG_DM_GPIO
+# undef CONFIG_DM_MMC
+# endif
+#endif
+
+#endif /* __IMX6QLD_ICORE_RQS_CONFIG_H */
diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h
new file mode 100644
index 0000000..48b1120
--- /dev/null
+++ b/include/configs/imx6ul_geam.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam GEAM6UL Starter Kits.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX6UL_GEAM_CONFIG_H
+#define __IMX6UL_GEAM_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+# define CONFIG_ENV_OFFSET 0x100000
+/* Environment in NAND */
+# elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET 0x400000
+# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x87800000\0" \
+ "boot_fdt=try\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE UART1_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV 0
+# define CONFIG_SYS_FSL_USDHC_NUM 1
+# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#endif
+
+/* NAND */
+#ifdef CONFIG_NAND_MXS
+# define CONFIG_SYS_MAX_NAND_DEVICE 1
+# define CONFIG_SYS_NAND_BASE 0x40000000
+# define CONFIG_SYS_NAND_5_ADDR_CYCLE
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
+
+/* MTD device */
+# define CONFIG_MTD_DEVICE
+# define CONFIG_CMD_MTDPARTS
+# define CONFIG_MTD_PARTITIONS
+# define MTDIDS_DEFAULT "nand0=nand"
+# define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl),2m(uboot)," \
+ "1m(env),4m(kernel),1m(dtb),-(rootfs)"
+
+# define CONFIG_APBH_DMA
+# define CONFIG_APBH_DMA_BURST
+# define CONFIG_APBH_DMA_BURST8
+#endif
+
+/* Ethernet */
+#ifdef CONFIG_FEC_MXC
+# define CONFIG_FEC_MXC_PHYADDR 0
+# define CONFIG_FEC_XCV_TYPE RMII
+
+# define CONFIG_MII
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_SMSC
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# ifdef CONFIG_NAND_MXS
+# define CONFIG_SPL_NAND_SUPPORT
+# else
+# define CONFIG_SPL_MMC_SUPPORT
+# endif
+
+# include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+# undef CONFIG_DM_GPIO
+# undef CONFIG_DM_MMC
+# endif
+#endif
+
+#endif /* __IMX6UL_GEAM_CONFIG_H */
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
new file mode 100644
index 0000000..a55d767
--- /dev/null
+++ b/include/configs/liteboard.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * Configuration settings for the Grinn liteBoard (i.MX6UL).
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __LITEBOARD_CONFIG_H
+#define __LITEBOARD_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 0
+#define CONFIG_MMCROOT "/dev/mmcblk0p2"
+
+#define CONFIG_CMD_BMODE
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_ENET_DEV 0
+
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#endif
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
new file mode 100644
index 0000000..87c75d4
--- /dev/null
+++ b/include/configs/mx53cx9020.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Configuration settings for Beckhoff CX9020.
+ *
+ * Based on Freescale's Linux i.MX mx53loco.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MXC_UART_BASE UART2_BASE
+
+#define CONFIG_FPGA_COUNT 1
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+
+/* bootz: zImage/initrd.img support */
+#define CONFIG_DOS_PARTITION
+
+/* Eth Configs */
+#define CONFIG_MII
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_FEC_MXC_PHYADDR 0x1F
+
+/* USB Configs */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE 0x77800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr=0x71ff0000\0" \
+ "rdaddr=0x72000000\0" \
+ "console=ttymxc1,115200\0" \
+ "uenv=/boot/uEnv.txt\0" \
+ "optargs=\0" \
+ "cmdline=\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcrootfstype=ext4 rootwait fixrtc\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline}\0" \
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile};" \
+ "setenv rdsize ${filesize}\0" \
+ "loadfdt=echo loading ${fdt_path} ...;" \
+ "load mmc ${bootpart} ${fdt_addr} ${fdt_path}\0" \
+ "mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "echo Checking for: ${uenv} ...;" \
+ "setenv bootpart ${mmcdev}:${mmcpart};" \
+ "if test -e mmc ${bootpart} ${uenv}; then " \
+ "load mmc ${bootpart} ${loadaddr} ${uenv};" \
+ "env import -t ${loadaddr} ${filesize};" \
+ "echo Loaded environment from ${uenv};" \
+ "if test -n ${dtb}; then " \
+ "setenv fdt_file ${dtb};" \
+ "echo Using: dtb=${fdt_file} ...;" \
+ "fi;" \
+ "echo Checking for uname_r in ${uenv}...;" \
+ "if test -n ${uname_r}; then " \
+ "echo Running uname_boot ...;" \
+ "run uname_boot;" \
+ "fi;" \
+ "fi;" \
+ "fi;\0" \
+ "uname_boot="\
+ "setenv bootdir /boot; " \
+ "setenv bootfile vmlinuz-${uname_r}; " \
+ "setenv ccatfile /boot/ccat.rbf; " \
+ "echo loading CCAT firmware from ${ccatfile}; " \
+ "load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
+ "echo loading ${bootdir}/${bootfile} ...; " \
+ "run loadimage;" \
+ "setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \
+ "if test -e mmc ${bootpart} ${fdt_path}; then " \
+ "run loadfdt;" \
+ "else " \
+ "echo; echo unable to find ${fdt_file} ...;" \
+ "echo booting legacy ...;"\
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr}] ... ;" \
+ "bootz ${loadaddr}; " \
+ "fi;" \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} - ${fdt_addr}] ... ;" \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run mmcboot;"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x70000000
+#define CONFIG_SYS_MEMTEST_END 0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2 CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE (gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* Framebuffer and LCD */
+#define CONFIG_PREBOOT
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 200000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index d28654b..e79ec21 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -44,7 +44,8 @@
#define CONFIG_REVISION_TAG
/* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL))
#define CONFIG_LOADADDR 0x82000000
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x87800000
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
new file mode 100644
index 0000000..b9f25cf
--- /dev/null
+++ b/include/configs/mx6sllevk.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* I2C Configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "epdc_waveform=epdc_splash.bin\0" \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6sll-evk.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=1\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "usb start; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_2G
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */
+#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
+
+#define CONFIG_ENV_OFFSET (12 * SZ_64K)
+#define CONFIG_ENV_IS_IN_MMC
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index 81e0481..aec39db 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -27,13 +27,11 @@
/* Command definition */
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/
/* Linux only */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0,115200\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=undefined\0" \
@@ -41,7 +39,6 @@
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcrootfstype=ext4\0" \
- "mmcautodetect=no\0" \
"findfdt="\
"if test $board_name = BASIC; then " \
"setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
@@ -61,7 +58,8 @@
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0)
+ func(MMC, mmc, 0) \
+ func(DHCP, dhcp, na)
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
@@ -91,4 +89,33 @@
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_IMX_THERMAL
+
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
+#define PFUZE3000_I2C_BUS 0
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+
+#define CONFIG_FEC_ENET_DEV 0
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC0"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
#endif /* __CONFIG_H */
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
new file mode 100644
index 0000000..d382fc7
--- /dev/null
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX5_H
+#define __DT_BINDINGS_CLOCK_IMX5_H
+
+#define IMX5_CLK_DUMMY 0
+#define IMX5_CLK_CKIL 1
+#define IMX5_CLK_OSC 2
+#define IMX5_CLK_CKIH1 3
+#define IMX5_CLK_CKIH2 4
+#define IMX5_CLK_AHB 5
+#define IMX5_CLK_IPG 6
+#define IMX5_CLK_AXI_A 7
+#define IMX5_CLK_AXI_B 8
+#define IMX5_CLK_UART_PRED 9
+#define IMX5_CLK_UART_ROOT 10
+#define IMX5_CLK_ESDHC_A_PRED 11
+#define IMX5_CLK_ESDHC_B_PRED 12
+#define IMX5_CLK_ESDHC_C_SEL 13
+#define IMX5_CLK_ESDHC_D_SEL 14
+#define IMX5_CLK_EMI_SEL 15
+#define IMX5_CLK_EMI_SLOW_PODF 16
+#define IMX5_CLK_NFC_PODF 17
+#define IMX5_CLK_ECSPI_PRED 18
+#define IMX5_CLK_ECSPI_PODF 19
+#define IMX5_CLK_USBOH3_PRED 20
+#define IMX5_CLK_USBOH3_PODF 21
+#define IMX5_CLK_USB_PHY_PRED 22
+#define IMX5_CLK_USB_PHY_PODF 23
+#define IMX5_CLK_CPU_PODF 24
+#define IMX5_CLK_DI_PRED 25
+#define IMX5_CLK_TVE_SEL 27
+#define IMX5_CLK_UART1_IPG_GATE 28
+#define IMX5_CLK_UART1_PER_GATE 29
+#define IMX5_CLK_UART2_IPG_GATE 30
+#define IMX5_CLK_UART2_PER_GATE 31
+#define IMX5_CLK_UART3_IPG_GATE 32
+#define IMX5_CLK_UART3_PER_GATE 33
+#define IMX5_CLK_I2C1_GATE 34
+#define IMX5_CLK_I2C2_GATE 35
+#define IMX5_CLK_GPT_IPG_GATE 36
+#define IMX5_CLK_PWM1_IPG_GATE 37
+#define IMX5_CLK_PWM1_HF_GATE 38
+#define IMX5_CLK_PWM2_IPG_GATE 39
+#define IMX5_CLK_PWM2_HF_GATE 40
+#define IMX5_CLK_GPT_HF_GATE 41
+#define IMX5_CLK_FEC_GATE 42
+#define IMX5_CLK_USBOH3_PER_GATE 43
+#define IMX5_CLK_ESDHC1_IPG_GATE 44
+#define IMX5_CLK_ESDHC2_IPG_GATE 45
+#define IMX5_CLK_ESDHC3_IPG_GATE 46
+#define IMX5_CLK_ESDHC4_IPG_GATE 47
+#define IMX5_CLK_SSI1_IPG_GATE 48
+#define IMX5_CLK_SSI2_IPG_GATE 49
+#define IMX5_CLK_SSI3_IPG_GATE 50
+#define IMX5_CLK_ECSPI1_IPG_GATE 51
+#define IMX5_CLK_ECSPI1_PER_GATE 52
+#define IMX5_CLK_ECSPI2_IPG_GATE 53
+#define IMX5_CLK_ECSPI2_PER_GATE 54
+#define IMX5_CLK_CSPI_IPG_GATE 55
+#define IMX5_CLK_SDMA_GATE 56
+#define IMX5_CLK_EMI_SLOW_GATE 57
+#define IMX5_CLK_IPU_SEL 58
+#define IMX5_CLK_IPU_GATE 59
+#define IMX5_CLK_NFC_GATE 60
+#define IMX5_CLK_IPU_DI1_GATE 61
+#define IMX5_CLK_VPU_SEL 62
+#define IMX5_CLK_VPU_GATE 63
+#define IMX5_CLK_VPU_REFERENCE_GATE 64
+#define IMX5_CLK_UART4_IPG_GATE 65
+#define IMX5_CLK_UART4_PER_GATE 66
+#define IMX5_CLK_UART5_IPG_GATE 67
+#define IMX5_CLK_UART5_PER_GATE 68
+#define IMX5_CLK_TVE_GATE 69
+#define IMX5_CLK_TVE_PRED 70
+#define IMX5_CLK_ESDHC1_PER_GATE 71
+#define IMX5_CLK_ESDHC2_PER_GATE 72
+#define IMX5_CLK_ESDHC3_PER_GATE 73
+#define IMX5_CLK_ESDHC4_PER_GATE 74
+#define IMX5_CLK_USB_PHY_GATE 75
+#define IMX5_CLK_HSI2C_GATE 76
+#define IMX5_CLK_MIPI_HSC1_GATE 77
+#define IMX5_CLK_MIPI_HSC2_GATE 78
+#define IMX5_CLK_MIPI_ESC_GATE 79
+#define IMX5_CLK_MIPI_HSP_GATE 80
+#define IMX5_CLK_LDB_DI1_DIV_3_5 81
+#define IMX5_CLK_LDB_DI1_DIV 82
+#define IMX5_CLK_LDB_DI0_DIV_3_5 83
+#define IMX5_CLK_LDB_DI0_DIV 84
+#define IMX5_CLK_LDB_DI1_GATE 85
+#define IMX5_CLK_CAN2_SERIAL_GATE 86
+#define IMX5_CLK_CAN2_IPG_GATE 87
+#define IMX5_CLK_I2C3_GATE 88
+#define IMX5_CLK_LP_APM 89
+#define IMX5_CLK_PERIPH_APM 90
+#define IMX5_CLK_MAIN_BUS 91
+#define IMX5_CLK_AHB_MAX 92
+#define IMX5_CLK_AIPS_TZ1 93
+#define IMX5_CLK_AIPS_TZ2 94
+#define IMX5_CLK_TMAX1 95
+#define IMX5_CLK_TMAX2 96
+#define IMX5_CLK_TMAX3 97
+#define IMX5_CLK_SPBA 98
+#define IMX5_CLK_UART_SEL 99
+#define IMX5_CLK_ESDHC_A_SEL 100
+#define IMX5_CLK_ESDHC_B_SEL 101
+#define IMX5_CLK_ESDHC_A_PODF 102
+#define IMX5_CLK_ESDHC_B_PODF 103
+#define IMX5_CLK_ECSPI_SEL 104
+#define IMX5_CLK_USBOH3_SEL 105
+#define IMX5_CLK_USB_PHY_SEL 106
+#define IMX5_CLK_IIM_GATE 107
+#define IMX5_CLK_USBOH3_GATE 108
+#define IMX5_CLK_EMI_FAST_GATE 109
+#define IMX5_CLK_IPU_DI0_GATE 110
+#define IMX5_CLK_GPC_DVFS 111
+#define IMX5_CLK_PLL1_SW 112
+#define IMX5_CLK_PLL2_SW 113
+#define IMX5_CLK_PLL3_SW 114
+#define IMX5_CLK_IPU_DI0_SEL 115
+#define IMX5_CLK_IPU_DI1_SEL 116
+#define IMX5_CLK_TVE_EXT_SEL 117
+#define IMX5_CLK_MX51_MIPI 118
+#define IMX5_CLK_PLL4_SW 119
+#define IMX5_CLK_LDB_DI1_SEL 120
+#define IMX5_CLK_DI_PLL4_PODF 121
+#define IMX5_CLK_LDB_DI0_SEL 122
+#define IMX5_CLK_LDB_DI0_GATE 123
+#define IMX5_CLK_USB_PHY1_GATE 124
+#define IMX5_CLK_USB_PHY2_GATE 125
+#define IMX5_CLK_PER_LP_APM 126
+#define IMX5_CLK_PER_PRED1 127
+#define IMX5_CLK_PER_PRED2 128
+#define IMX5_CLK_PER_PODF 129
+#define IMX5_CLK_PER_ROOT 130
+#define IMX5_CLK_SSI_APM 131
+#define IMX5_CLK_SSI1_ROOT_SEL 132
+#define IMX5_CLK_SSI2_ROOT_SEL 133
+#define IMX5_CLK_SSI3_ROOT_SEL 134
+#define IMX5_CLK_SSI_EXT1_SEL 135
+#define IMX5_CLK_SSI_EXT2_SEL 136
+#define IMX5_CLK_SSI_EXT1_COM_SEL 137
+#define IMX5_CLK_SSI_EXT2_COM_SEL 138
+#define IMX5_CLK_SSI1_ROOT_PRED 139
+#define IMX5_CLK_SSI1_ROOT_PODF 140
+#define IMX5_CLK_SSI2_ROOT_PRED 141
+#define IMX5_CLK_SSI2_ROOT_PODF 142
+#define IMX5_CLK_SSI_EXT1_PRED 143
+#define IMX5_CLK_SSI_EXT1_PODF 144
+#define IMX5_CLK_SSI_EXT2_PRED 145
+#define IMX5_CLK_SSI_EXT2_PODF 146
+#define IMX5_CLK_SSI1_ROOT_GATE 147
+#define IMX5_CLK_SSI2_ROOT_GATE 148
+#define IMX5_CLK_SSI3_ROOT_GATE 149
+#define IMX5_CLK_SSI_EXT1_GATE 150
+#define IMX5_CLK_SSI_EXT2_GATE 151
+#define IMX5_CLK_EPIT1_IPG_GATE 152
+#define IMX5_CLK_EPIT1_HF_GATE 153
+#define IMX5_CLK_EPIT2_IPG_GATE 154
+#define IMX5_CLK_EPIT2_HF_GATE 155
+#define IMX5_CLK_CAN_SEL 156
+#define IMX5_CLK_CAN1_SERIAL_GATE 157
+#define IMX5_CLK_CAN1_IPG_GATE 158
+#define IMX5_CLK_OWIRE_GATE 159
+#define IMX5_CLK_GPU3D_SEL 160
+#define IMX5_CLK_GPU2D_SEL 161
+#define IMX5_CLK_GPU3D_GATE 162
+#define IMX5_CLK_GPU2D_GATE 163
+#define IMX5_CLK_GARB_GATE 164
+#define IMX5_CLK_CKO1_SEL 165
+#define IMX5_CLK_CKO1_PODF 166
+#define IMX5_CLK_CKO1 167
+#define IMX5_CLK_CKO2_SEL 168
+#define IMX5_CLK_CKO2_PODF 169
+#define IMX5_CLK_CKO2 170
+#define IMX5_CLK_SRTC_GATE 171
+#define IMX5_CLK_PATA_GATE 172
+#define IMX5_CLK_SATA_GATE 173
+#define IMX5_CLK_SPDIF_XTAL_SEL 174
+#define IMX5_CLK_SPDIF0_SEL 175
+#define IMX5_CLK_SPDIF1_SEL 176
+#define IMX5_CLK_SPDIF0_PRED 177
+#define IMX5_CLK_SPDIF0_PODF 178
+#define IMX5_CLK_SPDIF1_PRED 179
+#define IMX5_CLK_SPDIF1_PODF 180
+#define IMX5_CLK_SPDIF0_COM_SEL 181
+#define IMX5_CLK_SPDIF1_COM_SEL 182
+#define IMX5_CLK_SPDIF0_GATE 183
+#define IMX5_CLK_SPDIF1_GATE 184
+#define IMX5_CLK_SPDIF_IPG_GATE 185
+#define IMX5_CLK_OCRAM 186
+#define IMX5_CLK_SAHARA_IPG_GATE 187
+#define IMX5_CLK_SATA_REF 188
+#define IMX5_CLK_STEP_SEL 189
+#define IMX5_CLK_CPU_PODF_SEL 190
+#define IMX5_CLK_ARM 191
+#define IMX5_CLK_FIRI_PRED 192
+#define IMX5_CLK_FIRI_SEL 193
+#define IMX5_CLK_FIRI_PODF 194
+#define IMX5_CLK_FIRI_SERIAL_GATE 195
+#define IMX5_CLK_FIRI_IPG_GATE 196
+#define IMX5_CLK_CSI0_MCLK1_PRED 197
+#define IMX5_CLK_CSI0_MCLK1_SEL 198
+#define IMX5_CLK_CSI0_MCLK1_PODF 199
+#define IMX5_CLK_CSI0_MCLK1_GATE 200
+#define IMX5_CLK_IEEE1588_PRED 201
+#define IMX5_CLK_IEEE1588_SEL 202
+#define IMX5_CLK_IEEE1588_PODF 203
+#define IMX5_CLK_IEEE1588_GATE 204
+#define IMX5_CLK_END 205
+
+#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
new file mode 100644
index 0000000..39c2567
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
+#define __DT_BINDINGS_CLOCK_IMX6SLL_H
+
+#define IMX6SLL_CLK_DUMMY 0
+#define IMX6SLL_CLK_CKIL 1
+#define IMX6SLL_CLK_OSC 2
+#define IMX6SLL_PLL1_BYPASS_SRC 3
+#define IMX6SLL_PLL2_BYPASS_SRC 4
+#define IMX6SLL_PLL3_BYPASS_SRC 5
+#define IMX6SLL_PLL4_BYPASS_SRC 6
+#define IMX6SLL_PLL5_BYPASS_SRC 7
+#define IMX6SLL_PLL6_BYPASS_SRC 8
+#define IMX6SLL_PLL7_BYPASS_SRC 9
+#define IMX6SLL_CLK_PLL1 10
+#define IMX6SLL_CLK_PLL2 11
+#define IMX6SLL_CLK_PLL3 12
+#define IMX6SLL_CLK_PLL4 13
+#define IMX6SLL_CLK_PLL5 14
+#define IMX6SLL_CLK_PLL6 15
+#define IMX6SLL_CLK_PLL7 16
+#define IMX6SLL_PLL1_BYPASS 17
+#define IMX6SLL_PLL2_BYPASS 18
+#define IMX6SLL_PLL3_BYPASS 19
+#define IMX6SLL_PLL4_BYPASS 20
+#define IMX6SLL_PLL5_BYPASS 21
+#define IMX6SLL_PLL6_BYPASS 22
+#define IMX6SLL_PLL7_BYPASS 23
+#define IMX6SLL_CLK_PLL1_SYS 24
+#define IMX6SLL_CLK_PLL2_BUS 25
+#define IMX6SLL_CLK_PLL3_USB_OTG 26
+#define IMX6SLL_CLK_PLL4_AUDIO 27
+#define IMX6SLL_CLK_PLL5_VIDEO 28
+#define IMX6SLL_CLK_PLL6_ENET 29
+#define IMX6SLL_CLK_PLL7_USB_HOST 30
+#define IMX6SLL_CLK_USBPHY1 31
+#define IMX6SLL_CLK_USBPHY2 32
+#define IMX6SLL_CLK_USBPHY1_GATE 33
+#define IMX6SLL_CLK_USBPHY2_GATE 34
+#define IMX6SLL_CLK_PLL2_PFD0 35
+#define IMX6SLL_CLK_PLL2_PFD1 36
+#define IMX6SLL_CLK_PLL2_PFD2 37
+#define IMX6SLL_CLK_PLL2_PFD3 38
+#define IMX6SLL_CLK_PLL3_PFD0 39
+#define IMX6SLL_CLK_PLL3_PFD1 40
+#define IMX6SLL_CLK_PLL3_PFD2 41
+#define IMX6SLL_CLK_PLL3_PFD3 42
+#define IMX6SLL_CLK_PLL4_POST_DIV 43
+#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
+#define IMX6SLL_CLK_PLL5_POST_DIV 45
+#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
+#define IMX6SLL_CLK_PLL2_198M 47
+#define IMX6SLL_CLK_PLL3_120M 48
+#define IMX6SLL_CLK_PLL3_80M 49
+#define IMX6SLL_CLK_PLL3_60M 50
+#define IMX6SLL_CLK_STEP 51
+#define IMX6SLL_CLK_PLL1_SW 52
+#define IMX6SLL_CLK_AXI_ALT_SEL 53
+#define IMX6SLL_CLK_AXI_SEL 54
+#define IMX6SLL_CLK_PERIPH_PRE 55
+#define IMX6SLL_CLK_PERIPH2_PRE 56
+#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
+#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
+#define IMX6SLL_CLK_PERCLK_SEL 59
+#define IMX6SLL_CLK_USDHC1_SEL 60
+#define IMX6SLL_CLK_USDHC2_SEL 61
+#define IMX6SLL_CLK_USDHC3_SEL 62
+#define IMX6SLL_CLK_SSI1_SEL 63
+#define IMX6SLL_CLK_SSI2_SEL 64
+#define IMX6SLL_CLK_SSI3_SEL 65
+#define IMX6SLL_CLK_PXP_SEL 66
+#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
+#define IMX6SLL_CLK_LCDIF_SEL 68
+#define IMX6SLL_CLK_EPDC_PRE_SEL 69
+#define IMX6SLL_CLK_SPDIF_SEL 70
+#define IMX6SLL_CLK_ECSPI_SEL 71
+#define IMX6SLL_CLK_UART_SEL 72
+#define IMX6SLL_CLK_ARM 73
+#define IMX6SLL_CLK_PERIPH 74
+#define IMX6SLL_CLK_PERIPH2 75
+#define IMX6SLL_CLK_PERIPH2_CLK2 76
+#define IMX6SLL_CLK_PERIPH_CLK2 77
+#define IMX6SLL_CLK_MMDC_PODF 78
+#define IMX6SLL_CLK_AXI_PODF 79
+#define IMX6SLL_CLK_AHB 80
+#define IMX6SLL_CLK_IPG 81
+#define IMX6SLL_CLK_PERCLK 82
+#define IMX6SLL_CLK_USDHC1_PODF 83
+#define IMX6SLL_CLK_USDHC2_PODF 84
+#define IMX6SLL_CLK_USDHC3_PODF 85
+#define IMX6SLL_CLK_SSI1_PRED 86
+#define IMX6SLL_CLK_SSI2_PRED 87
+#define IMX6SLL_CLK_SSI3_PRED 88
+#define IMX6SLL_CLK_SSI1_PODF 89
+#define IMX6SLL_CLK_SSI2_PODF 90
+#define IMX6SLL_CLK_SSI3_PODF 91
+#define IMX6SLL_CLK_PXP_PODF 92
+#define IMX6SLL_CLK_LCDIF_PRED 93
+#define IMX6SLL_CLK_LCDIF_PODF 94
+#define IMX6SLL_CLK_EPDC_SEL 95
+#define IMX6SLL_CLK_EPDC_PODF 96
+#define IMX6SLL_CLK_SPDIF_PRED 97
+#define IMX6SLL_CLK_SPDIF_PODF 98
+#define IMX6SLL_CLK_ECSPI_PODF 99
+#define IMX6SLL_CLK_UART_PODF 100
+
+/* CCGR 0 */
+#define IMX6SLL_CLK_AIPSTZ1 101
+#define IMX6SLL_CLK_AIPSTZ2 102
+#define IMX6SLL_CLK_DCP 103
+#define IMX6SLL_CLK_UART2_IPG 104
+#define IMX6SLL_CLK_UART2_SERIAL 105
+
+/* CCGR 1 */
+#define IMX6SLL_CLK_ECSPI1 106
+#define IMX6SLL_CLK_ECSPI2 107
+#define IMX6SLL_CLK_ECSPI3 108
+#define IMX6SLL_CLK_ECSPI4 109
+#define IMX6SLL_CLK_UART3_IPG 110
+#define IMX6SLL_CLK_UART3_SERIAL 111
+#define IMX6SLL_CLK_UART4_IPG 112
+#define IMX6SLL_CLK_UART4_SERIAL 113
+#define IMX6SLL_CLK_EPIT1 114
+#define IMX6SLL_CLK_EPIT2 115
+#define IMX6SLL_CLK_GPT_BUS 116
+#define IMX6SLL_CLK_GPT_SERIAL 117
+
+/* CCGR2 */
+#define IMX6SLL_CLK_CSI 118
+#define IMX6SLL_CLK_I2C1 119
+#define IMX6SLL_CLK_I2C2 120
+#define IMX6SLL_CLK_I2C3 121
+#define IMX6SLL_CLK_OCOTP 122
+#define IMX6SLL_CLK_LCDIF_APB 123
+#define IMX6SLL_CLK_PXP 124
+
+/* CCGR3 */
+#define IMX6SLL_CLK_UART5_IPG 125
+#define IMX6SLL_CLK_UART5_SERIAL 126
+#define IMX6SLL_CLK_EPDC_AXI 127
+#define IMX6SLL_CLK_EPDC_PIX 128
+#define IMX6SLL_CLK_LCDIF_PIX 129
+#define IMX6SLL_CLK_WDOG1 130
+#define IMX6SLL_CLK_MMDC_P0_FAST 131
+#define IMX6SLL_CLK_MMDC_P0_IPG 132
+#define IMX6SLL_CLK_OCRAM 133
+
+/* CCGR4 */
+#define IMX6SLL_CLK_PWM1 134
+#define IMX6SLL_CLK_PWM2 135
+#define IMX6SLL_CLK_PWM3 136
+#define IMX6SLL_CLK_PWM4 137
+
+/* CCGR 5 */
+#define IMX6SLL_CLK_ROM 138
+#define IMX6SLL_CLK_SDMA 139
+#define IMX6SLL_CLK_KPP 140
+#define IMX6SLL_CLK_WDOG2 141
+#define IMX6SLL_CLK_SPBA 142
+#define IMX6SLL_CLK_SPDIF 143
+#define IMX6SLL_CLK_SPDIF_GCLK 144
+#define IMX6SLL_CLK_SSI1 145
+#define IMX6SLL_CLK_SSI1_IPG 146
+#define IMX6SLL_CLK_SSI2 147
+#define IMX6SLL_CLK_SSI2_IPG 148
+#define IMX6SLL_CLK_SSI3 149
+#define IMX6SLL_CLK_SSI3_IPG 150
+#define IMX6SLL_CLK_UART1_IPG 151
+#define IMX6SLL_CLK_UART1_SERIAL 152
+
+/* CCGR 6 */
+#define IMX6SLL_CLK_USBOH3 153
+#define IMX6SLL_CLK_USDHC1 154
+#define IMX6SLL_CLK_USDHC2 155
+#define IMX6SLL_CLK_USDHC3 156
+
+#define IMX6SLL_CLK_IPP_DI0 157
+#define IMX6SLL_CLK_IPP_DI1 158
+#define IMX6SLL_CLK_LDB_DI0_SEL 159
+#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
+#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
+#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
+#define IMX6SLL_CLK_LDB_DI0 163
+#define IMX6SLL_CLK_LDB_DI1_SEL 164
+#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
+#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
+#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
+#define IMX6SLL_CLK_LDB_DI1 168
+#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
+#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
+#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
+#define IMX6SLL_CLK_EXTERN_AUDIO 172
+
+#define IMX6SLL_CLK_END 173
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index 18de070..4623f17 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -234,6 +234,7 @@
#define IMX6UL_CLK_CSI_SEL 221
#define IMX6UL_CLK_CSI_PODF 222
#define IMX6UL_CLK_PLL3_120M 223
+#define IMX6UL_CLK_KPP 224
/* For i.MX6ULL */
#define IMX6UL_CLK_ESAI_SEL 224
#define IMX6UL_CLK_ESAI_PRED 225
diff --git a/include/power/pfuze3000_pmic.h b/include/power/pfuze3000_pmic.h
index e8b892b..7d66ba4 100644
--- a/include/power/pfuze3000_pmic.h
+++ b/include/power/pfuze3000_pmic.h
@@ -75,4 +75,9 @@ enum {
int power_pfuze3000_init(unsigned char bus);
+/* Voltage Configuration */
+#define PFUZE3000_SW1AB_SETP(x) ((x - 7000) / 250)
+#define PFUZE3000_SW3_SETP(x) ((x - 9000) / 500)
+#define PFUZE3000_VLDO_SETP(x) ((x - 8000) / 500)
+
#endif
generated by cgit v0.10.2 at 2024-11-02 23:42:51 (GMT)