From 5608c0d38387a087ea926eea178ed6d5068bb676 Mon Sep 17 00:00:00 2001
From: Suresh Gupta <suresh.gupta@nxp.com>
Date: Thu, 17 Aug 2017 15:51:09 +0530
Subject: spi: fsl_qspi: Add controller busy check before new spi operation

It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 117f3fa..6e5c3b0 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -166,6 +166,26 @@ static inline u32 qspi_endian_xchg(u32 data)
 	return data;
 #endif
 }
+static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv)
+{
+	u32 sr;
+	u32 retry = 5;
+
+	do {
+		sr = qspi_read32(priv->flags, &priv->regs->sr);
+		if ((sr & QSPI_SR_BUSY_MASK) ||
+		    (sr & QSPI_SR_AHB_ACC_MASK) ||
+		    (sr & QSPI_SR_IP_ACC_MASK)) {
+			debug("The controller is busy, sr = 0x%x\n", sr);
+			udelay(1);
+		} else {
+			break;
+		}
+	} while (--retry);
+
+	return (sr & QSPI_SR_BUSY_MASK) ||
+		(sr & QSPI_SR_AHB_ACC_MASK) || (sr & QSPI_SR_IP_ACC_MASK);
+}
 
 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 {
@@ -759,6 +779,11 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 	static u32 wr_sfaddr;
 	u32 txbuf;
 
+	if (qspi_controller_busy(priv)) {
+		printf("ERROR : The controller is busy\n");
+		return -EBUSY;
+	}
+
 	if (dout) {
 		if (flags & SPI_XFER_BEGIN) {
 			priv->cur_seqid = *(u8 *)dout;
diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h
index 6cb3610..e468eb2 100644
--- a/drivers/spi/fsl_qspi.h
+++ b/drivers/spi/fsl_qspi.h
@@ -105,6 +105,10 @@ struct fsl_qspi_regs {
 #define QSPI_RBCT_RXBRD_SHIFT		8
 #define QSPI_RBCT_RXBRD_USEIPS		(1 << QSPI_RBCT_RXBRD_SHIFT)
 
+#define QSPI_SR_AHB_ACC_SHIFT		2
+#define QSPI_SR_AHB_ACC_MASK		(1 << QSPI_SR_AHB_ACC_SHIFT)
+#define QSPI_SR_IP_ACC_SHIFT		1
+#define QSPI_SR_IP_ACC_MASK		(1 << QSPI_SR_IP_ACC_SHIFT)
 #define QSPI_SR_BUSY_SHIFT		0
 #define QSPI_SR_BUSY_MASK		(1 << QSPI_SR_BUSY_SHIFT)
 
-- 
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