From 229dbba9b1a24d8f371f18fa8ff13a4cca864f06 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 10 Nov 2014 08:50:39 +0800 Subject: usb:ehci-mx6 add phy mode query function usb_phy_enable should return status bit, but not phy mode bit, thus add a new function usb_phy_mode to query the PHY for it's mode and make usb_phy_enable just return 0 but not 'phy_ctrl & USBPHY_CTRL_OTG_ID'. Include a new board weak function board_usb_phy_mode. If board code does not reimplement this function, it just call usb_phy_mode and return usb_phy_mode's return value. The reason to include such a weak function is: " SOC OTG core <--connect--> board HOST port, but no pin id for the board host port, so board can not use usb_phy_mode to return the phy mode, but define it's own rule." Signed-off-by: Peng Fan Signed-off-by: Ye Li diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 9ec5a0a..951dd3b 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -160,7 +160,7 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3); __raw_writel(val, phy_ctrl); - return val & USBPHY_CTRL_OTG_ID; + return 0; } /* Base address for this IP block is 0x02184800 */ @@ -193,6 +193,28 @@ static void usb_oc_config(int index) __raw_writel(val, ctrl); } +int usb_phy_mode(int port) +{ + void __iomem *phy_reg; + void __iomem *phy_ctrl; + u32 val; + + phy_reg = (void __iomem *)phy_bases[port]; + phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); + + val = __raw_readl(phy_ctrl); + + if (val & USBPHY_CTRL_OTG_ID) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; +} + +int __weak board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + int __weak board_ehci_hcd_init(int port) { return 0; @@ -221,7 +243,8 @@ int ehci_hcd_init(int index, enum usb_init_type init, usb_power_config(index); usb_oc_config(index); usb_internal_phy_clock_gate(index, 1); - type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST; + usb_phy_enable(index, ehci); + type = board_usb_phy_mode(index); *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); *hcor = (struct ehci_hcor *)((uint32_t)*hccr + diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index dd77ad6..22114c1 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -277,7 +277,9 @@ struct usb_ehci { #define MXC_EHCI_IPPUE_DOWN (1 << 10) #define MXC_EHCI_IPPUE_UP (1 << 11) +int usb_phy_mode(int port); /* Board-specific initialization */ int board_ehci_hcd_init(int port); +int board_usb_phy_mode(int port); #endif /* _EHCI_FSL_H */ -- cgit v0.10.2 From 3b9c1a5dc09e5ee773f5a4fe9280e568b64b7779 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 10 Nov 2014 08:50:41 +0800 Subject: imx:mx6slevk add board level support for usb Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to let host port work in host mode. Signed-off-by: Peng Fan Signed-off-by: Ye Li diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index d9db58c..9ded3d8 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -53,5 +53,10 @@ enum { MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index e76c343..3ae2c46 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -243,6 +245,48 @@ static int setup_fec(void) } #endif +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OTG1 */ + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif int board_early_init_f(void) { @@ -261,6 +305,11 @@ int board_init(void) #ifdef CONFIG_FEC_MXC setup_fec(); #endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 4fcaf51..bd57159 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -209,6 +209,20 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + #define CONFIG_SYS_FSL_USDHC_NUM 3 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ -- cgit v0.10.2 From a511a3e0e8dd48f4293096fbfb9dd7d57e89b0b4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 10 Nov 2014 08:50:40 +0800 Subject: imx:mx6sxsabresd add board level support for usb Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6sxsabresd board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to make host port work in HOST mode. Signed-off-by: Peng Fan Signed-off-by: Ye Li diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 68d3718..02e82b2 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -252,6 +254,10 @@ int board_early_init_f(void) /* Active high for ncp692 */ gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } @@ -272,6 +278,49 @@ int board_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OGT1 */ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + int board_init(void) { /* Address of boot parameters */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index e02ea18..8edf187 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -198,6 +198,20 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS + +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + #define CONFIG_CMD_PCI #ifdef CONFIG_CMD_PCI #define CONFIG_PCI -- cgit v0.10.2 From 5610b05789fb6f6af7e13ac8e7cac99e0b2422c7 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 5 Nov 2014 10:54:16 +0100 Subject: dfu: thor: fix: Modify dfu_get_alt() function to support absolute paths Recently the ext4 file system imposed passing absolute path with its file name parameter. As a result dfu_alt_info env variable has been modified to provide absolute path when ext4 file system is accessed (e.g. /uImage ext4 0 2;). Unfortunately, lthor flashing program provides plain file name (like uImage) and hence those two file names do not match anymore. Presented commit also allows lthor to write files to sub directories (like /boot/bin/uImage). Signed-off-by: Lukasz Majewski Reviewed-by: Marek Vasut diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 55e6a83..deafda2 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -544,10 +544,35 @@ struct dfu_entity *dfu_get_entity(int alt) int dfu_get_alt(char *name) { struct dfu_entity *dfu; + char *str; list_for_each_entry(dfu, &dfu_list, list) { - if (!strncmp(dfu->name, name, strlen(dfu->name))) - return dfu->alt; + if (dfu->name[0] != '/') { + if (!strncmp(dfu->name, name, strlen(dfu->name))) + return dfu->alt; + } else { + /* + * One must also consider absolute path + * (/boot/bin/uImage) available at dfu->name when + * compared "plain" file name (uImage) + * + * It is the case for e.g. thor gadget where lthor SW + * sends only the file name, so only the very last part + * of path must be checked for equality + */ + + str = strstr(dfu->name, name); + if (!str) + continue; + + /* + * Check if matching substring is the last element of + * dfu->name (uImage) + */ + if (strlen(dfu->name) == + ((str - dfu->name) + strlen(name))) + return dfu->alt; + } } return -ENODEV; -- cgit v0.10.2 From fbd3b79d77b136e85c115c09aaf5c9ce40446850 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 7 Nov 2014 14:05:55 +0100 Subject: test: ums: Add sleep before unmount directory This change helps to run script on machines with quite long uptime. Without this the following error emerges: File: ./dat_14M.img umount: /mnt/tmp-ums-test: device is busy. (In some cases useful info about processes that use the device is found by lsof(8) or fuser(1)) TX: md5sum:083d3d22b542d3ecba61b12d17e03f9f mount: /dev/sdd6 already mounted or /mnt/tmp-ums-test busy mount: according to mtab, /dev/sdd6 is already mounted on /mnt/tmp-ums-test Signed-off-by: Lukasz Majewski Reviewed-by: Stephen Warren diff --git a/test/ums/ums_gadget_test.sh b/test/ums/ums_gadget_test.sh index 56d4616..9da486b 100755 --- a/test/ums/ums_gadget_test.sh +++ b/test/ums/ums_gadget_test.sh @@ -11,6 +11,7 @@ clear COLOUR_RED="\33[31m" COLOUR_GREEN="\33[32m" +COLOUR_ORANGE="\33[33m" COLOUR_DEFAULT="\33[0m" DIR=./ @@ -59,8 +60,15 @@ ums_test_file () { fi cp ./$1 $MNT_DIR - umount $MNT_DIR + while true; do + umount $MNT_DIR > /dev/null 2>&1 + if [ $? -eq 0 ]; then + break + fi + printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n" + sleep 1 + done echo -n "TX: " calculate_md5sum $1 -- cgit v0.10.2 From 0c6de8853b2571251fdefe34598e0c344fe1372b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 17 Nov 2014 17:54:14 +0900 Subject: usb: ehci: do not set the LSB of Current qTD pointer According to EHCI specification, the LSB of DWORD 3 of Queue Head (Current qTD Pointer) is not T-bit, but always zero. Signed-off-by: Masahiro Yamada diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index c671c72..54e948a 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -971,7 +971,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | QH_ENDPT1_EPS(USB_SPEED_HIGH)); - qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); qh_list->qh_overlay.qt_token = -- cgit v0.10.2