1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
|
/*
* Copyright 2016 Scalys B.V.
* opensource@scalys.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm-generic/gpio.h>
#include <dm/platform_data/gpio_mpc8xxx.h>
#include <asm/mpc8xxx_gpio.h>
#include "dragonfruit.h"
/*
* SERDER MUX Configuration pins:
* IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
* IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
* IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
*
* MUX_SER0_1_SEL
* 0: SERDES A => Slot1, lane 0
* SERDES B => Slot1, lane 1
* 1: SERDES A => CS4315 retimer => SFP+ 0
* SERDES B => CS4315 retimer => SFP+ 1
*
* MUX_SER2_3_SEL
* 0: SERDES C => Slot1, lane 2
* SERDES D => Slot1, lane 3
* 1: SERDES C => QSFP+ 2
* SERDES D => QSFP+ 3
*
* SERDES E => Slot 4, lane 0
*
* MUX_SER5_6_SEL
* 0: SERDES F => SLOT4, lane 1
* SERDES G => SLOT4, lane 2
* 1: SERDES F => SLOT2
* SERDES G => SLOT3
*
* SERDES H => Slot 4, lane 3
*/
#define MUX_SER0_1_SEL MPC8XXX_GPIO_NR(2, 25)
#define MUX_SER2_3_SEL MPC8XXX_GPIO_NR(2, 26)
#define MUX_SER5_6_SEL MPC8XXX_GPIO_NR(2, 27)
#define SERDES_CLK_OE MPC8XXX_GPIO_NR(2, 29)
int scalys_carrier_setup_muxing(int serdes_config)
{
int ret = 0;
ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
if (ret != 0) {
printf("gpio request failed(%i)\n", ret);
}
gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
switch(serdes_config){
case 0x06:
/* A-D: PCIe1 (5/2.5G); E: PCIe2 (5/2.5G);
* F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5); H: SATA.1 (3/1.5G) */
gpio_direction_output(MUX_SER0_1_SEL, 0);
gpio_direction_output(MUX_SER2_3_SEL, 0);
gpio_direction_output(MUX_SER5_6_SEL, 1);
break;
case 0x81:
case 0x86:
case 0x88:
case 0x89:
/* A: PCIe1 (5/2.5G); B: sg.m3; C: sg.m1; D: sg.m2;
* E: PCIe2 (5/2.5G); F:PCIe3 (5/2.5G); G: SATA2(3/1.5G);
* H: SATA1(3/1.5G) */
gpio_direction_output(MUX_SER0_1_SEL, 1);
gpio_direction_output(MUX_SER2_3_SEL, 1);
gpio_direction_output(MUX_SER5_6_SEL, 1);
break;
default:
printf("Unsupported SERDES configuration (%02x)\n", serdes_config);
}
/* Enable serdes clock */
gpio_direction_output(SERDES_CLK_OE, 1);
return ret;
}
|