diff options
| author | Horia Geantă <horia.geanta@freescale.com> | 2015-10-29 17:55:21 (GMT) |
|---|---|---|
| committer | Horia Geantă <horia.geanta@freescale.com> | 2015-11-03 07:41:17 (GMT) |
| commit | 2c2766622da60bfddb25f67e04bba97e2cb4e97f (patch) | |
| tree | 412aeb7e2d5149d7c3f8f3cc2240a55cf18b2e9e | |
| parent | e82a7610e8e45f51f3490b894cae042be681148f (diff) | |
| download | linux-fsl-qoriq-2c2766622da60bfddb25f67e04bba97e2cb4e97f.tar.xz | |
crypto: caam - make write transactions bufferable on PPC platforms
Previous change (see "Fixes" tag) to the MCFGR register clears AWCACHE[0]
(which is "1" at POR).
For PPC-based platforms, this makes all writes non-bufferable, causing
a performance drop.
Rework previous change such that MCFGR[AWCACHE] is set to:
-4'b0001 (default value at POR) for PPC-based platforms
-4'b0011 (default value at POR + AWCACHE[1]) for ARM-based platforms
Fixes: bcd586241449 ("crypto: caam - fix snooping for write transactions")
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
| -rw-r--r-- | drivers/crypto/caam/ctrl.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 0359c71..0ced96f 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -16,6 +16,12 @@ #include "qi.h" #endif +#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) +static const bool is_arm = true; +#else +static const bool is_arm; +#endif + /* * Descriptor to instantiate RNG State Handle 0 in normal mode and * load the JDKEK, TDKEK and TDSK registers @@ -488,7 +494,7 @@ static int caam_probe(struct platform_device *pdev) #ifdef CONFIG_DEBUG_FS struct caam_perfmon *perfmon; #endif - u32 mcr, scfgr, comp_params; + u32 scfgr, comp_params; int pg_size; int BLOCK_OFFSET = 0; @@ -537,11 +543,9 @@ static int caam_probe(struct platform_device *pdev) * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register */ - mcr = rd_reg32(&ctrl->mcr); - mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT) | - MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? - MCFGR_LONG_PTR : 0); - wr_reg32(&ctrl->mcr, mcr); + setbits32(&ctrl->mcr, MCFGR_WDENABLE | + (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0) | + (is_arm ? 0x2 << MCFGR_AWCACHE_SHIFT : 0)); /* * Read the Compile Time paramters and SCFGR to determine @@ -820,7 +824,6 @@ static int caam_resume(struct device *dev) struct caam_drv_private *caam_priv; struct caam_ctrl __iomem *ctrl; struct caam_queue_if __iomem *qi; - u32 mcr; int ret; caam_priv = dev_get_drvdata(dev); @@ -830,11 +833,9 @@ static int caam_resume(struct device *dev) * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register */ - mcr = rd_reg32(&ctrl->mcr); - mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT) | - MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? - MCFGR_LONG_PTR : 0); - wr_reg32(&ctrl->mcr, mcr); + setbits32(&ctrl->mcr, MCFGR_WDENABLE | + (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0) | + (is_arm ? 0x2 << MCFGR_AWCACHE_SHIFT : 0)); /* Enable QI interface of SEC */ if (caam_priv->qi_present) |