ls1021a: dts: Add eTSEC info for 2nd interrupt groups

Enable support for the second interrupt group register block
and the corresponding Rx/Tx/Err interrupt sources, for each
eTSEC node.

Fix following non-critical issues and inconsistencies:
- eTSEC can support 8 H/W queues, show this in the device tree;
- remove "fsl,[r|t]x-bit-map" properties, they are obsoleted;
- register block size is 0x1000 (4kB memory page), not 0x8000;
- reg property has 2 "address" and resp. 2 "size" cells, not 1;
- use register block address as queue-group id for consistency;

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: Iada02221d1f3e06cc019a7b067c9b676c7c0b77d
Reviewed-on: http://git.am.freescale.net:8181/37273
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>

1 files changed, 43 insertions, 24 deletions

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c3a31b8..53231b4 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -616,22 +616,28 @@
 			fsl,magic-packet;
 			fsl,wake-on-filer;
 			sleep = <&rcpm 0x80000000 0x0>;
-			fsl,num_rx_queues = <0x1>;
-			fsl,num_tx_queues = <0x1>;
+			fsl,num_rx_queues = <0x8>;
+			fsl,num_tx_queues = <0x8>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			ranges;
 
-			queue-group@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				reg = <0x0 0x2d10000 0x0 0x8000>;
-				fsl,rx-bit-map = <0xff>;
-				fsl,tx-bit-map = <0xff>;
+			queue-group@2d10000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d10000 0x0 0x1000>;
 				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
+			queue-group@2d14000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d14000 0x0 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			};
 		};
 
 		enet1: ethernet@2d50000 {
@@ -642,22 +648,28 @@
 			interrupt-parent = <&gic>;
 			model = "eTSEC";
 			fsl,dma-endian-le;
-			fsl,num_rx_queues = <0x1>;
-			fsl,num_tx_queues = <0x1>;
+			fsl,num_rx_queues = <0x8>;
+			fsl,num_tx_queues = <0x8>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			ranges;
 
-			queue-group@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				reg = <0x0 0x2d50000 0x0 0x8000>;
-				fsl,rx-bit-map = <0xff>;
-				fsl,tx-bit-map = <0xff>;
+			queue-group@2d50000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d50000 0x0 0x1000>;
 				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
+			queue-group@2d54000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d54000 0x0 0x1000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			};
 		};
 
 		enet2: ethernet@2d90000 {
@@ -668,21 +680,28 @@
 			interrupt-parent = <&gic>;
 			model = "eTSEC";
 			fsl,dma-endian-le;
-			fsl,num_rx_queues = <0x1>;
-			fsl,num_tx_queues = <0x1>;
+			fsl,num_rx_queues = <0x8>;
+			fsl,num_tx_queues = <0x8>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			ranges;
 
-			queue-group@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				reg = <0x0 0x2d90000 0x0 0x8000>;
-				fsl,rx-bit-map = <0xff>;
-				fsl,tx-bit-map = <0xff>;
+			queue-group@2d90000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d90000 0x0 0x1000>;
 				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 			};
+
+			queue-group@2d94000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d94000 0x0 0x1000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			};
 		};
 
 		can0: can@2a70000 {