diff options
| author | Horia Geantă <horia.geanta@freescale.com> | 2015-10-30 12:30:19 (GMT) |
|---|---|---|
| committer | Horia Geantă <horia.geanta@freescale.com> | 2015-11-03 07:41:18 (GMT) |
| commit | 67ef9d132bb8d6e91863160e56ec62291c8b2be7 (patch) | |
| tree | 60115ccddab2f4751f49202af04bacebe8cd2be4 | |
| parent | 2c2766622da60bfddb25f67e04bba97e2cb4e97f (diff) | |
| download | linux-fsl-qoriq-67ef9d132bb8d6e91863160e56ec62291c8b2be7.tar.xz | |
crypto: caam - enable LARGE_BURST for enhancing DMA transactions size
Increasing CAAM DMA engine transaction size either
-reduces the number of required transactions or
-adds the ability to transfer more data with same transaction count
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
| -rw-r--r-- | drivers/crypto/caam/ctrl.c | 4 | ||||
| -rw-r--r-- | drivers/crypto/caam/regs.h | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 0ced96f..1615916 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -543,7 +543,7 @@ static int caam_probe(struct platform_device *pdev) * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register */ - setbits32(&ctrl->mcr, MCFGR_WDENABLE | + setbits32(&ctrl->mcr, MCFGR_WDENABLE | MCFGR_LARGE_BURST | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0) | (is_arm ? 0x2 << MCFGR_AWCACHE_SHIFT : 0)); @@ -833,7 +833,7 @@ static int caam_resume(struct device *dev) * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register */ - setbits32(&ctrl->mcr, MCFGR_WDENABLE | + setbits32(&ctrl->mcr, MCFGR_WDENABLE | MCFGR_LARGE_BURST | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0) | (is_arm ? 0x2 << MCFGR_AWCACHE_SHIFT : 0)); diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 72193f8..b2715d4 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -413,7 +413,8 @@ struct caam_ctrl { #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ -#define MCFGR_BURST_64 0x00000001 /* Max burst size */ +#define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */ +#define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */ /* JRSTART register offsets */ #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ |