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| author | Chenhui Zhao <chenhui.zhao@freescale.com> | 2015-07-08 10:10:55 (GMT) |
|---|---|---|
| committer | Zhengxiong Jin <Jason.Jin@freescale.com> | 2015-07-09 07:17:22 (GMT) |
| commit | 7a6dba419338704f39798b30c0ee8203d779db6e (patch) | |
| tree | a6ca74e6433a39031dbeac9dc6444643c6e489cb | |
| parent | 4e614179832ee15663e3486770263f9b3309ac7d (diff) | |
| download | linux-fsl-qoriq-7a6dba419338704f39798b30c0ee8203d779db6e.tar.xz | |
arm: ls1021a: change the order of setting PMC interrupt registers
In deep sleep process, set interrupt status and polarity registers
before enabling PMC interrupts. It is more stable, especially on
ls1021a-twr board.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: I8305e25a76f0bcc636b58178495165c915ac3c1a
Reviewed-on: http://git.am.freescale.net:8181/39478
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
| -rw-r--r-- | arch/arm/mach-imx/pm-ls1.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c index 67260a5..8ad1b85 100644 --- a/arch/arm/mach-imx/pm-ls1.c +++ b/arch/arm/mach-imx/pm-ls1.c @@ -195,11 +195,12 @@ static void ls1_setup_pmc_int(void) /* always set external IRQ pins as wakeup source */ pmcintecr |= CCSR_SCFG_PMCINTECR_IRQ0 | CCSR_SCFG_PMCINTECR_IRQ1; - /* enable wakeup interrupt during deep sleep */ - iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR); iowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTLECR); /* clear PMC interrupt status */ iowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR); + /* enable wakeup interrupt during deep sleep */ + iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR); + } static void ls1_clear_pmc_int(void) |