diff options
| author | Ondrej Zary <linux@rainbow-software.org> | 2011-05-16 19:38:08 (GMT) |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2011-05-16 20:24:21 (GMT) |
| commit | 865be7a81071a77014c83cd01536c989eed362b4 (patch) | |
| tree | 4fd71b4c50c40b174ea728f79a4301d765c4b88c | |
| parent | eecaaba5b2e4ae762b4726fae2e3b22630e137ec (diff) | |
| download | linux-fsl-qoriq-865be7a81071a77014c83cd01536c989eed362b4.tar.xz | |
x86, cpu: Fix detection of Celeron Covington stepping A1 and B0
Steppings A1 and B0 of Celeron Covington are currently misdetected as
Pentium II (Dixon). Fix it by removing the stepping check.
[ hpa: this fixes this specific bug... the CPUID documentation
specifies that the L2 cache size can disambiguate additional CPUs;
this patch does not fix that. ]
Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
Link: http://lkml.kernel.org/r/201105162138.15416.linux@rainbow-software.org
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index df86bc8..32e86aa 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -400,12 +400,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) switch (c->x86_model) { case 5: - if (c->x86_mask == 0) { - if (l2 == 0) - p = "Celeron (Covington)"; - else if (l2 == 256) - p = "Mobile Pentium II (Dixon)"; - } + if (l2 == 0) + p = "Celeron (Covington)"; + else if (l2 == 256) + p = "Mobile Pentium II (Dixon)"; break; case 6: |