diff options
| author | Horia Geantă <horia.geanta@freescale.com> | 2015-07-03 13:23:29 (GMT) |
|---|---|---|
| committer | Zhengxiong Jin <Jason.Jin@freescale.com> | 2015-07-09 06:15:01 (GMT) |
| commit | bcd586241449dc177a82069117e41e7be90683bd (patch) | |
| tree | e5f736d1f7a6814ba6056c45002707d4ec0831ec | |
| parent | eec616d163a4d795d40d7a85fcb0150dcfc3c955 (diff) | |
| download | linux-fsl-qoriq-bcd586241449dc177a82069117e41e7be90683bd.tar.xz | |
crypto: caam - fix snooping for write transactions
HW coherency won't work properly for CAAM write transactions
if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.
For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works
due to the IOMMU (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
Change-Id: I1f91a526c0bdf28b799d19cab9599b115cad55b3
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/39256
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
| -rw-r--r-- | drivers/crypto/caam/ctrl.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 321deb0..1d77f5a 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -488,7 +488,7 @@ static int caam_probe(struct platform_device *pdev) #ifdef CONFIG_DEBUG_FS struct caam_perfmon *perfmon; #endif - u32 scfgr, comp_params; + u32 mcr, scfgr, comp_params; int pg_size; int BLOCK_OFFSET = 0; @@ -537,8 +537,11 @@ static int caam_probe(struct platform_device *pdev) * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register */ - setbits32(&ctrl->mcr, MCFGR_WDENABLE | - (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); + mcr = rd_reg32(&ctrl->mcr); + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT) | + MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? + MCFGR_LONG_PTR : 0); + wr_reg32(&ctrl->mcr, mcr); /* * Read the Compile Time paramters and SCFGR to determine @@ -817,6 +820,7 @@ static int caam_resume(struct device *dev) struct caam_drv_private *caam_priv; struct caam_ctrl __iomem *ctrl; struct caam_queue_if __iomem *qi; + u32 mcr; int ret; caam_priv = dev_get_drvdata(dev); @@ -826,8 +830,11 @@ static int caam_resume(struct device *dev) * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, * long pointers in master configuration register */ - setbits32(&ctrl->mcr, MCFGR_WDENABLE | - (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); + mcr = rd_reg32(&ctrl->mcr); + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT) | + MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? + MCFGR_LONG_PTR : 0); + wr_reg32(&ctrl->mcr, mcr); /* Enable QI interface of SEC */ if (caam_priv->qi_present) |