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author | Jingchang Lu <jingchang.lu@freescale.com> | 2014-07-15 09:23:00 (GMT) |
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committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:35:34 (GMT) |
commit | bb35145e83b3a34bae2901370a0caf32aae2448c (patch) | |
tree | 3835925c0821588769a08a5a799808248b79b149 /Documentation | |
parent | 9d7475890589e7131bad4eb5cbd6f482af674821 (diff) | |
download | linux-fsl-qoriq-bb35145e83b3a34bae2901370a0caf32aae2448c.tar.xz |
dt-bindings: arm: add Freescale LS1021A SoC specific devict tree binding
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/arm/fsl.txt | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index e935d7d..2e9b283 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -74,3 +74,31 @@ Required root node properties: i.MX6q generic board Required root node properties: - compatible = "fsl,imx6q"; + + +------------------------------------------------ + +Freescale LS1021A platfform device tree bindings +------------------------------------------------ + +Each device tree must specify the following compatible values: + + "fsl,ls1021a" + +SoC-specific device tree bindings +------------------------------------------- + +Each device tree must specify the following SoC-specific compatible values: + + - compatible = "fsl,ls1021a-scfg": + scfg is the supplemental configuration unit, provides SoC specific + configuration and status registers for the chip.there isn't a dedicate + driver for it, device that has configuration and status register located + in this space can operate on it. Such as getting PEX port status. + + - compatible = "fsl,ls1021a-dcfg": + dcfg is the device configuration unit that provides general purpose + configuration and status for the device, there isn't a dedicate driver + for it, device that has configuration and status register located in + this space can operate on it. Such as setting the secondary core start + address and release the secondary core from holdoff and startup. |