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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-04 16:13:29 (GMT) |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-14 19:21:42 (GMT) |
| commit | ff2e27ae0b17f53a6a289c87d325f706598f3788 (patch) | |
| tree | 1288f491bce11b3d8a6d48604fd00d68bea6eb98 /arch/arm/mach-s5pv310 | |
| parent | 384895330e0f3954d9478fd0853145f9c169df12 (diff) | |
| download | linux-fsl-qoriq-ff2e27ae0b17f53a6a289c87d325f706598f3788.tar.xz | |
ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt. Move this into the common GIC code.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s5pv310')
| -rw-r--r-- | arch/arm/mach-s5pv310/cpu.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-s5pv310/include/mach/smp.h | 2 |
2 files changed, 0 insertions, 5 deletions
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index bce3e91..72ab289 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -24,8 +24,6 @@ #include <mach/regs-irq.h> -void __iomem *gic_cpu_base_addr; - extern int combiner_init(unsigned int combiner_nr, void __iomem *base, unsigned int irq_start); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); @@ -122,7 +120,6 @@ void __init s5pv310_init_irq(void) { int irq; - gic_cpu_base_addr = S5P_VA_GIC_CPU; gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); for (irq = 0; irq < MAX_COMBINER_NR; irq++) { diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h index b7ec252..e1cc6a2 100644 --- a/arch/arm/mach-s5pv310/include/mach/smp.h +++ b/arch/arm/mach-s5pv310/include/mach/smp.h @@ -9,8 +9,6 @@ #include <asm/hardware/gic.h> #include <asm/smp_mpidr.h> -extern void __iomem *gic_cpu_base_addr; - /* * We use IRQ1 as the IPI */ |