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| author | Catalin Marinas <catalin.marinas@arm.com> | 2009-07-24 11:35:06 (GMT) |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-07-24 11:35:06 (GMT) |
| commit | bdaaaec39792ee0035d6c5a5ad2520991e090a3c (patch) | |
| tree | 8e7b5f10c1d7c7e85c6f62304f18c16948681dea /arch/arm/mm | |
| parent | 8bdca0ac2b1ec35091941c57b4202f7096291c5b (diff) | |
| download | linux-fsl-qoriq-bdaaaec39792ee0035d6c5a5ad2520991e090a3c.tar.xz | |
nommu: Do not set PRRR and NMRR in proc-v7.S if !MMU
ARMv7-R profile CPUs do not have these registers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c19aecd..f3fa1c3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -234,7 +234,6 @@ __v7_setup: mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register -#endif /* * Memory region attributes with SCTLR.TRE=1 * @@ -267,6 +266,7 @@ __v7_setup: ldr r6, =0x40e040e0 @ NMRR mcr p15, 0, r5, c10, c2, 0 @ write PRRR mcr p15, 0, r6, c10, c2, 1 @ write NMRR +#endif adr r5, v7_crval ldmia r5, {r5, r6} #ifdef CONFIG_CPU_ENDIAN_BE8 |