diff options
| author | Vishwanath BS <vishwanath.bs@ti.com> | 2010-02-23 05:09:10 (GMT) |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2010-02-24 19:15:03 (GMT) |
| commit | 7356f0b26b3176610b4de439e8c7bfe10c797347 (patch) | |
| tree | b9a360d87fc520a8a7a8568c16f144350de63f8a /arch/arm/plat-omap | |
| parent | 678bc9a2eabb7f444ef8ad1cfc5ef394e2bd8bf2 (diff) | |
| download | linux-fsl-qoriq-7356f0b26b3176610b4de439e8c7bfe10c797347.tar.xz | |
OMAP3 clock: add support for 192Mhz DPLL4M2 output
In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at
192). This patch has changes to support this feature. 96MHz clock is
generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register.
SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's
functional clock. In summary changes done are:
1. Added a feature called omap3_has_192mhz_clk and enabled for 3630
2. Added a new clock node called omap_192m_alwon_ck
3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck
Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
[paul@pwsan.com: fixed whitespace]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index b80151c..ed8786c 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -439,6 +439,7 @@ extern u32 omap3_features; #define OMAP3_HAS_SGX BIT(2) #define OMAP3_HAS_NEON BIT(3) #define OMAP3_HAS_ISP BIT(4) +#define OMAP3_HAS_192MHZ_CLK BIT(5) #define OMAP3_HAS_FEATURE(feat,flag) \ static inline unsigned int omap3_has_ ##feat(void) \ @@ -451,5 +452,6 @@ OMAP3_HAS_FEATURE(sgx, SGX) OMAP3_HAS_FEATURE(iva, IVA) OMAP3_HAS_FEATURE(neon, NEON) OMAP3_HAS_FEATURE(isp, ISP) +OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) #endif |