diff options
| author | Steven J. Hill <sjhill@mips.com> | 2012-08-31 21:05:37 (GMT) |
|---|---|---|
| committer | Steven J. Hill <sjhill@mips.com> | 2012-09-13 20:43:47 (GMT) |
| commit | 0b271f5600b5ae56d331a18da830e33f9fb0acdc (patch) | |
| tree | d49f4e86e0563aa212545587adacb15170978082 /arch/mips/include/asm/gic.h | |
| parent | ec47b27434eff8ad41e7389efca1e5a6ca8b519a (diff) | |
| download | linux-fsl-qoriq-0b271f5600b5ae56d331a18da830e33f9fb0acdc.tar.xz | |
MIPS: Make GIC code platform independent.
The GIC interrupt code is used by multiple platforms and the
current code was half Malta dependent code. These changes
abstract away the platform specific differences.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Diffstat (limited to 'arch/mips/include/asm/gic.h')
| -rw-r--r-- | arch/mips/include/asm/gic.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 991b659..77207fa 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -341,15 +341,44 @@ struct gic_shared_intr_map { unsigned int local_intr_mask; }; +/* GIC nomenclature for Core Interrupt Pins. */ +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ +#define GIC_CPU_INT1 1 /* . */ +#define GIC_CPU_INT2 2 /* . */ +#define GIC_CPU_INT3 3 /* . */ +#define GIC_CPU_INT4 4 /* . */ +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ + +/* Local GIC interrupts. */ +#define GIC_INT_TMR (GIC_CPU_INT5) +#define GIC_INT_PERFCTR (GIC_CPU_INT5) + +/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */ +#define GIC_CPU_TO_VEC_OFFSET (2) + +/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ +#define GIC_PIN_TO_VEC_OFFSET (1) + +extern unsigned long _gic_base; +extern unsigned int gic_irq_base; +extern unsigned int gic_irq_flags[]; +extern struct gic_shared_intr_map gic_shared_intr_map[]; + extern void gic_init(unsigned long gic_base_addr, unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, unsigned int intrmap_size, unsigned int irqbase); +extern void gic_clocksource_init(unsigned int); extern unsigned int gic_get_int(void); extern void gic_send_ipi(unsigned int intr); extern unsigned int plat_ipi_call_int_xlate(unsigned int); extern unsigned int plat_ipi_resched_int_xlate(unsigned int); extern void gic_bind_eic_interrupt(int irq, int set); extern unsigned int gic_get_timer_pending(void); +extern void gic_enable_interrupt(int irq_vec); +extern void gic_disable_interrupt(int irq_vec); +extern void gic_irq_ack(struct irq_data *d); +extern void gic_finish_irq(struct irq_data *d); +extern void gic_platform_init(int irqs, struct irq_chip *irq_controller); #endif /* _ASM_GICREGS_H */ |