diff options
| author | Manuel Lauss <manuel.lauss@googlemail.com> | 2011-11-10 12:06:16 (GMT) |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-12-07 22:02:06 (GMT) |
| commit | f869d42e580f6260b5c29b5ab5c5cfcfd32a0756 (patch) | |
| tree | 279125640d5ae76e9bb8c278d34bea2a4591c254 /arch/mips/include/asm/mach-db1x00 | |
| parent | 64cd04d0cffa3b3af0e81aa3112b71f135739e1a (diff) | |
| download | linux-fsl-qoriq-f869d42e580f6260b5c29b5ab5c5cfcfd32a0756.tar.xz | |
MIPS: Alchemy: Improved DB1550 support, with audio and serial busses.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2868/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-db1x00')
| -rw-r--r-- | arch/mips/include/asm/mach-db1x00/bcsr.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-db1x00/db1x00.h | 16 |
2 files changed, 1 insertions, 17 deletions
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 0ef6300..bb9fc23 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -163,7 +163,7 @@ enum bcsr_whoami_boards { #define BCSR_BOARD_GPIO200RST 0x0400 #define BCSR_BOARD_PCICLKOUT 0x0800 #define BCSR_BOARD_PCICFG 0x1000 -#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ +#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */ #define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ #define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index a5affb0..51f1ebf 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -29,22 +29,6 @@ #include <asm/mach-au1x00/au1xxx_psc.h> -#ifdef CONFIG_MIPS_DB1550 - -#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX -#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX - -#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR -#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR -#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR -#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR - -#define NAND_PHYS_ADDR 0x20000000 - -#endif - /* * NAND defines * |