diff options
| author | David VomLehn <dvomlehn@cisco.com> | 2009-12-22 01:49:22 (GMT) |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-01-27 23:03:31 (GMT) |
| commit | 010c108d7af708d9e09b83724a058a76803fbc66 (patch) | |
| tree | 6b7108e6852b0306ecd686a8ce9b9ae5733985fa /arch/mips/include/asm/mipsregs.h | |
| parent | 59dfa2fcaecc39fb88bfa196cb15adca7146867a (diff) | |
| download | linux-fsl-qoriq-010c108d7af708d9e09b83724a058a76803fbc66.tar.xz | |
MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs
The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.
On MIPSR2 systems there is a solution - the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch uses
that bit to detect interrupts for MIPSR2 processors, which may be expected
to work regardless of how the timer interrupt may be routed in the hardware.
Signed-off-by: David VomLehn (dvomlehn@cisco.com)
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/804/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index a581d60..f4ab313 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -406,6 +406,16 @@ #define ST0_XX 0x80000000 /* MIPS IV naming */ /* + * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define INTCTLB_IPPCI 26 +#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) +#define INTCTLB_IPTI 29 +#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) + +/* * Bitfields and bit numbers in the coprocessor 0 cause register. * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. @@ -434,6 +444,8 @@ #define CAUSEF_IV (_ULCAST_(1) << 23) #define CAUSEB_CE 28 #define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_TI 30 +#define CAUSEF_TI (_ULCAST_(1) << 30) #define CAUSEB_BD 31 #define CAUSEF_BD (_ULCAST_(1) << 31) |