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| author | Chris Dearman <chris@mips.com> | 2006-08-07 14:08:01 (GMT) |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-09-27 12:37:33 (GMT) |
| commit | 847b9dfccad7dd34b2e44b1c6ceeb1c4cb88084a (patch) | |
| tree | 46374a118b2f42c17aef00ec478021043e56e38b /arch/mips/kernel/signal.c | |
| parent | bca70d24c09b740d6fd96b972011644cba8383d6 (diff) | |
| download | linux-fsl-qoriq-847b9dfccad7dd34b2e44b1c6ceeb1c4cb88084a.tar.xz | |
[MIPS] MT: Initialise all writable bits in Cause register to zero.
Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an
immediate exception when starting the second VPE.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/signal.c')
0 files changed, 0 insertions, 0 deletions