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| author | Scott Wood <scottwood@freescale.com> | 2014-04-07 23:49:35 (GMT) |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-04-07 23:49:35 (GMT) |
| commit | 62b8c978ee6b8d135d9e7953221de58000dba986 (patch) | |
| tree | 683b04b2e627f6710c22c151b23c8cc9a165315e /arch/mips | |
| parent | 78fd82238d0e5716578c326404184a27ba67fd6e (diff) | |
| download | linux-fsl-qoriq-62b8c978ee6b8d135d9e7953221de58000dba986.tar.xz | |
Rewind v3.13-rc3+ (78fd82238d0e5716) to v3.12
Diffstat (limited to 'arch/mips')
152 files changed, 7233 insertions, 2035 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 6e23912..d9d81c2 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -20,6 +20,7 @@ platforms += mti-sead3 platforms += netlogic platforms += pmcs-msp71xx platforms += pnx833x +platforms += powertv platforms += ralink platforms += rb532 platforms += sgi-ip22 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 650de39..f75ab4a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1,7 +1,6 @@ config MIPS bool default y - select ARCH_MIGHT_HAVE_PC_PARPORT select HAVE_CONTEXT_TRACKING select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE @@ -9,7 +8,6 @@ config MIPS select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_ARCH_KGDB - select HAVE_ARCH_TRACEHOOK select ARCH_HAVE_CUSTOM_GPIO_H select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACE_MCOUNT_TEST @@ -20,7 +18,6 @@ config MIPS select HAVE_KPROBES select HAVE_KRETPROBES select HAVE_DEBUG_KMEMLEAK - select HAVE_SYSCALL_TRACEPOINTS select ARCH_BINFMT_ELF_RANDOMIZE_PIE select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT select RTC_LIB if !MACH_LOONGSON @@ -149,7 +146,6 @@ config MIPS_COBALT select CSRC_R4K select CEVT_GT641XX select DMA_NONCOHERENT - select EARLY_PRINTK_8250 if EARLY_PRINTK select HW_HAS_PCI select I8253 select I8259 @@ -416,6 +412,23 @@ config PMC_MSP of integrated peripherals, interfaces and DSPs in addition to a variety of MIPS cores. +config POWERTV + bool "Cisco PowerTV" + select BOOT_ELF32 + select CEVT_R4K + select CPU_MIPSR2_IRQ_VI + select CPU_MIPSR2_IRQ_EI + select CSRC_POWERTV + select DMA_NONCOHERENT + select HW_HAS_PCI + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select USB_OHCI_LITTLE_ENDIAN + help + This enables support for the Cisco PowerTV Platform. + config RALINK bool "Ralink based machines" select CEVT_R4K @@ -798,6 +811,7 @@ source "arch/mips/jz4740/Kconfig" source "arch/mips/lantiq/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmcs-msp71xx/Kconfig" +source "arch/mips/powertv/Kconfig" source "arch/mips/ralink/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" @@ -876,6 +890,9 @@ config CSRC_BCM1480 config CSRC_IOASIC bool +config CSRC_POWERTV + bool + config CSRC_R4K bool @@ -1472,10 +1489,8 @@ config SYS_SUPPORTS_ZBOOT bool select HAVE_KERNEL_GZIP select HAVE_KERNEL_BZIP2 - select HAVE_KERNEL_LZ4 select HAVE_KERNEL_LZMA select HAVE_KERNEL_LZO - select HAVE_KERNEL_XZ config SYS_SUPPORTS_ZBOOT_UART16550 bool @@ -1962,7 +1977,6 @@ config MIPS_VPE_APSP_API config MIPS_CMP bool "MIPS CMP framework support" depends on SYS_SUPPORTS_MIPS_CMP - select SMP select SYNC_R4K select SYS_SUPPORTS_SMP select SYS_SUPPORTS_SCHED_SMT if SMP @@ -2126,6 +2140,7 @@ source "mm/Kconfig" config SMP bool "Multi-Processing support" depends on SYS_SUPPORTS_SMP + select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index b147e70..37871f0 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -20,14 +20,6 @@ config EARLY_PRINTK doesn't cooperate with an X server. You should normally say N here, unless you want to debug such a crash. -config EARLY_PRINTK_8250 - bool "8250/16550 and compatible serial early printk driver" - depends on EARLY_PRINTK - default n - help - If you say Y here, it will be possible to use a 8250/16550 serial - port as the boot console. - config CMDLINE_BOOL bool "Built-in kernel command line" default n diff --git a/arch/mips/Makefile b/arch/mips/Makefile index de300b9..ca8f834 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -285,19 +285,15 @@ endif # Other need ECOFF, so we build a 32-bit ELF binary for them which we then # convert to ECOFF using elf2ecoff. # -quiet_cmd_32 = OBJCOPY $@ - cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ vmlinux.32: vmlinux - $(call cmd,32) + $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ # # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit # ELF files from 32-bit files by conversion. # -quiet_cmd_64 = OBJCOPY $@ - cmd_64 = $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ vmlinux.64: vmlinux - $(call cmd,64) + $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ all: $(all-y) @@ -306,16 +302,10 @@ $(boot-y): $(vmlinux-32) FORCE $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \ $(bootvars-y) arch/mips/boot/$@ -ifdef CONFIG_SYS_SUPPORTS_ZBOOT # boot/compressed $(bootz-y): $(vmlinux-32) FORCE $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \ $(bootvars-y) 32bit-bfd=$(32bit-bfd) $@ -else -vmlinuz: FORCE - @echo ' CONFIG_SYS_SUPPORTS_ZBOOT is not enabled' - /bin/false -endif CLEAN_FILES += vmlinux.32 vmlinux.64 diff --git a/arch/mips/alchemy/devboards/db1235.c b/arch/mips/alchemy/devboards/db1235.c index bac19dc..c76a90f 100644 --- a/arch/mips/alchemy/devboards/db1235.c +++ b/arch/mips/alchemy/devboards/db1235.c @@ -59,7 +59,7 @@ void __init board_setup(void) ret = -ENODEV; } if (ret) - panic("cannot initialize board support"); + panic("cannot initialize board support\n"); } int __init db1235_arch_init(void) diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c index 516225d..c3b04c9 100644 --- a/arch/mips/ath79/dev-common.c +++ b/arch/mips/ath79/dev-common.c @@ -20,6 +20,7 @@ #include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ar933x_uart_platform.h> #include "common.h" #include "dev-common.h" @@ -67,11 +68,15 @@ static struct resource ar933x_uart_resources[] = { }, }; +static struct ar933x_uart_platform_data ar933x_uart_data; static struct platform_device ar933x_uart_device = { .name = "ar933x-uart", .id = -1, .resource = ar933x_uart_resources, .num_resources = ARRAY_SIZE(ar933x_uart_resources), + .dev = { + .platform_data = &ar933x_uart_data, + }, }; void __init ath79_register_uart(void) @@ -88,6 +93,7 @@ void __init ath79_register_uart(void) ath79_uart_data[0].uartclk = uart_clk_rate; platform_device_register(&ath79_uart_device); } else if (soc_is_ar933x()) { + ar933x_uart_data.uartclk = uart_clk_rate; platform_device_register(&ar933x_uart_device); } else { BUG(); diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index c52daf9..f3bf6d5 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile @@ -4,5 +4,4 @@ # obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o -obj-y += board.o obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c deleted file mode 100644 index f3f6bfe..0000000 --- a/arch/mips/bcm47xx/board.c +++ /dev/null @@ -1,309 +0,0 @@ -#include <linux/export.h> -#include <linux/string.h> -#include <bcm47xx_board.h> -#include <bcm47xx_nvram.h> - -struct bcm47xx_board_type { - const enum bcm47xx_board board; - const char *name; -}; - -struct bcm47xx_board_type_list1 { - struct bcm47xx_board_type board; - const char *value1; -}; - -struct bcm47xx_board_type_list2 { - struct bcm47xx_board_type board; - const char *value1; - const char *value2; -}; - -struct bcm47xx_board_type_list3 { - struct bcm47xx_board_type board; - const char *value1; - const char *value2; - const char *value3; -}; - -struct bcm47xx_board_store { - enum bcm47xx_board board; - char name[BCM47XX_BOARD_MAX_NAME]; -}; - -/* model_name */ -static const -struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = { - {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"}, - {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"}, - { {0}, 0}, -}; - -/* model_no */ -static const -struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = { - {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"}, - { {0}, 0}, -}; - -/* machine_name */ -static const -struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = { - {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"}, - { {0}, 0}, -}; - -/* hardware_version */ -static const -struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = { - {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"}, - {{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"}, - {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"}, - {{BCM47XX_BOARD_ASUS_WL500GD, "Asus WL500GD"}, "WL500gd-"}, - {{BCM47XX_BOARD_ASUS_WL500GPV1, "Asus WL500GP V1"}, "WL500gp-"}, - {{BCM47XX_BOARD_ASUS_WL500GPV2, "Asus WL500GP V2"}, "WL500GPV2-"}, - {{BCM47XX_BOARD_ASUS_WL500W, "Asus WL500W"}, "WL500gW-"}, - {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"}, - {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"}, - {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"}, - { {0}, 0}, -}; - -/* productid */ -static const -struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = { - {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"}, - {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"}, - {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"}, - {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U"}, - {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"}, - {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1"}, - {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1"}, - {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1"}, - {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP"}, - {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"}, - {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"}, - {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"}, - {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"}, - {{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"}, - {{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"}, - { {0}, 0}, -}; - -/* ModelId */ -static const -struct bcm47xx_board_type_list1 bcm47xx_board_list_ModelId[] __initconst = { - {{BCM47XX_BOARD_DELL_TM2300, "Dell WX-5565"}, "WX-5565"}, - {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"}, - {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"}, - {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"}, - { {0}, 0}, -}; - -/* melco_id or buf1falo_id */ -static const -struct bcm47xx_board_type_list1 bcm47xx_board_list_melco_id[] __initconst = { - {{BCM47XX_BOARD_BUFFALO_WBR2_G54, "Buffalo WBR2-G54"}, "29bb0332"}, - {{BCM47XX_BOARD_BUFFALO_WHR2_A54G54, "Buffalo WHR2-A54G54"}, "290441dd"}, - {{BCM47XX_BOARD_BUFFALO_WHR_G125, "Buffalo WHR-G125"}, "32093"}, - {{BCM47XX_BOARD_BUFFALO_WHR_G54S, "Buffalo WHR-G54S"}, "30182"}, - {{BCM47XX_BOARD_BUFFALO_WHR_HP_G54, "Buffalo WHR-HP-G54"}, "30189"}, - {{BCM47XX_BOARD_BUFFALO_WLA2_G54L, "Buffalo WLA2-G54L"}, "29129"}, - {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"}, - {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"}, - {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"}, - { {0}, 0}, -}; - -/* boot_hw_model, boot_hw_ver */ -static const -struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = { - /* like WRT160N v3.0 */ - {{BCM47XX_BOARD_CISCO_M10V1, "Cisco M10"}, "M10", "1.0"}, - /* like WRT310N v2.0 */ - {{BCM47XX_BOARD_CISCO_M20V1, "Cisco M20"}, "M20", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_E900V1, "Linksys E900 V1"}, "E900", "1.0"}, - /* like WRT160N v3.0 */ - {{BCM47XX_BOARD_LINKSYS_E1000V1, "Linksys E1000 V1"}, "E100", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_E1000V2, "Linksys E1000 V2"}, "E1000", "2.0"}, - {{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"}, - {{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"}, - {{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"}, - /* like WRT610N v2.0 */ - {{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_E4200V1, "Linksys E4200 V1"}, "E4200", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT150NV11, "Linksys WRT150N V1.1"}, "WRT150N", "1.1"}, - {{BCM47XX_BOARD_LINKSYS_WRT150NV1, "Linksys WRT150N V1"}, "WRT150N", "1"}, - {{BCM47XX_BOARD_LINKSYS_WRT160NV1, "Linksys WRT160N V1"}, "WRT160N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT160NV3, "Linksys WRT160N V3"}, "WRT160N", "3.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"}, - {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, - { {0}, 0}, -}; - -/* board_id */ -static const -struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = { - {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR4500V1, "Netgear WNDR4500 V1"}, "U12H189T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR4500V2, "Netgear WNDR4500 V2"}, "U12H224T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"}, - { {0}, 0}, -}; - -/* boardtype, boardnum, boardrev */ -static const -struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = { - {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, - {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, - {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, - { {0}, 0}, -}; - -static const -struct bcm47xx_board_type bcm47xx_board_unknown[] __initconst = { - {BCM47XX_BOARD_UNKNOWN, "Unknown Board"}, -}; - -static struct bcm47xx_board_store bcm47xx_board = {BCM47XX_BOARD_NO, "Unknown Board"}; - -static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void) -{ - char buf1[30]; - char buf2[30]; - char buf3[30]; - const struct bcm47xx_board_type_list1 *e1; - const struct bcm47xx_board_type_list2 *e2; - const struct bcm47xx_board_type_list3 *e3; - - if (bcm47xx_nvram_getenv("model_name", buf1, sizeof(buf1)) >= 0) { - for (e1 = bcm47xx_board_list_model_name; e1->value1; e1++) { - if (!strcmp(buf1, e1->value1)) - return &e1->board; - } - } - - if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) { - for (e1 = bcm47xx_board_list_model_no; e1->value1; e1++) { - if (strstarts(buf1, e1->value1)) - return &e1->board; - } - } - - if (bcm47xx_nvram_getenv("machine_name", buf1, sizeof(buf1)) >= 0) { - for (e1 = bcm47xx_board_list_machine_name; e1->value1; e1++) { - if (strstarts(buf1, e1->value1)) - return &e1->board; - } - } - - if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) { - for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) { - if (strstarts(buf1, e1->value1)) - return &e1->board; - } - } - - if (bcm47xx_nvram_getenv("productid", buf1, sizeof(buf1)) >= 0) { - for (e1 = bcm47xx_board_list_productid; e1->value1; e1++) { - if (!strcmp(buf1, e1->value1)) - return &e1->board; - } - } - - if (bcm47xx_nvram_getenv("ModelId", buf1, sizeof(buf1)) >= 0) { - for (e1 = bcm47xx_board_list_ModelId; e1->value1; e1++) { - if (!strcmp(buf1, e1->value1)) - return &e1->board; - } - } - - if (bcm47xx_nvram_getenv("melco_id", buf1, sizeof(buf1)) >= 0 || - bcm47xx_nvram_getenv("buf1falo_id", buf1, sizeof(buf1)) >= 0) { - /* buffalo hardware, check id for specific hardware matches */ - for (e1 = bcm47xx_board_list_melco_id; e1->value1; e1++) { - if (!strcmp(buf1, e1->value1)) - return &e1->board; - } - } - - if (bcm47xx_nvram_getenv("boot_hw_model", buf1, sizeof(buf1)) >= 0 && - bcm47xx_nvram_getenv("boot_hw_ver", buf2, sizeof(buf2)) >= 0) { - for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) { - if (!strcmp(buf1, e2->value1) && - !strcmp(buf2, e2->value2)) - return &e2->board; - } - } - - if (bcm47xx_nvram_getenv("board_id", buf1, sizeof(buf1)) >= 0) { - for (e1 = bcm47xx_board_list_board_id; e1->value1; e1++) { - if (!strcmp(buf1, e1->value1)) - return &e1->board; - } - } - - if (bcm47xx_nvram_getenv("boardtype", buf1, sizeof(buf1)) >= 0 && - bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0 && - bcm47xx_nvram_getenv("boardrev", buf3, sizeof(buf3)) >= 0) { - for (e3 = bcm47xx_board_list_board; e3->value1; e3++) { - if (!strcmp(buf1, e3->value1) && - !strcmp(buf2, e3->value2) && - !strcmp(buf3, e3->value3)) - return &e3->board; - } - } - return bcm47xx_board_unknown; -} - -void __init bcm47xx_board_detect(void) -{ - int err; - char buf[10]; - const struct bcm47xx_board_type *board_detected; - - if (bcm47xx_board.board != BCM47XX_BOARD_NO) - return; - - /* check if the nvram is available */ - err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf)); - - /* init of nvram failed, probably too early now */ - if (err == -ENXIO) { - return; - } - - board_detected = bcm47xx_board_get_nvram(); - bcm47xx_board.board = board_detected->board; - strlcpy(bcm47xx_board.name, board_detected->name, - BCM47XX_BOARD_MAX_NAME); -} - -enum bcm47xx_board bcm47xx_board_get(void) -{ - return bcm47xx_board.board; -} -EXPORT_SYMBOL(bcm47xx_board_get); - -const char *bcm47xx_board_get_name(void) -{ - return bcm47xx_board.name; -} -EXPORT_SYMBOL(bcm47xx_board_get_name); diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index b4c585b..cc40b74 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -190,23 +190,3 @@ int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len) return -ENOENT; } EXPORT_SYMBOL(bcm47xx_nvram_getenv); - -int bcm47xx_nvram_gpio_pin(const char *name) -{ - int i, err; - char nvram_var[10]; - char buf[30]; - - for (i = 0; i < 16; i++) { - err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i); - if (err <= 0) - continue; - err = bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf)); - if (err <= 0) - continue; - if (!strcmp(name, buf)) - return i; - } - return -ENOENT; -} -EXPORT_SYMBOL(bcm47xx_nvram_gpio_pin); diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 5cba318..8c155af 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -32,37 +32,12 @@ #include <asm/bootinfo.h> #include <asm/fw/cfe/cfe_api.h> #include <asm/fw/cfe/cfe_error.h> -#include <bcm47xx.h> -#include <bcm47xx_board.h> static int cfe_cons_handle; -static u16 get_chip_id(void) -{ - switch (bcm47xx_bus_type) { -#ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - return bcm47xx_bus.ssb.chip_id; -#endif -#ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: - return bcm47xx_bus.bcma.bus.chipinfo.id; -#endif - } - return 0; -} - const char *get_system_type(void) { - static char buf[50]; - u16 chip_id = get_chip_id(); - - snprintf(buf, sizeof(buf), - (chip_id > 0x9999) ? "Broadcom BCM%d (%s)" : - "Broadcom BCM%04X (%s)", - chip_id, bcm47xx_board_get_name()); - - return buf; + return "Broadcom BCM47XX"; } void prom_putchar(char c) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 1f30571..b2246cd 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -36,7 +36,6 @@ #include <asm/time.h> #include <bcm47xx.h> #include <bcm47xx_nvram.h> -#include <bcm47xx_board.h> union bcm47xx_bus bcm47xx_bus; EXPORT_SYMBOL(bcm47xx_bus); @@ -222,7 +221,6 @@ void __init plat_mem_setup(void) _machine_restart = bcm47xx_machine_restart; _machine_halt = bcm47xx_machine_halt; pm_power_off = bcm47xx_machine_halt; - bcm47xx_board_detect(); } static int __init bcm47xx_register_bus_complete(void) diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index 2c85d92..536374d 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c @@ -27,16 +27,10 @@ #include <linux/ssb/ssb.h> #include <asm/time.h> #include <bcm47xx.h> -#include <bcm47xx_nvram.h> -#include <bcm47xx_board.h> void __init plat_time_init(void) { unsigned long hz = 0; - u16 chip_id = 0; - char buf[10]; - int len; - enum bcm47xx_board board = bcm47xx_board_get(); /* * Use deterministic values for initial counter interrupt @@ -49,32 +43,15 @@ void __init plat_time_init(void) #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; - chip_id = bcm47xx_bus.ssb.chip_id; break; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2; - chip_id = bcm47xx_bus.bcma.bus.chipinfo.id; break; #endif } - if (chip_id == 0x5354) { - len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf)); - if (len >= 0 && !strncmp(buf, "200", 4)) - hz = 100000000; - } - - switch (board) { - case BCM47XX_BOARD_ASUS_WL520GC: - case BCM47XX_BOARD_ASUS_WL520GU: - hz = 100000000; - break; - default: - break; - } - if (!hz) hz = 100000000; diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index ca0c343..0048c08 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -37,10 +37,6 @@ vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o endif -ifdef CONFIG_KERNEL_XZ -vmlinuzobjs-y += $(obj)/../../lib/ashldi3.o -endif - targets += vmlinux.bin OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE @@ -48,10 +44,8 @@ $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE tool_$(CONFIG_KERNEL_GZIP) = gzip tool_$(CONFIG_KERNEL_BZIP2) = bzip2 -tool_$(CONFIG_KERNEL_LZ4) = lz4 tool_$(CONFIG_KERNEL_LZMA) = lzma tool_$(CONFIG_KERNEL_LZO) = lzo -tool_$(CONFIG_KERNEL_XZ) = xzkern targets += vmlinux.bin.z $(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c index a8c6fd6..2c95730 100644 --- a/arch/mips/boot/compressed/decompress.c +++ b/arch/mips/boot/compressed/decompress.c @@ -43,8 +43,7 @@ void error(char *x) /* activate the code for pre-boot environment */ #define STATIC static -#if defined(CONFIG_KERNEL_GZIP) || defined(CONFIG_KERNEL_XZ) || \ - defined(CONFIG_KERNEL_LZ4) +#ifdef CONFIG_KERNEL_GZIP void *memcpy(void *dest, const void *src, size_t n) { int i; @@ -55,8 +54,6 @@ void *memcpy(void *dest, const void *src, size_t n) d[i] = s[i]; return dest; } -#endif -#ifdef CONFIG_KERNEL_GZIP #include "../../../../lib/decompress_inflate.c" #endif @@ -73,10 +70,6 @@ void *memset(void *s, int c, size_t n) #include "../../../../lib/decompress_bunzip2.c" #endif -#ifdef CONFIG_KERNEL_LZ4 -#include "../../../../lib/decompress_unlz4.c" -#endif - #ifdef CONFIG_KERNEL_LZMA #include "../../../../lib/decompress_unlzma.c" #endif @@ -85,10 +78,6 @@ void *memset(void *s, int c, size_t n) #include "../../../../lib/decompress_unlzo.c" #endif -#ifdef CONFIG_KERNEL_XZ -#include "../../../../lib/decompress_unxz.c" -#endif - void decompress_kernel(unsigned long boot_heap_start) { unsigned long zimage_start, zimage_size; diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script index 5a33409..8e6b07c 100644 --- a/arch/mips/boot/compressed/ld.script +++ b/arch/mips/boot/compressed/ld.script @@ -8,9 +8,6 @@ OUTPUT_ARCH(mips) ENTRY(start) -PHDRS { - text PT_LOAD FLAGS(7); /* RWX */ -} SECTIONS { /* Text and read-only data */ @@ -18,7 +15,7 @@ SECTIONS .text : { *(.text) *(.rodata) - }: text + } /* End of text section */ /* Writable data */ diff --git a/arch/mips/boot/ecoff.h b/arch/mips/boot/ecoff.h index 7a75ce2..83e5c38 100644 --- a/arch/mips/boot/ecoff.h +++ b/arch/mips/boot/ecoff.h @@ -12,6 +12,7 @@ typedef struct filehdr { } FILHDR; #define FILHSZ sizeof(FILHDR) +#define OMAGIC 0407 #define MIPSEBMAGIC 0x160 #define MIPSELMAGIC 0x162 diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 331b837..b212ae1 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -999,7 +999,7 @@ void __init plat_mem_setup(void) if (total == 0) panic("Unable to allocate memory from " - "cvmx_bootmem_phy_alloc"); + "cvmx_bootmem_phy_alloc\n"); } /* @@ -1081,7 +1081,7 @@ void __init device_tree_init(void) /* Copy the default tree from init memory. */ initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); if (initial_boot_params == NULL) - panic("Could not allocate initial_boot_params"); + panic("Could not allocate initial_boot_params\n"); memcpy(initial_boot_params, fdt, dt_size); if (do_prune) { diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile index 558e949..61a334a 100644 --- a/arch/mips/cobalt/Makefile +++ b/arch/mips/cobalt/Makefile @@ -5,4 +5,5 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_EARLY_PRINTK) += console.o obj-$(CONFIG_MTD_PHYSMAP) += mtd.o diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c new file mode 100644 index 0000000..d1ba701 --- /dev/null +++ b/arch/mips/cobalt/console.c @@ -0,0 +1,20 @@ +/* + * (C) P. Horton 2006 + */ +#include <linux/io.h> +#include <linux/serial_reg.h> + +#include <cobalt.h> + +#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000)) + +void prom_putchar(char c) +{ + if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) + return; + + while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE)) + ; + + writeb(c, UART_BASE + UART_TX); +} diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 9a8c2fe..ec3b2c4 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -17,7 +17,6 @@ #include <asm/bootinfo.h> #include <asm/reboot.h> -#include <asm/setup.h> #include <asm/gt64120.h> #include <cobalt.h> @@ -113,8 +112,6 @@ void __init prom_init(void) } add_memory_region(0x0, memsz, BOOT_MEM_RAM); - - setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); } void __init prom_free_prom_memory(void) diff --git a/arch/mips/configs/db1235_defconfig b/arch/mips/configs/db1235_defconfig index 28e49f2..e2b4ad5 100644 --- a/arch/mips/configs/db1235_defconfig +++ b/arch/mips/configs/db1235_defconfig @@ -351,6 +351,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y CONFIG_MMC=y +CONFIG_MMC_CLKGATE=y CONFIG_MMC_AU1X=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig new file mode 100644 index 0000000..7fda0ce --- /dev/null +++ b/arch/mips/configs/powertv_defconfig @@ -0,0 +1,136 @@ +CONFIG_POWERTV=y +CONFIG_BOOTLOADER_FAMILY="R2" +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_HZ_1000=y +CONFIG_PREEMPT=y +# CONFIG_SECCOMP is not set +CONFIG_EXPERIMENTAL=y +CONFIG_CROSS_COMPILE="" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EXPERT=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS_ALL=y +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_PCI=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_IPV6_SIT is not set +CONFIG_IPV6_TUNNEL=y +CONFIG_NETFILTER=y +# CONFIG_BRIDGE_NETFILTER is not set +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_TBF=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_MISC_DEVICES is not set +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +# CONFIG_WLAN is not set +CONFIG_USB_RTL8150=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_VGA_ARB is not set +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_DNOTIFY is not set +CONFIG_FUSE_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_EARLY_PRINTK is not set +CONFIG_CMDLINE_BOOL=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index 41a2fa1..22afed1 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -118,7 +118,7 @@ * 7 FPU/R4k timer * * We handle the IRQ according to _our_ priority (see setup.c), - * then we just return. If multiple IRQs are pending then we will + * then we just return. If multiple IRQs are pending then we will * just take another exception, big deal. */ .align 5 @@ -146,7 +146,7 @@ /* * Find irq with highest priority */ - PTR_LA t1,cpu_mask_nr_tbl + PTR_LA t1,cpu_mask_nr_tbl 1: lw t2,(t1) nop and t2,t0 @@ -195,7 +195,7 @@ /* * Find irq with highest priority */ - PTR_LA t1,asic_mask_nr_tbl + PTR_LA t1,asic_mask_nr_tbl 2: lw t2,(t1) nop and t2,t0 @@ -221,7 +221,7 @@ FEXPORT(cpu_all_int) # HALT, timers, software junk li a0,DEC_CPU_IRQ_BASE srl t0,CAUSEB_IP - li t1,CAUSEF_IP>>CAUSEB_IP # mask + li t1,CAUSEF_IP>>CAUSEB_IP # mask b 1f li t2,4 # nr of bits / 2 diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index e04d973..4b3e3a4 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c @@ -1,7 +1,7 @@ /* * DEC I/O ASIC interrupts. * - * Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki + * Copyright (c) 2002, 2003 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -51,51 +51,22 @@ static struct irq_chip ioasic_irq_type = { .irq_unmask = unmask_ioasic_irq, }; -static void clear_ioasic_dma_irq(struct irq_data *d) +void clear_ioasic_dma_irq(unsigned int irq) { u32 sir; - sir = ~(1 << (d->irq - ioasic_irq_base)); + sir = ~(1 << (irq - ioasic_irq_base)); ioasic_write(IO_REG_SIR, sir); - fast_iob(); } static struct irq_chip ioasic_dma_irq_type = { .name = "IO-ASIC-DMA", - .irq_ack = clear_ioasic_dma_irq, + .irq_ack = ack_ioasic_irq, .irq_mask = mask_ioasic_irq, + .irq_mask_ack = ack_ioasic_irq, .irq_unmask = unmask_ioasic_irq, - .irq_eoi = clear_ioasic_dma_irq, }; -/* - * I/O ASIC implements two kinds of DMA interrupts, informational and - * error interrupts. - * - * The formers do not stop DMA and should be cleared as soon as possible - * so that if they retrigger before the handler has completed, usually as - * a side effect of actions taken by the handler, then they are reissued. - * These use the `handle_edge_irq' handler that clears the request right - * away. - * - * The latters stop DMA and do not resume it until the interrupt has been - * cleared. This cannot be done until after a corrective action has been - * taken and this also means they will not retrigger. Therefore they use - * the `handle_fasteoi_irq' handler that only clears the request on the - * way out. Because MIPS processor interrupt inputs, one of which the I/O - * ASIC is cascaded to, are level-triggered it is recommended that error - * DMA interrupt action handlers are registered with the IRQF_ONESHOT flag - * set so that they are run with the interrupt line masked. - * - * This mask has `1' bits in the positions of informational interrupts. - */ -#define IO_IRQ_DMA_INFO \ - (IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) | \ - IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) | \ - IO_IRQ_MASK(IO_INR_ISDN_TXDMA) | \ - IO_IRQ_MASK(IO_INR_ISDN_RXDMA) | \ - IO_IRQ_MASK(IO_INR_ASC_DMA)) - void __init init_ioasic_irqs(int base) { int i; @@ -108,9 +79,7 @@ void __init init_ioasic_irqs(int base) irq_set_chip_and_handler(i, &ioasic_irq_type, handle_level_irq); for (; i < base + IO_IRQ_LINES; i++) - irq_set_chip_and_handler(i, &ioasic_dma_irq_type, - 1 << (i - base) & IO_IRQ_DMA_INFO ? - handle_edge_irq : handle_fasteoi_irq); + irq_set_chip(i, &ioasic_dma_irq_type); ioasic_irq_base = base; } diff --git a/arch/mips/dec/prom/call_o32.S b/arch/mips/dec/prom/call_o32.S index 8c84981..c0d1522 100644 --- a/arch/mips/dec/prom/call_o32.S +++ b/arch/mips/dec/prom/call_o32.S @@ -14,7 +14,7 @@ /* Maximum number of arguments supported. Must be even! */ #define O32_ARGC 32 -/* Number of static registers we save. */ +/* Number of static registers we save. */ #define O32_STATC 11 /* Frame size for both of the above. */ #define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC) diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c index 4e1761e..468f665 100644 --- a/arch/mips/dec/prom/init.c +++ b/arch/mips/dec/prom/init.c @@ -104,7 +104,7 @@ void __init prom_init(void) if (prom_is_rex(magic)) rex_clear_cache(); - /* Register the early console. */ + /* Register the early console. */ register_prom_console(); /* Were we compiled with the right CPU option? */ diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c index 8c62316..0aadac7 100644 --- a/arch/mips/dec/prom/memory.c +++ b/arch/mips/dec/prom/memory.c @@ -22,7 +22,7 @@ volatile unsigned long mem_err; /* So we know an error occurred */ /* * Probe memory in 4MB chunks, waiting for an error to tell us we've fallen - * off the end of real memory. Only suitable for the 2100/3100's (PMAX). + * off the end of real memory. Only suitable for the 2100/3100's (PMAX). */ #define CHUNK_SIZE 0x400000 diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 56e6e2c..741cb42 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -65,7 +65,7 @@ EXPORT_SYMBOL(ioasic_base); /* * IRQ routing and priority tables. Priorites are set as follows: * - * KN01 KN230 KN02 KN02-BA KN02-CA KN03 + * KN01 KN230 KN02 KN02-BA KN02-CA KN03 * * MEMORY CPU CPU CPU ASIC CPU CPU * RTC CPU CPU CPU ASIC CPU CPU @@ -413,7 +413,7 @@ static void __init dec_init_kn02(void) /* * Machine-specific initialisation for KN02-BA, aka DS5000/1xx - * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka + * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka * DS5000/150, aka 4min. */ static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 1acbb8b..454ddf9 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -11,6 +11,5 @@ generic-y += sections.h generic-y += segment.h generic-y += serial.h generic-y += trace_clock.h -generic-y += preempt.h generic-y += ucontext.h generic-y += xor.h diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 3f74545..13d61c0 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -58,7 +58,7 @@ /* * Memory segments (64bit kernel mode addresses) - * The compatibility segments use the full 64-bit sign extended value. Note + * The compatibility segments use the full 64-bit sign extended value. Note * the R8000 doesn't have them so don't reference these in generic MIPS code. */ #define XKUSEG _CONST64_(0x0000000000000000) @@ -131,7 +131,7 @@ /* * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting - * the region, 3 bits for the CCA mode. This leaves 59 bits of which the + * the region, 3 bits for the CCA mode. This leaves 59 bits of which the * R8000 implements most with its 48-bit physical address space. */ #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 7eed2f2..08b6079 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -1,5 +1,5 @@ /* - * Atomic operations that C can't guarantee us. Useful for + * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. * * But use these as seldom as possible since they are much more slower diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index f26d8e1..314ab55 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -18,7 +18,7 @@ * over this barrier. All reads preceding this primitive are guaranteed * to access memory (but not necessarily other CPUs' caches) before any * reads following this primitive that depend on the data return by - * any of the preceding reads. This primitive is much lighter weight than + * any of the preceding reads. This primitive is much lighter weight than * rmb() on most CPUs, and is never heavier weight than is * rmb(). * @@ -43,7 +43,7 @@ * </programlisting> * * because the read of "*q" depends on the read of "p" and these - * two reads are separated by a read_barrier_depends(). However, + * two reads are separated by a read_barrier_depends(). However, * the following code, with the same initial values for "a" and "b": * * <programlisting> @@ -57,7 +57,7 @@ * </programlisting> * * does not enforce ordering, since there is no data dependency between - * the read of "a" and the read of "b". Therefore, on some CPUs, such + * the read of "a" and the read of "b". Therefore, on some CPUs, such * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() * in cases like this where there are no data dependencies. */ diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index c75025f..68f37e3 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -14,52 +14,56 @@ /* * Cache Operations available on all MIPS processors with R4000-style caches */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 /* * R4000-specific cacheops */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* * R4000SC and R4400SC-specific cacheops */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f /* * R5000-specific cacheops */ -#define R5K_Page_Invalidate_S 0x17 +#define R5K_Page_Invalidate_S 0x17 /* * RM7000-specific cacheops */ -#define Page_Invalidate_T 0x16 -#define Index_Store_Tag_T 0x0a -#define Index_Load_Tag_T 0x06 +#define Page_Invalidate_T 0x16 +#define Index_Store_Tag_T 0x0a +#define Index_Load_Tag_T 0x06 /* * R10000-specific cacheops @@ -67,22 +71,17 @@ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f - -/* - * Loongson2-specific cacheops - */ -#define Hit_Invalidate_I_Loongson23 0x00 +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f #endif /* __ASM_CACHEOPS_H */ diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h index be4d62a..a6e505a 100644 --- a/arch/mips/include/asm/dec/ioasic.h +++ b/arch/mips/include/asm/dec/ioasic.h @@ -31,6 +31,8 @@ static inline u32 ioasic_read(unsigned int reg) return ioasic_base[reg / 4]; } +extern void clear_ioasic_dma_irq(unsigned int irq); + extern void init_ioasic_irqs(int base); extern int dec_ioasic_clocksource_init(void); diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h index 8bd9597..a8665a7 100644 --- a/arch/mips/include/asm/dec/ioasic_addrs.h +++ b/arch/mips/include/asm/dec/ioasic_addrs.h @@ -40,7 +40,7 @@ #define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ #define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ #define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ -#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ +#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ #define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h index 88d9ffd..0eb3241 100644 --- a/arch/mips/include/asm/dec/kn01.h +++ b/arch/mips/include/asm/dec/kn01.h @@ -57,12 +57,12 @@ /* * System Control & Status Register bits. */ -#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ -#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ -#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ -#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ -#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ -#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ +#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ +#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ +#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ +#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ +#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ +#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ #define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */ #define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */ #define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */ diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h index 92c0fe2..69dc2a9 100644 --- a/arch/mips/include/asm/dec/kn02ca.h +++ b/arch/mips/include/asm/dec/kn02ca.h @@ -68,7 +68,7 @@ #define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */ #define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */ -#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ +#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ #define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */ #define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */ #define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */ diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h index c0ead63..4465777 100644 --- a/arch/mips/include/asm/dec/prom.h +++ b/arch/mips/include/asm/dec/prom.h @@ -49,7 +49,7 @@ #ifdef CONFIG_64BIT -#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ +#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ #else /* !CONFIG_64BIT */ diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index a66359e..cf3ae24 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -331,7 +331,6 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ dump_task_fpu(tsk, elf_fpregs) -#define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This yields a mask that user programs can use to figure out what diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 3296696..4d6fa0b 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -27,6 +27,13 @@ #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 +/* Don't support huge pages */ +#define KVM_HPAGE_GFN_SHIFT(x) 0 + +/* We don't currently support large pages. */ +#define KVM_NR_PAGE_SIZES 1 +#define KVM_PAGES_PER_HPAGE(x) 1 + /* Special address that contains the comm page, used for reducing # of traps */ diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h new file mode 100644 index 0000000..6cb30f2 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h @@ -0,0 +1,18 @@ +/* + * Platform data definition for Atheros AR933X UART + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _AR933X_UART_PLATFORM_H +#define _AR933X_UART_PLATFORM_H + +struct ar933x_uart_platform_data { + unsigned uartclk; +}; + +#endif /* _AR933X_UART_PLATFORM_H */ diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h deleted file mode 100644 index 00867dd..0000000 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +++ /dev/null @@ -1,110 +0,0 @@ -#ifndef __BCM47XX_BOARD_H -#define __BCM47XX_BOARD_H - -enum bcm47xx_board { - BCM47XX_BOARD_ASUS_RTAC66U, - BCM47XX_BOARD_ASUS_RTN10, - BCM47XX_BOARD_ASUS_RTN10D, - BCM47XX_BOARD_ASUS_RTN10U, - BCM47XX_BOARD_ASUS_RTN12, - BCM47XX_BOARD_ASUS_RTN12B1, - BCM47XX_BOARD_ASUS_RTN12C1, - BCM47XX_BOARD_ASUS_RTN12D1, - BCM47XX_BOARD_ASUS_RTN12HP, - BCM47XX_BOARD_ASUS_RTN15U, - BCM47XX_BOARD_ASUS_RTN16, - BCM47XX_BOARD_ASUS_RTN53, - BCM47XX_BOARD_ASUS_RTN66U, - BCM47XX_BOARD_ASUS_WL300G, - BCM47XX_BOARD_ASUS_WL320GE, - BCM47XX_BOARD_ASUS_WL330GE, - BCM47XX_BOARD_ASUS_WL500GD, - BCM47XX_BOARD_ASUS_WL500GPV1, - BCM47XX_BOARD_ASUS_WL500GPV2, - BCM47XX_BOARD_ASUS_WL500W, - BCM47XX_BOARD_ASUS_WL520GC, - BCM47XX_BOARD_ASUS_WL520GU, - BCM47XX_BOARD_ASUS_WL700GE, - BCM47XX_BOARD_ASUS_WLHDD, - - BCM47XX_BOARD_BELKIN_F7D4301, - - BCM47XX_BOARD_BUFFALO_WBR2_G54, - BCM47XX_BOARD_BUFFALO_WHR2_A54G54, - BCM47XX_BOARD_BUFFALO_WHR_G125, - BCM47XX_BOARD_BUFFALO_WHR_G54S, - BCM47XX_BOARD_BUFFALO_WHR_HP_G54, - BCM47XX_BOARD_BUFFALO_WLA2_G54L, - BCM47XX_BOARD_BUFFALO_WZR_G300N, - BCM47XX_BOARD_BUFFALO_WZR_RS_G54, - BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, - - BCM47XX_BOARD_CISCO_M10V1, - BCM47XX_BOARD_CISCO_M20V1, - - BCM47XX_BOARD_DELL_TM2300, - - BCM47XX_BOARD_DLINK_DIR130, - BCM47XX_BOARD_DLINK_DIR330, - - BCM47XX_BOARD_HUAWEI_E970, - - BCM47XX_BOARD_LINKSYS_E900V1, - BCM47XX_BOARD_LINKSYS_E1000V1, - BCM47XX_BOARD_LINKSYS_E1000V2, - BCM47XX_BOARD_LINKSYS_E1000V21, - BCM47XX_BOARD_LINKSYS_E1200V2, - BCM47XX_BOARD_LINKSYS_E2000V1, - BCM47XX_BOARD_LINKSYS_E3000V1, - BCM47XX_BOARD_LINKSYS_E3200V1, - BCM47XX_BOARD_LINKSYS_E4200V1, - BCM47XX_BOARD_LINKSYS_WRT150NV1, - BCM47XX_BOARD_LINKSYS_WRT150NV11, - BCM47XX_BOARD_LINKSYS_WRT160NV1, - BCM47XX_BOARD_LINKSYS_WRT160NV3, - BCM47XX_BOARD_LINKSYS_WRT300NV11, - BCM47XX_BOARD_LINKSYS_WRT310NV1, - BCM47XX_BOARD_LINKSYS_WRT310NV2, - BCM47XX_BOARD_LINKSYS_WRT54G3GV2, - BCM47XX_BOARD_LINKSYS_WRT610NV1, - BCM47XX_BOARD_LINKSYS_WRT610NV2, - BCM47XX_BOARD_LINKSYS_WRTSL54GS, - - BCM47XX_BOARD_MOTOROLA_WE800G, - BCM47XX_BOARD_MOTOROLA_WR850GP, - BCM47XX_BOARD_MOTOROLA_WR850GV2V3, - - BCM47XX_BOARD_NETGEAR_WGR614V8, - BCM47XX_BOARD_NETGEAR_WGR614V9, - BCM47XX_BOARD_NETGEAR_WNDR3300, - BCM47XX_BOARD_NETGEAR_WNDR3400V1, - BCM47XX_BOARD_NETGEAR_WNDR3400V2, - BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, - BCM47XX_BOARD_NETGEAR_WNDR3700V3, - BCM47XX_BOARD_NETGEAR_WNDR4000, - BCM47XX_BOARD_NETGEAR_WNDR4500V1, - BCM47XX_BOARD_NETGEAR_WNDR4500V2, - BCM47XX_BOARD_NETGEAR_WNR2000, - BCM47XX_BOARD_NETGEAR_WNR3500L, - BCM47XX_BOARD_NETGEAR_WNR3500U, - BCM47XX_BOARD_NETGEAR_WNR3500V2, - BCM47XX_BOARD_NETGEAR_WNR3500V2VC, - BCM47XX_BOARD_NETGEAR_WNR834BV2, - - BCM47XX_BOARD_PHICOMM_M1, - - BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE, - - BCM47XX_BOARD_ZTE_H218N, - - BCM47XX_BOARD_UNKNOWN, - BCM47XX_BOARD_NO, -}; - -#define BCM47XX_BOARD_MAX_NAME 30 - -void bcm47xx_board_detect(void); -enum bcm47xx_board bcm47xx_board_get(void); -const char *bcm47xx_board_get_name(void); - -#endif /* __BCM47XX_BOARD_H */ diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h index 36a3fc1..b8e7be8 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h @@ -48,6 +48,4 @@ static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6]) printk(KERN_WARNING "Can not parse mac address: %s\n", buf); } -int bcm47xx_nvram_gpio_pin(const char *name); - #endif /* __BCM47XX_NVRAM_H */ diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h index f9f4486..47fb247 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -52,11 +52,23 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 0; } +static inline void plat_extra_sync_for_device(struct device *dev) +{ + BUG(); +} + static inline int plat_device_is_coherent(struct device *dev) { return 1; } +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + BUG(); + return 0; +} + dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h deleted file mode 100644 index acce27f..0000000 --- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * CPU feature overrides for DECstation systems. Two variations - * are generally applicable. - * - * Copyright (C) 2013 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H - -/* Generic ones first. */ -#define cpu_has_tlb 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_fpu 1 -#define cpu_has_divec 0 -#define cpu_has_prefetch 0 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 -#define cpu_has_mips16 0 -#define cpu_has_mdmx 0 -#define cpu_has_mips3d 0 -#define cpu_has_smartmips 0 -#define cpu_has_rixi 0 -#define cpu_has_vtag_icache 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_pindexed_dcache 0 -#define cpu_has_local_ebase 0 -#define cpu_icache_snoops_remote_store 1 -#define cpu_has_mips_4 0 -#define cpu_has_mips_5 0 -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -/* R3k-specific ones. */ -#ifdef CONFIG_CPU_R3000 -#define cpu_has_4kex 0 -#define cpu_has_3k_cache 1 -#define cpu_has_4k_cache 0 -#define cpu_has_32fpr 0 -#define cpu_has_counter 0 -#define cpu_has_watch 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_llsc 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_mips_2 0 -#define cpu_has_mips_3 0 -#define cpu_has_nofpuex 1 -#define cpu_has_inclusive_pcaches 0 -#define cpu_dcache_line_size() 4 -#define cpu_icache_line_size() 4 -#define cpu_scache_line_size() 0 -#endif /* CONFIG_CPU_R3000 */ - -/* R4k-specific ones. */ -#ifdef CONFIG_CPU_R4X00 -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_32fpr 1 -#define cpu_has_counter 1 -#define cpu_has_watch 1 -#define cpu_has_vce 1 -#define cpu_has_cache_cdex_p 1 -#define cpu_has_cache_cdex_s 1 -#define cpu_has_llsc 1 -#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) -#define cpu_has_mips_2 1 -#define cpu_has_mips_3 1 -#define cpu_has_nofpuex 0 -#define cpu_has_inclusive_pcaches 1 -#define cpu_dcache_line_size() 16 -#define cpu_icache_line_size() 16 -#define cpu_scache_line_size() 32 -#endif /* CONFIG_CPU_R4X00 */ - -#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index a9e8f6b..74cb992 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -47,6 +47,16 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } +static inline void plat_extra_sync_for_device(struct device *dev) +{ +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + static inline int plat_device_is_coherent(struct device *dev) { #ifdef CONFIG_DMA_COHERENT diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h index 4ffddfd..06c4419 100644 --- a/arch/mips/include/asm/mach-ip27/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h @@ -58,6 +58,16 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } +static inline void plat_extra_sync_for_device(struct device *dev) +{ +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + static inline int plat_device_is_coherent(struct device *dev) { return 1; /* IP27 non-cohernet mode is unsupported */ diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h index 104cfbc..073f0c4 100644 --- a/arch/mips/include/asm/mach-ip32/dma-coherence.h +++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h @@ -80,6 +80,17 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } +static inline void plat_extra_sync_for_device(struct device *dev) +{ + return; +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + static inline int plat_device_is_coherent(struct device *dev) { return 0; /* IP32 is non-cohernet */ diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h index 949003e..9fc1e9a 100644 --- a/arch/mips/include/asm/mach-jazz/dma-coherence.h +++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h @@ -48,6 +48,16 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } +static inline void plat_extra_sync_for_device(struct device *dev) +{ +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + static inline int plat_device_is_coherent(struct device *dev) { return 0; diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index aeb2c05..e143305 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -53,6 +53,16 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) return 1; } +static inline void plat_extra_sync_for_device(struct device *dev) +{ +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + static inline int plat_device_is_coherent(struct device *dev) { return 0; diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h new file mode 100644 index 0000000..b341108 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic.h @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_ASIC_H +#define _ASM_MACH_POWERTV_ASIC_H + +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <asm/mach-powertv/asic_regs.h> + +#define DVR_CAPABLE (1<<0) +#define PCIE_CAPABLE (1<<1) +#define FFS_CAPABLE (1<<2) +#define DISPLAY_CAPABLE (1<<3) + +/* Platform Family types + * For compitability, the new value must be added in the end */ +enum family_type { + FAMILY_8500, + FAMILY_8500RNG, + FAMILY_4500, + FAMILY_1500, + FAMILY_8600, + FAMILY_4600, + FAMILY_4600VZA, + FAMILY_8600VZB, + FAMILY_1500VZE, + FAMILY_1500VZF, + FAMILY_8700, + FAMILIES +}; + +/* Register maps for each ASIC */ +extern const struct register_map calliope_register_map; +extern const struct register_map cronus_register_map; +extern const struct register_map gaia_register_map; +extern const struct register_map zeus_register_map; + +extern struct resource dvr_cronus_resources[]; +extern struct resource dvr_gaia_resources[]; +extern struct resource dvr_zeus_resources[]; +extern struct resource non_dvr_calliope_resources[]; +extern struct resource non_dvr_cronus_resources[]; +extern struct resource non_dvr_cronuslite_resources[]; +extern struct resource non_dvr_gaia_resources[]; +extern struct resource non_dvr_vz_calliope_resources[]; +extern struct resource non_dvr_vze_calliope_resources[]; +extern struct resource non_dvr_vzf_calliope_resources[]; +extern struct resource non_dvr_zeus_resources[]; + +extern void powertv_platform_init(void); +extern void platform_alloc_bootmem(void); +extern enum asic_type platform_get_asic(void); +extern enum family_type platform_get_family(void); +extern int platform_supports_dvr(void); +extern int platform_supports_ffs(void); +extern int platform_supports_pcie(void); +extern int platform_supports_display(void); +extern void configure_platform(void); + +/* Platform Resources */ +#define ASIC_RESOURCE_GET_EXISTS 1 +extern struct resource *asic_resource_get(const char *name); +extern void platform_release_memory(void *baddr, int size); + +/* USB configuration */ +struct usb_hcd; /* Forward reference */ +extern void platform_configure_usb_ehci(void); +extern void platform_unconfigure_usb_ehci(void); +extern void platform_configure_usb_ohci(void); +extern void platform_unconfigure_usb_ohci(void); + +/* Resource for ASIC registers */ +extern struct resource asic_resource; +extern int platform_usb_devices_init(struct platform_device **echi_dev, + struct platform_device **ohci_dev); + +/* Reboot Cause */ +extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); +extern void set_locked_reboot_cause(char code, unsigned int data, + unsigned int data2); + +enum sys_reboot_type { + sys_unknown_reboot = 0x00, /* Unknown reboot cause */ + sys_davic_change = 0x01, /* Reboot due to change in DAVIC + * mode */ + sys_user_reboot = 0x02, /* Reboot initiated by user */ + sys_system_reboot = 0x03, /* Reboot initiated by OS */ + sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */ + sys_silent_reboot = 0x05, /* Silent reboot */ + sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */ + sys_power_up_reboot = 0x07, /* Power on bootup. Older + * drivers may report as + * userReboot. */ + sys_code_change = 0x08, /* Reboot to take code change. + * Older drivers may report as + * userReboot. */ + sys_hardware_reset = 0x09, /* HW watchdog or front-panel + * reset button reset. Older + * drivers may report as + * userReboot. */ + sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ +}; + +#endif /* _ASM_MACH_POWERTV_ASIC_H */ diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h new file mode 100644 index 0000000..20348e8 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic_reg_map.h @@ -0,0 +1,90 @@ +/* + * asic_reg_map.h + * + * A macro-enclosed list of the elements for the register_map structure for + * use in defining and manipulating the structure. + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +REGISTER_MAP_ELEMENT(eic_slow0_strt_add) +REGISTER_MAP_ELEMENT(eic_cfg_bits) +REGISTER_MAP_ELEMENT(eic_ready_status) +REGISTER_MAP_ELEMENT(chipver3) +REGISTER_MAP_ELEMENT(chipver2) +REGISTER_MAP_ELEMENT(chipver1) +REGISTER_MAP_ELEMENT(chipver0) +REGISTER_MAP_ELEMENT(uart1_intstat) +REGISTER_MAP_ELEMENT(uart1_inten) +REGISTER_MAP_ELEMENT(uart1_config1) +REGISTER_MAP_ELEMENT(uart1_config2) +REGISTER_MAP_ELEMENT(uart1_divisorhi) +REGISTER_MAP_ELEMENT(uart1_divisorlo) +REGISTER_MAP_ELEMENT(uart1_data) +REGISTER_MAP_ELEMENT(uart1_status) +REGISTER_MAP_ELEMENT(int_stat_3) +REGISTER_MAP_ELEMENT(int_stat_2) +REGISTER_MAP_ELEMENT(int_stat_1) +REGISTER_MAP_ELEMENT(int_stat_0) +REGISTER_MAP_ELEMENT(int_config) +REGISTER_MAP_ELEMENT(int_int_scan) +REGISTER_MAP_ELEMENT(ien_int_3) +REGISTER_MAP_ELEMENT(ien_int_2) +REGISTER_MAP_ELEMENT(ien_int_1) +REGISTER_MAP_ELEMENT(ien_int_0) +REGISTER_MAP_ELEMENT(int_level_3_3) +REGISTER_MAP_ELEMENT(int_level_3_2) +REGISTER_MAP_ELEMENT(int_level_3_1) +REGISTER_MAP_ELEMENT(int_level_3_0) +REGISTER_MAP_ELEMENT(int_level_2_3) +REGISTER_MAP_ELEMENT(int_level_2_2) +REGISTER_MAP_ELEMENT(int_level_2_1) +REGISTER_MAP_ELEMENT(int_level_2_0) +REGISTER_MAP_ELEMENT(int_level_1_3) +REGISTER_MAP_ELEMENT(int_level_1_2) +REGISTER_MAP_ELEMENT(int_level_1_1) +REGISTER_MAP_ELEMENT(int_level_1_0) +REGISTER_MAP_ELEMENT(int_level_0_3) +REGISTER_MAP_ELEMENT(int_level_0_2) +REGISTER_MAP_ELEMENT(int_level_0_1) +REGISTER_MAP_ELEMENT(int_level_0_0) +REGISTER_MAP_ELEMENT(int_docsis_en) +REGISTER_MAP_ELEMENT(mips_pll_setup) +REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl) +REGISTER_MAP_ELEMENT(test_bus) +REGISTER_MAP_ELEMENT(crt_spare) +REGISTER_MAP_ELEMENT(usb2_ohci_int_mask) +REGISTER_MAP_ELEMENT(usb2_strap) +REGISTER_MAP_ELEMENT(ehci_hcapbase) +REGISTER_MAP_ELEMENT(ohci_hc_revision) +REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer) +REGISTER_MAP_ELEMENT(usb2_control) +REGISTER_MAP_ELEMENT(usb2_stbus_obc) +REGISTER_MAP_ELEMENT(usb2_stbus_mess_size) +REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size) +REGISTER_MAP_ELEMENT(pcie_regs) +REGISTER_MAP_ELEMENT(tim_ch) +REGISTER_MAP_ELEMENT(tim_cl) +REGISTER_MAP_ELEMENT(gpio_dout) +REGISTER_MAP_ELEMENT(gpio_din) +REGISTER_MAP_ELEMENT(gpio_dir) +REGISTER_MAP_ELEMENT(watchdog) +REGISTER_MAP_ELEMENT(front_panel) +REGISTER_MAP_ELEMENT(misc_clk_ctl1) +REGISTER_MAP_ELEMENT(misc_clk_ctl2) +REGISTER_MAP_ELEMENT(crt_ext_ctl) +REGISTER_MAP_ELEMENT(register_maps) diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h new file mode 100644 index 0000000..06712ab --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic_regs.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_MACH_POWERTV_ASIC_H_ +#define __ASM_MACH_POWERTV_ASIC_H_ +#include <linux/io.h> + +/* ASIC types */ +enum asic_type { + ASIC_UNKNOWN, + ASIC_ZEUS, + ASIC_CALLIOPE, + ASIC_CRONUS, + ASIC_CRONUSLITE, + ASIC_GAIA, + ASICS /* Number of supported ASICs */ +}; + +/* hardcoded values read from Chip Version registers */ +#define CRONUS_10 0x0B4C1C20 +#define CRONUS_11 0x0B4C1C21 +#define CRONUSLITE_10 0x0B4C1C40 + +#define NAND_FLASH_BASE 0x03000000 +#define CALLIOPE_IO_BASE 0x08000000 +#define GAIA_IO_BASE 0x09000000 +#define CRONUS_IO_BASE 0x09000000 +#define ZEUS_IO_BASE 0x09000000 + +#define ASIC_IO_SIZE 0x01000000 + +/* Definitions for backward compatibility */ +#define UART1_INTSTAT uart1_intstat +#define UART1_INTEN uart1_inten +#define UART1_CONFIG1 uart1_config1 +#define UART1_CONFIG2 uart1_config2 +#define UART1_DIVISORHI uart1_divisorhi +#define UART1_DIVISORLO uart1_divisorlo +#define UART1_DATA uart1_data +#define UART1_STATUS uart1_status + +/* ASIC register enumeration */ +union register_map_entry { + unsigned long phys; + u32 *virt; +}; + +#define REGISTER_MAP_ELEMENT(x) union register_map_entry x; +struct register_map { +#include <asm/mach-powertv/asic_reg_map.h> +}; +#undef REGISTER_MAP_ELEMENT + +/** + * register_map_offset_phys - add an offset to the physical address + * @map: Pointer to the &struct register_map + * @offset: Value to add + * + * Only adds the base to non-zero physical addresses + */ +static inline void register_map_offset_phys(struct register_map *map, + unsigned long offset) +{ +#define REGISTER_MAP_ELEMENT(x) do { \ + if (map->x.phys != 0) \ + map->x.phys += offset; \ + } while (false); + +#include <asm/mach-powertv/asic_reg_map.h> +#undef REGISTER_MAP_ELEMENT +} + +/** + * register_map_virtualize - Convert ®ister_map to virtual addresses + * @map: Pointer to ®ister_map to virtualize + */ +static inline void register_map_virtualize(struct register_map *map) +{ +#define REGISTER_MAP_ELEMENT(x) do { \ + map->x.virt = (!map->x.phys) ? NULL : \ + UNCAC_ADDR(phys_to_virt(map->x.phys)); \ + } while (false); + +#include <asm/mach-powertv/asic_reg_map.h> +#undef REGISTER_MAP_ELEMENT +} + +extern struct register_map _asic_register_map; +extern unsigned long asic_phy_base; + +/* + * Macros to interface to registers through their ioremapped address + * asic_reg_phys_addr Returns the physical address of the given register + * asic_reg_addr Returns the iomapped virtual address of the given + * register. + */ +#define asic_reg_addr(x) (_asic_register_map.x.virt) +#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \ + (unsigned long) asic_reg_addr(x)))) + +/* + * The asic_reg macro is gone. It should be replaced by either asic_read or + * asic_write, as appropriate. + */ + +#define asic_read(x) readl(asic_reg_addr(x)) +#define asic_write(v, x) writel(v, asic_reg_addr(x)) + +extern void asic_irq_init(void); +#endif diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h new file mode 100644 index 0000000..58c76ec --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2010 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ +#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_ +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 +#define cpu_has_dsp2 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_vint 1 +#define cpu_has_veic 1 +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#endif diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h new file mode 100644 index 0000000..f831672 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h @@ -0,0 +1,117 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Version from mach-generic modified to support PowerTV port + * Portions Copyright (C) 2009 Cisco Systems, Inc. + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> + * + */ + +#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H +#define __ASM_MACH_POWERTV_DMA_COHERENCE_H + +#include <linux/sched.h> +#include <linux/device.h> +#include <asm/mach-powertv/asic.h> + +static inline bool is_kseg2(void *addr) +{ + return (unsigned long)addr >= KSEG2; +} + +static inline unsigned long virt_to_phys_from_pte(void *addr) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *ptep, pte; + + unsigned long virt_addr = (unsigned long)addr; + unsigned long phys_addr = 0UL; + + /* get the page global directory. */ + pgd = pgd_offset_k(virt_addr); + + if (!pgd_none(*pgd)) { + /* get the page upper directory */ + pud = pud_offset(pgd, virt_addr); + if (!pud_none(*pud)) { + /* get the page middle directory */ + pmd = pmd_offset(pud, virt_addr); + if (!pmd_none(*pmd)) { + /* get a pointer to the page table entry */ + ptep = pte_offset(pmd, virt_addr); + pte = *ptep; + /* check for a valid page */ + if (pte_present(pte)) { + /* get the physical address the page is + * referring to */ + phys_addr = (unsigned long) + page_to_phys(pte_page(pte)); + /* add the offset within the page */ + phys_addr |= (virt_addr & ~PAGE_MASK); + } + } + } + } + + return phys_addr; +} + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + if (is_kseg2(addr)) + return phys_to_dma(virt_to_phys_from_pte(addr)); + else + return phys_to_dma(virt_to_phys(addr)); +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return phys_to_dma(page_to_phys(page)); +} + +static inline unsigned long plat_dma_addr_to_phys(struct device *dev, + dma_addr_t dma_addr) +{ + return dma_to_phys(dma_addr); +} + +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, + size_t size, enum dma_data_direction direction) +{ +} + +static inline int plat_dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if (mask < DMA_BIT_MASK(24)) + return 0; + + return 1; +} + +static inline void plat_extra_sync_for_device(struct device *dev) +{ +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + +static inline int plat_device_is_coherent(struct device *dev) +{ + return 0; +} + +#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h new file mode 100644 index 0000000..6c463be --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/interrupts.h @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ +#define _ASM_MACH_POWERTV_INTERRUPTS_H_ + +/* + * Defines for all of the interrupt lines + */ + +/* Definitions for backward compatibility */ +#define kIrq_Uart1 irq_uart1 + +#define ibase 0 + +/*------------- Register: int_stat_3 */ +/* 126 unused (bit 31) */ +#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */ +#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */ +#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */ +#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */ +#define irq_fdma_gp (ibase+122) /* FDMA GP Output */ +#define irq_mips_pic (ibase+121) /* MIPS Performance Counter + * Interrupt */ +#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */ +#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt + * -- Ored by glue logic inside + * SPARC ILC (see + * INT_MEM_PROT_STAT, below, + * for individual interrupts) + */ +/* 118 unused (bit 22) */ +#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by + * glue logic inside SPARC ILC + * (see INT_SBAG_STAT, below, + * for individual interrupts) */ +#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ +#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ +/* 114 unused (bit 18) */ +#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- + * Ored by glue logic inside + * SPARC ILC (see + * INT_MAILBOX_STAT, below, for + * individual interrupts) */ +#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */ +#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */ +#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse + * Status 3 */ +#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse + * Status 3 */ +#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0 + * Interrupt */ +#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1 + * Interrupt */ +#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE + * Interrupt */ +#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0 + * Interrupt */ +#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1 + * Interrupt */ +#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE + * Interrupt */ +#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */ +#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA + * Interrupt */ +#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */ +#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */ +#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */ +#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */ +#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */ +#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */ +/*------------- Register: int_stat_2 */ +#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */ +#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */ +#define irq_timer2 (ibase+93) /* Programmable Timer + * Interrupt 2 */ +#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */ +#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */ +#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */ +#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */ +#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */ +#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */ +#define irq_sata (ibase+87) /* SATA 1 Interrupt */ +#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ +#define irq_dtcp (ibase+86) /* DTCP Interrupt */ +#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ +/* 84 unused (bit 20) */ +/* 83 unused (bit 19) */ +/* 82 unused (bit 18) */ +#define irq_sata2 (ibase+81) /* SATA2 Interrupt */ +#define irq_uart2 (ibase+80) /* UART2 Interrupt */ +#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 + * Host module) */ +#define irq_pod (ibase+78) /* POD Interrupt */ +#define irq_slave_usb (ibase+77) /* Slave USB */ +#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */ +#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */ +#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */ +#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */ +#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */ +#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */ +#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ +#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ +#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ +/* 67 unused (bit 03) */ +/* 66 unused (bit 02) */ +/* 65 unused (bit 01) */ +/* 64 unused (bit 00) */ +/*------------- Register: int_stat_1 */ +/* 63 unused (bit 31) */ +/* 62 unused (bit 30) */ +/* 61 unused (bit 29) */ +/* 60 unused (bit 28) */ +/* 59 unused (bit 27) */ +/* 58 unused (bit 26) */ +/* 57 unused (bit 25) */ +/* 56 unused (bit 24) */ +#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory + * Interrupt */ +#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit + * Interrupt */ +#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit + * Interrupt */ +#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error + * Interrupt */ +#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive + * Interrupt */ +#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive + * Interrupt */ +#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error + * Interrupt */ +#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play + * Interrupt */ +#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error + * Interrupt */ +#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High + * (Chans 63-32) */ +#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low + * (Chans 31-0) */ +#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High + * (Chans 63-32) */ +#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low + * (Chans 31-0) */ +#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error + * Interrupt */ +#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */ +#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready + * Interrupt */ +#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */ +#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O + * Module */ +#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O + * Module (ABE_intN) */ +#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or + * Discontinuity 1 */ +#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or + * Discontinuity 2 */ +#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect + * (PEI) */ +#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error + * detect */ +#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */ +/*------------- Register: int_stat_0 */ +#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O + * Module */ +#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O + * Module */ +#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha + * (chan 3) Transmission + * Completed OK */ +#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2) + * Transmission Completed OK */ +#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation + * (chan 1) Transmission + * Completed OK */ +#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha + * (chan 3)Transmission + * completed with Errors. */ +#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2) + * Transmission completed with + * Errors. */ +#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation + * (chan 1) Transmission + * completed with Errors */ +#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha + * for N times. Aloha retry + * timeout for channel 3. */ +#define irq_timer1 (ibase+22) /* Programmable Timer + * Interrupt */ +#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */ +#define irq_i2c (ibase+20) /* I2C Module Interrupt */ +#define irq_spi (ibase+19) /* SPI Module Interrupt */ +#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */ +#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or + * Splice Detect Interrupt */ +#define irq_se_micro (ibase+16) /* Secure Micro I/F Module + * Interrupt */ +#define irq_uart1 (ibase+15) /* UART Interrupt */ +#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */ +#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */ +#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */ +#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ +#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error + * Interrupt */ +/* 9 unused (bit 09) */ +/* 8 unused (bit 08) */ +#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error + * Interrupt */ +#define irq_psilength_err (ibase+6) /* QAM PSI Length Error + * Interrupt */ +#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From + * Forward Path Reference - + * every 3ms when forward Mbits + * and forward slot control + * bytes are updated. */ +#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from + * Reverse Path Reference - + * delayed from forward mark by + * the ranging delay plus a + * fixed amount. When reverse + * Mbits and reverse slot + * control bytes are updated. + * Occurs every 3ms for 3.0M and + * 1.554 M upstream rates and + * every 6 ms for 256K upstream + * rate. */ +#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on + * Channel 1. */ +#define irq_reservation (ibase+2) /* Partial (or Incremental) + * Reservation Message Completed + * or Slotted aloha verify for + * channel 1. */ +#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify + * Interrupt or Reservation + * increment completed for + * channel 3. */ +#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ +#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h new file mode 100644 index 0000000..c86ef09 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/ioremap.h @@ -0,0 +1,167 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Portions Copyright (C) Cisco Systems, Inc. + */ +#ifndef __ASM_MACH_POWERTV_IOREMAP_H +#define __ASM_MACH_POWERTV_IOREMAP_H + +#include <linux/types.h> +#include <linux/log2.h> +#include <linux/compiler.h> + +#include <asm/pgtable-bits.h> +#include <asm/addrspace.h> + +/* We're going to mess with bits, so get sizes */ +#define IOR_BPC 8 /* Bits per char */ +#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t)) +#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t)) + +/* + * Define the granularity of physical/DMA mapping in terms of the number + * of bits that defines the offset within a grain. These will be the + * least significant bits of the address. The rest of a physical or DMA + * address will be used to index into an appropriate table to find the + * offset to add to the address to yield the corresponding DMA or physical + * address, respectively. + */ +#define IOR_LSBITS 22 /* Bits in a grain */ + +/* + * Compute the number of most significant address bits after removing those + * used for the offset within a grain and then compute the number of table + * entries for the conversion. + */ +#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS) +#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS) + +#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS) +#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS) + +/* + * Define data structures used as elements in the arrays for the conversion + * between physical and DMA addresses. We do some slightly fancy math to + * compute the width of the offset element of the conversion tables so + * that we can have the smallest conversion tables. Next, round up the + * sizes to the next higher power of two, i.e. the offset element will have + * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any + * bits. Finally, we compute a shift value that puts the most significant + * bits of the offset into the most significant bits of the offset element. + * This makes it more efficient on processors without barrel shifters and + * easier to see the values if the conversion table is dumped in binary. + */ +#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n)) +#define IOR_OFFSET_WIDTH(n) \ + (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n)) + +#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS) +#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS) + +#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS) +#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS) + +struct ior_phys_to_dma { + dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed + __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC)); +}; + +struct ior_dma_to_phys { + dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed + __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC)); +}; + +extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA]; +extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS]; + +static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys) +{ + return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset; +} + +static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma) +{ + return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset; +} + +/* These are not portable and should not be used in drivers. Drivers should + * be using ioremap() and friends to map physical addresses to virtual + * addresses and dma_map*() and friends to map virtual addresses into DMA + * addresses and back. + */ +static inline dma_addr_t phys_to_dma(phys_addr_t phys) +{ + return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT); +} + +static inline phys_addr_t dma_to_phys(dma_addr_t dma) +{ + return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT); +} + +extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias, + dma_addr_t size); + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +/* + * Handle the special case of addresses the area aliased into the first + * 512 MiB of the processor's physical address space. These turn into either + * kseg0 or kseg1 addresses, depending on flags. + */ +static inline void __iomem *plat_ioremap(phys_t start, unsigned long size, + unsigned long flags) +{ + phys_addr_t start_offset; + void __iomem *result = NULL; + + /* Start by checking to see whether this is an aliased address */ + start_offset = _dma_to_phys_offset_raw(start); + + /* + * If: + * o the memory is aliased into the first 512 MiB, and + * o the start and end are in the same RAM bank, and + * o we don't have a zero size or wrap around, and + * o we are supposed to create an uncached mapping, + * handle this is a kseg0 or kseg1 address + */ + if (start_offset != 0) { + phys_addr_t last; + dma_addr_t dma_to_phys_offset; + + last = start + size - 1; + dma_to_phys_offset = + _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT; + + if (dma_to_phys_offset == start_offset && + size != 0 && start <= last) { + phys_t adjusted_start; + adjusted_start = start + start_offset; + if (flags == _CACHE_UNCACHED) + result = (void __iomem *) (unsigned long) + CKSEG1ADDR(adjusted_start); + else + result = (void __iomem *) (unsigned long) + CKSEG0ADDR(adjusted_start); + } + } + + return result; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} +#endif /* __ASM_MACH_POWERTV_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h new file mode 100644 index 0000000..4bd5d0c --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/irq.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_IRQ_H +#define _ASM_MACH_POWERTV_IRQ_H +#include <asm/mach-powertv/interrupts.h> + +#define MIPS_CPU_IRQ_BASE ibase +#define NR_IRQS 127 +#endif diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h new file mode 100644 index 0000000..6f3e9a0 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* + * Local definitions for the powertv PCI code + */ + +#ifndef _POWERTV_PCI_POWERTV_PCI_H_ +#define _POWERTV_PCI_POWERTV_PCI_H_ +extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +extern int asic_pcie_init(void); +extern int asic_pcie_init(void); + +extern int log_level; +#endif diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h new file mode 100644 index 0000000..c5651c8 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/war.h @@ -0,0 +1,27 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * This version for the PowerTV platform copied from the Malta version. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + * Portions copyright (C) 2009 Cisco Systems, Inc. + */ +#ifndef __ASM_MACH_POWERTV_WAR_H +#define __ASM_MACH_POWERTV_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_POWERTV_WAR_H */ diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h index e332279..a02596c 100644 --- a/arch/mips/include/asm/mips-boards/piix4.h +++ b/arch/mips/include/asm/mips-boards/piix4.h @@ -1,7 +1,6 @@ /* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2013 Imagination Technologies Ltd. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -21,26 +20,61 @@ #ifndef __ASM_MIPS_BOARDS_PIIX4_H #define __ASM_MIPS_BOARDS_PIIX4_H -/* PIRQX Route Control */ -#define PIIX4_FUNC0_PIRQRC 0x60 -#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) -#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf -#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 -/* Top Of Memory */ -#define PIIX4_FUNC0_TOM 0x69 -#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 -/* Deterministic Latency Control */ -#define PIIX4_FUNC0_DLC 0x82 -#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) -#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) -#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) - -/* IDE Timing */ -#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 -#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41 -#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7) -#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42 -#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43 -#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7) +/************************************************************************ + * IO register offsets + ************************************************************************/ +#define PIIX4_ICTLR1_ICW1 0x20 +#define PIIX4_ICTLR1_ICW2 0x21 +#define PIIX4_ICTLR1_ICW3 0x21 +#define PIIX4_ICTLR1_ICW4 0x21 +#define PIIX4_ICTLR2_ICW1 0xa0 +#define PIIX4_ICTLR2_ICW2 0xa1 +#define PIIX4_ICTLR2_ICW3 0xa1 +#define PIIX4_ICTLR2_ICW4 0xa1 +#define PIIX4_ICTLR1_OCW1 0x21 +#define PIIX4_ICTLR1_OCW2 0x20 +#define PIIX4_ICTLR1_OCW3 0x20 +#define PIIX4_ICTLR1_OCW4 0x20 +#define PIIX4_ICTLR2_OCW1 0xa1 +#define PIIX4_ICTLR2_OCW2 0xa0 +#define PIIX4_ICTLR2_OCW3 0xa0 +#define PIIX4_ICTLR2_OCW4 0xa0 + + +/************************************************************************ + * Register encodings. + ************************************************************************/ +#define PIIX4_OCW2_NSEOI (0x1 << 5) +#define PIIX4_OCW2_SEOI (0x3 << 5) +#define PIIX4_OCW2_RNSEOI (0x5 << 5) +#define PIIX4_OCW2_RAEOIS (0x4 << 5) +#define PIIX4_OCW2_RAEOIC (0x0 << 5) +#define PIIX4_OCW2_RSEOI (0x7 << 5) +#define PIIX4_OCW2_SP (0x6 << 5) +#define PIIX4_OCW2_NOP (0x2 << 5) + +#define PIIX4_OCW2_SEL (0x0 << 3) + +#define PIIX4_OCW2_ILS_0 0 +#define PIIX4_OCW2_ILS_1 1 +#define PIIX4_OCW2_ILS_2 2 +#define PIIX4_OCW2_ILS_3 3 +#define PIIX4_OCW2_ILS_4 4 +#define PIIX4_OCW2_ILS_5 5 +#define PIIX4_OCW2_ILS_6 6 +#define PIIX4_OCW2_ILS_7 7 +#define PIIX4_OCW2_ILS_8 0 +#define PIIX4_OCW2_ILS_9 1 +#define PIIX4_OCW2_ILS_10 2 +#define PIIX4_OCW2_ILS_11 3 +#define PIIX4_OCW2_ILS_12 4 +#define PIIX4_OCW2_ILS_13 5 +#define PIIX4_OCW2_ILS_14 6 +#define PIIX4_OCW2_ILS_15 7 + +#define PIIX4_OCW3_SEL (0x1 << 3) + +#define PIIX4_OCW3_IRR 0x2 +#define PIIX4_OCW3_ISR 0x3 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */ diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index e277bba..3b29079 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -24,21 +24,21 @@ #endif /* SMTC */ #include <asm-generic/mm_hooks.h> +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ do { \ extern void tlbmiss_handler_setup_pgd(unsigned long); \ tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ } while (0) -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT #define TLBMISS_HANDLER_SETUP() \ do { \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ - write_c0_xcontext((unsigned long) smp_processor_id() << \ - SMP_CPUID_REGSHIFT); \ + write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ } while (0) -#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ +#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ /* * For the fast tlb miss handlers, we keep a per cpu array of pointers @@ -47,11 +47,21 @@ do { \ */ extern unsigned long pgd_current[]; +#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ + pgd_current[smp_processor_id()] = (unsigned long)(pgd) + +#ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << \ - SMP_CPUID_REGSHIFT); \ + write_c0_context((unsigned long) smp_processor_id() << 25); \ back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) +#endif +#ifdef CONFIG_64BIT +#define TLBMISS_HANDLER_SETUP() \ + write_c0_context((unsigned long) smp_processor_id() << 26); \ + back_to_back_c0_hazard(); \ + TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) +#endif #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index 470f209..17daffb2 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -69,7 +69,6 @@ void nlm_hal_init(void); int xlp_get_dram_map(int n, uint64_t *dram_map); /* Device tree related */ -void xlp_early_init_devtree(void); void *xlp_dt_init(void *fdtp); static inline int cpu_is_xlpii(void) diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h index df69bfd..a76fe5a 100644 --- a/arch/mips/include/asm/octeon/cvmx-pip.h +++ b/arch/mips/include/asm/octeon/cvmx-pip.h @@ -192,13 +192,13 @@ typedef struct { /* Number of packets processed by PIP */ uint32_t packets; /* - * Number of identified L2 multicast packets. Does not + * Number of indentified L2 multicast packets. Does not * include broadcast packets. Only includes packets whose * parse mode is SKIP_TO_L2 */ uint32_t multicast_packets; /* - * Number of identified L2 broadcast packets. Does not + * Number of indentified L2 broadcast packets. Does not * include multicast packets. Only includes packets whose * parse mode is SKIP_TO_L2 */ diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h index b336037..881d18b 100644 --- a/arch/mips/include/asm/pgalloc.h +++ b/arch/mips/include/asm/pgalloc.h @@ -80,12 +80,9 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, struct page *pte; pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); - if (!pte) - return NULL; - clear_highpage(pte); - if (!pgtable_page_ctor(pte)) { - __free_page(pte); - return NULL; + if (pte) { + clear_highpage(pte); + pgtable_page_ctor(pte); } return pte; } diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h index ccd2b75..1e7e096 100644 --- a/arch/mips/include/asm/prom.h +++ b/arch/mips/include/asm/prom.h @@ -17,8 +17,22 @@ #include <linux/types.h> #include <asm/bootinfo.h> +extern int early_init_dt_scan_memory_arch(unsigned long node, + const char *uname, int depth, void *data); + extern void device_tree_init(void); +static inline unsigned long pci_address_to_pio(phys_addr_t address) +{ + /* + * The ioport address can be directly used by inX() / outX() + */ + BUG_ON(address > IO_SPACE_LIMIT); + + return (unsigned long) address; +} +#define pci_address_to_pio pci_address_to_pio + struct boot_param_header; extern void __dt_setup_arch(struct boot_param_header *bph); diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index 7bba9da..5e6cd09 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -81,6 +81,7 @@ static inline long regs_return_value(struct pt_regs *regs) #define instruction_pointer(regs) ((regs)->cp0_epc) #define profile_pc(regs) instruction_pointer(regs) +#define user_stack_pointer(r) ((r)->regs[29]) extern asmlinkage void syscall_trace_enter(struct pt_regs *regs); extern asmlinkage void syscall_trace_leave(struct pt_regs *regs); @@ -99,17 +100,4 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs) (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \ }) -/* Helpers for working with the user stack pointer */ - -static inline unsigned long user_stack_pointer(struct pt_regs *regs) -{ - return regs->regs[29]; -} - -static inline void user_stack_pointer_set(struct pt_regs *regs, - unsigned long val) -{ - regs->regs[29] = val; -} - #endif /* _ASM_PTRACE_H */ diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index 34d1a19..a0b2650 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -15,7 +15,6 @@ #include <asm/asm.h> #include <asm/cacheops.h> #include <asm/cpu-features.h> -#include <asm/cpu-type.h> #include <asm/mipsmtregs.h> /* @@ -163,15 +162,7 @@ static inline void flush_scache_line_indexed(unsigned long addr) static inline void flush_icache_line(unsigned long addr) { __iflush_prologue - switch (boot_cpu_type()) { - case CPU_LOONGSON2: - cache_op(Hit_Invalidate_I_Loongson23, addr); - break; - - default: - cache_op(Hit_Invalidate_I, addr); - break; - } + cache_op(Hit_Invalidate_I, addr); __iflush_epilogue } @@ -217,15 +208,7 @@ static inline void flush_scache_line(unsigned long addr) */ static inline void protected_flush_icache_line(unsigned long addr) { - switch (boot_cpu_type()) { - case CPU_LOONGSON2: - protected_cache_op(Hit_Invalidate_I_Loongson23, addr); - break; - - default: - protected_cache_op(Hit_Invalidate_I, addr); - break; - } + protected_cache_op(Hit_Invalidate_I, addr); } /* @@ -429,8 +412,8 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) /* build blast_xxx_range, protected_blast_xxx_range */ -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ -static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ +static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ unsigned long end) \ { \ unsigned long lsize = cpu_##desc##_line_size(); \ @@ -449,15 +432,13 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, __##pfx##flush_epilogue \ } -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \ - protected_, loongson23_) -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) /* blast_inv_dcache_range */ -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) #endif /* _ASM_R4KCACHE_H */ diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index d7bfdeb..e26589e 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -5,14 +5,6 @@ extern void setup_early_printk(void); -#ifdef CONFIG_EARLY_PRINTK_8250 -extern void setup_8250_early_printk_port(unsigned long base, - unsigned int reg_shift, unsigned int timeout); -#else -static inline void setup_8250_early_printk_port(unsigned long base, - unsigned int reg_shift, unsigned int timeout) {} -#endif - extern void set_handler(unsigned long offset, void *addr, unsigned long len); extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 4857e2c..23fc95e 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -17,7 +17,6 @@ #include <asm/asmmacro.h> #include <asm/mipsregs.h> #include <asm/asm-offsets.h> -#include <asm/thread_info.h> /* * For SMTC kernel, global IE should be left set, and interrupts @@ -94,8 +93,21 @@ .endm #ifdef CONFIG_SMP +#ifdef CONFIG_MIPS_MT_SMTC +#define PTEBASE_SHIFT 19 /* TCBIND */ +#define CPU_ID_REG CP0_TCBIND +#define CPU_ID_MFC0 mfc0 +#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) +#define PTEBASE_SHIFT 48 /* XCONTEXT */ +#define CPU_ID_REG CP0_XCONTEXT +#define CPU_ID_MFC0 MFC0 +#else +#define PTEBASE_SHIFT 23 /* CONTEXT */ +#define CPU_ID_REG CP0_CONTEXT +#define CPU_ID_MFC0 MFC0 +#endif .macro get_saved_sp /* SMP variation */ - ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG + CPU_ID_MFC0 k0, CPU_ID_REG #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -105,17 +117,17 @@ daddiu k1, %hi(kernelsp) dsll k1, 16 #endif - LONG_SRL k0, SMP_CPUID_PTRSHIFT + LONG_SRL k0, PTEBASE_SHIFT LONG_ADDU k1, k0 LONG_L k1, %lo(kernelsp)(k1) .endm .macro set_saved_sp stackp temp temp2 - ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG - LONG_SRL \temp, SMP_CPUID_PTRSHIFT + CPU_ID_MFC0 \temp, CPU_ID_REG + LONG_SRL \temp, PTEBASE_SHIFT LONG_S \stackp, kernelsp(\temp) .endm -#else /* !CONFIG_SMP */ +#else .macro get_saved_sp /* Uniprocessor variation */ #ifdef CONFIG_CPU_JUMP_WORKAROUNDS /* diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h deleted file mode 100644 index 81c8913..0000000 --- a/arch/mips/include/asm/syscall.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Access to user system call parameters and results - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * See asm-generic/syscall.h for descriptions of what we must do here. - * - * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> - */ - -#ifndef __ASM_MIPS_SYSCALL_H -#define __ASM_MIPS_SYSCALL_H - -#include <linux/audit.h> -#include <linux/elf-em.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/uaccess.h> -#include <asm/ptrace.h> - -static inline long syscall_get_nr(struct task_struct *task, - struct pt_regs *regs) -{ - return regs->regs[2]; -} - -static inline unsigned long mips_get_syscall_arg(unsigned long *arg, - struct task_struct *task, struct pt_regs *regs, unsigned int n) -{ - unsigned long usp = regs->regs[29]; - - switch (n) { - case 0: case 1: case 2: case 3: - *arg = regs->regs[4 + n]; - - return 0; - -#ifdef CONFIG_32BIT - case 4: case 5: case 6: case 7: - return get_user(*arg, (int *)usp + 4 * n); -#endif - -#ifdef CONFIG_64BIT - case 4: case 5: case 6: case 7: -#ifdef CONFIG_MIPS32_O32 - if (test_thread_flag(TIF_32BIT_REGS)) - return get_user(*arg, (int *)usp + 4 * n); - else -#endif - *arg = regs->regs[4 + n]; - - return 0; -#endif - - default: - BUG(); - } -} - -static inline long syscall_get_return_value(struct task_struct *task, - struct pt_regs *regs) -{ - return regs->regs[2]; -} - -static inline void syscall_set_return_value(struct task_struct *task, - struct pt_regs *regs, - int error, long val) -{ - if (error) { - regs->regs[2] = -error; - regs->regs[7] = -1; - } else { - regs->regs[2] = val; - regs->regs[7] = 0; - } -} - -static inline void syscall_get_arguments(struct task_struct *task, - struct pt_regs *regs, - unsigned int i, unsigned int n, - unsigned long *args) -{ - unsigned long arg; - int ret; - - while (n--) - ret |= mips_get_syscall_arg(&arg, task, regs, i++); - - /* - * No way to communicate an error because this is a void function. - */ -#if 0 - return ret; -#endif -} - -extern const unsigned long sys_call_table[]; -extern const unsigned long sys32_call_table[]; -extern const unsigned long sysn32_call_table[]; - -static inline int __syscall_get_arch(void) -{ - int arch = EM_MIPS; -#ifdef CONFIG_64BIT - arch |= __AUDIT_ARCH_64BIT; -#endif -#if defined(__LITTLE_ENDIAN) - arch |= __AUDIT_ARCH_LE; -#endif - return arch; -} - -#endif /* __ASM_MIPS_SYSCALL_H */ diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 4f58ef6..61215a3 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -92,6 +92,8 @@ static inline struct thread_info *current_thread_info(void) #define STACK_WARN (THREAD_SIZE / 8) +#define PREEMPT_ACTIVE 0x10000000 + /* * thread information flags * - these are process state flags that various assembly files may need to @@ -114,7 +116,6 @@ static inline struct thread_info *current_thread_info(void) #define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ #define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ -#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) @@ -131,54 +132,21 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) #define _TIF_FPUBOUND (1<<TIF_FPUBOUND) #define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) -#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) #define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ - _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT) + _TIF_SYSCALL_AUDIT) /* work to do in syscall_trace_leave() */ #define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ - _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT) + _TIF_SYSCALL_AUDIT) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK \ (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) /* work to do on any return to u-space */ #define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \ - _TIF_WORK_SYSCALL_EXIT | \ - _TIF_SYSCALL_TRACEPOINT) - -/* - * We stash processor id into a COP0 register to retrieve it fast - * at kernel exception entry. - */ -#if defined(CONFIG_MIPS_MT_SMTC) -#define SMP_CPUID_REG 2, 2 /* TCBIND */ -#define ASM_SMP_CPUID_REG $2, 2 -#define SMP_CPUID_PTRSHIFT 19 -#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) -#define SMP_CPUID_REG 20, 0 /* XCONTEXT */ -#define ASM_SMP_CPUID_REG $20 -#define SMP_CPUID_PTRSHIFT 48 -#else -#define SMP_CPUID_REG 4, 0 /* CONTEXT */ -#define ASM_SMP_CPUID_REG $4 -#define SMP_CPUID_PTRSHIFT 23 -#endif - -#ifdef CONFIG_64BIT -#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3) -#else -#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2) -#endif - -#ifdef CONFIG_MIPS_MT_SMTC -#define ASM_CPUID_MFC0 mfc0 -#define UASM_i_CPUID_MFC0 uasm_i_mfc0 -#else -#define ASM_CPUID_MFC0 MFC0 -#define UASM_i_CPUID_MFC0 UASM_i_MFC0 -#endif + _TIF_WORK_SYSCALL_EXIT) #endif /* __KERNEL__ */ + #endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 24f534a..2d7b9df 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void); static inline int init_mips_clocksource(void) { -#ifdef CONFIG_CSRC_R4K +#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC) return init_r4k_clocksource(); #else return 0; diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index 4d3b928..63c9c88 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h @@ -14,13 +14,6 @@ #include <uapi/asm/unistd.h> -#ifdef CONFIG_MIPS32_N32 -#define NR_syscalls (__NR_N32_Linux + __NR_N32_Linux_syscalls) -#elif defined(CONFIG_64BIT) -#define NR_syscalls (__NR_64_Linux + __NR_64_Linux_syscalls) -#else -#define NR_syscalls (__NR_O32_Linux + __NR_O32_Linux_syscalls) -#endif #ifndef __ASSEMBLY__ diff --git a/arch/mips/include/uapi/asm/errno.h b/arch/mips/include/uapi/asm/errno.h index 02d645d..31575e2f 100644 --- a/arch/mips/include/uapi/asm/errno.h +++ b/arch/mips/include/uapi/asm/errno.h @@ -102,7 +102,7 @@ #define EWOULDBLOCK EAGAIN /* Operation would block */ #define EALREADY 149 /* Operation already in progress */ #define EINPROGRESS 150 /* Operation now in progress */ -#define ESTALE 151 /* Stale file handle */ +#define ESTALE 151 /* Stale NFS file handle */ #define ECANCELED 158 /* AIO operation canceled */ /* diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h index e811744..88e292b 100644 --- a/arch/mips/include/uapi/asm/siginfo.h +++ b/arch/mips/include/uapi/asm/siginfo.h @@ -33,8 +33,6 @@ struct siginfo; #error _MIPS_SZLONG neither 32 nor 64 #endif -#define __ARCH_SIGSYS - #include <asm-generic/siginfo.h> typedef struct siginfo { @@ -99,13 +97,6 @@ typedef struct siginfo { __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */ int _fd; } _sigpoll; - - /* SIGSYS */ - struct { - void __user *_call_addr; /* calling user insn */ - int _syscall; /* triggering system call number */ - unsigned int _arch; /* AUDIT_ARCH_* of syscall */ - } _sigsys; } _sifields; } siginfo_t; diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h index 0df9787..61c01f0 100644 --- a/arch/mips/include/uapi/asm/socket.h +++ b/arch/mips/include/uapi/asm/socket.h @@ -94,6 +94,4 @@ #define SO_BUSY_POLL 46 -#define SO_MAX_PACING_RATE 47 - #endif /* _UAPI_ASM_SOCKET_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 1c1b717..423d871 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o obj-$(CONFIG_CSRC_GIC) += csrc-gic.o obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o +obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o @@ -34,7 +35,6 @@ obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += mips_ksyms.o module.o obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o -obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o @@ -84,7 +84,6 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o crash.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c814287..5465dc1 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -376,33 +376,13 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "R4000PC"; } } else { - int cca = read_c0_config() & CONF_CM_CMASK; - int mc; - - /* - * SC and MC versions can't be reliably told apart, - * but only the latter support coherent caching - * modes so assume the firmware has set the KSEG0 - * coherency attribute reasonably (if uncached, we - * assume SC). - */ - switch (cca) { - case CONF_CM_CACHABLE_CE: - case CONF_CM_CACHABLE_COW: - case CONF_CM_CACHABLE_CUW: - mc = 1; - break; - default: - mc = 0; - break; - } if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400) { - c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; - __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; + c->cputype = CPU_R4400SC; + __cpu_name[cpu] = "R4400SC"; } else { - c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; - __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; + c->cputype = CPU_R4000SC; + __cpu_name[cpu] = "R4000SC"; } } @@ -1099,8 +1079,8 @@ void cpu_report(void) { struct cpuinfo_mips *c = ¤t_cpu_data; - pr_info("CPU%d revision is: %08x (%s)\n", - smp_processor_id(), c->processor_id, cpu_name_string()); + printk(KERN_INFO "CPU revision is: %08x (%s)\n", + c->processor_id, cpu_name_string()); if (c->options & MIPS_CPU_FPU) printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); } diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c new file mode 100644 index 0000000..abd99ea --- /dev/null +++ b/arch/mips/kernel/csrc-powertv.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2008 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +/* + * The file comes from kernel/csrc-r4k.c + */ +#include <linux/clocksource.h> +#include <linux/init.h> + +#include <asm/time.h> /* Not included in linux/time.h */ + +#include <asm/mach-powertv/asic_regs.h> +#include "powertv-clock.h" + +/* MIPS PLL Register Definitions */ +#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF) +#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF) +#define PLL_GET_P(x) (((x) >> 24) & 0x00000007) + +/* + * returns: Clock frequency in kHz + */ +unsigned int __init mips_get_pll_freq(void) +{ + unsigned int pll_reg, m, n, p; + unsigned int fin = 54000; /* Base frequency in kHz */ + unsigned int fout; + + /* Read PLL register setting */ + pll_reg = asic_read(mips_pll_setup); + m = PLL_GET_M(pll_reg); + n = PLL_GET_N(pll_reg); + p = PLL_GET_P(pll_reg); + pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); + + /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ + fout = ((2 * n * fin) / (m * (0x01 << p))); + + pr_info("MIPS Clock Freq=%d kHz\n", fout); + + return fout; +} + +static cycle_t c0_hpt_read(struct clocksource *cs) +{ + return read_c0_count(); +} + +static struct clocksource clocksource_mips = { + .name = "powertv-counter", + .read = c0_hpt_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __init powertv_c0_hpt_clocksource_init(void) +{ + unsigned int pll_freq = mips_get_pll_freq(); + + pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000, + (pll_freq % 1000) * 100 / 1000); + + mips_hpt_frequency = pll_freq / 2 * 1000; + + clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + + clocksource_register_hz(&clocksource_mips, mips_hpt_frequency); +} + +/** + * struct tim_c - free running counter + * @hi: High 16 bits of the counter + * @lo: Low 32 bits of the counter + * + * Lays out the structure of the free running counter in memory. This counter + * increments at a rate of 27 MHz/8 on all platforms. + */ +struct tim_c { + unsigned int hi; + unsigned int lo; +}; + +static struct tim_c *tim_c; + +static cycle_t tim_c_read(struct clocksource *cs) +{ + unsigned int hi; + unsigned int next_hi; + unsigned int lo; + + hi = readl(&tim_c->hi); + + for (;;) { + lo = readl(&tim_c->lo); + next_hi = readl(&tim_c->hi); + if (next_hi == hi) + break; + hi = next_hi; + } + +pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo); + return ((u64) hi << 32) | lo; +} + +#define TIM_C_SIZE 48 /* # bits in the timer */ + +static struct clocksource clocksource_tim_c = { + .name = "powertv-tim_c", + .read = tim_c_read, + .mask = CLOCKSOURCE_MASK(TIM_C_SIZE), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/** + * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock + * + * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to + * 1 / (27,000,000/8) seconds. + */ +static void __init powertv_tim_c_clocksource_init(void) +{ + const unsigned long counts_per_second = 27000000 / 8; + + clocksource_tim_c.rating = 200; + + clocksource_register_hz(&clocksource_tim_c, counts_per_second); + tim_c = (struct tim_c *) asic_reg_addr(tim_ch); +} + +/** + powertv_clocksource_init - initialize all clocksources + */ +void __init powertv_clocksource_init(void) +{ + powertv_c0_hpt_clocksource_init(); + powertv_tim_c_clocksource_init(); +} diff --git a/arch/mips/kernel/early_printk_8250.c b/arch/mips/kernel/early_printk_8250.c deleted file mode 100644 index 83cea37..0000000 --- a/arch/mips/kernel/early_printk_8250.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * 8250/16550-type serial ports prom_putchar() - * - * Copyright (C) 2010 Yoichi Yuasa <yuasa@linux-mips.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <linux/io.h> -#include <linux/serial_core.h> -#include <linux/serial_reg.h> - -static void __iomem *serial8250_base; -static unsigned int serial8250_reg_shift; -static unsigned int serial8250_tx_timeout; - -void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift, - unsigned int timeout) -{ - serial8250_base = (void __iomem *)base; - serial8250_reg_shift = reg_shift; - serial8250_tx_timeout = timeout; -} - -static inline u8 serial_in(int offset) -{ - return readb(serial8250_base + (offset << serial8250_reg_shift)); -} - -static inline void serial_out(int offset, char value) -{ - writeb(value, serial8250_base + (offset << serial8250_reg_shift)); -} - -void prom_putchar(char c) -{ - unsigned int timeout; - int status, bits; - - if (!serial8250_base) - return; - - timeout = serial8250_tx_timeout; - bits = UART_LSR_TEMT | UART_LSR_THRE; - - do { - status = serial_in(UART_LSR); - - if (--timeout == 0) - break; - } while ((status & bits) != bits); - - if (timeout) - serial_out(UART_TX, c); -} diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 185ba25..dba90ec 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -11,14 +11,11 @@ #include <linux/uaccess.h> #include <linux/init.h> #include <linux/ftrace.h> -#include <linux/syscalls.h> #include <asm/asm.h> #include <asm/asm-offsets.h> #include <asm/cacheflush.h> -#include <asm/syscall.h> #include <asm/uasm.h> -#include <asm/unistd.h> #include <asm-generic/sections.h> @@ -367,33 +364,3 @@ out: WARN_ON(1); } #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ - -#ifdef CONFIG_FTRACE_SYSCALLS - -#ifdef CONFIG_32BIT -unsigned long __init arch_syscall_addr(int nr) -{ - return (unsigned long)sys_call_table[nr - __NR_O32_Linux]; -} -#endif - -#ifdef CONFIG_64BIT - -unsigned long __init arch_syscall_addr(int nr) -{ -#ifdef CONFIG_MIPS32_N32 - if (nr >= __NR_N32_Linux && nr <= __NR_N32_Linux + __NR_N32_Linux_syscalls) - return (unsigned long)sysn32_call_table[nr - __NR_N32_Linux]; -#endif - if (nr >= __NR_64_Linux && nr <= __NR_64_Linux + __NR_64_Linux_syscalls) - return (unsigned long)sys_call_table[nr - __NR_64_Linux]; -#ifdef CONFIG_MIPS32_O32 - if (nr >= __NR_O32_Linux && nr <= __NR_O32_Linux + __NR_O32_Linux_syscalls) - return (unsigned long)sys32_call_table[nr - __NR_O32_Linux]; -#endif - - return (unsigned long) &sys_ni_syscall; -} -#endif - -#endif /* CONFIG_FTRACE_SYSCALLS */ diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 47d7583..31fa856 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -374,20 +374,12 @@ NESTED(except_vec_nmi, 0, sp) NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat - /* - * Clear ERL - restore segment mapping - * Clear BEV - required for page fault exception handler to work - */ - mfc0 k0, CP0_STATUS - ori k0, k0, ST0_EXL - li k1, ~(ST0_BEV | ST0_ERL) - and k0, k0, k1 - mtc0 k0, CP0_STATUS - _ehb SAVE_ALL move a0, sp jal nmi_exception_handler - /* nmi_exception_handler never returns */ + RESTORE_ALL + .set mips3 + eret .set pop END(nmi_handler) diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index e498f2b..72ef2d2 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -150,7 +150,7 @@ int __init mips_cpu_intc_init(struct device_node *of_node, domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, &mips_cpu_intc_irq_domain_ops, NULL); if (!domain) - panic("Failed to add irqdomain for MIPS CPU"); + panic("Failed to add irqdomain for MIPS CPU\n"); return 0; } diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index 2a52568..977a623 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -23,7 +23,6 @@ #include <linux/moduleloader.h> #include <linux/elf.h> #include <linux/mm.h> -#include <linux/numa.h> #include <linux/vmalloc.h> #include <linux/slab.h> #include <linux/fs.h> @@ -47,7 +46,7 @@ static DEFINE_SPINLOCK(dbe_lock); void *module_alloc(unsigned long size) { return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, - GFP_KERNEL, PAGE_KERNEL, NUMA_NO_NODE, + GFP_KERNEL, PAGE_KERNEL, -1, __builtin_return_address(0)); } #endif diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 3c3b0df..0fa0b69 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -13,9 +13,12 @@ #include <linux/errno.h> #include <linux/types.h> #include <linux/bootmem.h> +#include <linux/initrd.h> #include <linux/debugfs.h> #include <linux/of.h> #include <linux/of_fdt.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> #include <asm/page.h> #include <asm/prom.h> @@ -37,6 +40,13 @@ char *mips_get_machine_name(void) } #ifdef CONFIG_OF +int __init early_init_dt_scan_memory_arch(unsigned long node, + const char *uname, int depth, + void *data) +{ + return early_init_dt_scan_memory(node, uname, depth, data); +} + void __init early_init_dt_add_memory_arch(u64 base, u64 size) { return add_memory_region(base, size, BOOT_MEM_RAM); @@ -47,11 +57,57 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); } +#ifdef CONFIG_BLK_DEV_INITRD +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) +{ + initrd_start = (unsigned long)__va(start); + initrd_end = (unsigned long)__va(end); + initrd_below_start_ok = 1; +} +#endif + +int __init early_init_dt_scan_model(unsigned long node, const char *uname, + int depth, void *data) +{ + if (!depth) { + char *model = of_get_flat_dt_prop(node, "model", NULL); + + if (model) + mips_set_machine_name(model); + } + return 0; +} + +void __init early_init_devtree(void *params) +{ + /* Setup flat device-tree pointer */ + initial_boot_params = params; + + /* Retrieve various informations from the /chosen node of the + * device-tree, including the platform type, initrd location and + * size, and more ... + */ + of_scan_flat_dt(early_init_dt_scan_chosen, arcs_cmdline); + + + /* Scan memory nodes */ + of_scan_flat_dt(early_init_dt_scan_root, NULL); + of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL); + + /* try to load the mips machine name */ + of_scan_flat_dt(early_init_dt_scan_model, NULL); +} + void __init __dt_setup_arch(struct boot_param_header *bph) { - if (!early_init_dt_scan(bph)) + if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { + pr_err("DTB has bad magic, ignoring builtin OF DTB\n"); + return; + } + + initial_boot_params = bph; - mips_set_machine_name(of_flat_dt_get_machine_name()); + early_init_devtree(initial_boot_params); } #endif diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index b52e1d2..8ae1ebe 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -16,20 +16,16 @@ */ #include <linux/compiler.h> #include <linux/context_tracking.h> -#include <linux/elf.h> #include <linux/kernel.h> #include <linux/sched.h> #include <linux/mm.h> #include <linux/errno.h> #include <linux/ptrace.h> -#include <linux/regset.h> #include <linux/smp.h> #include <linux/user.h> #include <linux/security.h> -#include <linux/tracehook.h> #include <linux/audit.h> #include <linux/seccomp.h> -#include <linux/ftrace.h> #include <asm/byteorder.h> #include <asm/cpu.h> @@ -39,14 +35,10 @@ #include <asm/mipsmtregs.h> #include <asm/pgtable.h> #include <asm/page.h> -#include <asm/syscall.h> #include <asm/uaccess.h> #include <asm/bootinfo.h> #include <asm/reg.h> -#define CREATE_TRACE_POINTS -#include <trace/events/syscalls.h> - /* * Called by kernel/ptrace.c when detaching.. * @@ -263,133 +255,6 @@ int ptrace_set_watch_regs(struct task_struct *child, return 0; } -/* regset get/set implementations */ - -static int gpr_get(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - void *kbuf, void __user *ubuf) -{ - struct pt_regs *regs = task_pt_regs(target); - - return user_regset_copyout(&pos, &count, &kbuf, &ubuf, - regs, 0, sizeof(*regs)); -} - -static int gpr_set(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - const void *kbuf, const void __user *ubuf) -{ - struct pt_regs newregs; - int ret; - - ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - &newregs, - 0, sizeof(newregs)); - if (ret) - return ret; - - *task_pt_regs(target) = newregs; - - return 0; -} - -static int fpr_get(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - void *kbuf, void __user *ubuf) -{ - return user_regset_copyout(&pos, &count, &kbuf, &ubuf, - &target->thread.fpu, - 0, sizeof(elf_fpregset_t)); - /* XXX fcr31 */ -} - -static int fpr_set(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - const void *kbuf, const void __user *ubuf) -{ - return user_regset_copyin(&pos, &count, &kbuf, &ubuf, - &target->thread.fpu, - 0, sizeof(elf_fpregset_t)); - /* XXX fcr31 */ -} - -enum mips_regset { - REGSET_GPR, - REGSET_FPR, -}; - -static const struct user_regset mips_regsets[] = { - [REGSET_GPR] = { - .core_note_type = NT_PRSTATUS, - .n = ELF_NGREG, - .size = sizeof(unsigned int), - .align = sizeof(unsigned int), - .get = gpr_get, - .set = gpr_set, - }, - [REGSET_FPR] = { - .core_note_type = NT_PRFPREG, - .n = ELF_NFPREG, - .size = sizeof(elf_fpreg_t), - .align = sizeof(elf_fpreg_t), - .get = fpr_get, - .set = fpr_set, - }, -}; - -static const struct user_regset_view user_mips_view = { - .name = "mips", - .e_machine = ELF_ARCH, - .ei_osabi = ELF_OSABI, - .regsets = mips_regsets, - .n = ARRAY_SIZE(mips_regsets), -}; - -static const struct user_regset mips64_regsets[] = { - [REGSET_GPR] = { - .core_note_type = NT_PRSTATUS, - .n = ELF_NGREG, - .size = sizeof(unsigned long), - .align = sizeof(unsigned long), - .get = gpr_get, - .set = gpr_set, - }, - [REGSET_FPR] = { - .core_note_type = NT_PRFPREG, - .n = ELF_NFPREG, - .size = sizeof(elf_fpreg_t), - .align = sizeof(elf_fpreg_t), - .get = fpr_get, - .set = fpr_set, - }, -}; - -static const struct user_regset_view user_mips64_view = { - .name = "mips", - .e_machine = ELF_ARCH, - .ei_osabi = ELF_OSABI, - .regsets = mips64_regsets, - .n = ARRAY_SIZE(mips_regsets), -}; - -const struct user_regset_view *task_user_regset_view(struct task_struct *task) -{ -#ifdef CONFIG_32BIT - return &user_mips_view; -#endif - -#ifdef CONFIG_MIPS32_O32 - if (test_thread_flag(TIF_32BIT_REGS)) - return &user_mips_view; -#endif - - return &user_mips64_view; -} - long arch_ptrace(struct task_struct *child, long request, unsigned long addr, unsigned long data) { @@ -652,27 +517,52 @@ long arch_ptrace(struct task_struct *child, long request, return ret; } +static inline int audit_arch(void) +{ + int arch = EM_MIPS; +#ifdef CONFIG_64BIT + arch |= __AUDIT_ARCH_64BIT; +#endif +#if defined(__LITTLE_ENDIAN) + arch |= __AUDIT_ARCH_LE; +#endif + return arch; +} + /* * Notification of system call entry/exit * - triggered by current->work.syscall_trace */ asmlinkage void syscall_trace_enter(struct pt_regs *regs) { - long ret = 0; user_exit(); /* do the secure computing check first */ secure_computing_strict(regs->regs[2]); - if (test_thread_flag(TIF_SYSCALL_TRACE) && - tracehook_report_syscall_entry(regs)) - ret = -1; + if (!(current->ptrace & PT_PTRACED)) + goto out; + + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + goto out; - if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) - trace_sys_enter(regs, regs->regs[2]); + /* The 0x80 provides a way for the tracing parent to distinguish + between a syscall stop and SIGTRAP delivery */ + ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? + 0x80 : 0)); + + /* + * this isn't the same as continuing with a signal, but it will do + * for normal use. strace only continues with a signal if the + * stopping signal is not SIGTRAP. -brl + */ + if (current->exit_code) { + send_sig(current->exit_code, current, 1); + current->exit_code = 0; + } - audit_syscall_entry(__syscall_get_arch(), - regs->regs[2], +out: + audit_syscall_entry(audit_arch(), regs->regs[2], regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); } @@ -692,11 +582,26 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs) audit_syscall_exit(regs); - if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) - trace_sys_exit(regs, regs->regs[2]); + if (!(current->ptrace & PT_PTRACED)) + return; + + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + return; + + /* The 0x80 provides a way for the tracing parent to distinguish + between a syscall stop and SIGTRAP delivery */ + ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? + 0x80 : 0)); - if (test_thread_flag(TIF_SYSCALL_TRACE)) - tracehook_report_syscall_exit(regs, 0); + /* + * this isn't the same as continuing with a signal, but it will do + * for normal use. strace only continues with a signal if the + * stopping signal is not SIGTRAP. -brl + */ + if (current->exit_code) { + send_sig(current->exit_code, current, 1); + current->exit_code = 0; + } user_enter(); } diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 2c12ea1..d763f11 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -172,9 +172,8 @@ int rtlx_open(int index, int can_sleep) if (rtlx == NULL) { if( (p = vpe_get_shared(tclimit)) == NULL) { if (can_sleep) { - ret = __wait_event_interruptible( - channel_wqs[index].lx_queue, - (p = vpe_get_shared(tclimit))); + __wait_event_interruptible(channel_wqs[index].lx_queue, + (p = vpe_get_shared(tclimit)), ret); if (ret) goto out_fail; } else { @@ -264,10 +263,11 @@ unsigned int rtlx_read_poll(int index, int can_sleep) /* data available to read? */ if (chan->lx_read == chan->lx_write) { if (can_sleep) { - int ret = __wait_event_interruptible( - channel_wqs[index].lx_queue, + int ret = 0; + + __wait_event_interruptible(channel_wqs[index].lx_queue, (chan->lx_read != chan->lx_write) || - sp_stopping); + sp_stopping, ret); if (ret) return ret; @@ -440,13 +440,14 @@ static ssize_t file_write(struct file *file, const char __user * buffer, /* any space left... */ if (!rtlx_write_poll(minor)) { - int ret; + int ret = 0; if (file->f_flags & O_NONBLOCK) return -EAGAIN; - ret = __wait_event_interruptible(channel_wqs[minor].rt_queue, - rtlx_write_poll(minor)); + __wait_event_interruptible(channel_wqs[minor].rt_queue, + rtlx_write_poll(minor), + ret); if (ret) return ret; } diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index e8e541b..e774bb1 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -40,58 +40,17 @@ NESTED(handle_sys, PT_SIZE, sp) sw t1, PT_EPC(sp) beqz t0, illegal_syscall - sll t0, v0, 2 + sll t0, v0, 3 la t1, sys_call_table addu t1, t0 lw t2, (t1) # syscall routine + lw t3, 4(t1) # >= 0 if we need stack arguments beqz t2, illegal_syscall sw a3, PT_R26(sp) # save a3 for syscall restarting + bgez t3, stackargs - /* - * More than four arguments. Try to deal with it by copying the - * stack arguments from the user stack to the kernel stack. - * This Sucks (TM). - */ - lw t0, PT_R29(sp) # get old user stack pointer - - /* - * We intentionally keep the kernel stack a little below the top of - * userspace so we don't have to do a slower byte accurate check here. - */ - lw t5, TI_ADDR_LIMIT($28) - addu t4, t0, 32 - and t5, t4 - bltz t5, bad_stack # -> sp is bad - - /* - * Ok, copy the args from the luser stack to the kernel stack. - * t3 is the precomputed number of instruction bytes needed to - * load or store arguments 6-8. - */ - - .set push - .set noreorder - .set nomacro - -1: lw t5, 16(t0) # argument #5 from usp -4: lw t6, 20(t0) # argument #6 from usp -3: lw t7, 24(t0) # argument #7 from usp -2: lw t8, 28(t0) # argument #8 from usp - - sw t5, 16(sp) # argument #5 to ksp - sw t6, 20(sp) # argument #6 to ksp - sw t7, 24(sp) # argument #7 to ksp - sw t8, 28(sp) # argument #8 to ksp - .set pop - - .section __ex_table,"a" - PTR 1b,bad_stack - PTR 2b,bad_stack - PTR 3b,bad_stack - PTR 4b,bad_stack - .previous - +stack_done: lw t0, TI_FLAGS($28) # syscall tracing enabled? li t1, _TIF_WORK_SYSCALL_ENTRY and t0, t1 @@ -143,6 +102,66 @@ syscall_trace_entry: /* ------------------------------------------------------------------------ */ /* + * More than four arguments. Try to deal with it by copying the + * stack arguments from the user stack to the kernel stack. + * This Sucks (TM). + */ +stackargs: + lw t0, PT_R29(sp) # get old user stack pointer + + /* + * We intentionally keep the kernel stack a little below the top of + * userspace so we don't have to do a slower byte accurate check here. + */ + lw t5, TI_ADDR_LIMIT($28) + addu t4, t0, 32 + and t5, t4 + bltz t5, bad_stack # -> sp is bad + + /* Ok, copy the args from the luser stack to the kernel stack. + * t3 is the precomputed number of instruction bytes needed to + * load or store arguments 6-8. + */ + + la t1, 5f # load up to 3 arguments + subu t1, t3 +1: lw t5, 16(t0) # argument #5 from usp + .set push + .set noreorder + .set nomacro + jr t1 + addiu t1, 6f - 5f + +2: lw t8, 28(t0) # argument #8 from usp +3: lw t7, 24(t0) # argument #7 from usp +4: lw t6, 20(t0) # argument #6 from usp +5: jr t1 + sw t5, 16(sp) # argument #5 to ksp + +#ifdef CONFIG_CPU_MICROMIPS + sw t8, 28(sp) # argument #8 to ksp + nop + sw t7, 24(sp) # argument #7 to ksp + nop + sw t6, 20(sp) # argument #6 to ksp + nop +#else + sw t8, 28(sp) # argument #8 to ksp + sw t7, 24(sp) # argument #7 to ksp + sw t6, 20(sp) # argument #6 to ksp +#endif +6: j stack_done # go back + nop + .set pop + + .section __ex_table,"a" + PTR 1b,bad_stack + PTR 2b,bad_stack + PTR 3b,bad_stack + PTR 4b,bad_stack + .previous + + /* * The stackpointer for a call with more than 4 arguments is bad. * We probably should handle this case a bit more drastic. */ @@ -168,7 +187,7 @@ illegal_syscall: subu t0, a0, __NR_O32_Linux # check syscall number sltiu v0, t0, __NR_O32_Linux_syscalls + 1 beqz t0, einval # do not recurse - sll t1, t0, 2 + sll t1, t0, 3 beqz v0, einval lw t2, sys_call_table(t1) # syscall routine @@ -199,248 +218,260 @@ einval: li v0, -ENOSYS jr ra END(sys_syscall) - .align 2 - .type sys_call_table, @object -EXPORT(sys_call_table) - PTR sys_syscall /* 4000 */ - PTR sys_exit - PTR __sys_fork - PTR sys_read - PTR sys_write - PTR sys_open /* 4005 */ - PTR sys_close - PTR sys_waitpid - PTR sys_creat - PTR sys_link - PTR sys_unlink /* 4010 */ - PTR sys_execve - PTR sys_chdir - PTR sys_time - PTR sys_mknod - PTR sys_chmod /* 4015 */ - PTR sys_lchown - PTR sys_ni_syscall - PTR sys_ni_syscall /* was sys_stat */ - PTR sys_lseek - PTR sys_getpid /* 4020 */ - PTR sys_mount - PTR sys_oldumount - PTR sys_setuid - PTR sys_getuid - PTR sys_stime /* 4025 */ - PTR sys_ptrace - PTR sys_alarm - PTR sys_ni_syscall /* was sys_fstat */ - PTR sys_pause - PTR sys_utime /* 4030 */ - PTR sys_ni_syscall - PTR sys_ni_syscall - PTR sys_access - PTR sys_nice - PTR sys_ni_syscall /* 4035 */ - PTR sys_sync - PTR sys_kill - PTR sys_rename - PTR sys_mkdir - PTR sys_rmdir /* 4040 */ - PTR sys_dup - PTR sysm_pipe - PTR sys_times - PTR sys_ni_syscall - PTR sys_brk /* 4045 */ - PTR sys_setgid - PTR sys_getgid - PTR sys_ni_syscall /* was signal(2) */ - PTR sys_geteuid - PTR sys_getegid /* 4050 */ - PTR sys_acct - PTR sys_umount - PTR sys_ni_syscall - PTR sys_ioctl - PTR sys_fcntl /* 4055 */ - PTR sys_ni_syscall - PTR sys_setpgid - PTR sys_ni_syscall - PTR sys_olduname - PTR sys_umask /* 4060 */ - PTR sys_chroot - PTR sys_ustat - PTR sys_dup2 - PTR sys_getppid - PTR sys_getpgrp /* 4065 */ - PTR sys_setsid - PTR sys_sigaction - PTR sys_sgetmask - PTR sys_ssetmask - PTR sys_setreuid /* 4070 */ - PTR sys_setregid - PTR sys_sigsuspend - PTR sys_sigpending - PTR sys_sethostname - PTR sys_setrlimit /* 4075 */ - PTR sys_getrlimit - PTR sys_getrusage - PTR sys_gettimeofday - PTR sys_settimeofday - PTR sys_getgroups /* 4080 */ - PTR sys_setgroups - PTR sys_ni_syscall /* old_select */ - PTR sys_symlink - PTR sys_ni_syscall /* was sys_lstat */ - PTR sys_readlink /* 4085 */ - PTR sys_uselib - PTR sys_swapon - PTR sys_reboot - PTR sys_old_readdir - PTR sys_mips_mmap /* 4090 */ - PTR sys_munmap - PTR sys_truncate - PTR sys_ftruncate - PTR sys_fchmod - PTR sys_fchown /* 4095 */ - PTR sys_getpriority - PTR sys_setpriority - PTR sys_ni_syscall - PTR sys_statfs - PTR sys_fstatfs /* 4100 */ - PTR sys_ni_syscall /* was ioperm(2) */ - PTR sys_socketcall - PTR sys_syslog - PTR sys_setitimer - PTR sys_getitimer /* 4105 */ - PTR sys_newstat - PTR sys_newlstat - PTR sys_newfstat - PTR sys_uname - PTR sys_ni_syscall /* 4110 was iopl(2) */ - PTR sys_vhangup - PTR sys_ni_syscall /* was sys_idle() */ - PTR sys_ni_syscall /* was sys_vm86 */ - PTR sys_wait4 - PTR sys_swapoff /* 4115 */ - PTR sys_sysinfo - PTR sys_ipc - PTR sys_fsync - PTR sys_sigreturn - PTR __sys_clone /* 4120 */ - PTR sys_setdomainname - PTR sys_newuname - PTR sys_ni_syscall /* sys_modify_ldt */ - PTR sys_adjtimex - PTR sys_mprotect /* 4125 */ - PTR sys_sigprocmask - PTR sys_ni_syscall /* was create_module */ - PTR sys_init_module - PTR sys_delete_module - PTR sys_ni_syscall /* 4130 was get_kernel_syms */ - PTR sys_quotactl - PTR sys_getpgid - PTR sys_fchdir - PTR sys_bdflush - PTR sys_sysfs /* 4135 */ - PTR sys_personality - PTR sys_ni_syscall /* for afs_syscall */ - PTR sys_setfsuid - PTR sys_setfsgid - PTR sys_llseek /* 4140 */ - PTR sys_getdents - PTR sys_select - PTR sys_flock - PTR sys_msync - PTR sys_readv /* 4145 */ - PTR sys_writev - PTR sys_cacheflush - PTR sys_cachectl - PTR sys_sysmips - PTR sys_ni_syscall /* 4150 */ - PTR sys_getsid - PTR sys_fdatasync - PTR sys_sysctl - PTR sys_mlock - PTR sys_munlock /* 4155 */ - PTR sys_mlockall - PTR sys_munlockall - PTR sys_sched_setparam - PTR sys_sched_getparam - PTR sys_sched_setscheduler /* 4160 */ - PTR sys_sched_getscheduler - PTR sys_sched_yield - PTR sys_sched_get_priority_max - PTR sys_sched_get_priority_min - PTR sys_sched_rr_get_interval /* 4165 */ - PTR sys_nanosleep - PTR sys_mremap - PTR sys_accept - PTR sys_bind - PTR sys_connect /* 4170 */ - PTR sys_getpeername - PTR sys_getsockname - PTR sys_getsockopt - PTR sys_listen - PTR sys_recv /* 4175 */ - PTR sys_recvfrom - PTR sys_recvmsg - PTR sys_send - PTR sys_sendmsg - PTR sys_sendto /* 4180 */ - PTR sys_setsockopt - PTR sys_shutdown - PTR sys_socket - PTR sys_socketpair - PTR sys_setresuid /* 4185 */ - PTR sys_getresuid - PTR sys_ni_syscall /* was sys_query_module */ - PTR sys_poll - PTR sys_ni_syscall /* was nfsservctl */ - PTR sys_setresgid /* 4190 */ - PTR sys_getresgid - PTR sys_prctl - PTR sys_rt_sigreturn - PTR sys_rt_sigaction - PTR sys_rt_sigprocmask /* 4195 */ - PTR sys_rt_sigpending - PTR sys_rt_sigtimedwait - PTR sys_rt_sigqueueinfo - PTR sys_rt_sigsuspend - PTR sys_pread64 /* 4200 */ - PTR sys_pwrite64 - PTR sys_chown - PTR sys_getcwd - PTR sys_capget - PTR sys_capset /* 4205 */ - PTR sys_sigaltstack - PTR sys_sendfile - PTR sys_ni_syscall - PTR sys_ni_syscall - PTR sys_mips_mmap2 /* 4210 */ - PTR sys_truncate64 - PTR sys_ftruncate64 - PTR sys_stat64 - PTR sys_lstat64 - PTR sys_fstat64 /* 4215 */ - PTR sys_pivot_root - PTR sys_mincore - PTR sys_madvise - PTR sys_getdents64 - PTR sys_fcntl64 /* 4220 */ - PTR sys_ni_syscall - PTR sys_gettid - PTR sys_readahead - PTR sys_setxattr - PTR sys_lsetxattr /* 4225 */ - PTR sys_fsetxattr - PTR sys_getxattr - PTR sys_lgetxattr - PTR sys_fgetxattr - PTR sys_listxattr /* 4230 */ - PTR sys_llistxattr - PTR sys_flistxattr - PTR sys_removexattr - PTR sys_lremovexattr - PTR sys_fremovexattr /* 4235 */ - PTR sys_tkill - PTR sys_sendfile64 - PTR sys_futex + .macro fifty ptr, nargs, from=1, to=50 + sys \ptr \nargs + .if \to-\from + fifty \ptr,\nargs,"(\from+1)",\to + .endif + .endm + + .macro mille ptr, nargs, from=1, to=20 + fifty \ptr,\nargs + .if \to-\from + mille \ptr,\nargs,"(\from+1)",\to + .endif + .endm + + .macro syscalltable + sys sys_syscall 8 /* 4000 */ + sys sys_exit 1 + sys __sys_fork 0 + sys sys_read 3 + sys sys_write 3 + sys sys_open 3 /* 4005 */ + sys sys_close 1 + sys sys_waitpid 3 + sys sys_creat 2 + sys sys_link 2 + sys sys_unlink 1 /* 4010 */ + sys sys_execve 0 + sys sys_chdir 1 + sys sys_time 1 + sys sys_mknod 3 + sys sys_chmod 2 /* 4015 */ + sys sys_lchown 3 + sys sys_ni_syscall 0 + sys sys_ni_syscall 0 /* was sys_stat */ + sys sys_lseek 3 + sys sys_getpid 0 /* 4020 */ + sys sys_mount 5 + sys sys_oldumount 1 + sys sys_setuid 1 + sys sys_getuid 0 + sys sys_stime 1 /* 4025 */ + sys sys_ptrace 4 + sys sys_alarm 1 + sys sys_ni_syscall 0 /* was sys_fstat */ + sys sys_pause 0 + sys sys_utime 2 /* 4030 */ + sys sys_ni_syscall 0 + sys sys_ni_syscall 0 + sys sys_access 2 + sys sys_nice 1 + sys sys_ni_syscall 0 /* 4035 */ + sys sys_sync 0 + sys sys_kill 2 + sys sys_rename 2 + sys sys_mkdir 2 + sys sys_rmdir 1 /* 4040 */ + sys sys_dup 1 + sys sysm_pipe 0 + sys sys_times 1 + sys sys_ni_syscall 0 + sys sys_brk 1 /* 4045 */ + sys sys_setgid 1 + sys sys_getgid 0 + sys sys_ni_syscall 0 /* was signal(2) */ + sys sys_geteuid 0 + sys sys_getegid 0 /* 4050 */ + sys sys_acct 1 + sys sys_umount 2 + sys sys_ni_syscall 0 + sys sys_ioctl 3 + sys sys_fcntl 3 /* 4055 */ + sys sys_ni_syscall 2 + sys sys_setpgid 2 + sys sys_ni_syscall 0 + sys sys_olduname 1 + sys sys_umask 1 /* 4060 */ + sys sys_chroot 1 + sys sys_ustat 2 + sys sys_dup2 2 + sys sys_getppid 0 + sys sys_getpgrp 0 /* 4065 */ + sys sys_setsid 0 + sys sys_sigaction 3 + sys sys_sgetmask 0 + sys sys_ssetmask 1 + sys sys_setreuid 2 /* 4070 */ + sys sys_setregid 2 + sys sys_sigsuspend 0 + sys sys_sigpending 1 + sys sys_sethostname 2 + sys sys_setrlimit 2 /* 4075 */ + sys sys_getrlimit 2 + sys sys_getrusage 2 + sys sys_gettimeofday 2 + sys sys_settimeofday 2 + sys sys_getgroups 2 /* 4080 */ + sys sys_setgroups 2 + sys sys_ni_syscall 0 /* old_select */ + sys sys_symlink 2 + sys sys_ni_syscall 0 /* was sys_lstat */ + sys sys_readlink 3 /* 4085 */ + sys sys_uselib 1 + sys sys_swapon 2 + sys sys_reboot 3 + sys sys_old_readdir 3 + sys sys_mips_mmap 6 /* 4090 */ + sys sys_munmap 2 + sys sys_truncate 2 + sys sys_ftruncate 2 + sys sys_fchmod 2 + sys sys_fchown 3 /* 4095 */ + sys sys_getpriority 2 + sys sys_setpriority 3 + sys sys_ni_syscall 0 + sys sys_statfs 2 + sys sys_fstatfs 2 /* 4100 */ + sys sys_ni_syscall 0 /* was ioperm(2) */ + sys sys_socketcall 2 + sys sys_syslog 3 + sys sys_setitimer 3 + sys sys_getitimer 2 /* 4105 */ + sys sys_newstat 2 + sys sys_newlstat 2 + sys sys_newfstat 2 + sys sys_uname 1 + sys sys_ni_syscall 0 /* 4110 was iopl(2) */ + sys sys_vhangup 0 + sys sys_ni_syscall 0 /* was sys_idle() */ + sys sys_ni_syscall 0 /* was sys_vm86 */ + sys sys_wait4 4 + sys sys_swapoff 1 /* 4115 */ + sys sys_sysinfo 1 + sys sys_ipc 6 + sys sys_fsync 1 + sys sys_sigreturn 0 + sys __sys_clone 6 /* 4120 */ + sys sys_setdomainname 2 + sys sys_newuname 1 + sys sys_ni_syscall 0 /* sys_modify_ldt */ + sys sys_adjtimex 1 + sys sys_mprotect 3 /* 4125 */ + sys sys_sigprocmask 3 + sys sys_ni_syscall 0 /* was create_module */ + sys sys_init_module 5 + sys sys_delete_module 1 + sys sys_ni_syscall 0 /* 4130 was get_kernel_syms */ + sys sys_quotactl 4 + sys sys_getpgid 1 + sys sys_fchdir 1 + sys sys_bdflush 2 + sys sys_sysfs 3 /* 4135 */ + sys sys_personality 1 + sys sys_ni_syscall 0 /* for afs_syscall */ + sys sys_setfsuid 1 + sys sys_setfsgid 1 + sys sys_llseek 5 /* 4140 */ + sys sys_getdents 3 + sys sys_select 5 + sys sys_flock 2 + sys sys_msync 3 + sys sys_readv 3 /* 4145 */ + sys sys_writev 3 + sys sys_cacheflush 3 + sys sys_cachectl 3 + sys sys_sysmips 4 + sys sys_ni_syscall 0 /* 4150 */ + sys sys_getsid 1 + sys sys_fdatasync 1 + sys sys_sysctl 1 + sys sys_mlock 2 + sys sys_munlock 2 /* 4155 */ + sys sys_mlockall 1 + sys sys_munlockall 0 + sys sys_sched_setparam 2 + sys sys_sched_getparam 2 + sys sys_sched_setscheduler 3 /* 4160 */ + sys sys_sched_getscheduler 1 + sys sys_sched_yield 0 + sys sys_sched_get_priority_max 1 + sys sys_sched_get_priority_min 1 + sys sys_sched_rr_get_interval 2 /* 4165 */ + sys sys_nanosleep, 2 + sys sys_mremap, 5 + sys sys_accept 3 + sys sys_bind 3 + sys sys_connect 3 /* 4170 */ + sys sys_getpeername 3 + sys sys_getsockname 3 + sys sys_getsockopt 5 + sys sys_listen 2 + sys sys_recv 4 /* 4175 */ + sys sys_recvfrom 6 + sys sys_recvmsg 3 + sys sys_send 4 + sys sys_sendmsg 3 + sys sys_sendto 6 /* 4180 */ + sys sys_setsockopt 5 + sys sys_shutdown 2 + sys sys_socket 3 + sys sys_socketpair 4 + sys sys_setresuid 3 /* 4185 */ + sys sys_getresuid 3 + sys sys_ni_syscall 0 /* was sys_query_module */ + sys sys_poll 3 + sys sys_ni_syscall 0 /* was nfsservctl */ + sys sys_setresgid 3 /* 4190 */ + sys sys_getresgid 3 + sys sys_prctl 5 + sys sys_rt_sigreturn 0 + sys sys_rt_sigaction 4 + sys sys_rt_sigprocmask 4 /* 4195 */ + sys sys_rt_sigpending 2 + sys sys_rt_sigtimedwait 4 + sys sys_rt_sigqueueinfo 3 + sys sys_rt_sigsuspend 0 + sys sys_pread64 6 /* 4200 */ + sys sys_pwrite64 6 + sys sys_chown 3 + sys sys_getcwd 2 + sys sys_capget 2 + sys sys_capset 2 /* 4205 */ + sys sys_sigaltstack 0 + sys sys_sendfile 4 + sys sys_ni_syscall 0 + sys sys_ni_syscall 0 + sys sys_mips_mmap2 6 /* 4210 */ + sys sys_truncate64 4 + sys sys_ftruncate64 4 + sys sys_stat64 2 + sys sys_lstat64 2 + sys sys_fstat64 2 /* 4215 */ + sys sys_pivot_root 2 + sys sys_mincore 3 + sys sys_madvise 3 + sys sys_getdents64 3 + sys sys_fcntl64 3 /* 4220 */ + sys sys_ni_syscall 0 + sys sys_gettid 0 + sys sys_readahead 5 + sys sys_setxattr 5 + sys sys_lsetxattr 5 /* 4225 */ + sys sys_fsetxattr 5 + sys sys_getxattr 4 + sys sys_lgetxattr 4 + sys sys_fgetxattr 4 + sys sys_listxattr 3 /* 4230 */ + sys sys_llistxattr 3 + sys sys_flistxattr 3 + sys sys_removexattr 2 + sys sys_lremovexattr 2 + sys sys_fremovexattr 2 /* 4235 */ + sys sys_tkill 2 + sys sys_sendfile64 5 + sys sys_futex 6 #ifdef CONFIG_MIPS_MT_FPAFF /* * For FPU affinity scheduling on MIPS MT processors, we need to @@ -449,117 +480,132 @@ EXPORT(sys_call_table) * these hooks for the 32-bit kernel - there is no MIPS64 MT processor * atm. */ - PTR mipsmt_sys_sched_setaffinity - PTR mipsmt_sys_sched_getaffinity + sys mipsmt_sys_sched_setaffinity 3 + sys mipsmt_sys_sched_getaffinity 3 #else - PTR sys_sched_setaffinity - PTR sys_sched_getaffinity /* 4240 */ + sys sys_sched_setaffinity 3 + sys sys_sched_getaffinity 3 /* 4240 */ #endif /* CONFIG_MIPS_MT_FPAFF */ - PTR sys_io_setup - PTR sys_io_destroy - PTR sys_io_getevents - PTR sys_io_submit - PTR sys_io_cancel /* 4245 */ - PTR sys_exit_group - PTR sys_lookup_dcookie - PTR sys_epoll_create - PTR sys_epoll_ctl - PTR sys_epoll_wait /* 4250 */ - PTR sys_remap_file_pages - PTR sys_set_tid_address - PTR sys_restart_syscall - PTR sys_fadvise64_64 - PTR sys_statfs64 /* 4255 */ - PTR sys_fstatfs64 - PTR sys_timer_create - PTR sys_timer_settime - PTR sys_timer_gettime - PTR sys_timer_getoverrun /* 4260 */ - PTR sys_timer_delete - PTR sys_clock_settime - PTR sys_clock_gettime - PTR sys_clock_getres - PTR sys_clock_nanosleep /* 4265 */ - PTR sys_tgkill - PTR sys_utimes - PTR sys_mbind - PTR sys_ni_syscall /* sys_get_mempolicy */ - PTR sys_ni_syscall /* 4270 sys_set_mempolicy */ - PTR sys_mq_open - PTR sys_mq_unlink - PTR sys_mq_timedsend - PTR sys_mq_timedreceive - PTR sys_mq_notify /* 4275 */ - PTR sys_mq_getsetattr - PTR sys_ni_syscall /* sys_vserver */ - PTR sys_waitid - PTR sys_ni_syscall /* available, was setaltroot */ - PTR sys_add_key /* 4280 */ - PTR sys_request_key - PTR sys_keyctl - PTR sys_set_thread_area - PTR sys_inotify_init - PTR sys_inotify_add_watch /* 4285 */ - PTR sys_inotify_rm_watch - PTR sys_migrate_pages - PTR sys_openat - PTR sys_mkdirat - PTR sys_mknodat /* 4290 */ - PTR sys_fchownat - PTR sys_futimesat - PTR sys_fstatat64 - PTR sys_unlinkat - PTR sys_renameat /* 4295 */ - PTR sys_linkat - PTR sys_symlinkat - PTR sys_readlinkat - PTR sys_fchmodat - PTR sys_faccessat /* 4300 */ - PTR sys_pselect6 - PTR sys_ppoll - PTR sys_unshare - PTR sys_splice - PTR sys_sync_file_range /* 4305 */ - PTR sys_tee - PTR sys_vmsplice - PTR sys_move_pages - PTR sys_set_robust_list - PTR sys_get_robust_list /* 4310 */ - PTR sys_kexec_load - PTR sys_getcpu - PTR sys_epoll_pwait - PTR sys_ioprio_set - PTR sys_ioprio_get /* 4315 */ - PTR sys_utimensat - PTR sys_signalfd - PTR sys_ni_syscall /* was timerfd */ - PTR sys_eventfd - PTR sys_fallocate /* 4320 */ - PTR sys_timerfd_create - PTR sys_timerfd_gettime - PTR sys_timerfd_settime - PTR sys_signalfd4 - PTR sys_eventfd2 /* 4325 */ - PTR sys_epoll_create1 - PTR sys_dup3 - PTR sys_pipe2 - PTR sys_inotify_init1 - PTR sys_preadv /* 4330 */ - PTR sys_pwritev - PTR sys_rt_tgsigqueueinfo - PTR sys_perf_event_open - PTR sys_accept4 - PTR sys_recvmmsg /* 4335 */ - PTR sys_fanotify_init - PTR sys_fanotify_mark - PTR sys_prlimit64 - PTR sys_name_to_handle_at - PTR sys_open_by_handle_at /* 4340 */ - PTR sys_clock_adjtime - PTR sys_syncfs - PTR sys_sendmmsg - PTR sys_setns - PTR sys_process_vm_readv /* 4345 */ - PTR sys_process_vm_writev - PTR sys_kcmp - PTR sys_finit_module + sys sys_io_setup 2 + sys sys_io_destroy 1 + sys sys_io_getevents 5 + sys sys_io_submit 3 + sys sys_io_cancel 3 /* 4245 */ + sys sys_exit_group 1 + sys sys_lookup_dcookie 4 + sys sys_epoll_create 1 + sys sys_epoll_ctl 4 + sys sys_epoll_wait 4 /* 4250 */ + sys sys_remap_file_pages 5 + sys sys_set_tid_address 1 + sys sys_restart_syscall 0 + sys sys_fadvise64_64 7 + sys sys_statfs64 3 /* 4255 */ + sys sys_fstatfs64 2 + sys sys_timer_create 3 + sys sys_timer_settime 4 + sys sys_timer_gettime 2 + sys sys_timer_getoverrun 1 /* 4260 */ + sys sys_timer_delete 1 + sys sys_clock_settime 2 + sys sys_clock_gettime 2 + sys sys_clock_getres 2 + sys sys_clock_nanosleep 4 /* 4265 */ + sys sys_tgkill 3 + sys sys_utimes 2 + sys sys_mbind 4 + sys sys_ni_syscall 0 /* sys_get_mempolicy */ + sys sys_ni_syscall 0 /* 4270 sys_set_mempolicy */ + sys sys_mq_open 4 + sys sys_mq_unlink 1 + sys sys_mq_timedsend 5 + sys sys_mq_timedreceive 5 + sys sys_mq_notify 2 /* 4275 */ + sys sys_mq_getsetattr 3 + sys sys_ni_syscall 0 /* sys_vserver */ + sys sys_waitid 5 + sys sys_ni_syscall 0 /* available, was setaltroot */ + sys sys_add_key 5 /* 4280 */ + sys sys_request_key 4 + sys sys_keyctl 5 + sys sys_set_thread_area 1 + sys sys_inotify_init 0 + sys sys_inotify_add_watch 3 /* 4285 */ + sys sys_inotify_rm_watch 2 + sys sys_migrate_pages 4 + sys sys_openat 4 + sys sys_mkdirat 3 + sys sys_mknodat 4 /* 4290 */ + sys sys_fchownat 5 + sys sys_futimesat 3 + sys sys_fstatat64 4 + sys sys_unlinkat 3 + sys sys_renameat 4 /* 4295 */ + sys sys_linkat 5 + sys sys_symlinkat 3 + sys sys_readlinkat 4 + sys sys_fchmodat 3 + sys sys_faccessat 3 /* 4300 */ + sys sys_pselect6 6 + sys sys_ppoll 5 + sys sys_unshare 1 + sys sys_splice 6 + sys sys_sync_file_range 7 /* 4305 */ + sys sys_tee 4 + sys sys_vmsplice 4 + sys sys_move_pages 6 + sys sys_set_robust_list 2 + sys sys_get_robust_list 3 /* 4310 */ + sys sys_kexec_load 4 + sys sys_getcpu 3 + sys sys_epoll_pwait 6 + sys sys_ioprio_set 3 + sys sys_ioprio_get 2 /* 4315 */ + sys sys_utimensat 4 + sys sys_signalfd 3 + sys sys_ni_syscall 0 /* was timerfd */ + sys sys_eventfd 1 + sys sys_fallocate 6 /* 4320 */ + sys sys_timerfd_create 2 + sys sys_timerfd_gettime 2 + sys sys_timerfd_settime 4 + sys sys_signalfd4 4 + sys sys_eventfd2 2 /* 4325 */ + sys sys_epoll_create1 1 + sys sys_dup3 3 + sys sys_pipe2 2 + sys sys_inotify_init1 1 + sys sys_preadv 6 /* 4330 */ + sys sys_pwritev 6 + sys sys_rt_tgsigqueueinfo 4 + sys sys_perf_event_open 5 + sys sys_accept4 4 + sys sys_recvmmsg 5 /* 4335 */ + sys sys_fanotify_init 2 + sys sys_fanotify_mark 6 + sys sys_prlimit64 4 + sys sys_name_to_handle_at 5 + sys sys_open_by_handle_at 3 /* 4340 */ + sys sys_clock_adjtime 2 + sys sys_syncfs 1 + sys sys_sendmmsg 4 + sys sys_setns 2 + sys sys_process_vm_readv 6 /* 4345 */ + sys sys_process_vm_writev 6 + sys sys_kcmp 5 + sys sys_finit_module 3 + .endm + + /* We pre-compute the number of _instruction_ bytes needed to + load or store the arguments 6-8. Negative values are ignored. */ + + .macro sys function, nargs + PTR \function + LONG (\nargs << 2) - (5 << 2) + .endm + + .align 3 + .type sys_call_table,@object +EXPORT(sys_call_table) + syscalltable + .size sys_call_table, . - sys_call_table diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 57e3742..be6627e 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -114,8 +114,7 @@ illegal_syscall: END(handle_sys64) .align 3 - .type sys_call_table, @object -EXPORT(sys_call_table) +sys_call_table: PTR sys_read /* 5000 */ PTR sys_write PTR sys_open diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 2f48f59..cab1507 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -103,7 +103,6 @@ not_n32_scall: END(handle_sysn32) - .type sysn32_call_table, @object EXPORT(sysn32_call_table) PTR sys_read /* 6000 */ PTR sys_write diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index f1acdb4..37605dc 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -53,7 +53,7 @@ NESTED(handle_sys, PT_SIZE, sp) sll a3, a3, 0 dsll t0, v0, 3 # offset into table - ld t2, (sys32_call_table - (__NR_O32_Linux * 8))(t0) + ld t2, (sys_call_table - (__NR_O32_Linux * 8))(t0) sd a3, PT_R26(sp) # save a3 for syscall restarting @@ -168,7 +168,7 @@ LEAF(sys32_syscall) beqz t0, einval # do not recurse dsll t1, t0, 3 beqz v0, einval - ld t2, sys32_call_table(t1) # syscall routine + ld t2, sys_call_table(t1) # syscall routine move a0, a1 # shift argument registers move a1, a2 @@ -190,8 +190,8 @@ einval: li v0, -ENOSYS END(sys32_syscall) .align 3 - .type sys32_call_table,@object -EXPORT(sys32_call_table) + .type sys_call_table,@object +sys_call_table: PTR sys32_syscall /* 4000 */ PTR sys_exit PTR __sys_fork @@ -541,4 +541,4 @@ EXPORT(sys32_call_table) PTR compat_sys_process_vm_writev PTR sys_kcmp PTR sys_finit_module - .size sys32_call_table,.-sys32_call_table + .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index a842154..c538d6e 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -300,13 +300,12 @@ static void __init bootmem_init(void) int i; /* - * Sanity check any INITRD first. We don't take it into account - * for bootmem setup initially, rely on the end-of-kernel-code - * as our memory range starting point. Once bootmem is inited we - * will reserve the area used for the initrd. + * Init any data related to initrd. It's a nop if INITRD is + * not selected. Once that done we can determine the low bound + * of usable memory. */ - init_initrd(); - reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end)); + reserved_end = max(init_initrd(), + (unsigned long) PFN_UP(__pa_symbol(&_end))); /* * max_low_pfn is not a number of pages. The number of pages @@ -363,14 +362,6 @@ static void __init bootmem_init(void) max_low_pfn = PFN_DOWN(HIGHMEM_START); } -#ifdef CONFIG_BLK_DEV_INITRD - /* - * mapstart should be after initrd_end - */ - if (initrd_end) - mapstart = max(mapstart, (unsigned long)PFN_UP(__pa(initrd_end))); -#endif - /* * Initialize the boot-time allocator with low memory only. */ diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 1905a41..57de8b7 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -314,7 +314,7 @@ SYSCALL_DEFINE3(32_sigaction, long, sig, const struct compat_sigaction __user *, return ret; } -int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from) +int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from) { int err; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 2362665..126da74 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -136,10 +136,10 @@ static void bmips_prepare_cpus(unsigned int max_cpus) { if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, "smp_ipi0", NULL)) - panic("Can't request IPI0 interrupt"); + panic("Can't request IPI0 interrupt\n"); if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, "smp_ipi1", NULL)) - panic("Can't request IPI1 interrupt"); + panic("Can't request IPI1 interrupt\n"); } /* diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 0a022ee..5c208ed 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -150,6 +150,7 @@ asmlinkage void start_secondary(void) void __irq_entry smp_call_function_interrupt(void) { irq_enter(); + generic_smp_call_function_single_interrupt(); generic_smp_call_function_interrupt(); irq_exit(); } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f9c8746..524841f 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -330,7 +330,6 @@ void show_regs(struct pt_regs *regs) void show_registers(struct pt_regs *regs) { const int field = 2 * sizeof(unsigned long); - mm_segment_t old_fs = get_fs(); __show_regs(regs); print_modules(); @@ -345,13 +344,9 @@ void show_registers(struct pt_regs *regs) printk("*HwTLS: %0*lx\n", field, tls); } - if (!user_mode(regs)) - /* Necessary for getting the correct stack content */ - set_fs(KERNEL_DS); show_stacktrace(current, regs); show_code((unsigned int __user *) regs->cp0_epc); printk("\n"); - set_fs(old_fs); } static int regs_to_trapnr(struct pt_regs *regs) @@ -371,8 +366,7 @@ void __noreturn die(const char *str, struct pt_regs *regs) oops_enter(); - if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), - SIGSEGV) == NOTIFY_STOP) + if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) sig = 0; console_verbose(); @@ -463,8 +457,8 @@ asmlinkage void do_be(struct pt_regs *regs) printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", data ? "Data" : "Instruction", field, regs->cp0_epc, field, regs->regs[31]); - if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), - SIGBUS) == NOTIFY_STOP) + if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) + == NOTIFY_STOP) goto out; die_if_kernel("Oops", regs); @@ -733,8 +727,8 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) siginfo_t info = {0}; prev_state = exception_enter(); - if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), - SIGFPE) == NOTIFY_STOP) + if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) + == NOTIFY_STOP) goto out; die_if_kernel("FP exception in kernel code", regs); @@ -804,8 +798,7 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, return; #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ - if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), - SIGTRAP) == NOTIFY_STOP) + if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) return; /* @@ -899,14 +892,12 @@ asmlinkage void do_bp(struct pt_regs *regs) */ switch (bcode) { case BRK_KPROBE_BP: - if (notify_die(DIE_BREAK, "debug", regs, bcode, - regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) + if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) goto out; else break; case BRK_KPROBE_SSTEPBP: - if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, - regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) + if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) goto out; else break; @@ -970,8 +961,8 @@ asmlinkage void do_ri(struct pt_regs *regs) int status = -1; prev_state = exception_enter(); - if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), - SIGILL) == NOTIFY_STOP) + if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) + == NOTIFY_STOP) goto out; die_if_kernel("Reserved instruction in kernel code", regs); @@ -1497,14 +1488,10 @@ int register_nmi_notifier(struct notifier_block *nb) void __noreturn nmi_exception_handler(struct pt_regs *regs) { - char str[100]; - raw_notifier_call_chain(&nmi_chain, 0, regs); bust_spinlocks(1); - snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", - smp_processor_id(), regs->cp0_epc); - regs->cp0_epc = read_c0_errorepc(); - die(str, regs); + printk("NMI taken!!!!\n"); + die("NMI", regs); } #define VECTORSPACING 0x100 /* for EI/VI mode */ @@ -1567,6 +1554,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) unsigned char *b; BUG_ON(!cpu_has_veic && !cpu_has_vint); + BUG_ON((n < 0) && (n > 9)); if (addr == NULL) { handler = (unsigned long) do_default_vi; diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c index 73b3482..a7b0445 100644 --- a/arch/mips/kvm/kvm_mips.c +++ b/arch/mips/kvm/kvm_mips.c @@ -198,13 +198,12 @@ kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) return -ENOIOCTLCMD; } -void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, +void kvm_arch_free_memslot(struct kvm_memory_slot *free, struct kvm_memory_slot *dont) { } -int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, - unsigned long npages) +int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages) { return 0; } diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 85685e1..eb3e186 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -390,7 +390,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) ret = of_irq_to_resource_table(eiu_node, ltq_eiu_irq, exin_avail); if (ret != exin_avail) - panic("failed to load external irq resources"); + panic("failed to load external irq resources\n"); if (request_mem_region(res.start, resource_size(&res), res.name) < 0) diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 19686c5..49c4603 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -14,7 +14,6 @@ #include <asm/bootinfo.h> #include <asm/time.h> -#include <asm/prom.h> #include <lantiq.h> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 51804b1..c24924f 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -128,7 +128,7 @@ static int pmu_enable(struct clk *clk) do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits)); if (!retry) - panic("activating PMU module failed!"); + panic("activating PMU module failed!\n"); return 0; } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 62ffd20..bc6f96f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -346,8 +346,14 @@ static void r4k_blast_scache_setup(void) static inline void local_r4k___flush_cache_all(void * args) { +#if defined(CONFIG_CPU_LOONGSON2) + r4k_blast_scache(); + return; +#endif + r4k_blast_dcache(); + r4k_blast_icache(); + switch (current_cpu_type()) { - case CPU_LOONGSON2: case CPU_R4000SC: case CPU_R4000MC: case CPU_R4400SC: @@ -355,18 +361,7 @@ static inline void local_r4k___flush_cache_all(void * args) case CPU_R10000: case CPU_R12000: case CPU_R14000: - /* - * These caches are inclusive caches, that is, if something - * is not cached in the S-cache, we know it also won't be - * in one of the primary caches. - */ r4k_blast_scache(); - break; - - default: - r4k_blast_dcache(); - r4k_blast_icache(); - break; } } @@ -577,17 +572,8 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo if (end - start > icache_size) r4k_blast_icache(); - else { - switch (boot_cpu_type()) { - case CPU_LOONGSON2: - protected_blast_icache_range(start, end); - break; - - default: - protected_loongson23_blast_icache_range(start, end); - break; - } - } + else + protected_blast_icache_range(start, end); } static inline void local_r4k_flush_icache_range_ipi(void *args) @@ -1123,15 +1109,16 @@ static void probe_pcache(void) case CPU_ALCHEMY: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; - - case CPU_LOONGSON2: - /* - * LOONGSON2 has 4 way icache, but when using indexed cache op, - * one op will act on all 4 ways - */ - c->icache.ways = 1; } +#ifdef CONFIG_CPU_LOONGSON2 + /* + * LOONGSON2 has 4 way icache, but when using indexed cache op, + * one op will act on all 4 ways + */ + c->icache.ways = 1; +#endif + printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", @@ -1206,6 +1193,7 @@ static int probe_scache(void) return 1; } +#if defined(CONFIG_CPU_LOONGSON2) static void __init loongson2_sc_init(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -1221,6 +1209,7 @@ static void __init loongson2_sc_init(void) c->options |= MIPS_CPU_INCLUSIVE_CACHES; } +#endif extern int r5k_sc_init(void); extern int rm7k_sc_init(void); @@ -1270,10 +1259,11 @@ static void setup_scache(void) #endif return; +#if defined(CONFIG_CPU_LOONGSON2) case CPU_LOONGSON2: loongson2_sc_init(); return; - +#endif case CPU_XLP: /* don't need to worry about L2, fully coherent */ return; diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 2e94185..5f8b955 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -297,6 +297,7 @@ static void mips_dma_sync_single_for_cpu(struct device *dev, static void mips_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { + plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) __dma_sync(dma_addr_to_page(dev, dma_handle), dma_handle & ~PAGE_MASK, size, direction); @@ -326,7 +327,7 @@ static void mips_dma_sync_sg_for_device(struct device *dev, int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { - return 0; + return plat_dma_mapping_error(dev, dma_addr); } int mips_dma_supported(struct device *dev, u64 mask) @@ -339,6 +340,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, { BUG_ON(direction == DMA_NONE); + plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) __dma_sync_virtual(vaddr, size, direction); } diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 1215617..e205ef5 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -124,7 +124,7 @@ void *kmap_coherent(struct page *page, unsigned long addr) BUG_ON(Page_dcache_dirty(page)); - pagefault_disable(); + inc_preempt_count(); idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); #ifdef CONFIG_MIPS_MT_SMTC idx += FIX_N_COLOURS * smp_processor_id() + @@ -193,7 +193,8 @@ void kunmap_coherent(void) write_c0_entryhi(old_ctx); EXIT_CRITICAL(flags); #endif - pagefault_enable(); + dec_preempt_count(); + preempt_check_resched(); } void copy_user_highpage(struct page *to, struct page *from, diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S index 30a494d..79bca31 100644 --- a/arch/mips/mm/tlb-funcs.S +++ b/arch/mips/mm/tlb-funcs.S @@ -16,10 +16,12 @@ #define FASTPATH_SIZE 128 +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT LEAF(tlbmiss_handler_setup_pgd) .space 16 * 4 END(tlbmiss_handler_setup_pgd) EXPORT(tlbmiss_handler_setup_pgd_end) +#endif LEAF(handle_tlbm) .space FASTPATH_SIZE * 4 diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index da3b0b9..bb3a5f64 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -52,26 +52,21 @@ extern void build_tlb_refill_handler(void); #endif /* CONFIG_MIPS_MT_SMTC */ +#if defined(CONFIG_CPU_LOONGSON2) /* * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, * unfortrunately, itlb is not totally transparent to software. */ -static inline void flush_itlb(void) -{ - switch (current_cpu_type()) { - case CPU_LOONGSON2: - write_c0_diag(4); - break; - default: - break; - } -} +#define FLUSH_ITLB write_c0_diag(4); -static inline void flush_itlb_vm(struct vm_area_struct *vma) -{ - if (vma->vm_flags & VM_EXEC) - flush_itlb(); -} +#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); } + +#else + +#define FLUSH_ITLB +#define FLUSH_ITLB_VM(vma) + +#endif void local_flush_tlb_all(void) { @@ -98,7 +93,7 @@ void local_flush_tlb_all(void) } tlbw_use_hazard(); write_c0_entryhi(old_ctx); - flush_itlb(); + FLUSH_ITLB; EXIT_CRITICAL(flags); } EXPORT_SYMBOL(local_flush_tlb_all); @@ -160,7 +155,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, } else { drop_mmu_context(mm, cpu); } - flush_itlb(); + FLUSH_ITLB; EXIT_CRITICAL(flags); } } @@ -202,7 +197,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) } else { local_flush_tlb_all(); } - flush_itlb(); + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -235,7 +230,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) finish: write_c0_entryhi(oldpid); - flush_itlb_vm(vma); + FLUSH_ITLB_VM(vma); EXIT_CRITICAL(flags); } } @@ -267,7 +262,7 @@ void local_flush_tlb_one(unsigned long page) tlbw_use_hazard(); } write_c0_entryhi(oldpid); - flush_itlb(); + FLUSH_ITLB; EXIT_CRITICAL(flags); } @@ -340,7 +335,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) tlb_write_indexed(); } tlbw_use_hazard(); - flush_itlb_vm(vma); + FLUSH_ITLB_VM(vma); EXIT_CRITICAL(flags); } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 183f2b5..9bb3a93 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -340,6 +340,10 @@ static struct work_registers build_get_work_registers(u32 **p) { struct work_registers r; + int smp_processor_id_reg; + int smp_processor_id_sel; + int smp_processor_id_shift; + if (scratch_reg >= 0) { /* Save in CPU local C0_KScratch? */ UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); @@ -350,9 +354,25 @@ static struct work_registers build_get_work_registers(u32 **p) } if (num_possible_cpus() > 1) { +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + smp_processor_id_shift = 51; + smp_processor_id_reg = 20; /* XContext */ + smp_processor_id_sel = 0; +#else +# ifdef CONFIG_32BIT + smp_processor_id_shift = 25; + smp_processor_id_reg = 4; /* Context */ + smp_processor_id_sel = 0; +# endif +# ifdef CONFIG_64BIT + smp_processor_id_shift = 26; + smp_processor_id_reg = 4; /* Context */ + smp_processor_id_sel = 0; +# endif +#endif /* Get smp_processor_id */ - UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); - UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); + UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel); + UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift); /* handler_reg_save index in K0 */ UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); @@ -799,11 +819,11 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, } /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT if (pgd_reg != -1) { /* pgd is in pgd_reg */ UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); } else { -#if defined(CONFIG_MIPS_PGD_C0_CONTEXT) /* * &pgd << 11 stored in CONTEXT [23..63]. */ @@ -815,18 +835,30 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, /* 1 0 1 0 1 << 6 xkphys cached */ uasm_i_ori(p, ptr, ptr, 0x540); uasm_i_drotr(p, ptr, ptr, 11); + } #elif defined(CONFIG_SMP) - UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); - uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_daddu(p, ptr, ptr, tmp); - uasm_i_dmfc0(p, tmp, C0_BADVADDR); - uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); +# ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC uses TCBind value as "CPU" index + */ + uasm_i_mfc0(p, ptr, C0_TCBIND); + uasm_i_dsrl_safe(p, ptr, ptr, 19); +# else + /* + * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 + * stored in CONTEXT. + */ + uasm_i_dmfc0(p, ptr, C0_CONTEXT); + uasm_i_dsrl_safe(p, ptr, ptr, 23); +# endif + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_daddu(p, ptr, ptr, tmp); + uasm_i_dmfc0(p, tmp, C0_BADVADDR); + uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); #else - UASM_i_LA_mostly(p, ptr, pgdc); - uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); + UASM_i_LA_mostly(p, ptr, pgdc); + uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); #endif - } uasm_l_vmalloc_done(l, *p); @@ -921,25 +953,31 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, static void __maybe_unused build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { - if (pgd_reg != -1) { - /* pgd is in pgd_reg */ - uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); - uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ - } else { - long pgdc = (long)pgd_current; + long pgdc = (long)pgd_current; - /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ + /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ #ifdef CONFIG_SMP - uasm_i_mfc0(p, ptr, SMP_CPUID_REG); - UASM_i_LA_mostly(p, tmp, pgdc); - uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); - uasm_i_addu(p, ptr, tmp, ptr); +#ifdef CONFIG_MIPS_MT_SMTC + /* + * SMTC uses TCBind value as "CPU" index + */ + uasm_i_mfc0(p, ptr, C0_TCBIND); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_srl(p, ptr, ptr, 19); #else - UASM_i_LA_mostly(p, ptr, pgdc); + /* + * smp_processor_id() << 2 is stored in CONTEXT. + */ + uasm_i_mfc0(p, ptr, C0_CONTEXT); + UASM_i_LA_mostly(p, tmp, pgdc); + uasm_i_srl(p, ptr, ptr, 23); #endif - uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ - uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); - } + uasm_i_addu(p, ptr, tmp, ptr); +#else + UASM_i_LA_mostly(p, ptr, pgdc); +#endif + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ + uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -1311,100 +1349,95 @@ static void build_r4000_tlb_refill_handler(void) * need three, with the second nop'ed and the third being * unused. */ - switch (boot_cpu_type()) { - default: - if (sizeof(long) == 4) { - case CPU_LOONGSON2: - /* Loongson2 ebase is different than r4k, we have more space */ - if ((p - tlb_handler) > 64) - panic("TLB refill handler space exceeded"); + /* Loongson2 ebase is different than r4k, we have more space */ +#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) + if ((p - tlb_handler) > 64) + panic("TLB refill handler space exceeded"); +#else + if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) + || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) + && uasm_insn_has_bdelay(relocs, + tlb_handler + MIPS64_REFILL_INSNS - 3))) + panic("TLB refill handler space exceeded"); +#endif + + /* + * Now fold the handler in the TLB refill handler space. + */ +#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) + f = final_handler; + /* Simplest case, just copy the handler. */ + uasm_copy_handler(relocs, labels, tlb_handler, p, f); + final_len = p - tlb_handler; +#else /* CONFIG_64BIT */ + f = final_handler + MIPS64_REFILL_INSNS; + if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { + /* Just copy the handler. */ + uasm_copy_handler(relocs, labels, tlb_handler, p, f); + final_len = p - tlb_handler; + } else { +#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT + const enum label_id ls = label_tlb_huge_update; +#else + const enum label_id ls = label_vmalloc; +#endif + u32 *split; + int ov = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) + ; + BUG_ON(i == ARRAY_SIZE(labels)); + split = labels[i].addr; + + /* + * See if we have overflown one way or the other. + */ + if (split > tlb_handler + MIPS64_REFILL_INSNS || + split < p - MIPS64_REFILL_INSNS) + ov = 1; + + if (ov) { /* - * Now fold the handler in the TLB refill handler space. + * Split two instructions before the end. One + * for the branch and one for the instruction + * in the delay slot. */ - f = final_handler; - /* Simplest case, just copy the handler. */ - uasm_copy_handler(relocs, labels, tlb_handler, p, f); - final_len = p - tlb_handler; - break; - } else { - if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) - || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) - && uasm_insn_has_bdelay(relocs, - tlb_handler + MIPS64_REFILL_INSNS - 3))) - panic("TLB refill handler space exceeded"); + split = tlb_handler + MIPS64_REFILL_INSNS - 2; + /* - * Now fold the handler in the TLB refill handler space. + * If the branch would fall in a delay slot, + * we must back up an additional instruction + * so that it is no longer in a delay slot. */ - f = final_handler + MIPS64_REFILL_INSNS; - if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { - /* Just copy the handler. */ - uasm_copy_handler(relocs, labels, tlb_handler, p, f); - final_len = p - tlb_handler; - } else { -#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT - const enum label_id ls = label_tlb_huge_update; -#else - const enum label_id ls = label_vmalloc; -#endif - u32 *split; - int ov = 0; - int i; - - for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) - ; - BUG_ON(i == ARRAY_SIZE(labels)); - split = labels[i].addr; - - /* - * See if we have overflown one way or the other. - */ - if (split > tlb_handler + MIPS64_REFILL_INSNS || - split < p - MIPS64_REFILL_INSNS) - ov = 1; - - if (ov) { - /* - * Split two instructions before the end. One - * for the branch and one for the instruction - * in the delay slot. - */ - split = tlb_handler + MIPS64_REFILL_INSNS - 2; - - /* - * If the branch would fall in a delay slot, - * we must back up an additional instruction - * so that it is no longer in a delay slot. - */ - if (uasm_insn_has_bdelay(relocs, split - 1)) - split--; - } - /* Copy first part of the handler. */ - uasm_copy_handler(relocs, labels, tlb_handler, split, f); - f += split - tlb_handler; - - if (ov) { - /* Insert branch. */ - uasm_l_split(&l, final_handler); - uasm_il_b(&f, &r, label_split); - if (uasm_insn_has_bdelay(relocs, split)) - uasm_i_nop(&f); - else { - uasm_copy_handler(relocs, labels, - split, split + 1, f); - uasm_move_labels(labels, f, f + 1, -1); - f++; - split++; - } - } - - /* Copy the rest of the handler. */ - uasm_copy_handler(relocs, labels, split, p, final_handler); - final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + - (p - split); + if (uasm_insn_has_bdelay(relocs, split - 1)) + split--; + } + /* Copy first part of the handler. */ + uasm_copy_handler(relocs, labels, tlb_handler, split, f); + f += split - tlb_handler; + + if (ov) { + /* Insert branch. */ + uasm_l_split(&l, final_handler); + uasm_il_b(&f, &r, label_split); + if (uasm_insn_has_bdelay(relocs, split)) + uasm_i_nop(&f); + else { + uasm_copy_handler(relocs, labels, + split, split + 1, f); + uasm_move_labels(labels, f, f + 1, -1); + f++; + split++; } } - break; + + /* Copy the rest of the handler. */ + uasm_copy_handler(relocs, labels, split, p, final_handler); + final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + + (p - split); } +#endif /* CONFIG_64BIT */ uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB refill handler (%u instructions).\n", @@ -1418,30 +1451,28 @@ static void build_r4000_tlb_refill_handler(void) extern u32 handle_tlbl[], handle_tlbl_end[]; extern u32 handle_tlbs[], handle_tlbs_end[]; extern u32 handle_tlbm[], handle_tlbm_end[]; + +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; -static void build_setup_pgd(void) +static void build_r4000_setup_pgd(void) { const int a0 = 4; - const int __maybe_unused a1 = 5; - const int __maybe_unused a2 = 6; + const int a1 = 5; u32 *p = tlbmiss_handler_setup_pgd; const int tlbmiss_handler_setup_pgd_size = tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT - long pgdc = (long)pgd_current; -#endif + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * sizeof(tlbmiss_handler_setup_pgd[0])); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); + pgd_reg = allocate_kscratch(); -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - if (pgd_reg == -1) { - struct uasm_label *l = labels; - struct uasm_reloc *r = relocs; + if (pgd_reg == -1) { /* PGD << 11 in c0_Context */ /* * If it is a ckseg0 address, convert to a physical @@ -1463,26 +1494,6 @@ static void build_setup_pgd(void) uasm_i_jr(&p, 31); UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); } -#else -#ifdef CONFIG_SMP - /* Save PGD to pgd_current[smp_processor_id()] */ - UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); - UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); - UASM_i_LA_mostly(&p, a2, pgdc); - UASM_i_ADDU(&p, a2, a2, a1); - UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); -#else - UASM_i_LA_mostly(&p, a2, pgdc); - UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); -#endif /* SMP */ - uasm_i_jr(&p, 31); - - /* if pgd_reg is allocated, save PGD also to scratch register */ - if (pgd_reg != -1) - UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); - else - uasm_i_nop(&p); -#endif if (p >= tlbmiss_handler_setup_pgd_end) panic("tlbmiss_handler_setup_pgd space exceeded"); @@ -1493,6 +1504,7 @@ static void build_setup_pgd(void) dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, tlbmiss_handler_setup_pgd_size); } +#endif static void iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) @@ -2185,8 +2197,10 @@ static void flush_tlb_handlers(void) (unsigned long)handle_tlbs_end); local_flush_icache_range((unsigned long)handle_tlbm, (unsigned long)handle_tlbm_end); +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, (unsigned long)tlbmiss_handler_setup_pgd_end); +#endif } void build_tlb_refill_handler(void) @@ -2218,7 +2232,6 @@ void build_tlb_refill_handler(void) if (!run_once) { if (!cpu_has_local_ebase) build_r3000_tlb_refill_handler(); - build_setup_pgd(); build_r3000_tlb_load_handler(); build_r3000_tlb_store_handler(); build_r3000_tlb_modify_handler(); @@ -2242,7 +2255,9 @@ void build_tlb_refill_handler(void) default: if (!run_once) { scratch_reg = allocate_kscratch(); - build_setup_pgd(); +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + build_r4000_setup_pgd(); +#endif build_r4000_tlb_load_handler(); build_r4000_tlb_store_handler(); build_r4000_tlb_modify_handler(); diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 0892575..5b28e81 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -37,6 +37,7 @@ #include <asm/irq_regs.h> #include <asm/mips-boards/malta.h> #include <asm/mips-boards/maltaint.h> +#include <asm/mips-boards/piix4.h> #include <asm/gt64120.h> #include <asm/mips-boards/generic.h> #include <asm/mips-boards/msc01_pci.h> diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index 928ba84..b5059dc 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -10,8 +10,6 @@ #include <linux/of_fdt.h> #include <linux/bootmem.h> -#include <asm/prom.h> - #include <asm/mips-boards/generic.h> const char *get_system_type(void) diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index c0eded0..6f8feb9 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -245,7 +245,7 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask) return threadmode; unsupp: - panic("Unsupported CPU mask %lx", + panic("Unsupported CPU mask %lx\n", (unsigned long)cpumask_bits(wakeup_mask)[0]); return 0; } diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c index 8316d54..88df445 100644 --- a/arch/mips/netlogic/xlp/dt.c +++ b/arch/mips/netlogic/xlp/dt.c @@ -39,11 +39,8 @@ #include <linux/of_platform.h> #include <linux/of_device.h> -#include <asm/prom.h> - extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_xlp_fvp_begin[], __dtb_start[]; -static void *xlp_fdt_blob; void __init *xlp_dt_init(void *fdtp) { @@ -70,26 +67,19 @@ void __init *xlp_dt_init(void *fdtp) break; } } - xlp_fdt_blob = fdtp; + initial_boot_params = fdtp; return fdtp; } -void __init xlp_early_init_devtree(void) -{ - __dt_setup_arch(xlp_fdt_blob); - strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); -} - void __init device_tree_init(void) { unsigned long base, size; - struct boot_param_header *fdtp = xlp_fdt_blob; - if (!fdtp) + if (!initial_boot_params) return; - base = virt_to_phys(fdtp); - size = be32_to_cpu(fdtp->totalsize); + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); /* Before we do anything, lets reserve the dt blob */ reserve_bootmem(base, size, BOOTMEM_DEFAULT); diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 6d981bb..76a7131 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -98,7 +98,7 @@ void __init plat_mem_setup(void) pm_power_off = nlm_linux_exit; /* memory and bootargs from DT */ - xlp_early_init_devtree(); + early_init_devtree(initial_boot_params); if (boot_mem_map.nr_map == 0) { pr_info("Using DRAM BARs for memory map.\n"); diff --git a/arch/mips/pci/fixup-lantiq.c b/arch/mips/pci/fixup-lantiq.c index c2ce41e..6c829df 100644 --- a/arch/mips/pci/fixup-lantiq.c +++ b/arch/mips/pci/fixup-lantiq.c @@ -25,5 +25,16 @@ int pcibios_plat_dev_init(struct pci_dev *dev) int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - return of_irq_parse_and_map_pci(dev, slot, pin); + struct of_irq dev_irq; + int irq; + + if (of_irq_map_pci(dev, &dev_irq)) { + dev_err(&dev->dev, "trying to map irq for unknown slot:%d pin:%d\n", + slot, pin); + return 0; + } + irq = irq_create_of_mapping(dev_irq.controller, dev_irq.specifier, + dev_irq.size); + dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, irq); + return irq; } diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index df36e23..07ada7f 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c @@ -1,6 +1,5 @@ #include <linux/init.h> #include <linux/pci.h> -#include <asm/mips-boards/piix4.h> /* PCI interrupt pins */ #define PCIA 1 @@ -54,8 +53,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) static void malta_piix_func0_fixup(struct pci_dev *pdev) { unsigned char reg_val; - /* PIIX PIRQC[A:D] irq mappings */ - static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = { + static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */ 0, 0, 0, 3, 4, 5, 6, 7, 0, 9, 10, 11, @@ -65,12 +63,11 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev) /* Interrogate PIIX4 to get PCI IRQ mapping */ for (i = 0; i <= 3; i++) { - pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, ®_val); - if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) + pci_read_config_byte(pdev, 0x60+i, ®_val); + if (reg_val & 0x80) pci_irq[PCIA+i] = 0; /* Disabled */ else - pci_irq[PCIA+i] = piixirqmap[reg_val & - PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK]; + pci_irq[PCIA+i] = piixirqmap[reg_val & 15]; } /* Done by YAMON 2.00 onwards */ @@ -79,9 +76,8 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev) * Set top of main memory accessible by ISA or DMA * devices to 16 Mb. */ - pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, ®_val); - pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | - PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK); + pci_read_config_byte(pdev, 0x69, ®_val); + pci_write_config_byte(pdev, 0x69, reg_val | 0xf0); } } @@ -97,14 +93,10 @@ static void malta_piix_func1_fixup(struct pci_dev *pdev) /* * IDE Decode enable. */ - pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI, - ®_val); - pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI, - reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN); - pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI, - ®_val); - pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI, - reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN); + pci_read_config_byte(pdev, 0x41, ®_val); + pci_write_config_byte(pdev, 0x41, reg_val|0x80); + pci_read_config_byte(pdev, 0x43, ®_val); + pci_write_config_byte(pdev, 0x43, reg_val|0x80); } } @@ -116,12 +108,10 @@ static void quirk_dlcsetup(struct pci_dev *dev) { u8 odlc, ndlc; - (void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc); + (void) pci_read_config_byte(dev, 0x82, &odlc); /* Enable passive releases and delayed transaction */ - ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN | - PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN | - PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN; - (void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc); + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index d471a26..18517dd 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -363,6 +363,9 @@ static int ar71xx_pci_probe(struct platform_device *pdev) spin_lock_init(&apc->lock); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); + if (!res) + return -EINVAL; + apc->cfg_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(apc->cfg_base)) return PTR_ERR(apc->cfg_base); diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 785b265..65ec032 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -362,16 +362,25 @@ static int ar724x_pci_probe(struct platform_device *pdev) return -ENOMEM; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); + if (!res) + return -EINVAL; + apc->ctrl_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(apc->ctrl_base)) return PTR_ERR(apc->ctrl_base); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); + if (!res) + return -EINVAL; + apc->devcfg_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(apc->devcfg_base)) return PTR_ERR(apc->devcfg_base); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base"); + if (!res) + return -EINVAL; + apc->crp_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(apc->crp_base)) return PTR_ERR(apc->crp_base); diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c index adeff2b..95c9d41 100644 --- a/arch/mips/pci/pci-rt3883.c +++ b/arch/mips/pci/pci-rt3883.c @@ -583,7 +583,29 @@ err_put_intc_node: int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - return of_irq_parse_and_map_pci(dev, slot, pin); + struct of_irq dev_irq; + int err; + int irq; + + err = of_irq_map_pci(dev, &dev_irq); + if (err) { + pr_err("pci %s: unable to get irq map, err=%d\n", + pci_name((struct pci_dev *) dev), err); + return 0; + } + + irq = irq_create_of_mapping(dev_irq.controller, + dev_irq.specifier, + dev_irq.size); + + if (irq == 0) + pr_crit("pci %s: no irq found for pin %u\n", + pci_name((struct pci_dev *) dev), pin); + else + pr_info("pci %s: using irq %d for pin %u\n", + pci_name((struct pci_dev *) dev), irq, pin); + + return irq; } int pcibios_plat_dev_init(struct pci_dev *dev) diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 1bf60b1..33e7aa5 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -120,37 +120,51 @@ static void pcibios_scanbus(struct pci_controller *hose) #ifdef CONFIG_OF void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) { - struct of_pci_range range; - struct of_pci_range_parser parser; + const __be32 *ranges; + int rlen; + int pna = of_n_addr_cells(node); + int np = pna + 5; pr_info("PCI host bridge %s ranges:\n", node->full_name); - hose->of_node = node; - - if (of_pci_range_parser_init(&parser, node)) + ranges = of_get_property(node, "ranges", &rlen); + if (ranges == NULL) return; + hose->of_node = node; - for_each_of_pci_range(&parser, &range) { + while ((rlen -= np * 4) >= 0) { + u32 pci_space; struct resource *res = NULL; - - switch (range.flags & IORESOURCE_TYPE_BITS) { - case IORESOURCE_IO: + u64 addr, size; + + pci_space = be32_to_cpup(&ranges[0]); + addr = of_translate_address(node, ranges + 3); + size = of_read_number(ranges + pna + 3, 2); + ranges += np; + switch ((pci_space >> 24) & 0x3) { + case 1: /* PCI IO space */ pr_info(" IO 0x%016llx..0x%016llx\n", - range.cpu_addr, - range.cpu_addr + range.size - 1); + addr, addr + size - 1); hose->io_map_base = - (unsigned long)ioremap(range.cpu_addr, - range.size); + (unsigned long)ioremap(addr, size); res = hose->io_resource; + res->flags = IORESOURCE_IO; break; - case IORESOURCE_MEM: + case 2: /* PCI Memory space */ + case 3: /* PCI 64 bits Memory space */ pr_info(" MEM 0x%016llx..0x%016llx\n", - range.cpu_addr, - range.cpu_addr + range.size - 1); + addr, addr + size - 1); res = hose->mem_resource; + res->flags = IORESOURCE_MEM; break; } - if (res != NULL) - of_pci_range_to_resource(&range, node, res); + if (res != NULL) { + res->start = addr; + res->name = node->full_name; + res->end = res->start + size - 1; + res->parent = NULL; + res->sibling = NULL; + res->child = NULL; + } } } diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig new file mode 100644 index 0000000..dd91fba --- /dev/null +++ b/arch/mips/powertv/Kconfig @@ -0,0 +1,12 @@ +config BOOTLOADER_FAMILY + string "POWERTV Bootloader Family string" + default "85" + depends on POWERTV + help + This value should be specified when the bootloader driver is disabled + and must be exactly two characters long. Families supported are: + R1 - RNG-100 R2 - RNG-200 + A1 - Class A B1 - Class B + E1 - Class E F1 - Class F + 44 - 45xx 46 - 46xx + 85 - 85xx 86 - 86xx diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile new file mode 100644 index 0000000..39ca9f8 --- /dev/null +++ b/arch/mips/powertv/Makefile @@ -0,0 +1,29 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. +# Portions copyright (C) 2009 Cisco Systems, Inc. +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# Makefile for the Cisco PowerTV-specific kernel interface routines +# under Linux. +# + +obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \ + asic/ pci/ + +obj-$(CONFIG_USB) += powertv-usb.o diff --git a/arch/mips/powertv/Platform b/arch/mips/powertv/Platform new file mode 100644 index 0000000..4eb5af1 --- /dev/null +++ b/arch/mips/powertv/Platform @@ -0,0 +1,7 @@ +# +# Cisco PowerTV Platform +# +platform-$(CONFIG_POWERTV) += powertv/ +cflags-$(CONFIG_POWERTV) += \ + -I$(srctree)/arch/mips/include/asm/mach-powertv +load-$(CONFIG_POWERTV) += 0xffffffff90800000 diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile new file mode 100644 index 0000000..35dcc53 --- /dev/null +++ b/arch/mips/powertv/asic/Makefile @@ -0,0 +1,21 @@ +# +# Copyright (C) 2009 Scientific-Atlanta, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \ + asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \ + prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c new file mode 100644 index 0000000..2f539b4 --- /dev/null +++ b/arch/mips/powertv/asic/asic-calliope.c @@ -0,0 +1,101 @@ +/* + * Locations of devices in the Calliope ASIC. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef <ds@schleef.org> + * + * Description: Defines the platform resources for the SA settop. + */ + +#include <linux/init.h> +#include <asm/mach-powertv/asic.h> + +#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x)) + +const struct register_map calliope_register_map __initconst = { + .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)}, + .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)}, + .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)}, + + .chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)}, + .chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)}, + .chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)}, + .chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)}, + + /* The registers of IRBlaster */ + .uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)}, + .uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)}, + .uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)}, + .uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)}, + .uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)}, + .uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)}, + .uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)}, + .uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)}, + + .int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)}, + .int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)}, + .int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)}, + .int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)}, + .int_config = {.phys = CALLIOPE_ADDR(0xA02810)}, + .int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)}, + .ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)}, + .ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)}, + .ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)}, + .ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)}, + .int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)}, + .int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)}, + .int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)}, + .int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)}, + .int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)}, + .int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)}, + .int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)}, + .int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)}, + .int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)}, + .int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)}, + .int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)}, + .int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)}, + .int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)}, + .int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)}, + .int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)}, + .int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)}, + .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)}, + + .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)}, + .fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)}, + .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)}, + .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)}, + .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)}, + .usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)}, + .ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)}, + .ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)}, + .bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)}, + .usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)}, + .usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)}, + .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)}, + .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)}, + + .pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */ + .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)}, + .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)}, + .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)}, + .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)}, + .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)}, + .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)}, + .front_panel = {.phys = 0x000000}, /* -not used- */ +}; diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c new file mode 100644 index 0000000..7f8f342 --- /dev/null +++ b/arch/mips/powertv/asic/asic-cronus.c @@ -0,0 +1,101 @@ +/* + * Locations of devices in the Cronus ASIC + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef <ds@schleef.org> + * + * Description: Defines the platform resources for the SA settop. + */ + +#include <linux/init.h> +#include <asm/mach-powertv/asic.h> + +#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x)) + +const struct register_map cronus_register_map __initconst = { + .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)}, + .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)}, + .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)}, + + .chipver3 = {.phys = CRONUS_ADDR(0x2A0800)}, + .chipver2 = {.phys = CRONUS_ADDR(0x2A0804)}, + .chipver1 = {.phys = CRONUS_ADDR(0x2A0808)}, + .chipver0 = {.phys = CRONUS_ADDR(0x2A080C)}, + + /* The registers of IRBlaster */ + .uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)}, + .uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)}, + .uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)}, + .uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)}, + .uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)}, + .uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)}, + .uart1_data = {.phys = CRONUS_ADDR(0x2A1818)}, + .uart1_status = {.phys = CRONUS_ADDR(0x2A181C)}, + + .int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)}, + .int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)}, + .int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)}, + .int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)}, + .int_config = {.phys = CRONUS_ADDR(0x2A2810)}, + .int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)}, + .ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)}, + .ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)}, + .ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)}, + .ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)}, + .int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)}, + .int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)}, + .int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)}, + .int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)}, + .int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)}, + .int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)}, + .int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)}, + .int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)}, + .int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)}, + .int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)}, + .int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)}, + .int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)}, + .int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)}, + .int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)}, + .int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)}, + .int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)}, + .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)}, + + .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)}, + .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)}, + .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)}, + .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)}, + .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)}, + .usb2_strap = {.phys = CRONUS_ADDR(0x200014)}, + .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)}, + .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)}, + .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)}, + .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)}, + .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)}, + .usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)}, + .usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)}, + + .pcie_regs = {.phys = CRONUS_ADDR(0x220000)}, + .tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)}, + .tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)}, + .gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)}, + .gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)}, + .gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)}, + .watchdog = {.phys = CRONUS_ADDR(0x2A2C30)}, + .front_panel = {.phys = CRONUS_ADDR(0x2A3800)}, +}; diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c new file mode 100644 index 0000000..1265b49 --- /dev/null +++ b/arch/mips/powertv/asic/asic-gaia.c @@ -0,0 +1,96 @@ +/* + * Locations of devices in the Gaia ASIC + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#include <linux/init.h> +#include <asm/mach-powertv/asic.h> + +const struct register_map gaia_register_map __initconst = { + .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000}, + .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038}, + .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C}, + + .chipver3 = {.phys = GAIA_IO_BASE + 0x2A0800}, + .chipver2 = {.phys = GAIA_IO_BASE + 0x2A0804}, + .chipver1 = {.phys = GAIA_IO_BASE + 0x2A0808}, + .chipver0 = {.phys = GAIA_IO_BASE + 0x2A080C}, + + /* The registers of IRBlaster */ + .uart1_intstat = {.phys = GAIA_IO_BASE + 0x2A1800}, + .uart1_inten = {.phys = GAIA_IO_BASE + 0x2A1804}, + .uart1_config1 = {.phys = GAIA_IO_BASE + 0x2A1808}, + .uart1_config2 = {.phys = GAIA_IO_BASE + 0x2A180C}, + .uart1_divisorhi = {.phys = GAIA_IO_BASE + 0x2A1810}, + .uart1_divisorlo = {.phys = GAIA_IO_BASE + 0x2A1814}, + .uart1_data = {.phys = GAIA_IO_BASE + 0x2A1818}, + .uart1_status = {.phys = GAIA_IO_BASE + 0x2A181C}, + + .int_stat_3 = {.phys = GAIA_IO_BASE + 0x2A2800}, + .int_stat_2 = {.phys = GAIA_IO_BASE + 0x2A2804}, + .int_stat_1 = {.phys = GAIA_IO_BASE + 0x2A2808}, + .int_stat_0 = {.phys = GAIA_IO_BASE + 0x2A280C}, + .int_config = {.phys = GAIA_IO_BASE + 0x2A2810}, + .int_int_scan = {.phys = GAIA_IO_BASE + 0x2A2818}, + .ien_int_3 = {.phys = GAIA_IO_BASE + 0x2A2830}, + .ien_int_2 = {.phys = GAIA_IO_BASE + 0x2A2834}, + .ien_int_1 = {.phys = GAIA_IO_BASE + 0x2A2838}, + .ien_int_0 = {.phys = GAIA_IO_BASE + 0x2A283C}, + .int_level_3_3 = {.phys = GAIA_IO_BASE + 0x2A2880}, + .int_level_3_2 = {.phys = GAIA_IO_BASE + 0x2A2884}, + .int_level_3_1 = {.phys = GAIA_IO_BASE + 0x2A2888}, + .int_level_3_0 = {.phys = GAIA_IO_BASE + 0x2A288C}, + .int_level_2_3 = {.phys = GAIA_IO_BASE + 0x2A2890}, + .int_level_2_2 = {.phys = GAIA_IO_BASE + 0x2A2894}, + .int_level_2_1 = {.phys = GAIA_IO_BASE + 0x2A2898}, + .int_level_2_0 = {.phys = GAIA_IO_BASE + 0x2A289C}, + .int_level_1_3 = {.phys = GAIA_IO_BASE + 0x2A28A0}, + .int_level_1_2 = {.phys = GAIA_IO_BASE + 0x2A28A4}, + .int_level_1_1 = {.phys = GAIA_IO_BASE + 0x2A28A8}, + .int_level_1_0 = {.phys = GAIA_IO_BASE + 0x2A28AC}, + .int_level_0_3 = {.phys = GAIA_IO_BASE + 0x2A28B0}, + .int_level_0_2 = {.phys = GAIA_IO_BASE + 0x2A28B4}, + .int_level_0_1 = {.phys = GAIA_IO_BASE + 0x2A28B8}, + .int_level_0_0 = {.phys = GAIA_IO_BASE + 0x2A28BC}, + .int_docsis_en = {.phys = GAIA_IO_BASE + 0x2A28F4}, + + .mips_pll_setup = {.phys = GAIA_IO_BASE + 0x1C0000}, + .fs432x4b4_usb_ctl = {.phys = GAIA_IO_BASE + 0x1C0024}, + .test_bus = {.phys = GAIA_IO_BASE + 0x1C00CC}, + .crt_spare = {.phys = GAIA_IO_BASE + 0x1c0108}, + .usb2_ohci_int_mask = {.phys = GAIA_IO_BASE + 0x20000C}, + .usb2_strap = {.phys = GAIA_IO_BASE + 0x200014}, + .ehci_hcapbase = {.phys = GAIA_IO_BASE + 0x21FE00}, + .ohci_hc_revision = {.phys = GAIA_IO_BASE + 0x21fc00}, + .bcm1_bs_lmi_steer = {.phys = GAIA_IO_BASE + 0x2E0004}, + .usb2_control = {.phys = GAIA_IO_BASE + 0x2E004C}, + .usb2_stbus_obc = {.phys = GAIA_IO_BASE + 0x21FF00}, + .usb2_stbus_mess_size = {.phys = GAIA_IO_BASE + 0x21FF04}, + .usb2_stbus_chunk_size = {.phys = GAIA_IO_BASE + 0x21FF08}, + + .pcie_regs = {.phys = GAIA_IO_BASE + 0x220000}, + .tim_ch = {.phys = GAIA_IO_BASE + 0x2A2C10}, + .tim_cl = {.phys = GAIA_IO_BASE + 0x2A2C14}, + .gpio_dout = {.phys = GAIA_IO_BASE + 0x2A2C20}, + .gpio_din = {.phys = GAIA_IO_BASE + 0x2A2C24}, + .gpio_dir = {.phys = GAIA_IO_BASE + 0x2A2C2C}, + .watchdog = {.phys = GAIA_IO_BASE + 0x2A2C30}, + .front_panel = {.phys = GAIA_IO_BASE + 0x2A3800}, +}; diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c new file mode 100644 index 0000000..14e7de1 --- /dev/null +++ b/arch/mips/powertv/asic/asic-zeus.c @@ -0,0 +1,101 @@ +/* + * Locations of devices in the Zeus ASIC + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef <ds@schleef.org> + * + * Description: Defines the platform resources for the SA settop. + */ + +#include <linux/init.h> +#include <asm/mach-powertv/asic.h> + +#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x)) + +const struct register_map zeus_register_map __initconst = { + .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)}, + .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)}, + .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)}, + + .chipver3 = {.phys = ZEUS_ADDR(0x280800)}, + .chipver2 = {.phys = ZEUS_ADDR(0x280804)}, + .chipver1 = {.phys = ZEUS_ADDR(0x280808)}, + .chipver0 = {.phys = ZEUS_ADDR(0x28080c)}, + + /* The registers of IRBlaster */ + .uart1_intstat = {.phys = ZEUS_ADDR(0x281800)}, + .uart1_inten = {.phys = ZEUS_ADDR(0x281804)}, + .uart1_config1 = {.phys = ZEUS_ADDR(0x281808)}, + .uart1_config2 = {.phys = ZEUS_ADDR(0x28180C)}, + .uart1_divisorhi = {.phys = ZEUS_ADDR(0x281810)}, + .uart1_divisorlo = {.phys = ZEUS_ADDR(0x281814)}, + .uart1_data = {.phys = ZEUS_ADDR(0x281818)}, + .uart1_status = {.phys = ZEUS_ADDR(0x28181C)}, + + .int_stat_3 = {.phys = ZEUS_ADDR(0x282800)}, + .int_stat_2 = {.phys = ZEUS_ADDR(0x282804)}, + .int_stat_1 = {.phys = ZEUS_ADDR(0x282808)}, + .int_stat_0 = {.phys = ZEUS_ADDR(0x28280c)}, + .int_config = {.phys = ZEUS_ADDR(0x282810)}, + .int_int_scan = {.phys = ZEUS_ADDR(0x282818)}, + .ien_int_3 = {.phys = ZEUS_ADDR(0x282830)}, + .ien_int_2 = {.phys = ZEUS_ADDR(0x282834)}, + .ien_int_1 = {.phys = ZEUS_ADDR(0x282838)}, + .ien_int_0 = {.phys = ZEUS_ADDR(0x28283c)}, + .int_level_3_3 = {.phys = ZEUS_ADDR(0x282880)}, + .int_level_3_2 = {.phys = ZEUS_ADDR(0x282884)}, + .int_level_3_1 = {.phys = ZEUS_ADDR(0x282888)}, + .int_level_3_0 = {.phys = ZEUS_ADDR(0x28288c)}, + .int_level_2_3 = {.phys = ZEUS_ADDR(0x282890)}, + .int_level_2_2 = {.phys = ZEUS_ADDR(0x282894)}, + .int_level_2_1 = {.phys = ZEUS_ADDR(0x282898)}, + .int_level_2_0 = {.phys = ZEUS_ADDR(0x28289c)}, + .int_level_1_3 = {.phys = ZEUS_ADDR(0x2828a0)}, + .int_level_1_2 = {.phys = ZEUS_ADDR(0x2828a4)}, + .int_level_1_1 = {.phys = ZEUS_ADDR(0x2828a8)}, + .int_level_1_0 = {.phys = ZEUS_ADDR(0x2828ac)}, + .int_level_0_3 = {.phys = ZEUS_ADDR(0x2828b0)}, + .int_level_0_2 = {.phys = ZEUS_ADDR(0x2828b4)}, + .int_level_0_1 = {.phys = ZEUS_ADDR(0x2828b8)}, + .int_level_0_0 = {.phys = ZEUS_ADDR(0x2828bc)}, + .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)}, + + .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)}, + .fs432x4b4_usb_ctl = {.phys = ZEUS_ADDR(0x1a0018)}, + .test_bus = {.phys = ZEUS_ADDR(0x1a0238)}, + .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)}, + .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)}, + .usb2_strap = {.phys = ZEUS_ADDR(0x1e0014)}, + .ehci_hcapbase = {.phys = ZEUS_ADDR(0x1FFE00)}, + .ohci_hc_revision = {.phys = ZEUS_ADDR(0x1FFC00)}, + .bcm1_bs_lmi_steer = {.phys = ZEUS_ADDR(0x2C0008)}, + .usb2_control = {.phys = ZEUS_ADDR(0x2c01a0)}, + .usb2_stbus_obc = {.phys = ZEUS_ADDR(0x1FFF00)}, + .usb2_stbus_mess_size = {.phys = ZEUS_ADDR(0x1FFF04)}, + .usb2_stbus_chunk_size = {.phys = ZEUS_ADDR(0x1FFF08)}, + + .pcie_regs = {.phys = ZEUS_ADDR(0x200000)}, + .tim_ch = {.phys = ZEUS_ADDR(0x282C10)}, + .tim_cl = {.phys = ZEUS_ADDR(0x282C14)}, + .gpio_dout = {.phys = ZEUS_ADDR(0x282c20)}, + .gpio_din = {.phys = ZEUS_ADDR(0x282c24)}, + .gpio_dir = {.phys = ZEUS_ADDR(0x282c2C)}, + .watchdog = {.phys = ZEUS_ADDR(0x282c30)}, + .front_panel = {.phys = ZEUS_ADDR(0x283800)}, +}; diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c new file mode 100644 index 0000000..8380605 --- /dev/null +++ b/arch/mips/powertv/asic/asic_devices.c @@ -0,0 +1,549 @@ +/* + * + * Description: Defines the platform resources for Gaia-based settops. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * NOTE: The bootloader allocates persistent memory at an address which is + * 16 MiB below the end of the highest address in KSEG0. All fixed + * address memory reservations must avoid this region. + */ + +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/resource.h> +#include <linux/serial_reg.h> +#include <linux/io.h> +#include <linux/bootmem.h> +#include <linux/mm.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <asm/page.h> +#include <linux/swap.h> +#include <linux/highmem.h> +#include <linux/dma-mapping.h> + +#include <asm/mach-powertv/asic.h> +#include <asm/mach-powertv/asic_regs.h> +#include <asm/mach-powertv/interrupts.h> + +#ifdef CONFIG_BOOTLOADER_DRIVER +#include <asm/mach-powertv/kbldr.h> +#endif +#include <asm/bootinfo.h> + +#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) + +/* + * Forward Prototypes + */ +static void pmem_setup_resource(void); + +/* + * Global Variables + */ +enum asic_type asic; + +unsigned int platform_features; +unsigned int platform_family; +struct register_map _asic_register_map; +EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */ +unsigned long asic_phy_base; +unsigned long asic_base; +EXPORT_SYMBOL(asic_base); /* Exported for testing */ +struct resource *gp_resources; + +/* + * Don't recommend to use it directly, it is usually used by kernel internally. + * Portable code should be using interfaces such as ioremp, dma_map_single, etc. + */ +unsigned long phys_to_dma_offset; +EXPORT_SYMBOL(phys_to_dma_offset); + +/* + * + * IO Resource Definition + * + */ + +struct resource asic_resource = { + .name = "ASIC Resource", + .start = 0, + .end = ASIC_IO_SIZE, + .flags = IORESOURCE_MEM, +}; + +/* + * Allow override of bootloader-specified model + * Returns zero on success, a negative errno value on failure. This parameter + * allows overriding of the bootloader-specified model. + */ +static char __initdata cmdline[COMMAND_LINE_SIZE]; + +#define FORCEFAMILY_PARAM "forcefamily" + +/* + * check_forcefamily - check for, and parse, forcefamily command line parameter + * @forced_family: Pointer to two-character array in which to store the + * value of the forcedfamily parameter, if any. + */ +static __init int check_forcefamily(unsigned char forced_family[2]) +{ + const char *p; + + forced_family[0] = '\0'; + forced_family[1] = '\0'; + + /* Check the command line for a forcefamily directive */ + strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1); + p = strstr(cmdline, FORCEFAMILY_PARAM); + if (p && (p != cmdline) && (*(p - 1) != ' ')) + p = strstr(p, " " FORCEFAMILY_PARAM "="); + + if (p) { + p += strlen(FORCEFAMILY_PARAM "="); + + if (*p == '\0' || *(p + 1) == '\0' || + (*(p + 2) != '\0' && *(p + 2) != ' ')) + pr_err(FORCEFAMILY_PARAM " must be exactly two " + "characters long, ignoring value\n"); + + else { + forced_family[0] = *p; + forced_family[1] = *(p + 1); + } + } + + return 0; +} + +/* + * platform_set_family - determine major platform family type. + * + * Returns family type; -1 if none + * Returns the family type; -1 if none + * + */ +static __init noinline void platform_set_family(void) +{ + unsigned char forced_family[2]; + unsigned short bootldr_family; + + if (check_forcefamily(forced_family) == 0) + bootldr_family = BOOTLDRFAMILY(forced_family[0], + forced_family[1]); + else + bootldr_family = (unsigned short) BOOTLDRFAMILY( + CONFIG_BOOTLOADER_FAMILY[0], + CONFIG_BOOTLOADER_FAMILY[1]); + + pr_info("Bootloader Family = 0x%04X\n", bootldr_family); + + switch (bootldr_family) { + case BOOTLDRFAMILY('R', '1'): + platform_family = FAMILY_1500; + break; + case BOOTLDRFAMILY('4', '4'): + platform_family = FAMILY_4500; + break; + case BOOTLDRFAMILY('4', '6'): + platform_family = FAMILY_4600; + break; + case BOOTLDRFAMILY('A', '1'): + platform_family = FAMILY_4600VZA; + break; + case BOOTLDRFAMILY('8', '5'): + platform_family = FAMILY_8500; + break; + case BOOTLDRFAMILY('R', '2'): + platform_family = FAMILY_8500RNG; + break; + case BOOTLDRFAMILY('8', '6'): + platform_family = FAMILY_8600; + break; + case BOOTLDRFAMILY('B', '1'): + platform_family = FAMILY_8600VZB; + break; + case BOOTLDRFAMILY('E', '1'): + platform_family = FAMILY_1500VZE; + break; + case BOOTLDRFAMILY('F', '1'): + platform_family = FAMILY_1500VZF; + break; + case BOOTLDRFAMILY('8', '7'): + platform_family = FAMILY_8700; + break; + default: + platform_family = -1; + } +} + +unsigned int platform_get_family(void) +{ + return platform_family; +} +EXPORT_SYMBOL(platform_get_family); + +/* + * platform_get_asic - determine the ASIC type. + * + * Returns the ASIC type, or ASIC_UNKNOWN if unknown + * + */ +enum asic_type platform_get_asic(void) +{ + return asic; +} +EXPORT_SYMBOL(platform_get_asic); + +/* + * set_register_map - set ASIC register configuration + * @phys_base: Physical address of the base of the ASIC registers + * @map: Description of key ASIC registers + */ +static void __init set_register_map(unsigned long phys_base, + const struct register_map *map) +{ + asic_phy_base = phys_base; + _asic_register_map = *map; + register_map_virtualize(&_asic_register_map); + asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE); +} + +/** + * configure_platform - configuration based on platform type. + */ +void __init configure_platform(void) +{ + platform_set_family(); + + switch (platform_family) { + case FAMILY_1500: + case FAMILY_1500VZE: + case FAMILY_1500VZF: + platform_features = FFS_CAPABLE; + asic = ASIC_CALLIOPE; + set_register_map(CALLIOPE_IO_BASE, &calliope_register_map); + + if (platform_family == FAMILY_1500VZE) { + gp_resources = non_dvr_vze_calliope_resources; + pr_info("Platform: 1500/Vz Class E - " + "CALLIOPE, NON_DVR_CAPABLE\n"); + } else if (platform_family == FAMILY_1500VZF) { + gp_resources = non_dvr_vzf_calliope_resources; + pr_info("Platform: 1500/Vz Class F - " + "CALLIOPE, NON_DVR_CAPABLE\n"); + } else { + gp_resources = non_dvr_calliope_resources; + pr_info("Platform: 1500/RNG100 - CALLIOPE, " + "NON_DVR_CAPABLE\n"); + } + break; + + case FAMILY_4500: + platform_features = FFS_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + asic = ASIC_ZEUS; + set_register_map(ZEUS_IO_BASE, &zeus_register_map); + gp_resources = non_dvr_zeus_resources; + + pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n"); + break; + + case FAMILY_4600: + { + unsigned int chipversion = 0; + + /* The settop has PCIE but it isn't used, so don't advertise + * it*/ + platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; + + /* Cronus and Cronus Lite have the same register map */ + set_register_map(CRONUS_IO_BASE, &cronus_register_map); + + /* ASIC version will determine if this is a real CronusLite or + * Castrati(Cronus) */ + chipversion = asic_read(chipver3) << 24; + chipversion |= asic_read(chipver2) << 16; + chipversion |= asic_read(chipver1) << 8; + chipversion |= asic_read(chipver0); + + if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11)) + asic = ASIC_CRONUS; + else + asic = ASIC_CRONUSLITE; + + gp_resources = non_dvr_cronuslite_resources; + pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " + "chipversion=0x%08X\n", + (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE", + chipversion); + break; + } + case FAMILY_4600VZA: + platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; + asic = ASIC_CRONUS; + set_register_map(CRONUS_IO_BASE, &cronus_register_map); + gp_resources = non_dvr_cronus_resources; + + pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n"); + break; + + case FAMILY_8500: + case FAMILY_8500RNG: + platform_features = DVR_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + asic = ASIC_ZEUS; + set_register_map(ZEUS_IO_BASE, &zeus_register_map); + gp_resources = dvr_zeus_resources; + + pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n"); + break; + + case FAMILY_8600: + case FAMILY_8600VZB: + platform_features = DVR_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + asic = ASIC_CRONUS; + set_register_map(CRONUS_IO_BASE, &cronus_register_map); + gp_resources = dvr_cronus_resources; + + pr_info("Platform: 8600/Vz Class B - CRONUS, " + "DVR_CAPABLE\n"); + break; + + case FAMILY_8700: + platform_features = FFS_CAPABLE | PCIE_CAPABLE; + asic = ASIC_GAIA; + set_register_map(GAIA_IO_BASE, &gaia_register_map); + gp_resources = dvr_gaia_resources; + + pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n"); + break; + + default: + pr_crit("Platform: UNKNOWN PLATFORM\n"); + break; + } + + switch (asic) { + case ASIC_ZEUS: + phys_to_dma_offset = 0x30000000; + break; + case ASIC_CALLIOPE: + phys_to_dma_offset = 0x10000000; + break; + case ASIC_CRONUSLITE: + /* Fall through */ + case ASIC_CRONUS: + /* + * TODO: We suppose 0x10000000 aliases into 0x20000000- + * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000- + * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000. + */ + phys_to_dma_offset = 0x10000000; + break; + default: + phys_to_dma_offset = 0x00000000; + break; + } +} + +/* + * RESOURCE ALLOCATION + * + */ +/* + * Allocates/reserves the Platform memory resources early in the boot process. + * This ignores any resources that are designated IORESOURCE_IO + */ +void __init platform_alloc_bootmem(void) +{ + int i; + int total = 0; + + /* Get persistent memory data from command line before allocating + * resources. This need to happen before normal command line parsing + * has been done */ + pmem_setup_resource(); + + /* Loop through looking for resources that want a particular address */ + for (i = 0; gp_resources[i].flags != 0; i++) { + int size = resource_size(&gp_resources[i]); + if ((gp_resources[i].start != 0) && + ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { + reserve_bootmem(dma_to_phys(gp_resources[i].start), + size, 0); + total += resource_size(&gp_resources[i]); + pr_info("reserve resource %s at %08x (%u bytes)\n", + gp_resources[i].name, gp_resources[i].start, + resource_size(&gp_resources[i])); + } + } + + /* Loop through assigning addresses for those that are left */ + for (i = 0; gp_resources[i].flags != 0; i++) { + int size = resource_size(&gp_resources[i]); + if ((gp_resources[i].start == 0) && + ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { + void *mem = alloc_bootmem_pages(size); + + if (mem == NULL) + pr_err("Unable to allocate bootmem pages " + "for %s\n", gp_resources[i].name); + + else { + gp_resources[i].start = + phys_to_dma(virt_to_phys(mem)); + gp_resources[i].end = + gp_resources[i].start + size - 1; + total += size; + pr_info("allocate resource %s at %08x " + "(%u bytes)\n", + gp_resources[i].name, + gp_resources[i].start, size); + } + } + } + + pr_info("Total Platform driver memory allocation: 0x%08x\n", total); + + /* indicate resources that are platform I/O related */ + for (i = 0; gp_resources[i].flags != 0; i++) { + if ((gp_resources[i].start != 0) && + ((gp_resources[i].flags & IORESOURCE_IO) != 0)) { + pr_info("reserved platform resource %s at %08x\n", + gp_resources[i].name, gp_resources[i].start); + } + } +} + +/* + * + * PERSISTENT MEMORY (PMEM) CONFIGURATION + * + */ +static unsigned long pmemaddr __initdata; + +static int __init early_param_pmemaddr(char *p) +{ + pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0); + return 0; +} +early_param("pmemaddr", early_param_pmemaddr); + +static long pmemlen __initdata; + +static int __init early_param_pmemlen(char *p) +{ +/* TODO: we can use this code when and if the bootloader ever changes this */ +#if 0 + pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); +#else + pmemlen = 0x20000; +#endif + return 0; +} +early_param("pmemlen", early_param_pmemlen); + +/* + * Set up persistent memory. If we were given values, we patch the array of + * resources. Otherwise, persistent memory may be allocated anywhere at all. + */ +static void __init pmem_setup_resource(void) +{ + struct resource *resource; + resource = asic_resource_get("DiagPersistentMemory"); + + if (resource && pmemaddr && pmemlen) { + /* The address provided by bootloader is in kseg0. Convert to + * a bus address. */ + resource->start = phys_to_dma(pmemaddr - 0x80000000); + resource->end = resource->start + pmemlen - 1; + + pr_info("persistent memory: start=0x%x end=0x%x\n", + resource->start, resource->end); + } +} + +/* + * + * RESOURCE ACCESS FUNCTIONS + * + */ + +/** + * asic_resource_get - retrieves parameters for a platform resource. + * @name: string to match resource + * + * Returns a pointer to a struct resource corresponding to the given name. + * + * CANNOT BE NAMED platform_resource_get, which would be the obvious choice, + * as this function name is already declared + */ +struct resource *asic_resource_get(const char *name) +{ + int i; + + for (i = 0; gp_resources[i].flags != 0; i++) { + if (strcmp(gp_resources[i].name, name) == 0) + return &gp_resources[i]; + } + + return NULL; +} +EXPORT_SYMBOL(asic_resource_get); + +/** + * platform_release_memory - release pre-allocated memory + * @ptr: pointer to memory to release + * @size: size of resource + * + * This must only be called for memory allocated or reserved via the boot + * memory allocator. + */ +void platform_release_memory(void *ptr, int size) +{ + free_reserved_area(ptr, ptr + size, -1, NULL); +} +EXPORT_SYMBOL(platform_release_memory); + +/* + * + * FEATURE AVAILABILITY FUNCTIONS + * + */ +int platform_supports_dvr(void) +{ + return (platform_features & DVR_CAPABLE) != 0; +} + +int platform_supports_ffs(void) +{ + return (platform_features & FFS_CAPABLE) != 0; +} + +int platform_supports_pcie(void) +{ + return (platform_features & PCIE_CAPABLE) != 0; +} + +int platform_supports_display(void) +{ + return (platform_features & DISPLAY_CAPABLE) != 0; +} diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c new file mode 100644 index 0000000..f44cd92 --- /dev/null +++ b/arch/mips/powertv/asic/asic_int.c @@ -0,0 +1,125 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the PowerTV + * platform. + * + * The interrupt controller is located in the South Bridge a PIIX4 device + * with two internal 82C95 interrupt controllers. + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/kernel_stat.h> +#include <linux/kernel.h> +#include <linux/random.h> + +#include <asm/irq_cpu.h> +#include <linux/io.h> +#include <asm/irq_regs.h> +#include <asm/setup.h> +#include <asm/mips-boards/generic.h> + +#include <asm/mach-powertv/asic_regs.h> + +static DEFINE_RAW_SPINLOCK(asic_irq_lock); + +static inline int get_int(void) +{ + unsigned long flags; + int irq; + + raw_spin_lock_irqsave(&asic_irq_lock, flags); + + irq = (asic_read(int_int_scan) >> 4) - 1; + + if (irq == 0 || irq >= NR_IRQS) + irq = -1; + + raw_spin_unlock_irqrestore(&asic_irq_lock, flags); + + return irq; +} + +static void asic_irqdispatch(void) +{ + int irq; + + irq = get_int(); + if (irq < 0) + return; /* interrupt has already been cleared */ + + do_IRQ(irq); +} + +static inline int clz(unsigned long x) +{ + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +/* + * Version of ffs that only looks at bits 12..15. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ + return fls(pending) - 1 + CAUSEB_IP; +} + +/* + * TODO: check how it works under EIC mode. + */ +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq == CAUSEF_IP3) + asic_irqdispatch(); + else if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + int i; + + asic_irq_init(); + + /* + * Initialize interrupt exception vectors. + */ + if (cpu_has_veic || cpu_has_vint) { + int nvec = cpu_has_veic ? 64 : 8; + for (i = 0; i < nvec; i++) + set_vi_handler(i, asic_irqdispatch); + } +} diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c new file mode 100644 index 0000000..9344902 --- /dev/null +++ b/arch/mips/powertv/asic/irq_asic.c @@ -0,0 +1,115 @@ +/* + * Portions copyright (C) 2005-2009 Scientific Atlanta + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * Modified from arch/mips/kernel/irq-rm7000.c: + * Copyright (C) 2003 Ralf Baechle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/irq.h> + +#include <asm/irq_cpu.h> +#include <asm/mipsregs.h> + +#include <asm/mach-powertv/asic_regs.h> + +static inline void unmask_asic_irq(struct irq_data *d) +{ + unsigned long enable_bit; + unsigned int irq = d->irq; + + enable_bit = (1 << (irq & 0x1f)); + + switch (irq >> 5) { + case 0: + asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0); + break; + case 1: + asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1); + break; + case 2: + asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2); + break; + case 3: + asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3); + break; + default: + BUG(); + } +} + +static inline void mask_asic_irq(struct irq_data *d) +{ + unsigned long disable_mask; + unsigned int irq = d->irq; + + disable_mask = ~(1 << (irq & 0x1f)); + + switch (irq >> 5) { + case 0: + asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0); + break; + case 1: + asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1); + break; + case 2: + asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2); + break; + case 3: + asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3); + break; + default: + BUG(); + } +} + +static struct irq_chip asic_irq_chip = { + .name = "ASIC Level", + .irq_mask = mask_asic_irq, + .irq_unmask = unmask_asic_irq, +}; + +void __init asic_irq_init(void) +{ + int i; + + /* set priority to 0 */ + write_c0_status(read_c0_status() & ~(0x0000fc00)); + + asic_write(0, ien_int_0); + asic_write(0, ien_int_1); + asic_write(0, ien_int_2); + asic_write(0, ien_int_3); + + asic_write(0x0fffffff, int_level_3_3); + asic_write(0xffffffff, int_level_3_2); + asic_write(0xffffffff, int_level_3_1); + asic_write(0xffffffff, int_level_3_0); + asic_write(0xffffffff, int_level_2_3); + asic_write(0xffffffff, int_level_2_2); + asic_write(0xffffffff, int_level_2_1); + asic_write(0xffffffff, int_level_2_0); + asic_write(0xffffffff, int_level_1_3); + asic_write(0xffffffff, int_level_1_2); + asic_write(0xffffffff, int_level_1_1); + asic_write(0xffffffff, int_level_1_0); + asic_write(0xffffffff, int_level_0_3); + asic_write(0xffffffff, int_level_0_2); + asic_write(0xffffffff, int_level_0_1); + asic_write(0xffffffff, int_level_0_0); + + asic_write(0xf, int_int_scan); + + /* + * Initialize interrupt handlers. + */ + for (i = 0; i < NR_IRQS; i++) + irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq); +} diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c new file mode 100644 index 0000000..98dc516 --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-calliope.c @@ -0,0 +1,385 @@ +/* + * Memory pre-allocations for Calliope boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef <ds@schleef.org> + */ + +#include <linux/init.h> +#include <linux/ioport.h> +#include <asm/mach-powertv/asic.h> +#include "prealloc.h" + +/* + * NON_DVR_CAPABLE CALLIOPE RESOURCES + */ +struct resource non_dvr_calliope_resources[] __initdata = +{ + /* + * VIDEO / LX1 + */ + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~36.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26700000-1, + IORESOURCE_MEM) + + /* + * Sysaudio Driver + */ + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * STAVEM driver/STAPI + */ + /* 6MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * DOCSIS Subsystem + */ + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x27500000, 0x27c00000-1, IORESOURCE_MEM) + + /* + * GHW HAL Driver + */ + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x26700000, 0x26700000+(14*1048576)-1, + IORESOURCE_MEM) + + /* + * multi com buffer area + */ + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1, + IORESOURCE_MEM) + + /* + * DMA Ring buffer (don't need recording buffers) + */ + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit0 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * AVFS: player HAL memory + */ + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * PMEM + */ + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * NAND Flash + */ + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * Synopsys GMAC Memory Region + */ + /* 64KiB */ + PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * TFTPBuffer + * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images + */ + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Add other resources here + */ + + /* + * End of Resource marker + */ + { + .flags = 0, + }, +}; + + +struct resource non_dvr_vze_calliope_resources[] __initdata = +{ + /* + * VIDEO / LX1 + */ + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x22000000, 0x22200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x22200000, 0x22202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (10.12MiB) */ + PREALLOC_NORMAL("MediaMemory1", 0x22202000, 0x22C20B85-1, + IORESOURCE_MEM) + + /* + * Sysaudio Driver + */ + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * STAVEM driver/STAPI + */ + /* 3.125MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x20396000, 0x206B6000-1, + IORESOURCE_MEM) + + /* + * GHW HAL Driver + */ + /* PowerTV Graphics Heap (2.59MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x20100000, 0x20396000-1, + IORESOURCE_MEM) + + /* + * multi com buffer area + */ + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x206B6000, 0x206D6000-1, + IORESOURCE_MEM) + + /* + * DMA Ring buffer (don't need recording buffers) + */ + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit0 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * PMEM + */ + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * NAND Flash + */ + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * Synopsys GMAC Memory Region + */ + /* 64KiB */ + PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Add other resources here + */ + + /* + * End of Resource marker + */ + { + .flags = 0, + }, +}; + +struct resource non_dvr_vzf_calliope_resources[] __initdata = +{ + /* + * VIDEO / LX1 + */ + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~19.4 (21.5MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x25580000-1, + IORESOURCE_MEM) + + /* + * Sysaudio Driver + */ + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * STAVEM driver/STAPI + */ + /* 4.5MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00480000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * GHW HAL Driver + */ + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x25600000, 0x25600000+(14*1048576)-1, + IORESOURCE_MEM) + + /* + * multi com buffer area + */ + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x23700000, 0x23720000-1, + IORESOURCE_MEM) + + /* + * DMA Ring buffer (don't need recording buffers) + */ + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit0 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit1 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * AVFS: player HAL memory + */ + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * PMEM + */ + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * NAND Flash + */ + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * Synopsys GMAC Memory Region + */ + /* 64KiB */ + PREALLOC_NORMAL("GMAC", 0x00000000, 0x00010000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Add other resources here + */ + + /* + * End of Resource marker + */ + { + .flags = 0, + }, +}; diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c new file mode 100644 index 0000000..7c6ce75 --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-cronus.c @@ -0,0 +1,340 @@ +/* + * Memory pre-allocations for Cronus boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef <ds@schleef.org> + */ + +#include <linux/init.h> +#include <linux/ioport.h> +#include <asm/mach-powertv/asic.h> +#include "prealloc.h" + +/* + * DVR_CAPABLE CRONUS RESOURCES + */ +struct resource dvr_cronus_resources[] __initdata = +{ + /* + * VIDEO1 / LX1 + */ + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1, + IORESOURCE_MEM) + + /* + * VIDEO2 / LX2 + */ + /* Delta-Mu 2 image (2MiB) */ + PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 monitor (8KiB) */ + PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1, + IORESOURCE_MEM) + + /* + * Sysaudio Driver + */ + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * STAVEM driver/STAPI + * + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + */ + /* 12MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, + IORESOURCE_MEM) + + /* + * DOCSIS Subsystem + */ + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) + + /* + * GHW HAL Driver + */ + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, + IORESOURCE_MEM) + + /* + * multi com buffer area + */ + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, + IORESOURCE_MEM) + + /* + * DMA Ring buffer + */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x002EA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit0 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit1 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + IORESOURCE_MEM) + + /* + * ITFS + */ + /* 815,104 bytes each for 2 ITFS partitions. */ + PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1, IORESOURCE_MEM) + + /* + * AVFS + */ + /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1, + IORESOURCE_MEM) + + /* 4KiB */ + PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1, + IORESOURCE_MEM) + + /* + * PMEM + */ + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + IORESOURCE_MEM) + + /* + * KAVNET + */ + /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ + PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, + IORESOURCE_MEM) + /* NP Image - must be video bank 1 (320KiB) */ + PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) + /* NP IPC - must be video bank 2 (512KiB) */ + PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) + + /* + * TFTPBuffer + * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images + */ + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Add other resources here + */ + + /* + * End of Resource marker + */ + { + .flags = 0, + }, +}; + +/* + * NON_DVR_CAPABLE CRONUS RESOURCES + */ +struct resource non_dvr_cronus_resources[] __initdata = +{ + /* + * VIDEO1 / LX1 + */ + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x24000000, 0x24200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x24200000, 0x24202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x24202000, 0x26000000-1, + IORESOURCE_MEM) + + /* + * VIDEO2 / LX2 + */ + /* Delta-Mu 2 image (2MiB) */ + PREALLOC_NORMAL("ST231bImage", 0x60000000, 0x60200000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 monitor (8KiB) */ + PREALLOC_NORMAL("ST231bMonitor", 0x60200000, 0x60202000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory2", 0x60202000, 0x62000000-1, + IORESOURCE_MEM) + + /* + * Sysaudio Driver + */ + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * STAVEM driver/STAPI + * + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + */ + /* 12MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, + IORESOURCE_MEM) + + /* + * DOCSIS Subsystem + */ + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) + + /* + * GHW HAL Driver + */ + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, + IORESOURCE_MEM) + + /* + * multi com buffer area + */ + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, + IORESOURCE_MEM) + + /* + * DMA Ring buffer (don't need recording buffers) + */ + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit0 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit1 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + IORESOURCE_MEM) + + /* + * AVFS: player HAL memory + */ + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, IORESOURCE_MEM) + + /* + * PMEM + */ + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM) + + /* + * KAVNET + */ + /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ + PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, + IORESOURCE_MEM) + /* NP Image - must be video bank 1 (320KiB) */ + PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) + /* NP IPC - must be video bank 2 (512KiB) */ + PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) + + /* + * NAND Flash + */ + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * Add other resources here + */ + + /* + * End of Resource marker + */ + { + .flags = 0, + }, +}; diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c new file mode 100644 index 0000000..a7937ba --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-cronuslite.c @@ -0,0 +1,174 @@ +/* + * Memory pre-allocations for Cronus Lite boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef <ds@schleef.org> + */ + +#include <linux/init.h> +#include <linux/ioport.h> +#include <asm/mach-powertv/asic.h> +#include "prealloc.h" + +/* + * NON_DVR_CAPABLE CRONUSLITE RESOURCES + */ +struct resource non_dvr_cronuslite_resources[] __initdata = +{ + /* + * VIDEO2 / LX2 + */ + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x60000000, 0x60200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x60200000, 0x60202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x60202000, 0x62000000-1, + IORESOURCE_MEM) + + /* + * Sysaudio Driver + */ + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (128KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00020000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * STAVEM driver/STAPI + * + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + */ + /* 6MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, + IORESOURCE_MEM) + + /* + * DOCSIS Subsystem + */ + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x67500000, 0x67c00000-1, IORESOURCE_MEM) + + /* + * GHW HAL Driver + */ + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x62700000, 0x63500000-1, + IORESOURCE_MEM) + + /* + * multi com buffer area + */ + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x26000000, 0x26020000-1, + IORESOURCE_MEM) + + /* + * DMA Ring buffer (don't need recording buffers) + */ + /* 680KiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x000AA000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit0 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit1 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + IORESOURCE_MEM) + + /* + * AVFS: player HAL memory + */ + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * PMEM + */ + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, IORESOURCE_MEM) + + /* + * KAVNET + */ + /* NP Reset Vector - must be of the form xxCxxxxx (4KiB) */ + PREALLOC_NORMAL("NP_Reset_Vector", 0x27c00000, 0x27c01000-1, + IORESOURCE_MEM) + /* NP Image - must be video bank 1 (320KiB) */ + PREALLOC_NORMAL("NP_Image", 0x27020000, 0x27070000-1, IORESOURCE_MEM) + /* NP IPC - must be video bank 2 (512KiB) */ + PREALLOC_NORMAL("NP_IPC", 0x63500000, 0x63580000-1, IORESOURCE_MEM) + + /* + * NAND Flash + */ + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * TFTPBuffer + * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images + */ + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Add other resources here + */ + + /* + * End of Resource marker + */ + { + .flags = 0, + }, +}; diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c new file mode 100644 index 0000000..2303bbf --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-gaia.c @@ -0,0 +1,589 @@ +/* + * Memory pre-allocations for Gaia boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#include <linux/init.h> +#include <asm/mach-powertv/asic.h> + +/* + * DVR_CAPABLE GAIA RESOURCES + */ +struct resource dvr_gaia_resources[] __initdata = { + /* + * + * VIDEO1 / LX1 + * + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x241FFFFF, /* 2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24201FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /* + * + * VIDEO2 / LX2 + * + */ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + */ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x64180000 - 1, /* 12 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + */ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x00280000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + */ + { + .name = "DisplayBins1", + .start = 0x64AD4000, + .end = 0x64AD5000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * ITFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "ITFS", + .start = 0x64180000, + /* 815,104 bytes each for 2 ITFS partitions. */ + .end = 0x6430DFFF, + .flags = IORESOURCE_IO, + }, + /* + * + * AVFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "AvfsDmaMem", + .start = 0x6430E000, + /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ + .end = 0x64AD0000 - 1, + .flags = IORESOURCE_IO, + }, + { + .name = "AvfsFileSys", + .start = 0x64AD0000, + .end = 0x64AD1000 - 1, /* 4K */ + .flags = IORESOURCE_IO, + }, + /* + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + */ + { + .name = "SmartCardInfo", + .start = 0x64AD1000, + .end = 0x64AD3800 - 1, + .flags = IORESOURCE_IO, + }, + /* + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + */ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + /* + * Add other resources here + */ + { }, +}; + +/* + * NON_DVR_CAPABLE GAIA RESOURCES + */ +struct resource non_dvr_gaia_resources[] __initdata = { + /* + * + * VIDEO1 / LX1 + * + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x241FFFFF, /* 2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24201FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /* + * + * VIDEO2 / LX2 + * + */ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + */ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x64180000 - 1, /* 12 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + */ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + */ + { + .name = "DisplayBins1", + .start = 0x64AD4000, + .end = 0x64AD5000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * AVFS: player HAL memory + * + * + */ + { + .name = "AvfsDmaMem", + .start = 0x6430E000, + .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_IO, + }, + /* + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + */ + { + .name = "SmartCardInfo", + .start = 0x64AD1000, + .end = 0x64AD3800 - 1, + .flags = IORESOURCE_IO, + }, + /* + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + */ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + { }, +}; diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c new file mode 100644 index 0000000..6e76f09 --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-zeus.c @@ -0,0 +1,304 @@ +/* + * Memory pre-allocations for Zeus boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef <ds@schleef.org> + */ + +#include <linux/init.h> +#include <linux/ioport.h> +#include <asm/mach-powertv/asic.h> +#include "prealloc.h" + +/* + * DVR_CAPABLE RESOURCES + */ +struct resource dvr_zeus_resources[] __initdata = +{ + /* + * VIDEO1 / LX1 + */ + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1, + IORESOURCE_MEM) + + /* + * VIDEO2 / LX2 + */ + /* Delta-Mu 2 image (2MiB) */ + PREALLOC_NORMAL("ST231bImage", 0x30000000, 0x30200000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 monitor (8KiB) */ + PREALLOC_NORMAL("ST231bMonitor", 0x30200000, 0x30202000-1, + IORESOURCE_MEM) + /* Delta-Mu 2 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory2", 0x30202000, 0x32000000-1, + IORESOURCE_MEM) + + /* + * Sysaudio Driver + */ + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * STAVEM driver/STAPI + * + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + */ + /* 12MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00c00000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * DOCSIS Subsystem + */ + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM) + + /* + * GHW HAL Driver + */ + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1, + IORESOURCE_MEM) + + /* + * multi com buffer area + */ + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1, + IORESOURCE_MEM) + + /* + * DMA Ring buffer + */ + /* 2.5MiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit0 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit1 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins1", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * ITFS + */ + /* 815,104 bytes each for 2 ITFS partitions. */ + PREALLOC_NORMAL("ITFS", 0x00000000, 0x0018E000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * AVFS + */ + /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x007c2000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* 4KiB */ + PREALLOC_NORMAL("AvfsFileSys", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * PMEM + */ + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * TFTPBuffer + * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images + */ + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Add other resources here + */ + + /* + * End of Resource marker + */ + { + .flags = 0, + }, +}; + +/* + * NON_DVR_CAPABLE ZEUS RESOURCES + */ +struct resource non_dvr_zeus_resources[] __initdata = +{ + /* + * VIDEO1 / LX1 + */ + /* Delta-Mu 1 image (2MiB) */ + PREALLOC_NORMAL("ST231aImage", 0x20000000, 0x20200000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 monitor (8KiB) */ + PREALLOC_NORMAL("ST231aMonitor", 0x20200000, 0x20202000-1, + IORESOURCE_MEM) + /* Delta-Mu 1 RAM (~29.9MiB (32MiB - (2MiB + 8KiB))) */ + PREALLOC_NORMAL("MediaMemory1", 0x20202000, 0x22000000-1, + IORESOURCE_MEM) + + /* + * Sysaudio Driver + */ + /* DSP code and data images (1MiB) */ + PREALLOC_NORMAL("DSP_Image_Buff", 0x00000000, 0x00100000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC CPU PCM buffer (40KiB) */ + PREALLOC_NORMAL("ADSC_CPU_PCM_Buff", 0x00000000, 0x0000A000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC AUX buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_AUX_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + /* ADSC Main buffer (16KiB) */ + PREALLOC_NORMAL("ADSC_Main_Buff", 0x00000000, 0x00004000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * STAVEM driver/STAPI + */ + /* 6MiB */ + PREALLOC_NORMAL("AVMEMPartition0", 0x00000000, 0x00600000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * DOCSIS Subsystem + */ + /* 7MiB */ + PREALLOC_DOCSIS("Docsis", 0x40100000, 0x40800000-1, IORESOURCE_MEM) + + /* + * GHW HAL Driver + */ + /* PowerTV Graphics Heap (14MiB) */ + PREALLOC_NORMAL("GraphicsHeap", 0x46900000, 0x47700000-1, + IORESOURCE_MEM) + + /* + * multi com buffer area + */ + /* 128KiB */ + PREALLOC_NORMAL("MulticomSHM", 0x47900000, 0x47920000-1, + IORESOURCE_MEM) + + /* + * DMA Ring buffer + */ + /* 2.5MiB */ + PREALLOC_NORMAL("BMM_Buffer", 0x00000000, 0x00280000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Display bins buffer for unit0 + */ + /* 4KiB */ + PREALLOC_NORMAL("DisplayBins0", 0x00000000, 0x00001000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * AVFS: player HAL memory + */ + /* 945K * 3 for playback */ + PREALLOC_NORMAL("AvfsDmaMem", 0x00000000, 0x002c4c00-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * PMEM + */ + /* Persistent memory for diagnostics (64KiB) */ + PREALLOC_PMEM("DiagPersistentMemory", 0x00000000, 0x10000-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Smartcard + */ + /* Read and write buffers for Internal/External cards (10KiB) */ + PREALLOC_NORMAL("SmartCardInfo", 0x00000000, 0x2800-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * NAND Flash + */ + /* 10KiB */ + PREALLOC_NORMAL("NandFlash", NAND_FLASH_BASE, NAND_FLASH_BASE+0x400-1, + IORESOURCE_MEM) + + /* + * TFTPBuffer + * + * This buffer is used in some minimal configurations (e.g. two-way + * loader) for storing software images + */ + PREALLOC_TFTP("TFTPBuffer", 0x00000000, MEBIBYTE(80)-1, + (IORESOURCE_MEM|IORESOURCE_PTV_RES_LOEXT)) + + /* + * Add other resources here + */ + + /* + * End of Resource marker + */ + { + .flags = 0, + }, +}; diff --git a/arch/mips/powertv/asic/prealloc.h b/arch/mips/powertv/asic/prealloc.h new file mode 100644 index 0000000..8e682df --- /dev/null +++ b/arch/mips/powertv/asic/prealloc.h @@ -0,0 +1,70 @@ +/* + * Definitions for memory preallocations + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H +#define _ARCH_MIPS_POWERTV_ASIC_PREALLOC_H + +#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ +#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ + +/* "struct resource" array element definition */ +#define PREALLOC(NAME, START, END, FLAGS) { \ + .name = (NAME), \ + .start = (START), \ + .end = (END), \ + .flags = (FLAGS) \ + }, + +/* Individual resources in the preallocated resource arrays are defined using + * macros. These macros are conditionally defined based on their + * corresponding kernel configuration flag: + * - CONFIG_PREALLOC_NORMAL: preallocate resources for a normal settop box + * - CONFIG_PREALLOC_TFTP: preallocate the TFTP download resource + * - CONFIG_PREALLOC_DOCSIS: preallocate the DOCSIS resource + * - CONFIG_PREALLOC_PMEM: reserve space for persistent memory + */ +#ifdef CONFIG_PREALLOC_NORMAL +#define PREALLOC_NORMAL(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_NORMAL(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_TFTP +#define PREALLOC_TFTP(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_TFTP(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_DOCSIS +#define PREALLOC_DOCSIS(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_DOCSIS(name, start, end, flags) +#endif + +#ifdef CONFIG_PREALLOC_PMEM +#define PREALLOC_PMEM(name, start, end, flags) \ + PREALLOC(name, start, end, flags) +#else +#define PREALLOC_PMEM(name, start, end, flags) +#endif +#endif diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c new file mode 100644 index 0000000..4989263 --- /dev/null +++ b/arch/mips/powertv/init.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard <carstenl@mips.com> + * Maciej W. Rozycki <macro@mips.com> + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library initialisation code. + */ +#include <linux/init.h> +#include <linux/string.h> +#include <linux/kernel.h> + +#include <asm/bootinfo.h> +#include <linux/io.h> +#include <asm/cacheflush.h> +#include <asm/traps.h> + +#include <asm/mips-boards/generic.h> +#include <asm/mach-powertv/asic.h> + +#include "init.h" + +static int *_prom_envp; +unsigned long _prom_memsize; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +char *prom_getenv(char *envname) +{ + char *result = NULL; + + if (_prom_envp != NULL) { + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index = 0; + + i = strlen(envname); + + while (prom_envp(index)) { + if (strncmp(envname, prom_envp(index), i) == 0) { + result = prom_envp(index + 1); + break; + } + index += 2; + } + } + + return result; +} + +void __init prom_init(void) +{ + int prom_argc; + char *prom_argv; + + prom_argc = fw_arg0; + prom_argv = (char *) fw_arg1; + _prom_envp = (int *) fw_arg2; + _prom_memsize = (unsigned long) fw_arg3; + + if (prom_argc == 1) { + strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); + strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE); + } + + configure_platform(); + prom_meminit(); +} diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h new file mode 100644 index 0000000..c1a8bd0 --- /dev/null +++ b/arch/mips/powertv/init.h @@ -0,0 +1,28 @@ +/* + * Definitions from powertv init.c file + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#ifndef _POWERTV_INIT_H +#define _POWERTV_INIT_H +extern unsigned long _prom_memsize; +extern void prom_meminit(void); +extern char *prom_getenv(char *name); +#endif diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c new file mode 100644 index 0000000..d060478 --- /dev/null +++ b/arch/mips/powertv/ioremap.c @@ -0,0 +1,136 @@ +/* + * ioremap.c + * + * Support for mapping between dma_addr_t values a phys_addr_t values. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn <dvomlehn@cisco.com> + * + * Description: Defines the platform resources for the SA settop. + * + * NOTE: The bootloader allocates persistent memory at an address which is + * 16 MiB below the end of the highest address in KSEG0. All fixed + * address memory reservations must avoid this region. + */ + +#include <linux/kernel.h> +#include <linux/module.h> + +#include <asm/mach-powertv/ioremap.h> + +/* + * Define the sizes of and masks for grains in physical and DMA space. The + * values are the same but the types are not. + */ +#define IOR_PHYS_GRAIN ((phys_addr_t) 1 << IOR_LSBITS) +#define IOR_PHYS_GRAIN_MASK (IOR_PHYS_GRAIN - 1) + +#define IOR_DMA_GRAIN ((dma_addr_t) 1 << IOR_LSBITS) +#define IOR_DMA_GRAIN_MASK (IOR_DMA_GRAIN - 1) + +/* + * Values that, when accessed by an index derived from a phys_addr_t and + * added to phys_addr_t value, yield a DMA address + */ +struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA]; +EXPORT_SYMBOL(_ior_phys_to_dma); + +/* + * Values that, when accessed by an index derived from a dma_addr_t and + * added to that dma_addr_t value, yield a physical address + */ +struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS]; +EXPORT_SYMBOL(_ior_dma_to_phys); + +/** + * setup_dma_to_phys - set up conversion from DMA to physical addresses + * @dma_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index + * into the array _dma_to_phys. + * @delta: Value that, when added to the DMA address, will yield the + * physical address + * @s: Number of bytes in the section of memory with the given delta + * between DMA and physical addresses. + */ +static void setup_dma_to_phys(dma_addr_t dma, phys_addr_t delta, dma_addr_t s) +{ + int dma_idx, first_idx, last_idx; + phys_addr_t first, last; + + /* + * Calculate the first and last indices, rounding the first up and + * the second down. + */ + first = dma & ~IOR_DMA_GRAIN_MASK; + last = (dma + s - 1) & ~IOR_DMA_GRAIN_MASK; + first_idx = first >> IOR_LSBITS; /* Convert to indices */ + last_idx = last >> IOR_LSBITS; + + for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++) + _ior_dma_to_phys[dma_idx].offset = delta >> IOR_DMA_SHIFT; +} + +/** + * setup_phys_to_dma - set up conversion from DMA to physical addresses + * @phys_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index + * into the array _phys_to_dma. + * @delta: Value that, when added to the DMA address, will yield the + * physical address + * @s: Number of bytes in the section of memory with the given delta + * between DMA and physical addresses. + */ +static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s) +{ + int phys_idx, first_idx, last_idx; + phys_addr_t first, last; + + /* + * Calculate the first and last indices, rounding the first up and + * the second down. + */ + first = phys & ~IOR_PHYS_GRAIN_MASK; + last = (phys + s - 1) & ~IOR_PHYS_GRAIN_MASK; + first_idx = first >> IOR_LSBITS; /* Convert to indices */ + last_idx = last >> IOR_LSBITS; + + for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++) + _ior_phys_to_dma[phys_idx].offset = delta >> IOR_PHYS_SHIFT; +} + +/** + * ioremap_add_map - add to the physical and DMA address conversion arrays + * @phys: Process's view of the address of the start of the memory chunk + * @dma: DMA address of the start of the memory chunk + * @size: Size, in bytes, of the chunk of memory + * + * NOTE: It might be obvious, but the assumption is that all @size bytes have + * the same offset between the physical address and the DMA address. + */ +void ioremap_add_map(phys_addr_t phys, phys_addr_t dma, phys_addr_t size) +{ + if (size == 0) + return; + + if ((dma & IOR_DMA_GRAIN_MASK) != 0 || + (phys & IOR_PHYS_GRAIN_MASK) != 0 || + (size & IOR_PHYS_GRAIN_MASK) != 0) + pr_crit("Memory allocation must be in chunks of 0x%x bytes\n", + IOR_PHYS_GRAIN); + + setup_dma_to_phys(dma, phys - dma, size); + setup_phys_to_dma(phys, dma - phys, size); +} diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c new file mode 100644 index 0000000..bc2f3ca --- /dev/null +++ b/arch/mips/powertv/memory.c @@ -0,0 +1,353 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Apparently originally from arch/mips/malta-memory.c. Modified to work + * with the PowerTV bootloader. + */ +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/bootmem.h> +#include <linux/pfn.h> +#include <linux/string.h> + +#include <asm/bootinfo.h> +#include <asm/page.h> +#include <asm/sections.h> + +#include <asm/mach-powertv/asic.h> +#include <asm/mach-powertv/ioremap.h> + +#include "init.h" + +/* Memory constants */ +#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ +#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ +#define DEFAULT_MEMSIZE MEBIBYTE(128) /* If no memsize provided */ + +#define BLDR_SIZE KIBIBYTE(256) /* Memory reserved for bldr */ +#define RV_SIZE MEBIBYTE(4) /* Size of reset vector */ + +#define LOW_MEM_END 0x20000000 /* Highest low memory address */ +#define BLDR_ALIAS 0x10000000 /* Bootloader address */ +#define RV_PHYS 0x1fc00000 /* Reset vector address */ +#define LOW_RAM_END RV_PHYS /* End of real RAM in low mem */ + +/* + * Very low-level conversion from processor physical address to device + * DMA address for the first bank of memory. + */ +#define PHYS_TO_DMA(paddr) ((paddr) + (CONFIG_LOW_RAM_DMA - LOW_RAM_ALIAS)) + +unsigned long ptv_memsize; + +/* + * struct low_mem_reserved - Items in low memory that are reserved + * @start: Physical address of item + * @size: Size, in bytes, of this item + * @is_aliased: True if this is RAM aliased from another location. If false, + * it is something other than aliased RAM and the RAM in the + * unaliased address is still visible outside of low memory. + */ +struct low_mem_reserved { + phys_addr_t start; + phys_addr_t size; + bool is_aliased; +}; + +/* + * Must be in ascending address order + */ +struct low_mem_reserved low_mem_reserved[] = { + {BLDR_ALIAS, BLDR_SIZE, true}, /* Bootloader RAM */ + {RV_PHYS, RV_SIZE, false}, /* Reset vector */ +}; + +/* + * struct mem_layout - layout of a piece of the system RAM + * @phys: Physical address of the start of this piece of RAM. This is the + * address at which both the processor and I/O devices see the + * RAM. + * @alias: Alias of this piece of memory in order to make it appear in + * the low memory part of the processor's address space. I/O + * devices don't see anything here. + * @size: Size, in bytes, of this piece of RAM + */ +struct mem_layout { + phys_addr_t phys; + phys_addr_t alias; + phys_addr_t size; +}; + +/* + * struct mem_layout_list - list descriptor for layouts of system RAM pieces + * @family: Specifies the family being described + * @n: Number of &struct mem_layout elements + * @layout: Pointer to the list of &mem_layout structures + */ +struct mem_layout_list { + enum family_type family; + size_t n; + struct mem_layout *layout; +}; + +static struct mem_layout f1500_layout[] = { + {0x20000000, 0x10000000, MEBIBYTE(256)}, +}; + +static struct mem_layout f4500_layout[] = { + {0x40000000, 0x10000000, MEBIBYTE(256)}, + {0x20000000, 0x20000000, MEBIBYTE(32)}, +}; + +static struct mem_layout f8500_layout[] = { + {0x40000000, 0x10000000, MEBIBYTE(256)}, + {0x20000000, 0x20000000, MEBIBYTE(32)}, + {0x30000000, 0x30000000, MEBIBYTE(32)}, +}; + +static struct mem_layout fx600_layout[] = { + {0x20000000, 0x10000000, MEBIBYTE(256)}, + {0x60000000, 0x60000000, MEBIBYTE(128)}, +}; + +static struct mem_layout_list layout_list[] = { + {FAMILY_1500, ARRAY_SIZE(f1500_layout), f1500_layout}, + {FAMILY_1500VZE, ARRAY_SIZE(f1500_layout), f1500_layout}, + {FAMILY_1500VZF, ARRAY_SIZE(f1500_layout), f1500_layout}, + {FAMILY_4500, ARRAY_SIZE(f4500_layout), f4500_layout}, + {FAMILY_8500, ARRAY_SIZE(f8500_layout), f8500_layout}, + {FAMILY_8500RNG, ARRAY_SIZE(f8500_layout), f8500_layout}, + {FAMILY_4600, ARRAY_SIZE(fx600_layout), fx600_layout}, + {FAMILY_4600VZA, ARRAY_SIZE(fx600_layout), fx600_layout}, + {FAMILY_8600, ARRAY_SIZE(fx600_layout), fx600_layout}, + {FAMILY_8600VZB, ARRAY_SIZE(fx600_layout), fx600_layout}, +}; + +/* If we can't determine the layout, use this */ +static struct mem_layout default_layout[] = { + {0x20000000, 0x10000000, MEBIBYTE(128)}, +}; + +/** + * register_non_ram - register low memory not available for RAM usage + */ +static __init void register_non_ram(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(low_mem_reserved); i++) + add_memory_region(low_mem_reserved[i].start, + low_mem_reserved[i].size, BOOT_MEM_RESERVED); +} + +/** + * get_memsize - get the size of memory as a single bank + */ +static phys_addr_t get_memsize(void) +{ + static char cmdline[COMMAND_LINE_SIZE] __initdata; + phys_addr_t memsize = 0; + char *memsize_str; + char *ptr; + + /* Check the command line first for a memsize directive */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) { + memsize = memparse(ptr + 8, &ptr); + } else { + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + + if (memsize_str != NULL) { + pr_info("prom memsize = %s\n", memsize_str); + memsize = simple_strtol(memsize_str, NULL, 0); + } + + if (memsize == 0) { + if (_prom_memsize != 0) { + memsize = _prom_memsize; + pr_info("_prom_memsize = 0x%x\n", memsize); + /* add in memory that the bootloader doesn't + * report */ + memsize += BLDR_SIZE; + } else { + memsize = DEFAULT_MEMSIZE; + pr_info("Memsize not passed by bootloader, " + "defaulting to 0x%x\n", memsize); + } + } + } + + return memsize; +} + +/** + * register_low_ram - register an aliased section of RAM + * @p: Alias address of memory + * @n: Number of bytes in this section of memory + * + * Returns the number of bytes registered + * + */ +static __init phys_addr_t register_low_ram(phys_addr_t p, phys_addr_t n) +{ + phys_addr_t s; + int i; + phys_addr_t orig_n; + + orig_n = n; + + BUG_ON(p + n > RV_PHYS); + + for (i = 0; n != 0 && i < ARRAY_SIZE(low_mem_reserved); i++) { + phys_addr_t start; + phys_addr_t size; + + start = low_mem_reserved[i].start; + size = low_mem_reserved[i].size; + + /* Handle memory before this low memory section */ + if (p < start) { + phys_addr_t s; + s = min(n, start - p); + add_memory_region(p, s, BOOT_MEM_RAM); + p += s; + n -= s; + } + + /* Handle the low memory section itself. If it's aliased, + * we reduce the number of byes left, but if not, the RAM + * is available elsewhere and we don't reduce the number of + * bytes remaining. */ + if (p == start) { + if (low_mem_reserved[i].is_aliased) { + s = min(n, size); + n -= s; + p += s; + } else + p += n; + } + } + + return orig_n - n; +} + +/* + * register_ram - register real RAM + * @p: Address of memory as seen by devices + * @alias: If the memory is seen at an additional address by the processor, + * this will be the address, otherwise it is the same as @p. + * @n: Number of bytes in this section of memory + */ +static __init void register_ram(phys_addr_t p, phys_addr_t alias, + phys_addr_t n) +{ + /* + * If some or all of this memory has an alias, break it into the + * aliased and non-aliased portion. + */ + if (p != alias) { + phys_addr_t alias_size; + phys_addr_t registered; + + alias_size = min(n, LOW_RAM_END - alias); + registered = register_low_ram(alias, alias_size); + ioremap_add_map(alias, p, n); + n -= registered; + p += registered; + } + +#ifdef CONFIG_HIGHMEM + if (n != 0) { + add_memory_region(p, n, BOOT_MEM_RAM); + ioremap_add_map(p, p, n); + } +#endif +} + +/** + * register_address_space - register things in the address space + * @memsize: Number of bytes of RAM installed + * + * Takes the given number of bytes of RAM and registers as many of the regions, + * or partial regions, as it can. So, the default configuration might have + * two regions with 256 MiB each. If the memsize passed in on the command line + * is 384 MiB, it will register the first region with 256 MiB and the second + * with 128 MiB. + */ +static __init void register_address_space(phys_addr_t memsize) +{ + int i; + phys_addr_t size; + size_t n; + struct mem_layout *layout; + enum family_type family; + + /* + * Register all of the things that aren't available to the kernel as + * memory. + */ + register_non_ram(); + + /* Find the appropriate memory description */ + family = platform_get_family(); + + for (i = 0; i < ARRAY_SIZE(layout_list); i++) { + if (layout_list[i].family == family) + break; + } + + if (i == ARRAY_SIZE(layout_list)) { + n = ARRAY_SIZE(default_layout); + layout = default_layout; + } else { + n = layout_list[i].n; + layout = layout_list[i].layout; + } + + for (i = 0; memsize != 0 && i < n; i++) { + size = min(memsize, layout[i].size); + register_ram(layout[i].phys, layout[i].alias, size); + memsize -= size; + } +} + +void __init prom_meminit(void) +{ + ptv_memsize = get_memsize(); + register_address_space(ptv_memsize); +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile new file mode 100644 index 0000000..2610a6a --- /dev/null +++ b/arch/mips/powertv/pci/Makefile @@ -0,0 +1,19 @@ +# +# Copyright (C) 2009 Scientific-Atlanta, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +obj-$(CONFIG_PCI) += fixup-powertv.o diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c new file mode 100644 index 0000000..d7ecbae --- /dev/null +++ b/arch/mips/powertv/pci/fixup-powertv.c @@ -0,0 +1,37 @@ +#include <linux/init.h> +#include <linux/export.h> +#include <linux/pci.h> +#include <asm/mach-powertv/interrupts.h> +#include "powertv-pci.h" + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return asic_pcie_map_irq(dev, slot, pin); +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +/* + * asic_pcie_map_irq + * + * Parameters: + * *dev - pointer to a pci_dev structure (not used) + * slot - slot number (not used) + * pin - pin number (not used) + * + * Return Value: + * Returns: IRQ number (always the PCI Express IRQ number) + * + * Description: + * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt. + * + */ +int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return irq_pciexp; +} +EXPORT_SYMBOL(asic_pcie_map_irq); diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h new file mode 100644 index 0000000..1b5886b --- /dev/null +++ b/arch/mips/powertv/pci/powertv-pci.h @@ -0,0 +1,31 @@ +/* + * powertv-pci.c + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* + * Local definitions for the powertv PCI code + */ + +#ifndef _POWERTV_PCI_POWERTV_PCI_H_ +#define _POWERTV_PCI_POWERTV_PCI_H_ +extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +extern int asic_pcie_init(void); +extern int asic_pcie_init(void); + +extern int log_level; +#endif diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h new file mode 100644 index 0000000..d94c543 --- /dev/null +++ b/arch/mips/powertv/powertv-clock.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#ifndef _POWERTV_POWERTV_CLOCK_H +#define _POWERTV_POWERTV_CLOCK_H +extern int powertv_clockevent_init(void); +extern void powertv_clocksource_init(void); +extern unsigned int mips_get_pll_freq(void); +#endif diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c new file mode 100644 index 0000000..d845eac --- /dev/null +++ b/arch/mips/powertv/powertv-usb.c @@ -0,0 +1,404 @@ +/* + * powertv-usb.c + * + * Description: ASIC-specific USB device setup and shutdown + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef <ds@schleef.org> + * + * NOTE: The bootloader allocates persistent memory at an address which is + * 16 MiB below the end of the highest address in KSEG0. All fixed + * address memory reservations must avoid this region. + */ + +#include <linux/kernel.h> +#include <linux/export.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <asm/mach-powertv/asic.h> +#include <asm/mach-powertv/interrupts.h> + +/* misc_clk_ctl1 values */ +#define MCC1_30MHZ_POWERUP_SELECT (1 << 14) +#define MCC1_DIV9 (1 << 13) +#define MCC1_ETHMIPS_POWERUP_SELECT (1 << 11) +#define MCC1_USB_POWERUP_SELECT (1 << 1) +#define MCC1_CLOCK108_POWERUP_SELECT (1 << 0) + +/* Possible values for clock select */ +#define MCC1_USB_CLOCK_HIGH_Z (0 << 4) +#define MCC1_USB_CLOCK_48MHZ (1 << 4) +#define MCC1_USB_CLOCK_24MHZ (2 << 4) +#define MCC1_USB_CLOCK_6MHZ (3 << 4) + +#define MCC1_CONFIG (MCC1_30MHZ_POWERUP_SELECT | \ + MCC1_DIV9 | \ + MCC1_ETHMIPS_POWERUP_SELECT | \ + MCC1_USB_POWERUP_SELECT | \ + MCC1_CLOCK108_POWERUP_SELECT) + +/* misc_clk_ctl2 values */ +#define MCC2_GMII_GCLK_TO_PAD (1 << 31) +#define MCC2_ETHER125_0_CLOCK_SELECT (1 << 29) +#define MCC2_RMII_0_CLOCK_SELECT (1 << 28) +#define MCC2_GMII_TX0_CLOCK_SELECT (1 << 27) +#define MCC2_GMII_RX0_CLOCK_SELECT (1 << 26) +#define MCC2_ETHER125_1_CLOCK_SELECT (1 << 24) +#define MCC2_RMII_1_CLOCK_SELECT (1 << 23) +#define MCC2_GMII_TX1_CLOCK_SELECT (1 << 22) +#define MCC2_GMII_RX1_CLOCK_SELECT (1 << 21) +#define MCC2_ETHER125_2_CLOCK_SELECT (1 << 19) +#define MCC2_RMII_2_CLOCK_SELECT (1 << 18) +#define MCC2_GMII_TX2_CLOCK_SELECT (1 << 17) +#define MCC2_GMII_RX2_CLOCK_SELECT (1 << 16) + +#define ETHER_CLK_CONFIG (MCC2_GMII_GCLK_TO_PAD | \ + MCC2_ETHER125_0_CLOCK_SELECT | \ + MCC2_RMII_0_CLOCK_SELECT | \ + MCC2_GMII_TX0_CLOCK_SELECT | \ + MCC2_GMII_RX0_CLOCK_SELECT | \ + MCC2_ETHER125_1_CLOCK_SELECT | \ + MCC2_RMII_1_CLOCK_SELECT | \ + MCC2_GMII_TX1_CLOCK_SELECT | \ + MCC2_GMII_RX1_CLOCK_SELECT | \ + MCC2_ETHER125_2_CLOCK_SELECT | \ + MCC2_RMII_2_CLOCK_SELECT | \ + MCC2_GMII_TX2_CLOCK_SELECT | \ + MCC2_GMII_RX2_CLOCK_SELECT) + +/* misc_clk_ctl2 definitions for Gaia */ +#define FSX4A_REF_SELECT (1 << 16) +#define FSX4B_REF_SELECT (1 << 17) +#define FSX4C_REF_SELECT (1 << 18) +#define DDR_PLL_REF_SELECT (1 << 19) +#define MIPS_PLL_REF_SELECT (1 << 20) + +/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */ +#define QAM_FS_SDIV_SHIFT 29 +#define QAM_FS_MD_SHIFT 24 +#define QAM_FS_MD_MASK 0x1f /* Cut down to 5 bits */ +#define QAM_FS_PE_SHIFT 8 + +#define QAM_FS_DISABLE_DIVIDE_BY_3 (1 << 5) +#define QAM_FS_ENABLE_PROGRAM (1 << 4) +#define QAM_FS_ENABLE_OUTPUT (1 << 3) +#define QAM_FS_SELECT_TEST_BYPASS (1 << 2) +#define QAM_FS_DISABLE_DIGITAL_STANDBY (1 << 1) +#define QAM_FS_CHOOSE_FS (1 << 0) + +/* Definitions for fs432x4a_ctl register */ +#define QAM_FS_NSDIV_54MHZ (1 << 2) + +/* Definitions for bcm1_usb2_ctl register */ +#define BCM1_USB2_CTL_BISTOK (1 << 11) +#define BCM1_USB2_CTL_PORT2_SHIFT_JK (1 << 7) +#define BCM1_USB2_CTL_PORT1_SHIFT_JK (1 << 6) +#define BCM1_USB2_CTL_PORT2_FAST_EDGE (1 << 5) +#define BCM1_USB2_CTL_PORT1_FAST_EDGE (1 << 4) +#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH (1 << 1) +#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH (1 << 0) + +/* Definitions for crt_spare register */ +#define CRT_SPARE_PORT2_SHIFT_JK (1 << 21) +#define CRT_SPARE_PORT1_SHIFT_JK (1 << 20) +#define CRT_SPARE_PORT2_FAST_EDGE (1 << 19) +#define CRT_SPARE_PORT1_FAST_EDGE (1 << 18) +#define CRT_SPARE_DIVIDE_BY_9_FROM_432 (1 << 17) +#define CRT_SPARE_USB_DIVIDE_BY_9 (1 << 16) + +/* Definitions for usb2_stbus_obc register */ +#define USB_STBUS_OBC_STORE32_LOAD32 0x3 + +/* Definitions for usb2_stbus_mess_size register */ +#define USB2_STBUS_MESS_SIZE_2 0x1 /* 2 packets */ + +/* Definitions for usb2_stbus_chunk_size register */ +#define USB2_STBUS_CHUNK_SIZE_2 0x1 /* 2 packets */ + +/* Definitions for usb2_strap register */ +#define USB2_STRAP_HFREQ_SELECT 0x1 + +/* + * USB Host Resource Definition + */ + +static struct resource ehci_resources[] = { + { + .parent = &asic_resource, + .start = 0, + .end = 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = irq_usbehci, + .end = irq_usbehci, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = 0xffffffffULL; + +static struct platform_device ehci_device = { + .name = "powertv-ehci", + .id = 0, + .num_resources = 2, + .resource = ehci_resources, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct resource ohci_resources[] = { + { + .parent = &asic_resource, + .start = 0, + .end = 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = irq_usbohci, + .end = irq_usbohci, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ohci_dmamask = 0xffffffffULL; + +static struct platform_device ohci_device = { + .name = "powertv-ohci", + .id = 0, + .num_resources = 2, + .resource = ohci_resources, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +static unsigned usb_users; +static DEFINE_SPINLOCK(usb_regs_lock); + +/* + * + * fs_update - set frequency synthesizer for USB + * @pe_bits Phase tap setting + * @md_bits Coarse selector bus for algorithm of phase tap + * @sdiv_bits Output divider setting + * @disable_div_by_3 Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero + * @standby Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero + * + * QAM frequency selection code, which affects the frequency at which USB + * runs. The frequency is calculated as: + * 2^15 * ndiv * Fin + * Fout = ------------------------------------------------------------ + * (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32))) + * where: + * Fin 54 MHz + * ndiv QAM_FS_NSDIV_54MHZ ? 8 : 16 + * sdiv 1 << (sdiv_bits + 1) + * ipe Same as pe_bits + * md A five-bit, two's-complement integer (range [-16, 15]), which + * is the lower 5 bits of md_bits. + */ +static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits, + u32 disable_div_by_3, u32 standby) +{ + u32 val; + + val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) | + ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) | + (pe_bits << QAM_FS_PE_SHIFT) | + QAM_FS_ENABLE_OUTPUT | + standby | + disable_div_by_3); + asic_write(val, fs432x4b4_usb_ctl); + asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl); + asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS, + fs432x4b4_usb_ctl); +} + +/* + * usb_eye_configure - for optimizing the shape USB eye waveform + * @set: Bits to set in the register + * @clear: Bits to clear in the register; each bit with a one will + * be set in the register, zero bits will not be modified + */ +static void usb_eye_configure(u32 set, u32 clear) +{ + u32 old; + + old = asic_read(crt_spare); + old |= set; + old &= ~clear; + asic_write(old, crt_spare); +} + +/* + * platform_configure_usb - usb configuration based on platform type. + */ +static void platform_configure_usb(void) +{ + u32 bcm1_usb2_ctl_value; + enum asic_type asic_type; + unsigned long flags; + + spin_lock_irqsave(&usb_regs_lock, flags); + usb_users++; + + if (usb_users != 1) { + spin_unlock_irqrestore(&usb_regs_lock, flags); + return; + } + + asic_type = platform_get_asic(); + + switch (asic_type) { + case ASIC_ZEUS: + fs_update(0x0000, -15, 0x02, 0, 0); + bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | + BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; + break; + + case ASIC_CRONUS: + case ASIC_CRONUSLITE: + usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9); + fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3, + QAM_FS_DISABLE_DIGITAL_STANDBY); + bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | + BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; + break; + + case ASIC_CALLIOPE: + fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3, + QAM_FS_DISABLE_DIGITAL_STANDBY); + + switch (platform_get_family()) { + case FAMILY_1500VZE: + break; + + case FAMILY_1500VZF: + usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK | + CRT_SPARE_PORT1_SHIFT_JK | + CRT_SPARE_PORT2_FAST_EDGE | + CRT_SPARE_PORT1_FAST_EDGE, 0); + break; + + default: + usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK | + CRT_SPARE_PORT1_SHIFT_JK, 0); + break; + } + + bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK | + BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | + BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; + break; + + case ASIC_GAIA: + fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3, + QAM_FS_DISABLE_DIGITAL_STANDBY); + bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK | + BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH | + BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH; + break; + + default: + pr_err("Unknown ASIC type: %d\n", asic_type); + bcm1_usb2_ctl_value = 0; + break; + } + + /* turn on USB power */ + asic_write(0, usb2_strap); + /* Enable all OHCI interrupts */ + asic_write(bcm1_usb2_ctl_value, usb2_control); + /* usb2_stbus_obc store32/load32 */ + asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc); + /* usb2_stbus_mess_size 2 packets */ + asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size); + /* usb2_stbus_chunk_size 2 packets */ + asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size); + spin_unlock_irqrestore(&usb_regs_lock, flags); +} + +static void platform_unconfigure_usb(void) +{ + unsigned long flags; + + spin_lock_irqsave(&usb_regs_lock, flags); + usb_users--; + if (usb_users == 0) + asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap); + spin_unlock_irqrestore(&usb_regs_lock, flags); +} + +/* + * Set up the USB EHCI interface + */ +void platform_configure_usb_ehci() +{ + platform_configure_usb(); +} +EXPORT_SYMBOL(platform_configure_usb_ehci); + +/* + * Set up the USB OHCI interface + */ +void platform_configure_usb_ohci() +{ + platform_configure_usb(); +} +EXPORT_SYMBOL(platform_configure_usb_ohci); + +/* + * Shut the USB EHCI interface down + */ +void platform_unconfigure_usb_ehci() +{ + platform_unconfigure_usb(); +} +EXPORT_SYMBOL(platform_unconfigure_usb_ehci); + +/* + * Shut the USB OHCI interface down + */ +void platform_unconfigure_usb_ohci() +{ + platform_unconfigure_usb(); +} +EXPORT_SYMBOL(platform_unconfigure_usb_ohci); + +/** + * platform_devices_init - sets up USB device resourse. + */ +int __init platform_usb_devices_init(struct platform_device **ehci_dev, + struct platform_device **ohci_dev) +{ + *ehci_dev = &ehci_device; + ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase); + ehci_resources[0].end += ehci_resources[0].start; + + *ohci_dev = &ohci_device; + ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision); + ohci_resources[0].end += ohci_resources[0].start; + + return 0; +} diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c new file mode 100644 index 0000000..24689bf --- /dev/null +++ b/arch/mips/powertv/powertv_setup.c @@ -0,0 +1,319 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/ioport.h> +#include <linux/pci.h> +#include <linux/screen_info.h> +#include <linux/notifier.h> +#include <linux/etherdevice.h> +#include <linux/if_ether.h> +#include <linux/ctype.h> +#include <linux/cpu.h> +#include <linux/time.h> + +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/mips-boards/generic.h> +#include <asm/dma.h> +#include <asm/asm.h> +#include <asm/traps.h> +#include <asm/asm-offsets.h> +#include "reset.h" + +#define VAL(n) STR(n) + +/* + * Macros for loading addresses and storing registers: + * LONG_L_ Stringified version of LONG_L for use in asm() statement + * LONG_S_ Stringified version of LONG_S for use in asm() statement + * PTR_LA_ Stringified version of PTR_LA for use in asm() statement + * REG_SIZE Number of 8-bit bytes in a full width register + */ +#define LONG_L_ VAL(LONG_L) " " +#define LONG_S_ VAL(LONG_S) " " +#define PTR_LA_ VAL(PTR_LA) " " + +#ifdef CONFIG_64BIT +#warning TODO: 64-bit code needs to be verified +#define REG_SIZE "8" /* In bytes */ +#endif + +#ifdef CONFIG_32BIT +#define REG_SIZE "4" /* In bytes */ +#endif + +static void register_panic_notifier(void); +static int panic_handler(struct notifier_block *notifier_block, + unsigned long event, void *cause_string); + +const char *get_system_type(void) +{ + return "PowerTV"; +} + +void __init plat_mem_setup(void) +{ + panic_on_oops = 1; + register_panic_notifier(); + +#if 0 + mips_pcibios_init(); +#endif + mips_reboot_setup(); +} + +/* + * Install a panic notifier for platform-specific diagnostics + */ +static void register_panic_notifier() +{ + static struct notifier_block panic_notifier = { + .notifier_call = panic_handler, + .next = NULL, + .priority = INT_MAX + }; + atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier); +} + +static int panic_handler(struct notifier_block *notifier_block, + unsigned long event, void *cause_string) +{ + struct pt_regs my_regs; + + /* Save all of the registers */ + { + unsigned long at, v0, v1; /* Must be on the stack */ + + /* Start by saving $at and v0 on the stack. We use $at + * ourselves, but it looks like the compiler may use v0 or v1 + * to load the address of the pt_regs structure. We'll come + * back later to store the registers in the pt_regs + * structure. */ + __asm__ __volatile__ ( + ".set noat\n" + LONG_S_ "$at, %[at]\n" + LONG_S_ "$2, %[v0]\n" + LONG_S_ "$3, %[v1]\n" + : + [at] "=m" (at), + [v0] "=m" (v0), + [v1] "=m" (v1) + : + : "at" + ); + + __asm__ __volatile__ ( + ".set noat\n" + "move $at, %[pt_regs]\n" + + /* Argument registers */ + LONG_S_ "$4, " VAL(PT_R4) "($at)\n" + LONG_S_ "$5, " VAL(PT_R5) "($at)\n" + LONG_S_ "$6, " VAL(PT_R6) "($at)\n" + LONG_S_ "$7, " VAL(PT_R7) "($at)\n" + + /* Temporary regs */ + LONG_S_ "$8, " VAL(PT_R8) "($at)\n" + LONG_S_ "$9, " VAL(PT_R9) "($at)\n" + LONG_S_ "$10, " VAL(PT_R10) "($at)\n" + LONG_S_ "$11, " VAL(PT_R11) "($at)\n" + LONG_S_ "$12, " VAL(PT_R12) "($at)\n" + LONG_S_ "$13, " VAL(PT_R13) "($at)\n" + LONG_S_ "$14, " VAL(PT_R14) "($at)\n" + LONG_S_ "$15, " VAL(PT_R15) "($at)\n" + + /* "Saved" registers */ + LONG_S_ "$16, " VAL(PT_R16) "($at)\n" + LONG_S_ "$17, " VAL(PT_R17) "($at)\n" + LONG_S_ "$18, " VAL(PT_R18) "($at)\n" + LONG_S_ "$19, " VAL(PT_R19) "($at)\n" + LONG_S_ "$20, " VAL(PT_R20) "($at)\n" + LONG_S_ "$21, " VAL(PT_R21) "($at)\n" + LONG_S_ "$22, " VAL(PT_R22) "($at)\n" + LONG_S_ "$23, " VAL(PT_R23) "($at)\n" + + /* Add'l temp regs */ + LONG_S_ "$24, " VAL(PT_R24) "($at)\n" + LONG_S_ "$25, " VAL(PT_R25) "($at)\n" + + /* Kernel temp regs */ + LONG_S_ "$26, " VAL(PT_R26) "($at)\n" + LONG_S_ "$27, " VAL(PT_R27) "($at)\n" + + /* Global pointer, stack pointer, frame pointer and + * return address */ + LONG_S_ "$gp, " VAL(PT_R28) "($at)\n" + LONG_S_ "$sp, " VAL(PT_R29) "($at)\n" + LONG_S_ "$fp, " VAL(PT_R30) "($at)\n" + LONG_S_ "$ra, " VAL(PT_R31) "($at)\n" + + /* Now we can get the $at and v0 registers back and + * store them */ + LONG_L_ "$8, %[at]\n" + LONG_S_ "$8, " VAL(PT_R1) "($at)\n" + LONG_L_ "$8, %[v0]\n" + LONG_S_ "$8, " VAL(PT_R2) "($at)\n" + LONG_L_ "$8, %[v1]\n" + LONG_S_ "$8, " VAL(PT_R3) "($at)\n" + : + : + [at] "m" (at), + [v0] "m" (v0), + [v1] "m" (v1), + [pt_regs] "r" (&my_regs) + : "at", "t0" + ); + + /* Set the current EPC value to be the current location in this + * function */ + __asm__ __volatile__ ( + ".set noat\n" + "1:\n" + PTR_LA_ "$at, 1b\n" + LONG_S_ "$at, %[cp0_epc]\n" + : + [cp0_epc] "=m" (my_regs.cp0_epc) + : + : "at" + ); + + my_regs.cp0_cause = read_c0_cause(); + my_regs.cp0_status = read_c0_status(); + } + + pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " + "zzzz... \n"); + + return NOTIFY_DONE; +} + +/* Information about the RF MAC address, if one was supplied on the + * command line. */ +static bool have_rfmac; +static u8 rfmac[ETH_ALEN]; + +static int rfmac_param(char *p) +{ + u8 *q; + bool is_high_nibble; + int c; + + /* Skip a leading "0x", if present */ + if (*p == '0' && *(p+1) == 'x') + p += 2; + + q = rfmac; + is_high_nibble = true; + + for (c = (unsigned char) *p++; + isxdigit(c) && q - rfmac < ETH_ALEN; + c = (unsigned char) *p++) { + int nibble; + + nibble = (isdigit(c) ? (c - '0') : + (isupper(c) ? c - 'A' + 10 : c - 'a' + 10)); + + if (is_high_nibble) + *q = nibble << 4; + else + *q++ |= nibble; + + is_high_nibble = !is_high_nibble; + } + + /* If we parsed all the way to the end of the parameter value and + * parsed all ETH_ALEN bytes, we have a usable RF MAC address */ + have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN); + + return 0; +} + +early_param("rfmac", rfmac_param); + +/* + * Generate an Ethernet MAC address that has a good chance of being unique. + * @addr: Pointer to six-byte array containing the Ethernet address + * Generates an Ethernet MAC address that is highly likely to be unique for + * this particular system on a network with other systems of the same type. + * + * The problem we are solving is that, when eth_random_addr() is used to + * generate MAC addresses at startup, there isn't much entropy for the random + * number generator to use and the addresses it produces are fairly likely to + * be the same as those of other identical systems on the same local network. + * This is true even for relatively small numbers of systems (for the reason + * why, see the Wikipedia entry for "Birthday problem" at: + * http://en.wikipedia.org/wiki/Birthday_problem + * + * The good news is that we already have a MAC address known to be unique, the + * RF MAC address. The bad news is that this address is already in use on the + * RF interface. Worse, the obvious trick, taking the RF MAC address and + * turning on the locally managed bit, has already been used for other devices. + * Still, this does give us something to work with. + * + * The approach we take is: + * 1. If we can't get the RF MAC Address, just call eth_random_addr. + * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24 + * bits of the new address. This is very likely to be unique, except for + * the current box. + * 3. To avoid using addresses already on the current box, we set the top + * six bits of the address with a value different from any currently + * registered Scientific Atlanta organizationally unique identifyer + * (OUI). This avoids duplication with any addresses on the system that + * were generated from valid Scientific Atlanta-registered address by + * simply flipping the locally managed bit. + * 4. We aren't generating a multicast address, so we leave the multicast + * bit off. Since we aren't using a registered address, we have to set + * the locally managed bit. + * 5. We then randomly generate the remaining 16-bits. This does two + * things: + * a. It allows us to call this function for more than one device + * in this system + * b. It ensures that things will probably still work even if + * some device on the device network has a locally managed + * address that matches the top six bits from step 2. + */ +void platform_random_ether_addr(u8 addr[ETH_ALEN]) +{ + const int num_random_bytes = 2; + const unsigned char non_sciatl_oui_bits = 0xc0u; + const unsigned char mac_addr_locally_managed = (1 << 1); + + if (!have_rfmac) { + pr_warning("rfmac not available on command line; " + "generating random MAC address\n"); + eth_random_addr(addr); + } + + else { + int i; + + /* Set the first byte to something that won't match a Scientific + * Atlanta OUI, is locally managed, and isn't a multicast + * address */ + addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed; + + /* Get some bytes of random address information */ + get_random_bytes(&addr[1], num_random_bytes); + + /* Copy over the NIC-specific bits of the RF MAC address */ + for (i = 1 + num_random_bytes; i < ETH_ALEN; i++) + addr[i] = rfmac[i]; + } +} diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c new file mode 100644 index 0000000..11c32fb --- /dev/null +++ b/arch/mips/powertv/reset.c @@ -0,0 +1,35 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/pm.h> + +#include <linux/io.h> +#include <asm/reboot.h> /* Not included by linux/reboot.h */ + +#include <asm/mach-powertv/asic_regs.h> +#include "reset.h" + +static void mips_machine_restart(char *command) +{ + writel(0x1, asic_reg_addr(watchdog)); +} + +void mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; +} diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h new file mode 100644 index 0000000..888fd09 --- /dev/null +++ b/arch/mips/powertv/reset.h @@ -0,0 +1,26 @@ +/* + * Definitions from powertv reset.c file + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#ifndef _POWERTV_POWERTV_RESET_H +#define _POWERTV_POWERTV_RESET_H +extern void mips_reboot_setup(void); +#endif diff --git a/arch/mips/powertv/time.c b/arch/mips/powertv/time.c new file mode 100644 index 0000000..f38b0d4 --- /dev/null +++ b/arch/mips/powertv/time.c @@ -0,0 +1,36 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Setting up the clock on the MIPS boards. + */ + +#include <linux/init.h> +#include <asm/mach-powertv/interrupts.h> +#include <asm/time.h> + +#include "powertv-clock.h" + +unsigned int get_c0_compare_int(void) +{ + return irq_mips_timer; +} + +void __init plat_time_init(void) +{ + powertv_clocksource_init(); +} diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c index 5d0983d..bba0cdf 100644 --- a/arch/mips/ralink/clk.c +++ b/arch/mips/ralink/clk.c @@ -26,7 +26,7 @@ void ralink_clk_add(const char *dev, unsigned long rate) struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); if (!clk) - panic("failed to add clock"); + panic("failed to add clock\n"); clk->cl.dev_id = dev; clk->cl.clk = clk; diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index a3ad56c..d217509 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -350,7 +350,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) name = "MT7620A"; soc_info->compatible = "ralink,mt7620a-soc"; } else { - panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1); + panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1); } rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index eccc552..ce38d11 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -21,7 +21,6 @@ #include <asm/reboot.h> #include <asm/bootinfo.h> #include <asm/addrspace.h> -#include <asm/prom.h> #include "common.h" @@ -109,7 +108,7 @@ static int __init plat_of_setup(void) strncpy(of_ids[1].compatible, "palmbus", len); if (of_platform_populate(NULL, of_ids, NULL, NULL)) - panic("failed to populate DT"); + panic("failed to populate DT\n"); /* make sure ithat the reset controller is setup early */ ralink_rst_init(); diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index bb82a82..ca7ee3a 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -276,7 +276,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) name = "RT5350"; soc_info->compatible = "ralink,rt5350-soc"; } else { - panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1); + panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); } id = __raw_readl(sysc + SYSC_REG_CHIP_ID); |