diff options
| author | Magnus Damm <damm@opensource.se> | 2010-05-11 09:35:55 (GMT) |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-05-13 08:36:34 (GMT) |
| commit | 59aa69d9c20b1ee15fa26aa6631b555aaef91323 (patch) | |
| tree | b95b2d6ad2c09ac6fef4d5b25245e27240f22f59 /arch/sh | |
| parent | 8249a3113094b826c5010d27c8cf07a395be2abc (diff) | |
| download | linux-fsl-qoriq-59aa69d9c20b1ee15fa26aa6631b555aaef91323.tar.xz | |
sh: switch sh7366 to clkdev
This patch converts the remaining sh7366 clocks
to use clkdev for lookup. The now unused name
and id from struct clk are also removed.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7366.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c index 4c3a5a5..7ce5bbc 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c @@ -37,8 +37,6 @@ /* Fixed 32 KHz root clock for RTC and Power Management purposes */ static struct clk r_clk = { - .name = "rclk", - .id = -1, .rate = 32768, }; @@ -47,8 +45,6 @@ static struct clk r_clk = { * from the platform code. */ struct clk extal_clk = { - .name = "extal", - .id = -1, .rate = 33333333, }; @@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = { }; static struct clk dll_clk = { - .name = "dll_clk", - .id = -1, .ops = &dll_clk_ops, .parent = &r_clk, .flags = CLK_ENABLE_ON_INIT, @@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = { }; static struct clk pll_clk = { - .name = "pll_clk", - .id = -1, .ops = &pll_clk_ops, .flags = CLK_ENABLE_ON_INIT, }; @@ -203,6 +195,12 @@ static struct clk mstp_clks[MSTP_NR] = { #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("rclk", &r_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("dll_clk", &dll_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + /* DIV4 clocks */ CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), |