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| author | Jeremy Fitzhardinge <jeremy@goop.org> | 2009-09-03 19:27:15 (GMT) |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-09-03 19:30:51 (GMT) |
| commit | 1ea0d14e480c245683927eecc03a70faf06e80c8 (patch) | |
| tree | cc43a6966799aa55c0f076c1217c557fb107563c /arch/x86/include/asm/system.h | |
| parent | 23386d63bbb3199cf247313ec088878d72debcfd (diff) | |
| download | linux-fsl-qoriq-1ea0d14e480c245683927eecc03a70faf06e80c8.tar.xz | |
x86/i386: Make sure stack-protector segment base is cache aligned
The Intel Optimization Reference Guide says:
In Intel Atom microarchitecture, the address generation unit
assumes that the segment base will be 0 by default. Non-zero
segment base will cause load and store operations to experience
a delay.
- If the segment base isn't aligned to a cache line
boundary, the max throughput of memory operations is
reduced to one [e]very 9 cycles.
[...]
Assembly/Compiler Coding Rule 15. (H impact, ML generality)
For Intel Atom processors, use segments with base set to 0
whenever possible; avoid non-zero segment base address that is
not aligned to cache line boundary at all cost.
We can't avoid having a non-zero base for the stack-protector
segment, but we can make it cache-aligned.
Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Cc: <stable@kernel.org>
LKML-Reference: <4AA01893.6000507@goop.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/system.h')
| -rw-r--r-- | arch/x86/include/asm/system.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h index 75c49c7..f08f973 100644 --- a/arch/x86/include/asm/system.h +++ b/arch/x86/include/asm/system.h @@ -31,7 +31,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, "movl %P[task_canary](%[next]), %%ebx\n\t" \ "movl %%ebx, "__percpu_arg([stack_canary])"\n\t" #define __switch_canary_oparam \ - , [stack_canary] "=m" (per_cpu_var(stack_canary)) + , [stack_canary] "=m" (per_cpu_var(stack_canary.canary)) #define __switch_canary_iparam \ , [task_canary] "i" (offsetof(struct task_struct, stack_canary)) #else /* CC_STACKPROTECTOR */ |