diff options
| author | Stefan Roese <sr@denx.de> | 2008-05-05 06:53:19 (GMT) |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2008-05-06 15:36:20 (GMT) |
| commit | a96df496ed1496f3e52a9b3c860cf967aa48adda (patch) | |
| tree | 6cf14e3dcc3888181bc7dd074dfed658726fbcbf /arch | |
| parent | 9185ef6787f1c8f1c06aa0cb3c7746fb4f101f50 (diff) | |
| download | linux-fsl-qoriq-a96df496ed1496f3e52a9b3c860cf967aa48adda.tar.xz | |
[POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core
The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure
fields to the TLB2 word. Those are:
Bit 11 12 13 14 15
WL1 IL1I IL1D IL2I IL2D
With these bits the cache (L1 and L2) can be configured in a more flexible
way, instruction- and data-cache independently now. The "old" I and W bits
are still available and setting these old bits will automically set these
new bits too (for backward compatibilty).
The current code does not clear these fields resulting in disabling the cache
by chance. This patch now makes sure that these new bits are cleared when
the TLB2 word is written.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/kernel/head_44x.S | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index b84ec6a..c2b9dc4 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -653,7 +653,14 @@ finish_tlb_load: rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */ rlwimi r12, r10, 0, 26, 31 /* Insert static perms */ - rlwinm r12, r12, 0, 20, 15 /* Clear U0-U3 */ + + /* + * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added + * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see + * include/asm-powerpc/pgtable-ppc32.h for details). + */ + rlwinm r12, r12, 0, 20, 10 + tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */ /* Done...restore registers and get out of here. |