diff options
| author | Ilia Mirkin <imirkin@alum.mit.edu> | 2013-09-08 00:33:43 (GMT) |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2013-11-08 05:37:40 (GMT) |
| commit | 515de6b27f96fb7ff58f34bda6e1be44a6f9e46d (patch) | |
| tree | 5bdc20d27efd2fd802470e90d13361d8408bb85e /drivers/gpu/drm/nouveau/dispnv04/hw.c | |
| parent | 8aa816b0bbcefa8517d7e10586d7dbb0ead3c4c1 (diff) | |
| download | linux-fsl-qoriq-515de6b27f96fb7ff58f34bda6e1be44a6f9e46d.tar.xz | |
drm/nv10/kms: add plane support for nv10-nv40
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/dispnv04/hw.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv04/hw.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c index 3d51ae9..aca76af 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c @@ -27,6 +27,7 @@ #include "hw.h" #include <subdev/bios/pll.h> +#include <subdev/fb.h> #include <subdev/clock.h> #include <subdev/timer.h> @@ -664,6 +665,7 @@ nv_load_state_ext(struct drm_device *dev, int head, struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_device *device = nv_device(drm->device); struct nouveau_timer *ptimer = nouveau_timer(device); + struct nouveau_fb *pfb = nouveau_fb(device); struct nv04_crtc_reg *regp = &state->crtc_reg[head]; uint32_t reg900; int i; @@ -680,10 +682,10 @@ nv_load_state_ext(struct drm_device *dev, int head, nv_wr32(device, NV_PVIDEO_INTR_EN, 0); nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); - nv_wr32(device, NV_PVIDEO_LIMIT(0), 0); //drm->fb_available_size - 1); - nv_wr32(device, NV_PVIDEO_LIMIT(1), 0); //drm->fb_available_size - 1); - nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), 0); //drm->fb_available_size - 1); - nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), 0); //drm->fb_available_size - 1); + nv_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1); + nv_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1); + nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1); + nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1); nv_wr32(device, NV_PBUS_POWERCTRL_2, 0); NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); |