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| author | Michael Hennerich <michael.hennerich@analog.com> | 2007-06-21 03:34:16 (GMT) |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-06-21 03:34:16 (GMT) |
| commit | 1c5d2265a82f8d3fa0471a60ca98072b3c53c299 (patch) | |
| tree | d0644427e9d700df594fa8dbcbb1338bfd982ac2 /include/asm-blackfin/mach-bf561 | |
| parent | f8ffe652a01506e85e2dd579c58e50a3ba391921 (diff) | |
| download | linux-fsl-qoriq-1c5d2265a82f8d3fa0471a60ca98072b3c53c299.tar.xz | |
Blackfin arch: add missing implementations SIC_IWR crosses several registers
SIC_IWR crosses several registers
- add missing implementations
- make sure SIC_IWR is SET after boot
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf561')
| -rw-r--r-- | include/asm-blackfin/mach-bf561/cdefBF561.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index b14f872..6e8b816 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -57,12 +57,14 @@ /* Writing to VR_CTL initiates a PLL relock sequence. */ static __inline__ void bfin_write_VR_CTL(unsigned int val) { - unsigned long flags, iwr; + unsigned long flags, iwr0, iwr1; /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SICA_IWR0); + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); /* Only allow PPL Wakeup) */ bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); bfin_write16(VR_CTL, val); __builtin_bfin_ssync(); @@ -70,7 +72,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) local_irq_save(flags); asm("IDLE;"); local_irq_restore(flags); - bfin_write32(SICA_IWR0, iwr); + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); + } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) |