diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-07-14 12:24:05 (GMT) |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-20 17:57:39 (GMT) |
| commit | 17099b1142f6c0359fca60a3464dea8fb30badea (patch) | |
| tree | 26b9f3955dca84ccab594a76680c2a71e166768a /include/asm-mips/bitops.h | |
| parent | ed203dadcd1373e80e95b04075e1eefc554a914b (diff) | |
| download | linux-fsl-qoriq-17099b1142f6c0359fca60a3464dea8fb30badea.tar.xz | |
[MIPS] Make support for weakly ordered LL/SC a config option.
None of weakly ordered processor supported in tree need this but it seems
like this could change ...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/bitops.h')
| -rw-r--r-- | include/asm-mips/bitops.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index d9e81af..148bc79 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -38,8 +38,8 @@ /* * clear_bit() doesn't provide any barrier for the compiler. */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +#define smp_mb__before_clear_bit() smp_llsc_mb() +#define smp_mb__after_clear_bit() smp_llsc_mb() /* * set_bit - Atomically set a bit in memory @@ -289,7 +289,7 @@ static inline int test_and_set_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -377,7 +377,7 @@ static inline int test_and_clear_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -445,7 +445,7 @@ static inline int test_and_change_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } |