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authorRalf Baechle <ralf@linux-mips.org>2007-06-20 21:27:10 (GMT)
committerRalf Baechle <ralf@linux-mips.org>2007-06-20 21:27:10 (GMT)
commit3b1d4ed5353af04d6aa20be2701727b9cdb2ac61 (patch)
treee4a3335c925abd933f1650e1ee4786e6bfad8f35 /include/asm-mips/mips-boards/atlasint.h
parent7c8545e98468c53809fc06788a3b9a34dff05240 (diff)
downloadlinux-fsl-qoriq-3b1d4ed5353af04d6aa20be2701727b9cdb2ac61.tar.xz
[MIPS] Don't drag a platform specific header into generic arch code.
For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mips-boards/atlasint.h')
-rw-r--r--include/asm-mips/mips-boards/atlasint.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
index 76add42..93ba1c1 100644
--- a/include/asm-mips/mips-boards/atlasint.h
+++ b/include/asm-mips/mips-boards/atlasint.h
@@ -28,11 +28,6 @@
#include <irq.h>
-/*
- * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
- */
-#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
-
/* CPU interrupt offsets */
#define MIPSCPU_INT_SW0 0
#define MIPSCPU_INT_SW1 1
@@ -42,7 +37,6 @@
#define MIPSCPU_INT_MB2 4
#define MIPSCPU_INT_MB3 5
#define MIPSCPU_INT_MB4 6
-#define MIPSCPU_INT_CPUCTR 7
/*
* Interrupts 8..39 are used for Atlas interrupt controller interrupts