diff options
| -rw-r--r-- | arch/mips/Kconfig | 72 | ||||
| -rw-r--r-- | arch/mips/kernel/traps.c | 15 | ||||
| -rw-r--r-- | include/asm-mips/cpu-features.h | 20 |
3 files changed, 61 insertions, 46 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 002845e..05663e5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -308,6 +308,7 @@ config MIPS_ATLAS select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL help This enables support for the MIPS Technologies Atlas evaluation board. @@ -336,6 +337,7 @@ config MIPS_MALTA select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MULTITHREADING help This enables support for the MIPS Technologies Malta evaluation board. @@ -1495,34 +1497,57 @@ config SIBYTE_DMA_PAGEOPS config CPU_HAS_PREFETCH bool -config MIPS_MT - bool "Enable MIPS MT" - depends on CPU_MIPS32_R2 - #depends on CPU_MIPS64_R2 # later ... - choice prompt "MIPS MT options" - depends on MIPS_MT + +config MIPS_MT_DISABLED + bool "Disable multithreading support." + help + Use this option if your workload can't take advantage of + MIPS hardware multithreading support. On systems that don't have + the option of an MT-enabled processor this option will be the only + option in this menu. config MIPS_MT_SMTC bool "SMTC: Use all TCs on all VPEs for SMP" + depends on CPU_MIPS32_R2 + #depends on CPU_MIPS64_R2 # once there is hardware ... + depends on SYS_SUPPORTS_MULTITHREADING select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_SRS + select MIPS_MT select SMP + help + This is a kernel model which is known a SMTC or lately has been + marketesed into SMVP. config MIPS_MT_SMP bool "Use 1 TC on each available VPE for SMP" + depends on SYS_SUPPORTS_MULTITHREADING + select CPU_MIPSR2_IRQ_VI + select CPU_MIPSR2_SRS + select MIPS_MT select SMP + help + This is a kernel model which is also known a VSMP or lately + has been marketesed into SMVP. config MIPS_VPE_LOADER bool "VPE loader support." - depends on MIPS_MT + depends on SYS_SUPPORTS_MULTITHREADING + select MIPS_MT help Includes a loader for loading an elf relocatable object onto another VPE and running it. endchoice +config MIPS_MT + bool + +config SYS_SUPPORTS_MULTITHREADING + bool + config MIPS_MT_FPAFF bool "Dynamic FPU affinity for FP-intensive threads" depends on MIPS_MT @@ -1579,32 +1604,23 @@ config CPU_HAS_LLSC config CPU_HAS_WB bool +# +# Vectored interrupt mode is an R2 feature +# config CPU_MIPSR2_IRQ_VI - bool "Vectored interrupt mode" - depends on CPU_MIPSR2 - help - Vectored interrupt mode allowing faster dispatching of interrupts. - The board support code needs to be written to take advantage of this - mode. Compatibility code is included to allow the kernel to run on - a CPU that does not support vectored interrupts. It's safe to - say Y here. + bool +# +# Extended interrupt mode is an R2 feature +# config CPU_MIPSR2_IRQ_EI - bool "External interrupt controller mode" - depends on CPU_MIPSR2 - help - Extended interrupt mode takes advantage of an external interrupt - controller to allow fast dispatching from many possible interrupt - sources. Say N unless you know that external interrupt support is - required. + bool +# +# Shadow registers are an R2 feature +# config CPU_MIPSR2_SRS - bool "Make shadow set registers available for interrupt handlers" - depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI - help - Allow the kernel to use shadow register sets for fast interrupts. - Interrupt handlers must be specially written to use shadow sets. - Say N unless you know that shadow register set upport is needed. + bool config CPU_HAS_SYNC bool diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ad16ece..6797193 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1050,7 +1050,7 @@ void *set_except_vector(int n, void *addr) return (void *)old_handler; } -#ifdef CONFIG_CPU_MIPSR2 +#ifdef CONFIG_CPU_MIPSR2_SRS /* * MIPSR2 shadow register set allocation * FIXME: SMP... @@ -1069,11 +1069,9 @@ static struct shadow_registers { static void mips_srs_init(void) { -#ifdef CONFIG_CPU_MIPSR2_SRS shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; printk(KERN_INFO "%d MIPSR2 register sets available\n", shadow_registers.sr_supported); -#endif shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ } @@ -1198,7 +1196,14 @@ void *set_vi_handler(int n, void *addr) { return set_vi_srs_handler(n, addr, 0); } -#endif + +#else + +static inline void mips_srs_init(void) +{ +} + +#endif /* CONFIG_CPU_MIPSR2_SRS */ /* * This is used by native signal handling @@ -1388,9 +1393,7 @@ void __init trap_init(void) else ebase = CAC_BASE; -#ifdef CONFIG_CPU_MIPSR2 mips_srs_init(); -#endif per_cpu_trap_init(); diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 881ce1f..44285a9 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -187,19 +187,15 @@ # endif #endif -#ifdef CONFIG_CPU_MIPSR2 -# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) -# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) -# else -# define cpu_has_vint 0 -# endif -# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) -# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) -# else -# define cpu_has_veic 0 -# endif -#else +#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) +# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) +#elif !defined(cpu_has_vint) # define cpu_has_vint 0 +#endif + +#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) +# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) +#elif !defined(cpu_has_veic) # define cpu_has_veic 0 #endif |