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-rw-r--r--Documentation/devicetree/bindings/net/can/fsl-flexcan.txt4
-rw-r--r--arch/arm/boot/dts/ls1021a-qds.dts8
-rwxr-xr-xarch/arm/boot/dts/ls1021a-twr.dts122
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi102
-rw-r--r--arch/arm/configs/ls1021a_defconfig1
-rw-r--r--arch/arm/mach-imx/mach-ls1021a.c23
-rw-r--r--arch/arm/mach-imx/pm-ls1.c118
-rw-r--r--arch/arm/mach-imx/sleep-ls1.S23
-rw-r--r--drivers/crypto/caam/ctrl.c31
-rw-r--r--drivers/mmc/host/sdhci-pltfm.c3
-rw-r--r--drivers/mmc/host/sdhci.c94
-rw-r--r--drivers/net/can/Kconfig12
-rw-r--r--drivers/net/can/flexcan.c335
-rw-r--r--drivers/net/ethernet/freescale/gianfar.h9
-rw-r--r--drivers/net/wan/fsl_ucc_hdlc.c239
-rw-r--r--drivers/pci/host/pci-layerscape.c80
-rw-r--r--include/linux/mmc/sdhci.h3
-rw-r--r--include/sound/pcm.h2
-rw-r--r--sound/core/pcm_lib.c38
-rw-r--r--sound/soc/fsl/fsl_sai.c13
20 files changed, 672 insertions, 588 deletions
diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
index 56d6cc3..0d5e668 100644
--- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
@@ -18,6 +18,10 @@ Optional properties:
- xceiver-supply: Regulator that powers the CAN transceiver
+- little-endian: If the FlexCAN IP on this SoC is little-endian, use
+ this property. By default it is assumed that the IP
+ is big-endian
+
Example:
can@1c000 {
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 93cda05..c029e65 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -436,6 +436,14 @@
status = "okay";
};
+&can2 {
+ status = "disabled";
+};
+
+&can3 {
+ status = "disabled";
+};
+
&sai2 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index 6486178..db1c6b6 100755
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -58,6 +58,22 @@
};
};
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "disabled";
+};
+
+&can3 {
+ status = "disabled";
+};
+
&dcu0 {
display = <&display>;
status = "okay";
@@ -112,8 +128,24 @@
status = "okay";
};
+&ftm0 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220@41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
};
&i2c1 {
@@ -157,52 +189,69 @@
device-width = <1>;
partition@0 {
- /* 128KB for rcw */
- reg = <0x00000000 0x0020000>;
+ /* 128KB for bank0 RCW */
+ reg = <0x00000000 0x00020000>;
label = "NOR bank0 RCW Image";
};
- partition@20000 {
- /* 1MB for DTB */
- reg = <0x00020000 0x00100000>;
- label = "NOR DTB Image";
+ partition@100000 {
+ /* 1MB for bank0 u-boot Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NOR bank0 u-boot Image";
};
- partition@120000 {
- /* 8 MB for Linux Kernel Image */
- reg = <0x00120000 0x00800000>;
- label = "NOR Linux Kernel Image";
+ partition@200000 {
+ /* 1MB for bank0 DTB */
+ reg = <0x00200000 0x00100000>;
+ label = "NOR bank0 DTB Image";
};
- partition@920000 {
- /* 56MB for Ramdisk Root File System */
- reg = <0x00920000 0x03600000>;
- label = "NOR Ramdisk Root File System Image";
+ partition@300000 {
+ /* 7MB for bank0 Linux Kernel */
+ reg = <0x00300000 0x00700000>;
+ label = "NOR bank0 Linux Kernel Image";
};
- partition@3f80000 {
- /* 512KB for bank4 u-boot Image */
- reg = <0x03f80000 0x80000>;
- label = "NOR bank4 u-boot Image";
+ partition@a00000 {
+ /* 54MB for bank0 Ramdisk Root File System */
+ reg = <0x00a00000 0x03600000>;
+ label = "NOR bank0 Ramdisk Root File System Image";
};
partition@4000000 {
- /* 128KB for bank4 RCW Image */
- reg = <0x04000000 0x20000>;
+ /* 128KB for bank4 RCW */
+ reg = <0x04000000 0x00020000>;
label = "NOR bank4 RCW Image";
};
- partition@4020000 {
- /* 63MB JFFS2 ROOT File System Image */
- reg = <0x04020000 0x3f00000>;
- label = "NOR JFFS2 ROOT File System Image";
+ partition@4100000 {
+ /* 1MB for bank4 u-boot Image */
+ reg = <0x04100000 0x00100000>;
+ label = "NOR bank4 u-boot Image";
};
- partition@7f80000 {
- /* 512KB for bank0 u-boot Image */
- reg = <0x07f80000 0x80000>;
- label = "NOR bank0 u-boot Image";
+ partition@4200000 {
+ /* 1MB for bank4 DTB */
+ reg = <0x04200000 0x00100000>;
+ label = "NOR bank4 DTB Image";
+ };
+
+ partition@4300000 {
+ /* 7MB for bank4 Linux Kernel */
+ reg = <0x04300000 0x00700000>;
+ label = "NOR bank4 Linux Kernel Image";
};
+
+ partition@4a00000 {
+ /* 54MB for bank4 Ramdisk Root File System */
+ reg = <0x04a00000 0x03600000>;
+ label = "NOR bank4 Ramdisk Root File System Image";
+ };
+ };
+
+ cpld@2,0 {
+ compatible = "fsl,ls1021atwr-cpld";
+ reg = <0x2 0x0 0x100>;
};
};
@@ -271,6 +320,21 @@
};
};
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: compatible@0 {
+ compatible = "st,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
&sai1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c98b794..eddd576 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -257,6 +257,7 @@
clocks = <&platform_clk 1>;
spi-num-chipselects = <5>;
big-endian;
+ tcfq-mode;
status = "disabled";
};
@@ -555,7 +556,6 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 47>,
<&edma0 1 46>;
- big-endian-regs;
status = "disabled";
};
@@ -568,7 +568,6 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 45>,
<&edma0 1 44>;
- big-endian-regs;
status = "disabled";
};
@@ -618,22 +617,28 @@
fsl,magic-packet;
fsl,wake-on-filer;
sleep = <&rcpm 0x80000000 0x0>;
- fsl,num_rx_queues = <0x1>;
- fsl,num_tx_queues = <0x1>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x2d10000 0x0 0x8000>;
- fsl,rx-bit-map = <0xff>;
- fsl,tx-bit-map = <0xff>;
+ queue-group@2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d10000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};
+ queue-group@2d14000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
enet1: ethernet@2d50000 {
@@ -644,22 +649,28 @@
interrupt-parent = <&gic>;
model = "eTSEC";
fsl,dma-endian-le;
- fsl,num_rx_queues = <0x1>;
- fsl,num_tx_queues = <0x1>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x2d50000 0x0 0x8000>;
- fsl,rx-bit-map = <0xff>;
- fsl,tx-bit-map = <0xff>;
+ queue-group@2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d50000 0x0 0x1000>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
};
+ queue-group@2d54000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d54000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
enet2: ethernet@2d90000 {
@@ -670,65 +681,64 @@
interrupt-parent = <&gic>;
model = "eTSEC";
fsl,dma-endian-le;
- fsl,num_rx_queues = <0x1>;
- fsl,num_tx_queues = <0x1>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x2d90000 0x0 0x8000>;
- fsl,rx-bit-map = <0xff>;
- fsl,tx-bit-map = <0xff>;
+ queue-group@2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d90000 0x0 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ queue-group@2d94000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d94000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
can0: can@2a70000 {
- compatible = "fsl,ls1021a-flexcan";
+ compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a70000 0x0 0x1000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- clock-frequency = <150000000>;
- clock-names = "per";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ clock-names = "ipg", "per";
little-endian;
- status = "disabled";
};
can1: can@2a80000 {
- compatible = "fsl,ls1021a-flexcan";
+ compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a80000 0x0 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- clock-frequency = <150000000>;
- clock-names = "per";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ clock-names = "ipg", "per";
little-endian;
- status = "disabled";
};
can2: can@2a90000 {
- compatible = "fsl,ls1021a-flexcan";
+ compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a90000 0x0 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- clock-frequency = <150000000>;
- clock-names = "per";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ clock-names = "ipg", "per";
little-endian;
- status = "disabled";
};
can3: can@2aa0000 {
- compatible = "fsl,ls1021a-flexcan";
+ compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2aa0000 0x0 0x1000>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- clock-frequency = <150000000>;
- clock-names = "per";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ clock-names = "ipg", "per";
little-endian;
- status = "disabled";
};
usb@8600000 {
diff --git a/arch/arm/configs/ls1021a_defconfig b/arch/arm/configs/ls1021a_defconfig
index 12f5f84..8721e23 100644
--- a/arch/arm/configs/ls1021a_defconfig
+++ b/arch/arm/configs/ls1021a_defconfig
@@ -104,6 +104,7 @@ CONFIG_SATA_SIL24=y
CONFIG_NETDEVICES=y
CONFIG_GIANFAR=y
CONFIG_E1000E=y
+CONFIG_AT803X_PHY=y
CONFIG_VITESSE_PHY=y
CONFIG_BROADCOM_PHY=y
CONFIG_REALTEK_PHY=y
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
index 3692dd0..dbb0256 100644
--- a/arch/arm/mach-imx/mach-ls1021a.c
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -10,13 +10,36 @@
#include <linux/clk-provider.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
+#include <linux/dma-mapping.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "common.h"
+static int ls1021a_platform_notifier(struct notifier_block *nb,
+ unsigned long event, void *__dev)
+{
+ struct device *dev = __dev;
+
+ if (event != BUS_NOTIFY_ADD_DEVICE)
+ return NOTIFY_DONE;
+
+ if (of_device_is_compatible(dev->of_node, "fsl,etsec2"))
+ set_dma_ops(dev, &arm_coherent_dma_ops);
+ else if (of_property_read_bool(dev->of_node, "dma-coherent"))
+ set_dma_ops(dev, &arm_coherent_dma_ops);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block ls1021a_platform_nb = {
+ .notifier_call = ls1021a_platform_notifier,
+};
+
static void __init ls1021a_init_machine(void)
{
+ bus_register_notifier(&platform_bus_type, &ls1021a_platform_nb);
+
mxc_arch_reset_init_dt();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c
index b8bfdb5..d1af079 100644
--- a/arch/arm/mach-imx/pm-ls1.c
+++ b/arch/arm/mach-imx/pm-ls1.c
@@ -48,6 +48,8 @@
#define CCSR_SCFG_PMCINTSR 0x168
#define CCSR_SCFG_SPARECR2 0x504
#define CCSR_SCFG_SPARECR3 0x508
+#define CCSR_SCFG_CLUSTERPMCR 0x904
+#define CCSR_SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
#define CCSR_DCFG_CRSTSR 0x400
#define CCSR_DCFG_CRSTSR_VAL 0x00000008
@@ -65,6 +67,9 @@
#define CCSR_RCPM_IPPDEXPCR1_LPUART 0x40000000
#define CCSR_RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000
#define CCSR_RCPM_IPPDEXPCR1_OCRAM1 0x10000000
+#define CCSR_RCPM_NFIQOUTR 0x15c
+#define CCSR_RCPM_NIRQOUTR 0x16c
+#define CCSR_RCPM_DSIMSKR 0x18c
#define QIXIS_CTL_SYS 0x5
#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
@@ -101,11 +106,19 @@ static struct ls1_pm_baseaddr ls1_pm_base;
static unsigned int sleep_modes;
static suspend_state_t ls1_pm_state;
-static void ls1_pm_iomap(void)
+static int ls1_pm_iomap(int deepsleep)
{
struct device_node *np;
void *base;
+ np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-scfg");
+ base = of_iomap(np, 0);
+ BUG_ON(!base);
+ ls1_pm_base.scfg = base;
+
+ if (!deepsleep)
+ return 0;
+
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcsr-epu");
base = of_iomap(np, 0);
BUG_ON(!base);
@@ -119,41 +132,59 @@ static void ls1_pm_iomap(void)
BUG_ON(!base);
ls1_pm_base.dcsr_rcpm2 = base;
- np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-scfg");
- base = of_iomap(np, 0);
- BUG_ON(!base);
- ls1_pm_base.scfg = base;
-
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
base = of_iomap(np, 0);
BUG_ON(!base);
ls1_pm_base.dcfg = base;
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021aqds-fpga");
- base = of_iomap(np, 0);
- BUG_ON(!base);
- ls1_pm_base.fpga = base;
+ if (np) {
+ base = of_iomap(np, 0);
+ BUG_ON(!base);
+ ls1_pm_base.fpga = base;
+ } else {
+ np = of_find_compatible_node(NULL, NULL,
+ "fsl,ls1021atwr-cpld");
+ if (!np) {
+ pr_err("%s: Can not find cpld/fpga node.\n", __func__);
+ return -ENODEV;
+ }
+ }
base = ioremap(SRAM_CODE_BASE_PHY, PAGE_SIZE);
BUG_ON(!base);
ls1_pm_base.sram = base;
+
+ return 0;
}
-static void ls1_pm_uniomap(void)
+static void ls1_pm_uniomap(int deepsleep)
{
+ iounmap(ls1_pm_base.scfg);
+ if (!deepsleep)
+ return;
+
iounmap(ls1_pm_base.epu);
iounmap(ls1_pm_base.dcsr_rcpm1);
iounmap(ls1_pm_base.dcsr_rcpm2);
- iounmap(ls1_pm_base.scfg);
iounmap(ls1_pm_base.dcfg);
- iounmap(ls1_pm_base.fpga);
+
+ if (ls1_pm_base.fpga)
+ iounmap(ls1_pm_base.fpga);
+
iounmap(ls1_pm_base.sram);
}
-static void ls1_setup_pmc_int(void)
+static void ls1_deepsleep_irq(void)
{
u32 pmcintecr;
+ /* mask interrupts from GIC */
+ iowrite32be(0x0ffffffff, ls1_pm_base.rcpm + CCSR_RCPM_NFIQOUTR);
+ iowrite32be(0x0ffffffff, ls1_pm_base.rcpm + CCSR_RCPM_NIRQOUTR);
+ /* mask deep sleep wake-up interrupts during deep sleep entry */
+ iowrite32be(0x0ffffffff, ls1_pm_base.rcpm + CCSR_RCPM_DSIMSKR);
+
pmcintecr = 0;
if (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_ETSEC)
pmcintecr |= CCSR_SCFG_PMCINTECR_ETSECRXG0 |
@@ -173,11 +204,12 @@ static void ls1_setup_pmc_int(void)
/* always set external IRQ pins as wakeup source */
pmcintecr |= CCSR_SCFG_PMCINTECR_IRQ0 | CCSR_SCFG_PMCINTECR_IRQ1;
- /* enable wakeup interrupt during deep sleep */
- iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);
iowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTLECR);
/* clear PMC interrupt status */
iowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR);
+ /* enable wakeup interrupt during deep sleep */
+ iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);
+
}
static void ls1_clear_pmc_int(void)
@@ -299,15 +331,18 @@ static void ls1_enter_deepsleep(void)
/* setup the registers of the EPU FSM for deep sleep */
ls1_fsm_setup();
- /* connect the EVENT button to IRQ in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
- tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
- tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
- iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
-
- /* enable deep sleep signals in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
- iowrite8(tmp | QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ if (ls1_pm_base.fpga) {
+ /* connect the EVENT button to IRQ in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
+
+ /* enable deep sleep signals in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp | QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ }
/* enable Warm Device Reset */
ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
@@ -319,7 +354,7 @@ static void ls1_enter_deepsleep(void)
/* copy the last stage code to sram */
ls1_copy_sram_code();
- ls1_setup_pmc_int();
+ ls1_deepsleep_irq();
cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
@@ -329,9 +364,12 @@ static void ls1_enter_deepsleep(void)
ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
CCSR_SCFG_DPSLPCR_VAL, 0);
- /* disable deep sleep signals in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
- iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ if (ls1_pm_base.fpga) {
+ /* disable deep sleep signals in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ }
}
static void ls1_set_power_except(struct device *dev, int on)
@@ -367,11 +405,26 @@ static void ls1_set_wakeup_device(struct device *dev, void *enable)
ls1_set_power_except(dev, *((int *)enable));
}
+/* enable cluster to enter the PCL10 state */
+void ls1_set_clusterpm(int enable)
+{
+ u32 val;
+
+ if (enable)
+ val = CCSR_SCFG_CLUSTERPMCR_WFIL2EN;
+ else
+ val = 0;
+
+ BUG_ON(!ls1_pm_base.scfg);
+ iowrite32be(val, ls1_pm_base.scfg + CCSR_SCFG_CLUSTERPMCR);
+}
+
static int ls1_suspend_enter(suspend_state_t state)
{
int ret = 0;
ls1_set_powerdown();
+ ls1_set_clusterpm(1);
switch (state) {
case PM_SUSPEND_STANDBY:
@@ -391,6 +444,7 @@ static int ls1_suspend_enter(suspend_state_t state)
ret = -EINVAL;
}
+ ls1_set_clusterpm(0);
return ret;
}
@@ -414,7 +468,9 @@ static int ls1_suspend_begin(suspend_state_t state)
dpm_for_each_dev(NULL, ls1_set_wakeup_device);
if (ls1_pm_state == PM_SUSPEND_MEM)
- ls1_pm_iomap();
+ return ls1_pm_iomap(1);
+ else if (ls1_pm_state == PM_SUSPEND_STANDBY)
+ return ls1_pm_iomap(0);
return 0;
}
@@ -422,7 +478,9 @@ static int ls1_suspend_begin(suspend_state_t state)
static void ls1_suspend_end(void)
{
if (ls1_pm_state == PM_SUSPEND_MEM)
- ls1_pm_uniomap();
+ ls1_pm_uniomap(1);
+ else if (ls1_pm_state == PM_SUSPEND_STANDBY)
+ ls1_pm_uniomap(0);
}
static const struct platform_suspend_ops ls1_suspend_ops = {
diff --git a/arch/arm/mach-imx/sleep-ls1.S b/arch/arm/mach-imx/sleep-ls1.S
index b8d7f1a..f8fd8a4 100644
--- a/arch/arm/mach-imx/sleep-ls1.S
+++ b/arch/arm/mach-imx/sleep-ls1.S
@@ -25,6 +25,10 @@
#define DCSR_EPU_EPECR0 0x300
#define DCSR_EPU_EPECR15 0x33c
+#define CCSR_GIC_BASE 0x1400000
+#define CCSR_GICD_CTLR 0x1000
+#define CCSR_GICC_CTLR 0x2000
+
/* for big endian registers */
.macro ls1_set_bits, addr, value
ldr r4, \addr
@@ -85,6 +89,13 @@ ENTRY(ls1_start_fsm)
ls1_delay #2000
+ mov r7, #0
+ ldr r8, ls1_ccsr_gicd_ctlr
+ str r7, [r8]
+ ldr r9, ls1_ccsr_gicc_ctlr
+ str r7, [r9]
+ dsb
+
/* Enable all EPU Counters */
ls1_set_bits ls1_dcsr_epu_epgcr_addr, ls1_dcsr_epu_epgcr_val
@@ -92,8 +103,10 @@ ENTRY(ls1_start_fsm)
ls1_set_bits ls1_dcsr_epu_epecr15, ls1_dcsr_epu_epecr15_val
/* Enter WFI mode, and EPU FSM will start */
-20: wfi
- b 20b
+ isb
+ wfi
+ nop
+20: b 20b
ls1_ccsr_scfg_hrstcr_addr:
.word CCSR_SCFG_BASE + CCSR_SCFG_HRSTCR
@@ -120,6 +133,12 @@ ls1_dcsr_epu_epecr15:
ls1_dcsr_epu_epecr15_val:
.word 0x90000004
+ls1_ccsr_gicd_ctlr:
+ .word CCSR_GIC_BASE + CCSR_GICD_CTLR
+
+ls1_ccsr_gicc_ctlr:
+ .word CCSR_GIC_BASE + CCSR_GICC_CTLR
+
ENTRY(ls1_sram_code_size)
.word . - ls1_start_fsm
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 321deb0..0359c71 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -388,14 +388,14 @@ static void kick_trng(struct device *dev, int ent_delay)
int caam_get_era(void)
{
struct device_node *caam_node;
- for_each_compatible_node(caam_node, NULL, "fsl,sec-v4.0") {
- const uint32_t *prop = (uint32_t *)of_get_property(caam_node,
- "fsl,sec-era",
- NULL);
- return prop ? *prop : -ENOTSUPP;
- }
+ int ret;
+ u32 prop;
+
+ caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
+ of_node_put(caam_node);
- return -ENOTSUPP;
+ return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
}
EXPORT_SYMBOL(caam_get_era);
@@ -488,7 +488,7 @@ static int caam_probe(struct platform_device *pdev)
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
- u32 scfgr, comp_params;
+ u32 mcr, scfgr, comp_params;
int pg_size;
int BLOCK_OFFSET = 0;
@@ -537,8 +537,11 @@ static int caam_probe(struct platform_device *pdev)
* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
* long pointers in master configuration register
*/
- setbits32(&ctrl->mcr, MCFGR_WDENABLE |
- (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
+ mcr = rd_reg32(&ctrl->mcr);
+ mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT) |
+ MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
+ MCFGR_LONG_PTR : 0);
+ wr_reg32(&ctrl->mcr, mcr);
/*
* Read the Compile Time paramters and SCFGR to determine
@@ -817,6 +820,7 @@ static int caam_resume(struct device *dev)
struct caam_drv_private *caam_priv;
struct caam_ctrl __iomem *ctrl;
struct caam_queue_if __iomem *qi;
+ u32 mcr;
int ret;
caam_priv = dev_get_drvdata(dev);
@@ -826,8 +830,11 @@ static int caam_resume(struct device *dev)
* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
* long pointers in master configuration register
*/
- setbits32(&ctrl->mcr, MCFGR_WDENABLE |
- (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
+ mcr = rd_reg32(&ctrl->mcr);
+ mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT) |
+ MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
+ MCFGR_LONG_PTR : 0);
+ wr_reg32(&ctrl->mcr, mcr);
/* Enable QI interface of SEC */
if (caam_priv->qi_present)
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index 5c7c168..c1a37a6 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -112,7 +112,8 @@ void sdhci_get_of_property(struct platform_device *pdev)
of_device_is_compatible(np, "fsl,p5020-esdhc") ||
of_device_is_compatible(np, "fsl,p4080-esdhc") ||
of_device_is_compatible(np, "fsl,t1040-esdhc") ||
- of_device_is_compatible(np, "fsl,p1020-esdhc"))
+ of_device_is_compatible(np, "fsl,p1020-esdhc") ||
+ of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
clk = of_get_property(np, "clock-frequency", &size);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 7a0baef..8f0e396 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -132,27 +132,6 @@ static void sdhci_dumpregs(struct sdhci_host *host)
* *
\*****************************************************************************/
-static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
-{
- u32 ier;
-
- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
- ier &= ~clear;
- ier |= set;
- sdhci_writel(host, ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
-}
-
-static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
-{
- sdhci_clear_set_irqs(host, 0, irqs);
-}
-
-static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
-{
- sdhci_clear_set_irqs(host, irqs, 0);
-}
-
static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
{
u32 present, irqs;
@@ -166,9 +145,12 @@ static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
if (enable)
- sdhci_unmask_irqs(host, irqs);
+ host->ier |= irqs;
else
- sdhci_mask_irqs(host, irqs);
+ host->ier &= ~irqs;
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
static void sdhci_enable_card_detection(struct sdhci_host *host)
@@ -184,7 +166,6 @@ static void sdhci_disable_card_detection(struct sdhci_host *host)
void sdhci_reset(struct sdhci_host *host, u8 mask)
{
unsigned long timeout;
- u32 uninitialized_var(ier);
if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
@@ -192,9 +173,6 @@ void sdhci_reset(struct sdhci_host *host, u8 mask)
return;
}
- if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
-
if (host->ops->platform_reset_enter)
host->ops->platform_reset_enter(host, mask);
@@ -225,8 +203,10 @@ void sdhci_reset(struct sdhci_host *host, u8 mask)
if (host->ops->platform_reset_exit)
host->ops->platform_reset_exit(host, mask);
- if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
- sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
+ if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) {
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
@@ -238,25 +218,26 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
static void sdhci_init(struct sdhci_host *host, int soft)
{
- u32 pltm_irq = 0, irq = 0;
+ u32 pltm_irq = 0;
if (soft)
sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
else
sdhci_reset(host, SDHCI_RESET_ALL);
- irq = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
+ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
if (pltm_irq)
- irq |= pltm_irq;
+ host->ier |= pltm_irq;
if (host->flags & SDHCI_AUTO_CMD12)
- irq |= SDHCI_INT_ACMD12ERR;
+ host->ier |= SDHCI_INT_ACMD12ERR;
- sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, irq);
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
if (soft) {
/* force clock reconfiguration */
@@ -731,9 +712,12 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
if (host->flags & SDHCI_REQ_USE_DMA)
- sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
+ host->ier = (host->ier & ~pio_irqs) | dma_irqs;
else
- sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
+ host->ier = (host->ier & ~dma_irqs) | pio_irqs;
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
@@ -1733,9 +1717,12 @@ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
goto out;
if (enable)
- sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
+ host->ier |= SDHCI_INT_CARD_INT;
else
- sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
+ host->ier &= ~SDHCI_INT_CARD_INT;
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
out:
mmiowb();
}
@@ -1868,7 +1855,6 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct sdhci_host *host;
u16 ctrl;
- u32 ier;
int tuning_loop_counter = MAX_TUNING_LOOP;
unsigned long timeout;
int err = 0;
@@ -1916,8 +1902,8 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
* to make sure we don't hit a controller bug, we _only_
* enable Buffer Read Ready interrupt here.
*/
- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
- sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
/*
* Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
@@ -2052,7 +2038,8 @@ out:
if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
err = 0;
- sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
spin_unlock(&host->lock);
enable_irq(host->irq);
sdhci_runtime_pm_put(host);
@@ -2480,10 +2467,11 @@ again:
* More testing are needed here to ensure it works for other
* platforms though.
*/
- sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
- SDHCI_INT_CARD_REMOVE);
- sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
- SDHCI_INT_CARD_INSERT);
+ host->ier &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
+ host->ier |= present ? SDHCI_INT_CARD_REMOVE :
+ SDHCI_INT_CARD_INSERT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
@@ -2609,7 +2597,9 @@ int sdhci_suspend_host(struct sdhci_host *host)
}
if (!device_may_wakeup(mmc_dev(host->mmc))) {
- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
+ host->ier = 0;
+ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
free_irq(host->irq, host);
} else {
sdhci_enable_irq_wakeups(host);
@@ -2708,7 +2698,9 @@ int sdhci_runtime_suspend_host(struct sdhci_host *host)
}
spin_lock_irqsave(&host->lock, flags);
- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
+ host->ier = 0;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
spin_unlock_irqrestore(&host->lock, flags);
synchronize_irq(host->irq);
@@ -3307,7 +3299,8 @@ int sdhci_add_host(struct sdhci_host *host)
#ifdef SDHCI_USE_LEDS_CLASS
reset:
sdhci_reset(host, SDHCI_RESET_ALL);
- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
+ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
free_irq(host->irq, host);
#endif
untasklet:
@@ -3350,7 +3343,8 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
if (!dead)
sdhci_reset(host, SDHCI_RESET_ALL);
- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
+ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
+ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
free_irq(host->irq, host);
del_timer_sync(&host->timer);
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 5115a36..3c06947 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -108,18 +108,6 @@ config CAN_FLEXCAN
---help---
Say Y here if you want to support for Freescale FlexCAN.
-config CAN_FLEXCAN_RX_FIFO_EN
- tristate "Support for RX FIFO mode in Freescale FLEXCAN based chips"
- depends on CAN_FLEXCAN
- ---help---
- Say Y here if your Freescale SoC's FlexCAN module has support for RX FIFO MODE.
-
-config CAN_FLEXCAN_ERRATA_ERR005829
- tristate "ERRATA_ERR005829 applicable to certain variants of Freescale FLEXCAN based chips"
- depends on CAN_FLEXCAN
- ---help---
- Say Y here if your Freescale SoC's FlexCAN module needs s/w workaround for ERRATA ERR005829.
-
config PCH_CAN
tristate "Intel EG20T PCH CAN controller"
depends on PCI
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 805a923..b24352f 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -59,7 +59,6 @@
#define FLEXCAN_MCR_WAK_SRC BIT(19)
#define FLEXCAN_MCR_DOZE BIT(18)
#define FLEXCAN_MCR_SRX_DIS BIT(17)
-#define FLEXCAN_MCR_SRX_EN ~(BIT(17))
#define FLEXCAN_MCR_BCC BIT(16)
#define FLEXCAN_MCR_LPRIO_EN BIT(13)
#define FLEXCAN_MCR_AEN BIT(12)
@@ -147,25 +146,19 @@
FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
/* FLEXCAN interrupt flag register (IFLAG) bits */
-#ifdef CONFIG_CAN_FLEXCAN_ERRATA_ERR005829
/* Errata ERR005829 step7: Reserve first valid MB */
#define FLEXCAN_TX_BUF_RESERVED 8
#define FLEXCAN_TX_BUF_ID 9
-#else
-#define FLEXCAN_TX_BUF_ID 8
-#endif
#define FLEXCAN_IFLAG_BUF(x) BIT(x)
#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
#define FLEXCAN_IFLAG_DEFAULT \
(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
-#else
-#define FLEXCAN_IFLAG_DEFAULT \
- (FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
-#endif
+#define FLEXCAN_IFLAG_DEFAULT_RX_MB_MODE \
+ (FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
+#define FLEXCAN_IFLAG_RX_MB_RXMASK ((1 << FLEXCAN_TX_BUF_RESERVED) - 1)
/* FLEXCAN message buffers */
#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
@@ -208,6 +201,8 @@
#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
#define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */
+#define FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT \
+ BIT(4) /* No RX FIFO mode support */
/* Structure of the message buffer */
struct flexcan_mb {
@@ -263,6 +258,7 @@ struct flexcan_priv {
void __iomem *base;
u32 reg_esr;
u32 reg_ctrl_default;
+ u32 rx_msg_buf;
struct clk *clk_ipg;
struct clk *clk_per;
@@ -271,8 +267,8 @@ struct flexcan_priv {
struct regulator *reg_xceiver;
/* Read and Write APIs */
- u32 (*read) (void __iomem *addr);
- void (*write) (u32 val, void __iomem *addr);
+ u32 (*read)(void __iomem *addr);
+ void (*write)(u32 val, void __iomem *addr);
};
static struct flexcan_devtype_data fsl_p1010_devtype_data = {
@@ -287,7 +283,18 @@ static struct flexcan_devtype_data fsl_vf610_devtype_data = {
.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
};
+/* LS1021A-Rev1 has a broken RX-FIFO support. So only legacy RX message-buffers
+ * work here.
+ */
static struct flexcan_devtype_data fsl_ls1021a_devtype_data = {
+ .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES |
+ FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT,
+};
+
+/* LS1021A-Rev2 has functional RX-FIFO mode, so no need to fall back to
+ * the legacy mode.
+ */
+static struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
.features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
};
@@ -303,8 +310,7 @@ static const struct can_bittiming_const flexcan_bittiming_const = {
.brp_inc = 1,
};
-/*
- * FlexCAN module is essentially modelled as a little-endian IP in most
+/* FlexCAN module is essentially modelled as a little-endian IP in most
* SoCs, i.e the registers as well as the message buffer areas are
* implemented in a little-endian fashion.
*
@@ -315,7 +321,7 @@ static const struct can_bittiming_const flexcan_bittiming_const = {
* In addition, the FlexCAN module can be found on SoCs having ARM or
* PPC cores. So, we need to abstract off the register read/write
* functions, ensuring that these cater to all the combinations of module
- * endianess and underlying CPU endianess.
+ * endianness and underlying CPU endianness.
*/
static inline u32 flexcan_read_le(void __iomem *addr)
{
@@ -425,7 +431,6 @@ static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
reg = priv->read(&regs->mcr);
reg &= ~FLEXCAN_MCR_HALT;
- reg &= ~FLEXCAN_MCR_FRZ;
priv->write(reg, &regs->mcr);
while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
@@ -452,7 +457,6 @@ static int flexcan_chip_softreset(struct flexcan_priv *priv)
return 0;
}
-
static int __flexcan_get_berr_counter(const struct net_device *dev,
struct can_berr_counter *bec)
{
@@ -525,7 +529,7 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
priv->write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
priv->write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
-#ifdef CONFIG_CAN_FLEXCAN_ERRATA_ERR005829
+
/* Errata ERR005829 step8:
* Write twice INACTIVE(0x8) code to first MB.
*/
@@ -533,11 +537,6 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
&regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
-#endif
-
-#ifndef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
- netdev_info(dev, "XMIT done\n");
-#endif
return NETDEV_TX_OK;
}
@@ -719,13 +718,10 @@ static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
return 1;
}
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
-static void flexcan_read_fifo(const struct net_device *dev,
- struct can_frame *cf)
+static void flexcan_read_can_frame(const struct flexcan_priv *priv,
+ struct flexcan_mb __iomem *mb,
+ struct can_frame *cf)
{
- const struct flexcan_priv *priv = netdev_priv(dev);
- struct flexcan_regs __iomem *regs = priv->base;
- struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
u32 reg_ctrl, reg_id;
reg_ctrl = priv->read(&mb->can_ctrl);
@@ -741,67 +737,39 @@ static void flexcan_read_fifo(const struct net_device *dev,
*(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
*(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
-
- /* mark as read */
- priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
- priv->read(&regs->timer);
}
-#else
-static void flexcan_read_mailbox(const struct net_device *dev,
- struct can_frame *cf, u32 mailbox)
+
+static void flexcan_read_fifo(const struct net_device *dev,
+ struct can_frame *cf)
{
const struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->base;
- struct flexcan_mb __iomem *mb = &regs->cantxfg[mailbox];
- u32 reg_ctrl, reg_id;
-
- reg_ctrl = priv->read(&mb->can_ctrl);
- reg_id = priv->read(&mb->can_id);
- if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
- cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
- else
- cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
-
- if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
- cf->can_id |= CAN_RTR_FLAG;
- cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
+ struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
- *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
- *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
+ flexcan_read_can_frame(priv, mb, cf);
/* mark as read */
- priv->write(BIT(mailbox), &regs->iflag1);
+ priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
priv->read(&regs->timer);
}
-#endif
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
-static int flexcan_read_frame_fifo_mode(struct net_device *dev)
+static void flexcan_read_msg_buf(const struct net_device *dev,
+ struct can_frame *cf, u32 msg_buf)
{
- struct net_device_stats *stats = &dev->stats;
- struct can_frame *cf;
- struct sk_buff *skb;
-
- skb = alloc_can_skb(dev, &cf);
- if (unlikely(!skb)) {
- stats->rx_dropped++;
- return 0;
- }
-
- flexcan_read_fifo(dev, cf);
-
- netif_receive_skb(skb);
-
- stats->rx_packets++;
- stats->rx_bytes += cf->can_dlc;
+ const struct flexcan_priv *priv = netdev_priv(dev);
+ struct flexcan_regs __iomem *regs = priv->base;
+ struct flexcan_mb __iomem *mb = &regs->cantxfg[msg_buf];
- can_led_event(dev, CAN_LED_EVENT_RX);
+ flexcan_read_can_frame(priv, mb, cf);
- return 1;
+ /* mark as read */
+ priv->write(BIT(msg_buf), &regs->iflag1);
+ priv->read(&regs->timer);
}
-#else
-static int flexcan_read_frame_legacy_mode(struct net_device *dev, u32 mailbox)
+
+static int flexcan_read_frame(struct net_device *dev)
{
+ const struct flexcan_priv *priv = netdev_priv(dev);
struct net_device_stats *stats = &dev->stats;
struct can_frame *cf;
struct sk_buff *skb;
@@ -812,7 +780,10 @@ static int flexcan_read_frame_legacy_mode(struct net_device *dev, u32 mailbox)
return 0;
}
- flexcan_read_mailbox(dev, cf, mailbox);
+ if (priv->devtype_data->features & FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT)
+ flexcan_read_msg_buf(dev, cf, priv->rx_msg_buf);
+ else
+ flexcan_read_fifo(dev, cf);
netif_receive_skb(skb);
@@ -823,14 +794,14 @@ static int flexcan_read_frame_legacy_mode(struct net_device *dev, u32 mailbox)
return 1;
}
-#endif
static int flexcan_poll(struct napi_struct *napi, int quota)
{
struct net_device *dev = napi->dev;
- const struct flexcan_priv *priv = netdev_priv(dev);
+ struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->base;
u32 reg_iflag1, reg_esr;
+ unsigned long iflag1;
int work_done = 0;
/*
@@ -842,28 +813,26 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
/* handle state changes */
work_done += flexcan_poll_state(dev, reg_esr);
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
- /* handle RX-FIFO */
reg_iflag1 = priv->read(&regs->iflag1);
- while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
- work_done < quota) {
- work_done += flexcan_read_frame_fifo_mode(dev);
- reg_iflag1 = priv->read(&regs->iflag1);
- }
-#else
- unsigned long iflag1;
- u32 mailbox;
- /* handle RX-Buffers */
- reg_iflag1 = priv->read(&regs->iflag1);
- iflag1 = reg_iflag1 & (FLEXCAN_TX_BUF_ID - 1);
- while ((reg_iflag1 & (FLEXCAN_TX_BUF_ID - 1)) &&
- work_done < quota) {
- mailbox = find_first_bit(&iflag1, (FLEXCAN_TX_BUF_ID - 1));
- work_done += flexcan_read_frame_legacy_mode(dev, mailbox);
- reg_iflag1 = priv->read(&regs->iflag1);
+ if (priv->devtype_data->features & FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT) {
+ /* handle legacy RX mode */
+ iflag1 = reg_iflag1 & FLEXCAN_IFLAG_RX_MB_RXMASK;
+ while ((reg_iflag1 & FLEXCAN_IFLAG_RX_MB_RXMASK) &&
+ work_done < quota) {
+ priv->rx_msg_buf = find_first_bit(&iflag1,
+ (FLEXCAN_TX_BUF_ID - 1));
+ work_done += flexcan_read_frame(dev);
+ reg_iflag1 = priv->read(&regs->iflag1);
+ }
+ } else {
+ /* handle RX-FIFO */
+ while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
+ work_done < quota) {
+ work_done += flexcan_read_frame(dev);
+ reg_iflag1 = priv->read(&regs->iflag1);
+ }
}
-#endif
/* report bus errors */
if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
@@ -872,7 +841,13 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
if (work_done < quota) {
napi_complete(napi);
/* enable IRQs */
- priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+ if (priv->devtype_data->features &
+ FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT)
+ priv->write(FLEXCAN_IFLAG_DEFAULT_RX_MB_MODE |
+ FLEXCAN_IFLAG_RX_MB_RXMASK, &regs->imask1);
+ else
+ priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+
priv->write(priv->reg_ctrl_default, &regs->ctrl);
}
@@ -899,53 +874,54 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
* - state change IRQ
* - bus error IRQ and bus error reporting is activated
*/
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
- if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
- (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
- flexcan_has_and_handle_berr(priv, reg_esr)) {
- /*
- * The error bits are cleared on read,
- * save them for later use.
- */
- priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
- priv->write(FLEXCAN_IFLAG_DEFAULT &
- ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
- priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
- &regs->ctrl);
- napi_schedule(&priv->napi);
- }
+ if (priv->devtype_data->features & FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT) {
+ if ((reg_iflag1 & FLEXCAN_IFLAG_RX_MB_RXMASK) ||
+ (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
+ flexcan_has_and_handle_berr(priv, reg_esr)) {
+ /* The error bits are cleared on read,
+ * save them for later use.
+ */
+ priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
+ priv->write(FLEXCAN_IFLAG_DEFAULT_RX_MB_MODE &
+ ~FLEXCAN_IFLAG_RX_MB_RXMASK, &regs->imask1);
+ priv->write(priv->reg_ctrl_default &
+ ~FLEXCAN_CTRL_ERR_ALL, &regs->ctrl);
+
+ napi_schedule(&priv->napi);
+ }
+ } else {
+ if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
+ (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
+ flexcan_has_and_handle_berr(priv, reg_esr)) {
+ /* The error bits are cleared on read,
+ * save them for later use.
+ */
+ priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
+ priv->write(FLEXCAN_IFLAG_DEFAULT &
+ ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE,
+ &regs->imask1);
+ priv->write(priv->reg_ctrl_default &
+ ~FLEXCAN_CTRL_ERR_ALL, &regs->ctrl);
+ napi_schedule(&priv->napi);
+ }
- /* FIFO overflow */
- if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
- priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
- dev->stats.rx_over_errors++;
- dev->stats.rx_errors++;
- }
-#else
- if ((reg_iflag1 & (FLEXCAN_TX_BUF_ID - 1)) ||
- (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
- flexcan_has_and_handle_berr(priv, reg_esr)) {
- /*
- * The error bits are cleared on read,
- * save them for later use.
- */
- priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
- priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
- &regs->ctrl);
- napi_schedule(&priv->napi);
+ /* FIFO overflow */
+ if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
+ priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
+ &regs->iflag1);
+ dev->stats.rx_over_errors++;
+ dev->stats.rx_errors++;
+ }
}
-#endif
/* transmission complete interrupt */
if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
stats->tx_bytes += can_get_echo_skb(dev, 0);
stats->tx_packets++;
can_led_event(dev, CAN_LED_EVENT_TX);
-#ifndef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
/* after sending a RTR frame mailbox is in RX mode */
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
-#endif
priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
netif_wake_queue(dev);
}
@@ -1031,18 +1007,23 @@ static int flexcan_chip_start(struct net_device *dev)
*/
reg_mcr = priv->read(&regs->mcr);
reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
- reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
+ if (priv->devtype_data->features & FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT)
+ reg_mcr &= ~FLEXCAN_MCR_FEN;
+ else
+ reg_mcr |= FLEXCAN_MCR_FEN;
+
+#if 0
+ reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
#else
reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
- FLEXCAN_MCR_IDAM_A |
- FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
- reg_mcr &= FLEXCAN_MCR_SRX_EN;
+ FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
+ reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
#endif
+
netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
priv->write(reg_mcr, &regs->mcr);
@@ -1079,47 +1060,26 @@ static int flexcan_chip_start(struct net_device *dev)
priv->write(reg_ctrl, &regs->ctrl);
/* clear and invalidate all mailboxes first */
-#ifndef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
- for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
- priv->write(0, &regs->cantxfg[i].can_ctrl);
- priv->write(0, &regs->cantxfg[i].can_id);
- priv->write(0, &regs->cantxfg[i].data[0]);
- priv->write(0, &regs->cantxfg[i].data[1]);
-
- /* put MB into rx queue */
- priv->write(FLEXCAN_MB_CNT_CODE(0x4),
- &regs->cantxfg[i].can_ctrl);
- }
-#else
for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
&regs->cantxfg[i].can_ctrl);
}
-#endif
-#ifdef CONFIG_CAN_FLEXCAN_ERRATA_ERR005829
/* Errata ERR005829: mark first TX mailbox as INACTIVE */
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
-#endif
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
/* mark TX mailbox as INACTIVE */
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
-#endif
/* acceptance mask/acceptance code (accept everything) */
priv->write(0x0, &regs->rxgmask);
priv->write(0x0, &regs->rx14mask);
priv->write(0x0, &regs->rx15mask);
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
priv->write(0x0, &regs->rxfgmask);
-#else
- priv->write(0x0, &regs->rxfgmask);
-#endif
/*
* On Vybrid, disable memory error detection interrupts
@@ -1157,8 +1117,13 @@ static int flexcan_chip_start(struct net_device *dev)
priv->can.state = CAN_STATE_ERROR_ACTIVE;
- /* enable FIFO interrupts */
- priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+ if (priv->devtype_data->features & FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT)
+ /* enable mb interrupts */
+ priv->write(FLEXCAN_IFLAG_DEFAULT_RX_MB_MODE |
+ FLEXCAN_IFLAG_RX_MB_RXMASK, &regs->imask1);
+ else
+ /* enable FIFO interrupts */
+ priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
/* print chip status */
netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
@@ -1315,32 +1280,30 @@ static int register_flexcandev(struct net_device *dev)
if (err)
goto out_chip_disable;
- /* set freeze, halt and activate FIFO, restrict register access */
+ /* set freeze, halt and activate FIFO/legacy mode, restrict
+ * register access
+ */
reg = priv->read(&regs->mcr);
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
- reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
- FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
-#else
+ if (priv->devtype_data->features & FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT)
+ reg &= ~FLEXCAN_MCR_FEN;
+ else
+ reg |= FLEXCAN_MCR_FEN;
+
reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV;
-#endif
priv->write(reg, &regs->mcr);
- /*
- * Currently we only support newer versions of this core
- * featuring a RX FIFO. Older cores found on some Coldfire
- * derivates are not yet supported.
- */
- reg = priv->read(&regs->mcr);
-#ifdef CONFIG_CAN_FLEXCAN_RX_FIFO_EN
- if (!(reg & FLEXCAN_MCR_FEN)) {
- netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
- err = -ENODEV;
- goto out_chip_disable;
+ if (priv->devtype_data->features & FLEXCAN_HAS_ONLY_LEGACY_RX_SUPPORT) {
+ /* Legacy RX mode*/
+ netdev_info(dev, "Legacy mode (non RX-FIFO) enabled\n");
+ } else {
+ /* RX FIFO mode */
+ reg = priv->read(&regs->mcr);
+ if (!(reg & FLEXCAN_MCR_FEN)) {
+ netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
+ err = -ENODEV;
+ goto out_chip_disable;
+ }
}
-#else
- if (!(reg & FLEXCAN_MCR_FEN))
- netdev_info(dev, "Legacy mode (non-RX FIFO) supported\n");
-#endif
err = register_candev(dev);
@@ -1365,6 +1328,8 @@ static const struct of_device_id flexcan_of_match[] = {
{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
{ .compatible = "fsl,ls1021a-flexcan",
.data = &fsl_ls1021a_devtype_data, },
+ { .compatible = "fsl,ls1021ar2-flexcan",
+ .data = &fsl_ls1021a_r2_devtype_data, },
{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
{ /* sentinel */ },
@@ -1446,13 +1411,13 @@ static int flexcan_probe(struct platform_device *pdev)
module_is_little = true;
if ((core_is_little && module_is_little) ||
- (!core_is_little && !module_is_little)) {
+ (!core_is_little && !module_is_little)) {
priv->read = flexcan_read_le;
priv->write = flexcan_write_le;
}
if ((!core_is_little && module_is_little) ||
- (core_is_little && !module_is_little)) {
+ (core_is_little && !module_is_little)) {
priv->read = flexcan_read_be;
priv->write = flexcan_write_be;
}
diff --git a/drivers/net/ethernet/freescale/gianfar.h b/drivers/net/ethernet/freescale/gianfar.h
index 262e896..0f5bf84 100644
--- a/drivers/net/ethernet/freescale/gianfar.h
+++ b/drivers/net/ethernet/freescale/gianfar.h
@@ -325,11 +325,7 @@ extern const char gfar_driver_version[];
#define RQUEUE_EN_ALL 0x000000FF
/* Init to do tx snooping for buffers and descriptors */
-#ifdef CONFIG_SOC_LS1021A
-#define DMACTRL_INIT_SETTINGS 0x00000003
-#else
#define DMACTRL_INIT_SETTINGS 0x000000c3
-#endif
#define DMACTRL_GRS 0x00000010
#define DMACTRL_GTS 0x00000008
#define DMACTRL_LE 0x00008000
@@ -496,12 +492,7 @@ extern const char gfar_driver_version[];
#define ATTR_BUFSTASH 0x00004000
#define ATTR_SNOOPING 0x000000c0
-
-#ifdef CONFIG_SOC_LS1021A
-#define ATTR_INIT_SETTINGS 0
-#else
#define ATTR_INIT_SETTINGS ATTR_SNOOPING
-#endif
#define ATTRELI_INIT_SETTINGS 0x0
#define ATTRELI_EL_MASK 0x3fff0000
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index e5c0db9..39cd38d 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -27,7 +27,6 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
#include <linux/slab.h>
#include "fsl_ucc_hdlc.h"
@@ -135,27 +134,27 @@ static void dump_ucc(struct ucc_hdlc_private *priv)
ucc_fast_dump_regs(priv->uccf);
dev_info(priv->dev, "Dumping UCC %d Parameter RAM\n",
priv->uh_info->uf_info.ucc_num);
- dev_info(priv->dev, "rbase = 0x%x\n", in_be32(&ucc_pram->rbase));
- dev_info(priv->dev, "rbptr = 0x%x\n", in_be32(&ucc_pram->rbptr));
- dev_info(priv->dev, "mrblr = 0x%x\n", in_be16(&ucc_pram->mrblr));
- dev_info(priv->dev, "rbdlen = 0x%x\n", in_be16(&ucc_pram->rbdlen));
- dev_info(priv->dev, "rbdstat = 0x%x\n", in_be16(&ucc_pram->rbdstat));
- dev_info(priv->dev, "rstate = 0x%x\n", in_be32(&ucc_pram->rstate));
- dev_info(priv->dev, "rdptr = 0x%x\n", in_be32(&ucc_pram->rdptr));
- dev_info(priv->dev, "riptr = 0x%x\n", in_be16(&ucc_pram->riptr));
- dev_info(priv->dev, "tbase = 0x%x\n", in_be32(&ucc_pram->tbase));
- dev_info(priv->dev, "tbptr = 0x%x\n", in_be32(&ucc_pram->tbptr));
- dev_info(priv->dev, "tbdlen = 0x%x\n", in_be16(&ucc_pram->tbdlen));
- dev_info(priv->dev, "tbdstat = 0x%x\n", in_be16(&ucc_pram->tbdstat));
- dev_info(priv->dev, "tstate = 0x%x\n", in_be32(&ucc_pram->tstate));
- dev_info(priv->dev, "tdptr = 0x%x\n", in_be32(&ucc_pram->tdptr));
- dev_info(priv->dev, "tiptr = 0x%x\n", in_be16(&ucc_pram->tiptr));
- dev_info(priv->dev, "rcrc = 0x%x\n", in_be32(&ucc_pram->rcrc));
- dev_info(priv->dev, "tcrc = 0x%x\n", in_be32(&ucc_pram->tcrc));
- dev_info(priv->dev, "c_mask = 0x%x\n", in_be32(&ucc_pram->c_mask));
- dev_info(priv->dev, "c_pers = 0x%x\n", in_be32(&ucc_pram->c_pres));
- dev_info(priv->dev, "disfc = 0x%x\n", in_be16(&ucc_pram->disfc));
- dev_info(priv->dev, "crcec = 0x%x\n", in_be16(&ucc_pram->crcec));
+ dev_info(priv->dev, "rbase = 0x%x\n", ioread32be(&ucc_pram->rbase));
+ dev_info(priv->dev, "rbptr = 0x%x\n", ioread32be(&ucc_pram->rbptr));
+ dev_info(priv->dev, "mrblr = 0x%x\n", ioread16be(&ucc_pram->mrblr));
+ dev_info(priv->dev, "rbdlen = 0x%x\n", ioread16be(&ucc_pram->rbdlen));
+ dev_info(priv->dev, "rbdstat = 0x%x\n", ioread16be(&ucc_pram->rbdstat));
+ dev_info(priv->dev, "rstate = 0x%x\n", ioread32be(&ucc_pram->rstate));
+ dev_info(priv->dev, "rdptr = 0x%x\n", ioread32be(&ucc_pram->rdptr));
+ dev_info(priv->dev, "riptr = 0x%x\n", ioread16be(&ucc_pram->riptr));
+ dev_info(priv->dev, "tbase = 0x%x\n", ioread32be(&ucc_pram->tbase));
+ dev_info(priv->dev, "tbptr = 0x%x\n", ioread32be(&ucc_pram->tbptr));
+ dev_info(priv->dev, "tbdlen = 0x%x\n", ioread16be(&ucc_pram->tbdlen));
+ dev_info(priv->dev, "tbdstat = 0x%x\n", ioread16be(&ucc_pram->tbdstat));
+ dev_info(priv->dev, "tstate = 0x%x\n", ioread32be(&ucc_pram->tstate));
+ dev_info(priv->dev, "tdptr = 0x%x\n", ioread32be(&ucc_pram->tdptr));
+ dev_info(priv->dev, "tiptr = 0x%x\n", ioread16be(&ucc_pram->tiptr));
+ dev_info(priv->dev, "rcrc = 0x%x\n", ioread32be(&ucc_pram->rcrc));
+ dev_info(priv->dev, "tcrc = 0x%x\n", ioread32be(&ucc_pram->tcrc));
+ dev_info(priv->dev, "c_mask = 0x%x\n", ioread32be(&ucc_pram->c_mask));
+ dev_info(priv->dev, "c_pers = 0x%x\n", ioread32be(&ucc_pram->c_pres));
+ dev_info(priv->dev, "disfc = 0x%x\n", ioread16be(&ucc_pram->disfc));
+ dev_info(priv->dev, "crcec = 0x%x\n", ioread16be(&ucc_pram->crcec));
}
static void dump_bds(struct ucc_hdlc_private *priv)
@@ -237,18 +236,18 @@ static void init_si(struct ucc_hdlc_private *priv)
mask = 0x01 << i;
if (priv->tx_ts_mask & mask)
- out_be16(&siram[siram_entry_id * 32 + i],
- siram_entry_valid);
+ iowrite16be(siram_entry_valid,
+ &siram[siram_entry_id * 32 + i]);
else
- out_be16(&siram[siram_entry_id * 32 + i],
- siram_entry_closed);
+ iowrite16be(siram_entry_closed,
+ &siram[siram_entry_id * 32 + i]);
if (priv->rx_ts_mask & mask)
- out_be16(&siram[siram_entry_id * 32 + 0x200 + i],
- siram_entry_valid);
+ iowrite16be(siram_entry_valid,
+ &siram[siram_entry_id * 32 + 0x200 + i]);
else
- out_be16(&siram[siram_entry_id * 32 + 0x200 + i],
- siram_entry_closed);
+ iowrite16be(siram_entry_closed,
+ &siram[siram_entry_id * 32 + 0x200 + i]);
}
setbits16(&siram[(siram_entry_id * 32) + (priv->num_of_ts - 1)],
@@ -282,16 +281,16 @@ static void init_si(struct ucc_hdlc_private *priv)
switch (tdm_port) {
case 0:
- out_be16(&si_regs->sixmr1[0], sixmr);
+ iowrite16be(sixmr, &si_regs->sixmr1[0]);
break;
case 1:
- out_be16(&si_regs->sixmr1[1], sixmr);
+ iowrite16be(sixmr, &si_regs->sixmr1[1]);
break;
case 2:
- out_be16(&si_regs->sixmr1[2], sixmr);
+ iowrite16be(sixmr, &si_regs->sixmr1[2]);
break;
case 3:
- out_be16(&si_regs->sixmr1[3], sixmr);
+ iowrite16be(sixmr, &si_regs->sixmr1[3]);
break;
default:
dev_err(priv->dev, "can not find tdm sixmr reg\n");
@@ -336,10 +335,10 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
/* Loopback mode */
if (priv->loopback) {
- gumr = in_be32(&priv->uf_regs->gumr);
+ gumr = ioread32be(&priv->uf_regs->gumr);
gumr |= (0x40000000 | UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_TCI);
gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
- out_be32(&priv->uf_regs->gumr, gumr);
+ iowrite32be(gumr, &priv->uf_regs->gumr);
}
/* Initialize SI */
@@ -352,7 +351,7 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
(u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
/* Set UPSMR normal mode (need fixed)*/
- out_be32(&priv->uf_regs->upsmr, 0);
+ iowrite32be(0, &priv->uf_regs->upsmr);
priv->rx_ring_size = RX_BD_RING_LEN;
priv->tx_ring_size = TX_BD_RING_LEN;
@@ -429,32 +428,32 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
}
/* Set RIPTR, TIPTR */
- out_be16(&priv->ucc_pram->riptr, (u16)riptr);
- out_be16(&priv->ucc_pram->tiptr, (u16)tiptr);
+ iowrite16be((u16)riptr, &priv->ucc_pram->riptr);
+ iowrite16be((u16)tiptr, &priv->ucc_pram->tiptr);
/* Set MRBLR */
- out_be16(&priv->ucc_pram->mrblr, (u16)MAX_RX_BUF_LENGTH);
+ iowrite16be((u16)MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
/* Set RBASE, TBASE */
- out_be32(&priv->ucc_pram->rbase, (u32)priv->dma_rx_bd);
- out_be32(&priv->ucc_pram->tbase, (u32)priv->dma_tx_bd);
+ iowrite32be((u32)priv->dma_rx_bd, &priv->ucc_pram->rbase);
+ iowrite32be((u32)priv->dma_tx_bd, &priv->ucc_pram->tbase);
/* Set RSTATE, TSTATE */
- out_be32(&priv->ucc_pram->rstate, 0x30000000);
- out_be32(&priv->ucc_pram->tstate, 0x30000000);
+ iowrite32be(0x30000000, &priv->ucc_pram->rstate);
+ iowrite32be(0x30000000, &priv->ucc_pram->tstate);
/* Set C_MASK, C_PRES for 16bit CRC */
- out_be32(&priv->ucc_pram->c_mask, 0x0000F0B8);
- out_be32(&priv->ucc_pram->c_pres, 0x0000FFFF);
-
- out_be16(&priv->ucc_pram->mflr, MAX_RX_BUF_LENGTH + 8);
- out_be16(&priv->ucc_pram->rfthr, 1);
- out_be16(&priv->ucc_pram->rfcnt, 1);
- out_be16(&priv->ucc_pram->hmask, DEFAULT_ADDR_MASK);
- out_be16(&priv->ucc_pram->haddr2, DEFAULT_BROAD_ADDR);
- out_be16(&priv->ucc_pram->haddr1, DEFAULT_HDLC_ADDR);
- out_be16(&priv->ucc_pram->haddr3, DEFAULT_HDLC_ADDR);
- out_be16(&priv->ucc_pram->haddr4, DEFAULT_HDLC_ADDR);
+ iowrite32be(0x0000F0B8, &priv->ucc_pram->c_mask);
+ iowrite32be(0x0000FFFF, &priv->ucc_pram->c_pres);
+
+ iowrite16be(MAX_RX_BUF_LENGTH + 8, &priv->ucc_pram->mflr);
+ iowrite16be(1, &priv->ucc_pram->rfthr);
+ iowrite16be(1, &priv->ucc_pram->rfcnt);
+ iowrite16be(DEFAULT_ADDR_MASK, &priv->ucc_pram->hmask);
+ iowrite16be(DEFAULT_BROAD_ADDR, &priv->ucc_pram->haddr2);
+ iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
+ iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
+ iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
/* Get BD buffer */
bd_buffer = dma_alloc_coherent(priv->dev,
@@ -478,9 +477,9 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
else
bd_status = R_E | R_I | R_W;
- out_be32((u32 *)(priv->rx_bd_base + i), bd_status);
- out_be32(&priv->rx_bd_base[i].buf, priv->dma_rx_addr
- + i * MAX_RX_BUF_LENGTH);
+ iowrite32be(bd_status, (u32 *)(priv->rx_bd_base + i));
+ iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
+ &priv->rx_bd_base[i].buf);
}
for (i = 0; i < TX_BD_RING_LEN; i++) {
@@ -489,7 +488,7 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
else
bd_status = T_I | T_TC | T_W;
- out_be32((u32 *)(priv->tx_bd_base + i), bd_status);
+ iowrite32be(bd_status, (u32 *)(priv->tx_bd_base + i));
}
return 0;
@@ -532,7 +531,7 @@ static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
hdlc_head = (u32 *)skb->data;
tmp_head = *hdlc_head;
- tmp_head = (tmp_head & HDLC_HEAD_MASK) | DEFAULT_HDLC_HEAD;
+ tmp_head = (tmp_head & HDLC_HEAD_MASK) | cpu_to_be32(DEFAULT_HDLC_HEAD);
*hdlc_head = tmp_head;
dev->stats.tx_bytes += skb->len;
@@ -547,7 +546,7 @@ static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
/* Start from the next BD that should be filled */
bd = priv->curtx_bd;
- bd_status = in_be32((u32 __iomem *)bd);
+ bd_status = ioread32be((u32 __iomem *)bd);
/* Save the skb pointer so we can free it later */
priv->tx_skbuff[priv->skb_curtx] = skb;
@@ -556,14 +555,14 @@ static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
priv->skb_curtx =
(priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
/* set up the buffer descriptor */
- out_be32(&((struct qe_bd __iomem *)bd)->buf,
- dma_map_single(priv->dev, skb->data,
- skb->len, DMA_TO_DEVICE));
+ iowrite32be(dma_map_single(priv->dev, skb->data, skb->len,
+ DMA_TO_DEVICE),
+ &((struct qe_bd __iomem *)bd)->buf);
bd_status = (bd_status & T_W) | T_R | T_I | T_L | T_TC | skb->len;
/* set bd status and length */
- out_be32((u32 __iomem *)bd, bd_status);
+ iowrite32be(bd_status, (u32 __iomem *)bd);
/* Move to next BD in the ring */
if (!(bd_status & T_W))
@@ -583,7 +582,7 @@ static int hdlc_tx_done(struct ucc_hdlc_private *priv)
u32 bd_status;
bd = priv->dirty_tx;
- bd_status = in_be32((u32 __iomem *)bd);
+ bd_status = ioread32be((u32 __iomem *)bd);
/* Normal processing. */
while ((bd_status & T_R) == 0) {
@@ -599,7 +598,7 @@ static int hdlc_tx_done(struct ucc_hdlc_private *priv)
dev->stats.tx_packets++;
dma_unmap_single(priv->dev,
- in_be32(&((struct qe_bd __iomem *)bd)->buf),
+ ioread32be(&((struct qe_bd __iomem *)bd)->buf),
skb->len, DMA_TO_DEVICE);
dev_kfree_skb_irq(skb);
@@ -617,7 +616,7 @@ static int hdlc_tx_done(struct ucc_hdlc_private *priv)
bd += 1;
else
bd = priv->tx_bd_base;
- bd_status = in_be32((u32 __iomem *)bd);
+ bd_status = ioread32be((u32 __iomem *)bd);
}
priv->dirty_tx = bd;
@@ -636,7 +635,7 @@ static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
int i;
bd = priv->currx_bd;
- bd_status = in_be32((u32 __iomem *)bd);
+ bd_status = ioread32be((u32 __iomem *)bd);
/* while there are received buffers and BD is full (~R_E) */
while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
@@ -683,7 +682,7 @@ static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
else
priv->currx_bdnum = RX_BD_RING_LEN - 1;
- bd_status = in_be32((u32 __iomem *)bd);
+ bd_status = ioread32be((u32 __iomem *)bd);
}
priv->currx_bd = bd;
@@ -701,8 +700,8 @@ static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
uh_info = priv->uh_info;
uccf = priv->uccf;
- ucce = in_be32(uccf->p_ucce);
- uccm = in_be32(uccf->p_uccm);
+ ucce = ioread32be(uccf->p_ucce);
+ uccm = ioread32be(uccf->p_uccm);
if ((ucce >> 16) & (UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB))
hdlc_rx_done(priv, RX_CLEAN_MAX);
@@ -710,7 +709,7 @@ static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
if ((ucce >> 16) & UCC_HDLC_UCCE_TXB)
hdlc_tx_done(priv);
- out_be32(uccf->p_ucce, ucce);
+ iowrite32be(ucce, uccf->p_ucce);
return IRQ_HANDLED;
}
@@ -886,6 +885,7 @@ static int of_parse_hdlc_tdm(struct device_node *np,
const unsigned int *prop;
const char *sprop;
int ret = 0;
+ u32 val;
sprop = of_get_property(np, "fsl,rx-sync-clock", NULL);
if (sprop) {
@@ -913,54 +913,54 @@ static int of_parse_hdlc_tdm(struct device_node *np,
return -EINVAL;
}
- prop = of_get_property(np, "fsl,tx-timeslot", NULL);
- if (!prop) {
+ ret = of_property_read_u32_index(np, "fsl,tx-timeslot", 0, &val);
+ if (ret) {
ret = -EINVAL;
dev_err(priv->dev, "Invalid tx-timeslot property\n");
return ret;
}
- priv->tx_ts_mask = *prop;
+ priv->tx_ts_mask = val;
- prop = of_get_property(np, "fsl,rx-timeslot", NULL);
- if (!prop) {
+ ret = of_property_read_u32_index(np, "fsl,rx-timeslot", 0, &val);
+ if (ret) {
ret = -EINVAL;
dev_err(priv->dev, "Invalid rx-timeslot property\n");
return ret;
}
- priv->rx_ts_mask = *prop;
+ priv->rx_ts_mask = val;
- prop = of_get_property(np, "fsl,tdm-id", NULL);
- if (!prop) {
+ ret = of_property_read_u32_index(np, "fsl,tdm-id", 0, &val);
+ if (ret) {
ret = -EINVAL;
dev_err(priv->dev, "No fsl,tdm-id property for this UCC\n");
return ret;
}
- priv->tdm_port = *prop;
+ priv->tdm_port = ret;
uh_info->uf_info.tdm_num = priv->tdm_port;
- prop = of_get_property(np, "fsl,tdm-mode", NULL);
- if (!prop) {
+ sprop = of_get_property(np, "fsl,tdm-mode", NULL);
+ if (!sprop) {
ret = -EINVAL;
dev_err(priv->dev, "No tdm-mode property for UCC\n");
return ret;
}
- priv->tdm_mode = set_tdm_mode((const char *)prop);
+ priv->tdm_mode = set_tdm_mode(sprop);
- prop = of_get_property(np, "fsl,tdm-framer-type", NULL);
- if (!prop) {
+ sprop = of_get_property(np, "fsl,tdm-framer-type", NULL);
+ if (!sprop) {
ret = -EINVAL;
dev_err(priv->dev, "No tdm-framer-type property for UCC\n");
return ret;
}
- priv->tdm_framer_type = set_tdm_framer((const char *)prop);
+ priv->tdm_framer_type = set_tdm_framer(sprop);
- prop = of_get_property(np, "fsl,siram-entry-id", NULL);
- if (!prop) {
+ ret = of_property_read_u32_index(np, "fsl,siram-entry-id", 0, &val);
+ if (ret) {
ret = -EINVAL;
dev_err(priv->dev, "No siram entry id for UCC\n");
return ret;
}
- priv->siram_entry_id = *(const u32 *)prop;
+ priv->siram_entry_id = val;
set_si_param(priv);
@@ -993,11 +993,11 @@ static void store_clk_config(struct ucc_hdlc_private *priv)
struct qe_mux *qe_mux_reg = &qe_immr->qmx;
/* store si clk */
- priv->cmxsi1cr_h = in_be32(&qe_mux_reg->cmxsi1cr_h);
- priv->cmxsi1cr_l = in_be32(&qe_mux_reg->cmxsi1cr_l);
+ priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
+ priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
/* store si sync */
- priv->cmxsi1syr = in_be32(&qe_mux_reg->cmxsi1syr);
+ priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
/* store ucc clk */
memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
@@ -1009,10 +1009,10 @@ static void resume_clk_config(struct ucc_hdlc_private *priv)
memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
- out_be32(&qe_mux_reg->cmxsi1cr_h, priv->cmxsi1cr_h);
- out_be32(&qe_mux_reg->cmxsi1cr_l, priv->cmxsi1cr_l);
+ iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
+ iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
- out_be32(&qe_mux_reg->cmxsi1syr, priv->cmxsi1syr);
+ iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
}
@@ -1029,8 +1029,8 @@ static int uhdlc_suspend(struct device *dev)
uf_regs = priv->uf_regs;
/* backup gumr guemr*/
- priv->gumr = in_be32(&uf_regs->gumr);
- priv->guemr = in_8(&uf_regs->guemr);
+ priv->gumr = ioread32be(&uf_regs->gumr);
+ priv->guemr = ioread8(&uf_regs->guemr);
priv->ucc_pram_bak = kmalloc(sizeof(struct ucc_hdlc_param),
GFP_KERNEL);
@@ -1070,25 +1070,25 @@ static int uhdlc_resume(struct device *dev)
uccf = priv->uccf;
/* restore gumr guemr */
- out_8(&uf_regs->guemr, priv->guemr);
- out_be32(&uf_regs->gumr, priv->gumr);
+ iowrite8(priv->guemr, &uf_regs->guemr);
+ iowrite32be(priv->gumr, &uf_regs->gumr);
/* Set Virtual Fifo registers */
- out_be16(&uf_regs->urfs, uf_info->urfs);
- out_be16(&uf_regs->urfet, uf_info->urfet);
- out_be16(&uf_regs->urfset, uf_info->urfset);
- out_be16(&uf_regs->utfs, uf_info->utfs);
- out_be16(&uf_regs->utfet, uf_info->utfet);
- out_be16(&uf_regs->utftt, uf_info->utftt);
+ iowrite16be(uf_info->urfs, &uf_regs->urfs);
+ iowrite16be(uf_info->urfet, &uf_regs->urfet);
+ iowrite16be(uf_info->urfset, &uf_regs->urfset);
+ iowrite16be(uf_info->utfs, &uf_regs->utfs);
+ iowrite16be(uf_info->utfet, &uf_regs->utfet);
+ iowrite16be(uf_info->utftt, &uf_regs->utftt);
/* utfb, urfb are offsets from MURAM base */
- out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
- out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
+ iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
+ iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
/* Rx Tx and sync clock routing */
resume_clk_config(priv);
- out_be32(&uf_regs->uccm, uf_info->uccm_mask);
- out_be32(&uf_regs->ucce, 0xffffffff);
+ iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
+ iowrite32be(0xffffffff, &uf_regs->ucce);
ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
@@ -1102,7 +1102,7 @@ static int uhdlc_resume(struct device *dev)
(u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
/* Set UPSMR normal mode */
- out_be32(&uf_regs->upsmr, 0);
+ iowrite32be(0, &uf_regs->upsmr);
/* init parameter base */
cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
@@ -1124,9 +1124,9 @@ static int uhdlc_resume(struct device *dev)
else
bd_status = R_E | R_I | R_W;
- out_be32((u32 *)(priv->rx_bd_base + i), bd_status);
- out_be32(&priv->rx_bd_base[i].buf, priv->dma_rx_addr
- + i * MAX_RX_BUF_LENGTH);
+ iowrite32be(bd_status, (u32 *)(priv->rx_bd_base + i));
+ iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
+ &priv->rx_bd_base[i].buf);
}
for (i = 0; i < TX_BD_RING_LEN; i++) {
@@ -1135,7 +1135,7 @@ static int uhdlc_resume(struct device *dev)
else
bd_status = T_I | T_TC | T_W;
- out_be32((u32 *)(priv->tx_bd_base + i), bd_status);
+ iowrite32be(bd_status, (u32 *)(priv->tx_bd_base + i));
}
/* if hdlc is busy enable TX and RX */
@@ -1191,14 +1191,15 @@ static int ucc_hdlc_probe(struct platform_device *pdev)
const unsigned int *prop;
const char *sprop;
int ret;
+ u32 val;
- prop = of_get_property(np, "cell-index", NULL);
- if (!prop) {
+ ret = of_property_read_u32_index(np, "cell-index", 0, &val);
+ if (ret) {
dev_err(&pdev->dev, "Invalid ucc property\n");
return -ENODEV;
}
- ucc_num = *prop - 1;
+ ucc_num = val - 1;
if ((ucc_num > 3) || (ucc_num < 0)) {
dev_err(&pdev->dev, ": Invalid UCC num\n");
return -EINVAL;
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
index e3cceb6..c5633cf 100644
--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
@@ -37,8 +37,8 @@
#define SCFG_SPIMSICR 0x40
#define SCFG_SPIMSICLRCR 0x90
-#define MSI_LS1021A_ADDR 0x1570040
-#define MSI_LS1021A_DATA(pex_idx) (0xb3 + pex_idx)
+#define LS1021A_MSIIR_ADDR(idx) (0x1570e00 + (idx) * 8)
+#define LS1021A_MSIR_OFF(idx) (0x0e04 + (idx) * 8)
/* Symbol Timer Register and Filter Mask Register 1 */
#define PCIE_STRFMR1 0x71c
@@ -72,43 +72,53 @@ static int ls_pcie_link_up(struct pcie_port *pp)
static u32 ls_pcie_get_msi_addr(struct pcie_port *pp)
{
- return MSI_LS1021A_ADDR;
+ struct ls_pcie *pcie = to_ls_pcie(pp);
+
+ return LS1021A_MSIIR_ADDR(pcie->index);
}
static u32 ls_pcie_get_msi_data(struct pcie_port *pp, int pos)
{
- struct ls_pcie *pcie = to_ls_pcie(pp);
-
- return MSI_LS1021A_DATA(pcie->index);
+ return pos * 8;
}
static irqreturn_t ls_pcie_msi_irq_handler(int irq, void *data)
{
struct pcie_port *pp = data;
struct ls_pcie *pcie = to_ls_pcie(pp);
- unsigned int msi_irq;
-
- /* clear the interrupt */
- regmap_write(pcie->scfg, SCFG_SPIMSICLRCR,
- cpu_to_be32(MSI_LS1021A_DATA(pcie->index)));
-
- msi_irq = irq_find_mapping(pp->irq_domain, 0);
- if (!msi_irq) {
- /*
- * that's weird who triggered this?
- * just clear it
- */
- dev_err(pcie->dev, "unexpected MSI\n");
- return IRQ_NONE;
+ unsigned long val;
+ int msi_irq, ret, pos;
+
+ regmap_read(pcie->scfg, LS1021A_MSIR_OFF(pcie->index), (u32 *) &val);
+
+ if (val) {
+ ret = IRQ_HANDLED;
+ pos = 0;
+ while ((pos = find_next_bit(&val, 32, pos)) != 32) {
+ msi_irq = irq_find_mapping(pp->irq_domain, 31 - pos);
+ if (!msi_irq) {
+ /*
+ * that's weird who triggered this?
+ * just clear it
+ */
+ dev_err(pcie->dev, "unexpected MSI\n");
+ ret = IRQ_NONE;
+ continue;
+ }
+
+ #if defined(CONFIG_PREEMPT_RT_FULL) || defined(CONFIG_PREEMPT_RTB)
+ local_irq_disable();
+ #endif
+ generic_handle_irq(msi_irq);
+ #if defined(CONFIG_PREEMPT_RT_FULL) || defined(CONFIG_PREEMPT_RTB)
+ local_irq_enable();
+ #endif
+ ret = IRQ_HANDLED;
+ pos++;
+ }
}
-#if defined(CONFIG_PREEMPT_RT_FULL) || defined(CONFIG_PREEMPT_RTB)
- local_irq_disable();
-#endif
- generic_handle_irq(msi_irq);
-#if defined(CONFIG_PREEMPT_RT_FULL) || defined(CONFIG_PREEMPT_RTB)
- local_irq_enable();
-#endif
- return IRQ_HANDLED;
+
+ return ret;
}
static void ls_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
@@ -119,18 +129,6 @@ static void ls_pcie_msi_set_irq(struct pcie_port *pp, int irq)
{
}
-static void ls1021a_pcie_msi_fixup(struct pcie_port *pp)
-{
- int i;
-
- /*
- * LS1021A has only one MSI interrupt
- * Set all msi interrupts as used except the first one
- */
- for (i = 1; i < MAX_MSI_IRQS; i++)
- set_bit(i, pp->msi_irq_in_use);
-}
-
static void ls_pcie_host_init(struct pcie_port *pp)
{
struct ls_pcie *pcie = to_ls_pcie(pp);
@@ -156,8 +154,6 @@ static void ls_pcie_host_init(struct pcie_port *pp)
val = ioread32(pcie->dbi + PCIE_STRFMR1);
val &= 0xffff;
iowrite32(val, pcie->dbi + PCIE_STRFMR1);
-
- ls1021a_pcie_msi_fixup(pp);
}
}
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 91bb4c9..1539790 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -185,6 +185,9 @@ struct sdhci_host {
unsigned int ocr_avail_mmc;
u32 ocr_mask; /* available voltages */
+ /* cached registers */
+ u32 ier;
+
wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index a07b670..84b10f9 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -418,8 +418,6 @@ struct snd_pcm_substream {
#endif
/* misc flags */
unsigned int hw_opened: 1;
- /* data swapped flags */
- unsigned int data_swapped;
};
#define SUBSTREAM_BUSY(substream) ((substream)->ref_count > 0)
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
index 6dd3089..e1ef106 100644
--- a/sound/core/pcm_lib.c
+++ b/sound/core/pcm_lib.c
@@ -1964,9 +1964,6 @@ static int snd_pcm_lib_write_transfer(struct snd_pcm_substream *substream,
struct snd_pcm_runtime *runtime = substream->runtime;
int err;
char __user *buf = (char __user *) data + frames_to_bytes(runtime, off);
- int i;
- char tmp;
-
if (substream->ops->copy) {
if ((err = substream->ops->copy(substream, -1, hwoff, buf, frames)) < 0)
return err;
@@ -1974,22 +1971,6 @@ static int snd_pcm_lib_write_transfer(struct snd_pcm_substream *substream,
char *hwbuf = runtime->dma_area + frames_to_bytes(runtime, hwoff);
if (copy_from_user(hwbuf, buf, frames_to_bytes(runtime, frames)))
return -EFAULT;
-
- if (substream->data_swapped) {
- switch (runtime->format) {
- case SNDRV_PCM_FORMAT_S16_LE:
- for (i = 0;
- i < frames_to_bytes(runtime, frames);
- i = i + 2) {
- tmp = *(hwbuf + i);
- *(hwbuf + i) = *(hwbuf + i + 1);
- *(hwbuf + i + 1) = tmp;
- }
- break;
- default:
- return -EINVAL;
- }
- }
}
return 0;
}
@@ -2205,30 +2186,11 @@ static int snd_pcm_lib_read_transfer(struct snd_pcm_substream *substream,
struct snd_pcm_runtime *runtime = substream->runtime;
int err;
char __user *buf = (char __user *) data + frames_to_bytes(runtime, off);
- int i;
- char tmp;
-
if (substream->ops->copy) {
if ((err = substream->ops->copy(substream, -1, hwoff, buf, frames)) < 0)
return err;
} else {
char *hwbuf = runtime->dma_area + frames_to_bytes(runtime, hwoff);
- if (substream->data_swapped) {
- switch (runtime->format) {
- case SNDRV_PCM_FORMAT_S16_LE:
- for (i = 0;
- i < frames_to_bytes(runtime, frames);
- i = i + 2) {
- tmp = *(hwbuf + i);
- *(hwbuf + i) = *(hwbuf + i + 1);
- *(hwbuf + i + 1) = tmp;
- }
- break;
- default:
- return -EINVAL;
- }
- }
-
if (copy_to_user(buf, hwbuf, frames_to_bytes(runtime, frames)))
return -EFAULT;
}
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 3653b25..896f011 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -334,9 +334,6 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
u32 reg;
- if (sai->big_endian_regs)
- substream->data_swapped = 1;
-
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = FSL_SAI_TCR3;
else
@@ -555,14 +552,8 @@ static int fsl_sai_probe(struct platform_device *pdev)
return PTR_ERR(sai->regmap);
}
- if (sai->big_endian_regs) {
- sai->dma_params_rx.addr = res->start + FSL_SAI_RDR + 2;
- sai->dma_params_tx.addr = res->start + FSL_SAI_TDR + 2;
- } else {
- sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
- sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
- }
-
+ sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
+ sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
generated by cgit v0.10.2 at 2024-05-29 05:55:49 (GMT)