diff options
Diffstat (limited to 'arch/arm/mach-omap2/clock24xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/clock24xx.h | 535 |
1 files changed, 194 insertions, 341 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index ad6d98d..88c5acb 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -24,17 +24,13 @@ #include "cm-regbits-24xx.h" #include "sdrc.h" -static void omap2_table_mpu_recalc(struct clk *clk); +static unsigned long omap2_table_mpu_recalc(struct clk *clk); static int omap2_select_table_rate(struct clk *clk, unsigned long rate); static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); -static void omap2_sys_clk_recalc(struct clk *clk); -static void omap2_osc_clk_recalc(struct clk *clk); -static void omap2_sys_clk_recalc(struct clk *clk); -static void omap2_dpllcore_recalc(struct clk *clk); -static int omap2_clk_fixed_enable(struct clk *clk); -static void omap2_clk_fixed_disable(struct clk *clk); -static int omap2_enable_osc_ck(struct clk *clk); -static void omap2_disable_osc_ck(struct clk *clk); +static unsigned long omap2_sys_clk_recalc(struct clk *clk); +static unsigned long omap2_osc_clk_recalc(struct clk *clk); +static unsigned long omap2_sys_clk_recalc(struct clk *clk); +static unsigned long omap2_dpllcore_recalc(struct clk *clk); static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. @@ -623,41 +619,43 @@ static struct prcm_config rate_table[] = { /* Base external input clocks */ static struct clk func_32k_ck = { .name = "func_32k_ck", + .ops = &clkops_null, .rate = 32000, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, + .flags = RATE_FIXED, + .clkdm_name = "wkup_clkdm", +}; + +static struct clk secure_32k_ck = { + .name = "secure_32k_ck", + .ops = &clkops_null, + .rate = 32768, + .flags = RATE_FIXED, .clkdm_name = "wkup_clkdm", - .recalc = &propagate_rate, }; /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ .name = "osc_ck", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES, + .ops = &clkops_oscck, .clkdm_name = "wkup_clkdm", - .enable = &omap2_enable_osc_ck, - .disable = &omap2_disable_osc_ck, .recalc = &omap2_osc_clk_recalc, }; /* Without modem likely 12MHz, with modem likely 13MHz */ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ .name = "sys_ck", /* ~ ref_clk also */ + .ops = &clkops_null, .parent = &osc_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &omap2_sys_clk_recalc, }; static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .name = "alt_ck", + .ops = &clkops_null, .rate = 54000000, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, + .flags = RATE_FIXED, .clkdm_name = "wkup_clkdm", - .recalc = &propagate_rate, }; /* @@ -673,7 +671,12 @@ static struct dpll_data dpll_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP24XX_DPLL_MULT_MASK, .div1_mask = OMAP24XX_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP24XX_EN_DPLL_MASK, .max_multiplier = 1024, + .min_divider = 1, .max_divider = 16, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -684,10 +687,9 @@ static struct dpll_data dpll_dd = { */ static struct clk dpll_ck = { .name = "dpll_ck", + .ops = &clkops_null, .parent = &sys_ck, /* Can be func_32k also */ .dpll_data = &dpll_dd, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | ALWAYS_ENABLED, .clkdm_name = "wkup_clkdm", .recalc = &omap2_dpllcore_recalc, .set_rate = &omap2_reprogram_dpllcore, @@ -695,30 +697,24 @@ static struct clk dpll_ck = { static struct clk apll96_ck = { .name = "apll96_ck", + .ops = &clkops_fixed, .parent = &sys_ck, .rate = 96000000, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, + .flags = RATE_FIXED | ENABLE_ON_INIT, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .enable = &omap2_clk_fixed_enable, - .disable = &omap2_clk_fixed_disable, - .recalc = &propagate_rate, }; static struct clk apll54_ck = { .name = "apll54_ck", + .ops = &clkops_fixed, .parent = &sys_ck, .rate = 54000000, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, + .flags = RATE_FIXED | ENABLE_ON_INIT, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .enable = &omap2_clk_fixed_enable, - .disable = &omap2_clk_fixed_disable, - .recalc = &propagate_rate, }; /* @@ -745,9 +741,8 @@ static const struct clksel func_54m_clksel[] = { static struct clk func_54m_ck = { .name = "func_54m_ck", + .ops = &clkops_null, .parent = &apll54_ck, /* can also be alt_clk */ - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -758,9 +753,8 @@ static struct clk func_54m_ck = { static struct clk core_ck = { .name = "core_ck", + .ops = &clkops_null, .parent = &dpll_ck, /* can also be 32k */ - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -785,9 +779,8 @@ static const struct clksel func_96m_clksel[] = { /* The parent of this clock is not selectable on 2420. */ static struct clk func_96m_ck = { .name = "func_96m_ck", + .ops = &clkops_null, .parent = &apll96_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -818,9 +811,8 @@ static const struct clksel func_48m_clksel[] = { static struct clk func_48m_ck = { .name = "func_48m_ck", + .ops = &clkops_null, .parent = &apll96_ck, /* 96M or Alt */ - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -833,10 +825,9 @@ static struct clk func_48m_ck = { static struct clk func_12m_ck = { .name = "func_12m_ck", + .ops = &clkops_null, .parent = &func_48m_ck, .fixed_div = 4, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, .clkdm_name = "wkup_clkdm", .recalc = &omap2_fixed_divisor_recalc, }; @@ -844,8 +835,8 @@ static struct clk func_12m_ck = { /* Secure timer, only available in secure mode */ static struct clk wdt1_osc_ck = { .name = "ck_wdt1_osc", + .ops = &clkops_null, /* RMK: missing? */ .parent = &osc_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .recalc = &followparent_recalc, }; @@ -887,9 +878,8 @@ static const struct clksel common_clkout_src_clksel[] = { static struct clk sys_clkout_src = { .name = "sys_clkout_src", + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, @@ -918,9 +908,8 @@ static const struct clksel sys_clkout_clksel[] = { static struct clk sys_clkout = { .name = "sys_clkout", + .ops = &clkops_null, .parent = &sys_clkout_src, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - PARENT_CONTROLS_CLOCK, .clkdm_name = "wkup_clkdm", .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, @@ -933,8 +922,8 @@ static struct clk sys_clkout = { /* In 2430, new in 2420 ES2 */ static struct clk sys_clkout2_src = { .name = "sys_clkout2_src", + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, - .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, @@ -955,8 +944,8 @@ static const struct clksel sys_clkout2_clksel[] = { /* In 2430, new in 2420 ES2 */ static struct clk sys_clkout2 = { .name = "sys_clkout2", + .ops = &clkops_null, .parent = &sys_clkout2_src, - .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, .clkdm_name = "wkup_clkdm", .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, @@ -968,8 +957,8 @@ static struct clk sys_clkout2 = { static struct clk emul_ck = { .name = "emul_ck", + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, @@ -1003,10 +992,9 @@ static const struct clksel mpu_clksel[] = { static struct clk mpu_ck = { /* Control cpu */ .name = "mpu_ck", + .ops = &clkops_null, .parent = &core_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP | - CONFIG_PARTICIPANT | RATE_PROPAGATES, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "mpu_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), @@ -1046,9 +1034,9 @@ static const struct clksel dsp_fck_clksel[] = { static struct clk dsp_fck = { .name = "dsp_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | - CONFIG_PARTICIPANT | RATE_PROPAGATES, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "dsp_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, @@ -1076,9 +1064,9 @@ static const struct clksel dsp_irate_ick_clksel[] = { /* This clock does not exist as such in the TRM. */ static struct clk dsp_irate_ick = { .name = "dsp_irate_ick", + .ops = &clkops_null, .parent = &dsp_fck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | - CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, .clksel = dsp_irate_ick_clksel, @@ -1090,8 +1078,9 @@ static struct clk dsp_irate_ick = { /* 2420 only */ static struct clk dsp_ick = { .name = "dsp_ick", /* apparently ipi and isp */ + .ops = &clkops_omap2_dflt_wait, .parent = &dsp_irate_ick, - .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ }; @@ -1099,8 +1088,9 @@ static struct clk dsp_ick = { /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ static struct clk iva2_1_ick = { .name = "iva2_1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &dsp_irate_ick, - .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, }; @@ -1112,9 +1102,9 @@ static struct clk iva2_1_ick = { */ static struct clk iva1_ifck = { .name = "iva1_ifck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | - RATE_PROPAGATES | DELAYED_APP, + .flags = CONFIG_PARTICIPANT | DELAYED_APP, .clkdm_name = "iva1_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, @@ -1129,8 +1119,8 @@ static struct clk iva1_ifck = { /* IVA1 mpu/int/i/f clocks are /2 of parent */ static struct clk iva1_mpu_int_ifck = { .name = "iva1_mpu_int_ifck", + .ops = &clkops_omap2_dflt_wait, .parent = &iva1_ifck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "iva1_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, @@ -1175,10 +1165,9 @@ static const struct clksel core_l3_clksel[] = { static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ .name = "core_l3_ck", + .ops = &clkops_null, .parent = &core_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP | - CONFIG_PARTICIPANT | RATE_PROPAGATES, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "core_l3_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, @@ -1204,9 +1193,9 @@ static const struct clksel usb_l4_ick_clksel[] = { /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ static struct clk usb_l4_ick = { /* FS-USB interface clock */ .name = "usb_l4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - DELAYED_APP | CONFIG_PARTICIPANT, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_USB_SHIFT, @@ -1238,9 +1227,9 @@ static const struct clksel l4_clksel[] = { static struct clk l4_ck = { /* used both as an ick and fck */ .name = "l4_ck", + .ops = &clkops_null, .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, + .flags = DELAYED_APP, .clkdm_name = "core_l4_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, @@ -1276,9 +1265,9 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = { static struct clk ssi_ssr_sst_fck = { .name = "ssi_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - DELAYED_APP, + .flags = DELAYED_APP, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_SSI_SHIFT, @@ -1290,6 +1279,20 @@ static struct clk ssi_ssr_sst_fck = { .set_rate = &omap2_clksel_set_rate }; +/* + * Presumably this is the same as SSI_ICLK. + * TRM contradicts itself on what clockdomain SSI_ICLK is in + */ +static struct clk ssi_l4_ick = { + .name = "ssi_l4_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &l4_ck, + .clkdm_name = "core_l4_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_SSI_SHIFT, + .recalc = &followparent_recalc, +}; + /* * GFX clock domain @@ -1312,8 +1315,8 @@ static const struct clksel gfx_fck_clksel[] = { static struct clk gfx_3d_fck = { .name = "gfx_3d_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "gfx_clkdm", .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_3D_SHIFT, @@ -1327,8 +1330,8 @@ static struct clk gfx_3d_fck = { static struct clk gfx_2d_fck = { .name = "gfx_2d_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "gfx_clkdm", .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_2D_SHIFT, @@ -1342,8 +1345,8 @@ static struct clk gfx_2d_fck = { static struct clk gfx_ick = { .name = "gfx_ick", /* From l3 */ + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "gfx_clkdm", .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, @@ -1372,8 +1375,9 @@ static const struct clksel mdm_ick_clksel[] = { static struct clk mdm_ick = { /* used both as a ick and fck */ .name = "mdm_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "mdm_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, @@ -1387,8 +1391,8 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ static struct clk mdm_osc_ck = { .name = "mdm_osc_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &osc_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "mdm_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), .enable_bit = OMAP2430_EN_OSC_SHIFT, @@ -1432,8 +1436,8 @@ static const struct clksel dss1_fck_clksel[] = { static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ .name = "dss_ick", + .ops = &clkops_omap2_dflt, .parent = &l4_ck, /* really both l3 and l4 */ - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "dss_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_DSS1_SHIFT, @@ -1442,9 +1446,9 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ static struct clk dss1_fck = { .name = "dss1_fck", + .ops = &clkops_omap2_dflt, .parent = &core_ck, /* Core or sys */ - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - DELAYED_APP, + .flags = DELAYED_APP, .clkdm_name = "dss_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_DSS1_SHIFT, @@ -1475,9 +1479,9 @@ static const struct clksel dss2_fck_clksel[] = { static struct clk dss2_fck = { /* Alt clk used in power management */ .name = "dss2_fck", + .ops = &clkops_omap2_dflt, .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - DELAYED_APP, + .flags = DELAYED_APP, .clkdm_name = "dss_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_DSS2_SHIFT, @@ -1490,8 +1494,8 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ static struct clk dss_54m_fck = { /* Alt clk used in power management */ .name = "dss_54m_fck", /* 54m tv clk */ + .ops = &clkops_omap2_dflt_wait, .parent = &func_54m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "dss_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_TV_SHIFT, @@ -1518,8 +1522,8 @@ static const struct clksel omap24xx_gpt_clksel[] = { static struct clk gpt1_ick = { .name = "gpt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, @@ -1528,8 +1532,8 @@ static struct clk gpt1_ick = { static struct clk gpt1_fck = { .name = "gpt1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, @@ -1544,8 +1548,8 @@ static struct clk gpt1_fck = { static struct clk gpt2_ick = { .name = "gpt2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT2_SHIFT, @@ -1554,8 +1558,8 @@ static struct clk gpt2_ick = { static struct clk gpt2_fck = { .name = "gpt2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT2_SHIFT, @@ -1568,8 +1572,8 @@ static struct clk gpt2_fck = { static struct clk gpt3_ick = { .name = "gpt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT3_SHIFT, @@ -1578,8 +1582,8 @@ static struct clk gpt3_ick = { static struct clk gpt3_fck = { .name = "gpt3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT3_SHIFT, @@ -1592,8 +1596,8 @@ static struct clk gpt3_fck = { static struct clk gpt4_ick = { .name = "gpt4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT4_SHIFT, @@ -1602,8 +1606,8 @@ static struct clk gpt4_ick = { static struct clk gpt4_fck = { .name = "gpt4_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT4_SHIFT, @@ -1616,8 +1620,8 @@ static struct clk gpt4_fck = { static struct clk gpt5_ick = { .name = "gpt5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT5_SHIFT, @@ -1626,8 +1630,8 @@ static struct clk gpt5_ick = { static struct clk gpt5_fck = { .name = "gpt5_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT5_SHIFT, @@ -1640,8 +1644,8 @@ static struct clk gpt5_fck = { static struct clk gpt6_ick = { .name = "gpt6_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT6_SHIFT, @@ -1650,8 +1654,8 @@ static struct clk gpt6_ick = { static struct clk gpt6_fck = { .name = "gpt6_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT6_SHIFT, @@ -1664,8 +1668,8 @@ static struct clk gpt6_fck = { static struct clk gpt7_ick = { .name = "gpt7_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, .recalc = &followparent_recalc, @@ -1673,8 +1677,8 @@ static struct clk gpt7_ick = { static struct clk gpt7_fck = { .name = "gpt7_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, @@ -1687,8 +1691,8 @@ static struct clk gpt7_fck = { static struct clk gpt8_ick = { .name = "gpt8_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT8_SHIFT, @@ -1697,8 +1701,8 @@ static struct clk gpt8_ick = { static struct clk gpt8_fck = { .name = "gpt8_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT8_SHIFT, @@ -1711,8 +1715,8 @@ static struct clk gpt8_fck = { static struct clk gpt9_ick = { .name = "gpt9_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT9_SHIFT, @@ -1721,8 +1725,8 @@ static struct clk gpt9_ick = { static struct clk gpt9_fck = { .name = "gpt9_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT9_SHIFT, @@ -1735,8 +1739,8 @@ static struct clk gpt9_fck = { static struct clk gpt10_ick = { .name = "gpt10_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT10_SHIFT, @@ -1745,8 +1749,8 @@ static struct clk gpt10_ick = { static struct clk gpt10_fck = { .name = "gpt10_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT10_SHIFT, @@ -1759,8 +1763,8 @@ static struct clk gpt10_fck = { static struct clk gpt11_ick = { .name = "gpt11_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT11_SHIFT, @@ -1769,8 +1773,8 @@ static struct clk gpt11_ick = { static struct clk gpt11_fck = { .name = "gpt11_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT11_SHIFT, @@ -1783,8 +1787,8 @@ static struct clk gpt11_fck = { static struct clk gpt12_ick = { .name = "gpt12_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, @@ -1793,8 +1797,8 @@ static struct clk gpt12_ick = { static struct clk gpt12_fck = { .name = "gpt12_fck", - .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, + .ops = &clkops_omap2_dflt_wait, + .parent = &secure_32k_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, @@ -1807,9 +1811,9 @@ static struct clk gpt12_fck = { static struct clk mcbsp1_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, @@ -1818,9 +1822,9 @@ static struct clk mcbsp1_ick = { static struct clk mcbsp1_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, @@ -1829,9 +1833,9 @@ static struct clk mcbsp1_fck = { static struct clk mcbsp2_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, @@ -1840,9 +1844,9 @@ static struct clk mcbsp2_ick = { static struct clk mcbsp2_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, @@ -1851,9 +1855,9 @@ static struct clk mcbsp2_fck = { static struct clk mcbsp3_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, @@ -1862,9 +1866,9 @@ static struct clk mcbsp3_ick = { static struct clk mcbsp3_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, @@ -1873,9 +1877,9 @@ static struct clk mcbsp3_fck = { static struct clk mcbsp4_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, @@ -1884,9 +1888,9 @@ static struct clk mcbsp4_ick = { static struct clk mcbsp4_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, @@ -1895,9 +1899,9 @@ static struct clk mcbsp4_fck = { static struct clk mcbsp5_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 5, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, @@ -1906,9 +1910,9 @@ static struct clk mcbsp5_ick = { static struct clk mcbsp5_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 5, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, @@ -1917,10 +1921,10 @@ static struct clk mcbsp5_fck = { static struct clk mcspi1_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, .recalc = &followparent_recalc, @@ -1928,9 +1932,9 @@ static struct clk mcspi1_ick = { static struct clk mcspi1_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_48m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, @@ -1939,9 +1943,9 @@ static struct clk mcspi1_fck = { static struct clk mcspi2_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, @@ -1950,9 +1954,9 @@ static struct clk mcspi2_ick = { static struct clk mcspi2_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_48m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, @@ -1961,9 +1965,9 @@ static struct clk mcspi2_fck = { static struct clk mcspi3_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, @@ -1972,9 +1976,9 @@ static struct clk mcspi3_ick = { static struct clk mcspi3_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &func_48m_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, @@ -1983,8 +1987,8 @@ static struct clk mcspi3_fck = { static struct clk uart1_ick = { .name = "uart1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_UART1_SHIFT, @@ -1993,8 +1997,8 @@ static struct clk uart1_ick = { static struct clk uart1_fck = { .name = "uart1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_UART1_SHIFT, @@ -2003,8 +2007,8 @@ static struct clk uart1_fck = { static struct clk uart2_ick = { .name = "uart2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_UART2_SHIFT, @@ -2013,8 +2017,8 @@ static struct clk uart2_ick = { static struct clk uart2_fck = { .name = "uart2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_UART2_SHIFT, @@ -2023,8 +2027,8 @@ static struct clk uart2_fck = { static struct clk uart3_ick = { .name = "uart3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_UART3_SHIFT, @@ -2033,8 +2037,8 @@ static struct clk uart3_ick = { static struct clk uart3_fck = { .name = "uart3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_UART3_SHIFT, @@ -2043,8 +2047,8 @@ static struct clk uart3_fck = { static struct clk gpios_ick = { .name = "gpios_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, @@ -2053,8 +2057,8 @@ static struct clk gpios_ick = { static struct clk gpios_fck = { .name = "gpios_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, @@ -2063,8 +2067,8 @@ static struct clk gpios_fck = { static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, @@ -2073,8 +2077,8 @@ static struct clk mpu_wdt_ick = { static struct clk mpu_wdt_fck = { .name = "mpu_wdt_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, @@ -2083,9 +2087,9 @@ static struct clk mpu_wdt_fck = { static struct clk sync_32k_ick = { .name = "sync_32k_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ENABLE_ON_INIT, + .flags = ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, @@ -2094,8 +2098,8 @@ static struct clk sync_32k_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_WDT1_SHIFT, @@ -2104,9 +2108,9 @@ static struct clk wdt1_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ENABLE_ON_INIT, + .flags = ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, @@ -2115,8 +2119,8 @@ static struct clk omapctrl_ick = { static struct clk icr_ick = { .name = "icr_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP2430_EN_ICR_SHIFT, @@ -2125,8 +2129,8 @@ static struct clk icr_ick = { static struct clk cam_ick = { .name = "cam_ick", + .ops = &clkops_omap2_dflt, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_CAM_SHIFT, @@ -2140,8 +2144,8 @@ static struct clk cam_ick = { */ static struct clk cam_fck = { .name = "cam_fck", + .ops = &clkops_omap2_dflt, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_CAM_SHIFT, @@ -2150,8 +2154,8 @@ static struct clk cam_fck = { static struct clk mailboxes_ick = { .name = "mailboxes_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, @@ -2160,8 +2164,8 @@ static struct clk mailboxes_ick = { static struct clk wdt4_ick = { .name = "wdt4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_WDT4_SHIFT, @@ -2170,8 +2174,8 @@ static struct clk wdt4_ick = { static struct clk wdt4_fck = { .name = "wdt4_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_WDT4_SHIFT, @@ -2180,8 +2184,8 @@ static struct clk wdt4_fck = { static struct clk wdt3_ick = { .name = "wdt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_WDT3_SHIFT, @@ -2190,8 +2194,8 @@ static struct clk wdt3_ick = { static struct clk wdt3_fck = { .name = "wdt3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_WDT3_SHIFT, @@ -2200,8 +2204,8 @@ static struct clk wdt3_fck = { static struct clk mspro_ick = { .name = "mspro_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, @@ -2210,8 +2214,8 @@ static struct clk mspro_ick = { static struct clk mspro_fck = { .name = "mspro_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, @@ -2220,8 +2224,8 @@ static struct clk mspro_fck = { static struct clk mmc_ick = { .name = "mmc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_MMC_SHIFT, @@ -2230,8 +2234,8 @@ static struct clk mmc_ick = { static struct clk mmc_fck = { .name = "mmc_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_MMC_SHIFT, @@ -2240,8 +2244,8 @@ static struct clk mmc_fck = { static struct clk fac_ick = { .name = "fac_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_FAC_SHIFT, @@ -2250,8 +2254,8 @@ static struct clk fac_ick = { static struct clk fac_fck = { .name = "fac_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_12m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_FAC_SHIFT, @@ -2260,8 +2264,8 @@ static struct clk fac_fck = { static struct clk eac_ick = { .name = "eac_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_EAC_SHIFT, @@ -2270,8 +2274,8 @@ static struct clk eac_ick = { static struct clk eac_fck = { .name = "eac_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_EAC_SHIFT, @@ -2280,8 +2284,8 @@ static struct clk eac_fck = { static struct clk hdq_ick = { .name = "hdq_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_HDQ_SHIFT, @@ -2290,8 +2294,8 @@ static struct clk hdq_ick = { static struct clk hdq_fck = { .name = "hdq_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_12m_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_HDQ_SHIFT, @@ -2300,9 +2304,9 @@ static struct clk hdq_fck = { static struct clk i2c2_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_I2C2_SHIFT, @@ -2311,9 +2315,9 @@ static struct clk i2c2_ick = { static struct clk i2c2_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_12m_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_I2C2_SHIFT, @@ -2322,9 +2326,9 @@ static struct clk i2c2_fck = { static struct clk i2chs2_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, @@ -2333,9 +2337,9 @@ static struct clk i2chs2_fck = { static struct clk i2c1_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_I2C1_SHIFT, @@ -2344,9 +2348,9 @@ static struct clk i2c1_ick = { static struct clk i2c1_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_12m_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_I2C1_SHIFT, @@ -2355,9 +2359,9 @@ static struct clk i2c1_fck = { static struct clk i2chs1_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, @@ -2366,33 +2370,33 @@ static struct clk i2chs1_fck = { static struct clk gpmc_fck = { .name = "gpmc_fck", + .ops = &clkops_null, /* RMK: missing? */ .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ENABLE_ON_INIT, + .flags = ENABLE_ON_INIT, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk sdma_fck = { .name = "sdma_fck", + .ops = &clkops_null, /* RMK: missing? */ .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk sdma_ick = { .name = "sdma_ick", + .ops = &clkops_null, /* RMK: missing? */ .parent = &l4_ck, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk vlynq_ick = { .name = "vlynq_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, @@ -2426,8 +2430,9 @@ static const struct clksel vlynq_fck_clksel[] = { static struct clk vlynq_fck = { .name = "vlynq_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP242X | DELAYED_APP, + .flags = DELAYED_APP, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, @@ -2442,8 +2447,9 @@ static struct clk vlynq_fck = { static struct clk sdrc_ick = { .name = "sdrc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, + .flags = ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP2430_EN_SDRC_SHIFT, @@ -2452,8 +2458,8 @@ static struct clk sdrc_ick = { static struct clk des_ick = { .name = "des_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_DES_SHIFT, @@ -2462,8 +2468,8 @@ static struct clk des_ick = { static struct clk sha_ick = { .name = "sha_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_SHA_SHIFT, @@ -2472,8 +2478,8 @@ static struct clk sha_ick = { static struct clk rng_ick = { .name = "rng_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_RNG_SHIFT, @@ -2482,8 +2488,8 @@ static struct clk rng_ick = { static struct clk aes_ick = { .name = "aes_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_AES_SHIFT, @@ -2492,8 +2498,8 @@ static struct clk aes_ick = { static struct clk pka_ick = { .name = "pka_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_PKA_SHIFT, @@ -2502,8 +2508,8 @@ static struct clk pka_ick = { static struct clk usb_fck = { .name = "usb_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, - .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_USB_SHIFT, @@ -2512,8 +2518,8 @@ static struct clk usb_fck = { static struct clk usbhs_ick = { .name = "usbhs_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_USBHS_SHIFT, @@ -2522,8 +2528,8 @@ static struct clk usbhs_ick = { static struct clk mmchs1_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, @@ -2532,8 +2538,8 @@ static struct clk mmchs1_ick = { static struct clk mmchs1_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, @@ -2542,9 +2548,9 @@ static struct clk mmchs1_fck = { static struct clk mmchs2_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, @@ -2553,9 +2559,9 @@ static struct clk mmchs2_ick = { static struct clk mmchs2_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, - .flags = CLOCK_IN_OMAP243X, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, .recalc = &followparent_recalc, @@ -2563,8 +2569,8 @@ static struct clk mmchs2_fck = { static struct clk gpio5_ick = { .name = "gpio5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_GPIO5_SHIFT, @@ -2573,8 +2579,8 @@ static struct clk gpio5_ick = { static struct clk gpio5_fck = { .name = "gpio5_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_GPIO5_SHIFT, @@ -2583,8 +2589,8 @@ static struct clk gpio5_fck = { static struct clk mdm_intc_ick = { .name = "mdm_intc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, @@ -2593,8 +2599,8 @@ static struct clk mdm_intc_ick = { static struct clk mmchsdb1_fck = { .name = "mmchsdb_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, @@ -2603,9 +2609,9 @@ static struct clk mmchsdb1_fck = { static struct clk mmchsdb2_fck = { .name = "mmchsdb_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_32k_ck, - .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, @@ -2628,166 +2634,13 @@ static struct clk mmchsdb2_fck = { */ static struct clk virt_prcm_set = { .name = "virt_prcm_set", - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, + .ops = &clkops_null, + .flags = DELAYED_APP, .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ .set_rate = &omap2_select_table_rate, .round_rate = &omap2_round_to_table_rate, }; -static struct clk *onchip_24xx_clks[] __initdata = { - /* external root sources */ - &func_32k_ck, - &osc_ck, - &sys_ck, - &alt_ck, - /* internal analog sources */ - &dpll_ck, - &apll96_ck, - &apll54_ck, - /* internal prcm root sources */ - &func_54m_ck, - &core_ck, - &func_96m_ck, - &func_48m_ck, - &func_12m_ck, - &wdt1_osc_ck, - &sys_clkout_src, - &sys_clkout, - &sys_clkout2_src, - &sys_clkout2, - &emul_ck, - /* mpu domain clocks */ - &mpu_ck, - /* dsp domain clocks */ - &dsp_fck, - &dsp_irate_ick, - &dsp_ick, /* 242x */ - &iva2_1_ick, /* 243x */ - &iva1_ifck, /* 242x */ - &iva1_mpu_int_ifck, /* 242x */ - /* GFX domain clocks */ - &gfx_3d_fck, - &gfx_2d_fck, - &gfx_ick, - /* Modem domain clocks */ - &mdm_ick, - &mdm_osc_ck, - /* DSS domain clocks */ - &dss_ick, - &dss1_fck, - &dss2_fck, - &dss_54m_fck, - /* L3 domain clocks */ - &core_l3_ck, - &ssi_ssr_sst_fck, - &usb_l4_ick, - /* L4 domain clocks */ - &l4_ck, /* used as both core_l4 and wu_l4 */ - /* virtual meta-group clock */ - &virt_prcm_set, - /* general l4 interface ck, multi-parent functional clk */ - &gpt1_ick, - &gpt1_fck, - &gpt2_ick, - &gpt2_fck, - &gpt3_ick, - &gpt3_fck, - &gpt4_ick, - &gpt4_fck, - &gpt5_ick, - &gpt5_fck, - &gpt6_ick, - &gpt6_fck, - &gpt7_ick, - &gpt7_fck, - &gpt8_ick, - &gpt8_fck, - &gpt9_ick, - &gpt9_fck, - &gpt10_ick, - &gpt10_fck, - &gpt11_ick, - &gpt11_fck, - &gpt12_ick, - &gpt12_fck, - &mcbsp1_ick, - &mcbsp1_fck, - &mcbsp2_ick, - &mcbsp2_fck, - &mcbsp3_ick, - &mcbsp3_fck, - &mcbsp4_ick, - &mcbsp4_fck, - &mcbsp5_ick, - &mcbsp5_fck, - &mcspi1_ick, - &mcspi1_fck, - &mcspi2_ick, - &mcspi2_fck, - &mcspi3_ick, - &mcspi3_fck, - &uart1_ick, - &uart1_fck, - &uart2_ick, - &uart2_fck, - &uart3_ick, - &uart3_fck, - &gpios_ick, - &gpios_fck, - &mpu_wdt_ick, - &mpu_wdt_fck, - &sync_32k_ick, - &wdt1_ick, - &omapctrl_ick, - &icr_ick, - &cam_fck, - &cam_ick, - &mailboxes_ick, - &wdt4_ick, - &wdt4_fck, - &wdt3_ick, - &wdt3_fck, - &mspro_ick, - &mspro_fck, - &mmc_ick, - &mmc_fck, - &fac_ick, - &fac_fck, - &eac_ick, - &eac_fck, - &hdq_ick, - &hdq_fck, - &i2c1_ick, - &i2c1_fck, - &i2chs1_fck, - &i2c2_ick, - &i2c2_fck, - &i2chs2_fck, - &gpmc_fck, - &sdma_fck, - &sdma_ick, - &vlynq_ick, - &vlynq_fck, - &sdrc_ick, - &des_ick, - &sha_ick, - &rng_ick, - &aes_ick, - &pka_ick, - &usb_fck, - &usbhs_ick, - &mmchs1_ick, - &mmchs1_fck, - &mmchs2_ick, - &mmchs2_fck, - &gpio5_ick, - &gpio5_fck, - &mdm_intc_ick, - &mmchsdb1_fck, - &mmchsdb2_fck, -}; - #endif |