diff options
Diffstat (limited to 'arch/arm/mach-s5pc100/gpiolib.c')
| -rw-r--r-- | arch/arm/mach-s5pc100/gpiolib.c | 216 |
1 files changed, 72 insertions, 144 deletions
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index 0fab7f2..20856eb 100644 --- a/arch/arm/mach-s5pc100/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c @@ -1,5 +1,7 @@ -/* - * arch/arm/plat-s5pc100/gpiolib.c +/* linux/arch/arm/mach-s5pc100/gpiolib.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com * * Copyright 2009 Samsung Electronics Co * Kyungmin Park <kyungmin.park@samsung.com> @@ -61,30 +63,6 @@ * L3 8 4Bit None */ -static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) -{ - return S3C_IRQ_GPIO(chip->base + offset); -} - -static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) -{ - int base; - - base = chip->base - S5PC100_GPH0(0); - if (base == 0) - return IRQ_EINT(offset); - base = chip->base - S5PC100_GPH1(0); - if (base == 0) - return IRQ_EINT(8 + offset); - base = chip->base - S5PC100_GPH2(0); - if (base == 0) - return IRQ_EINT(16 + offset); - base = chip->base - S5PC100_GPH3(0); - if (base == 0) - return IRQ_EINT(24 + offset); - return -EINVAL; -} - static struct s3c_gpio_cfg gpio_cfg = { .set_config = s3c_gpio_setcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, @@ -104,209 +82,150 @@ static struct s3c_gpio_cfg gpio_cfg_noint = { .get_pull = s3c_gpio_getpull_updown, }; +/* + * GPIO bank's base address given the index of the bank in the + * list of all gpio banks. + */ +#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) + +/* + * Following are the gpio banks in S5PC100. + * + * The 'config' member when left to NULL, is initialized to the default + * structure gpio_cfg in the init function below. + * + * The 'base' member is also initialized in the init function below. + * Note: The initialization of 'base' member of s3c_gpio_chip structure + * uses the above macro and depends on the banks being listed in order here. + */ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { { - .base = S5PC100_GPA0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPA0(0), .ngpio = S5PC100_GPIO_A0_NR, .label = "GPA0", }, }, { - .base = S5PC100_GPA1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPA1(0), .ngpio = S5PC100_GPIO_A1_NR, .label = "GPA1", }, }, { - .base = S5PC100_GPB_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPB(0), .ngpio = S5PC100_GPIO_B_NR, .label = "GPB", }, }, { - .base = S5PC100_GPC_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPC(0), .ngpio = S5PC100_GPIO_C_NR, .label = "GPC", }, }, { - .base = S5PC100_GPD_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPD(0), .ngpio = S5PC100_GPIO_D_NR, .label = "GPD", }, }, { - .base = S5PC100_GPE0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPE0(0), .ngpio = S5PC100_GPIO_E0_NR, .label = "GPE0", }, }, { - .base = S5PC100_GPE1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPE1(0), .ngpio = S5PC100_GPIO_E1_NR, .label = "GPE1", }, }, { - .base = S5PC100_GPF0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPF0(0), .ngpio = S5PC100_GPIO_F0_NR, .label = "GPF0", }, }, { - .base = S5PC100_GPF1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPF1(0), .ngpio = S5PC100_GPIO_F1_NR, .label = "GPF1", }, }, { - .base = S5PC100_GPF2_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPF2(0), .ngpio = S5PC100_GPIO_F2_NR, .label = "GPF2", }, }, { - .base = S5PC100_GPF3_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPF3(0), .ngpio = S5PC100_GPIO_F3_NR, .label = "GPF3", }, }, { - .base = S5PC100_GPG0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPG0(0), .ngpio = S5PC100_GPIO_G0_NR, .label = "GPG0", }, }, { - .base = S5PC100_GPG1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPG1(0), .ngpio = S5PC100_GPIO_G1_NR, .label = "GPG1", }, }, { - .base = S5PC100_GPG2_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPG2(0), .ngpio = S5PC100_GPIO_G2_NR, .label = "GPG2", }, }, { - .base = S5PC100_GPG3_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPG3(0), .ngpio = S5PC100_GPIO_G3_NR, .label = "GPG3", }, }, { - .base = S5PC100_GPH0_BASE, - .config = &gpio_cfg_eint, - .chip = { - .base = S5PC100_GPH0(0), - .ngpio = S5PC100_GPIO_H0_NR, - .label = "GPH0", - }, - }, { - .base = S5PC100_GPH1_BASE, - .config = &gpio_cfg_eint, - .chip = { - .base = S5PC100_GPH1(0), - .ngpio = S5PC100_GPIO_H1_NR, - .label = "GPH1", - }, - }, { - .base = S5PC100_GPH2_BASE, - .config = &gpio_cfg_eint, - .chip = { - .base = S5PC100_GPH2(0), - .ngpio = S5PC100_GPIO_H2_NR, - .label = "GPH2", - }, - }, { - .base = S5PC100_GPH3_BASE, - .config = &gpio_cfg_eint, - .chip = { - .base = S5PC100_GPH3(0), - .ngpio = S5PC100_GPIO_H3_NR, - .label = "GPH3", - }, - }, { - .base = S5PC100_GPI_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPI(0), .ngpio = S5PC100_GPIO_I_NR, .label = "GPI", }, }, { - .base = S5PC100_GPJ0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ0(0), .ngpio = S5PC100_GPIO_J0_NR, .label = "GPJ0", }, }, { - .base = S5PC100_GPJ1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ1(0), .ngpio = S5PC100_GPIO_J1_NR, .label = "GPJ1", }, }, { - .base = S5PC100_GPJ2_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ2(0), .ngpio = S5PC100_GPIO_J2_NR, .label = "GPJ2", }, }, { - .base = S5PC100_GPJ3_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ3(0), .ngpio = S5PC100_GPIO_J3_NR, .label = "GPJ3", }, }, { - .base = S5PC100_GPJ4_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ4(0), .ngpio = S5PC100_GPIO_J4_NR, .label = "GPJ4", }, }, { - .base = S5PC100_GPK0_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPK0(0), @@ -314,7 +233,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPK0", }, }, { - .base = S5PC100_GPK1_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPK1(0), @@ -322,7 +240,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPK1", }, }, { - .base = S5PC100_GPK2_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPK2(0), @@ -330,7 +247,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPK2", }, }, { - .base = S5PC100_GPK3_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPK3(0), @@ -338,7 +254,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPK3", }, }, { - .base = S5PC100_GPL0_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL0(0), @@ -346,7 +261,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPL0", }, }, { - .base = S5PC100_GPL1_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL1(0), @@ -354,7 +268,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPL1", }, }, { - .base = S5PC100_GPL2_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL2(0), @@ -362,7 +275,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPL2", }, }, { - .base = S5PC100_GPL3_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL3(0), @@ -370,56 +282,72 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPL3", }, }, { - .base = S5PC100_GPL4_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL4(0), .ngpio = S5PC100_GPIO_L4_NR, .label = "GPL4", }, + }, { + .base = (S5P_VA_GPIO + 0xC00), + .config = &gpio_cfg_eint, + .irq_base = IRQ_EINT(0), + .chip = { + .base = S5PC100_GPH0(0), + .ngpio = S5PC100_GPIO_H0_NR, + .label = "GPH0", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC20), + .config = &gpio_cfg_eint, + .irq_base = IRQ_EINT(8), + .chip = { + .base = S5PC100_GPH1(0), + .ngpio = S5PC100_GPIO_H1_NR, + .label = "GPH1", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC40), + .config = &gpio_cfg_eint, + .irq_base = IRQ_EINT(16), + .chip = { + .base = S5PC100_GPH2(0), + .ngpio = S5PC100_GPIO_H2_NR, + .label = "GPH2", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC60), + .config = &gpio_cfg_eint, + .irq_base = IRQ_EINT(24), + .chip = { + .base = S5PC100_GPH3(0), + .ngpio = S5PC100_GPIO_H3_NR, + .label = "GPH3", + .to_irq = samsung_gpiolib_to_irq, + }, }, }; -/* FIXME move from irq-gpio.c */ -extern struct irq_chip s5pc100_gpioint; -extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); - -static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) +static __init int s5pc100_gpiolib_init(void) { - /* Interrupt */ - if (chip->config == &gpio_cfg) { - int i, irq; - - chip->chip.to_irq = s5pc100_gpiolib_to_irq; + struct s3c_gpio_chip *chip = s5pc100_gpio_chips; + int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); + int gpioint_group = 0; + int i; - for (i = 0; i < chip->chip.ngpio; i++) { - irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; - set_irq_chip(irq, &s5pc100_gpioint); - set_irq_data(irq, &chip->chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); + for (i = 0; i < nr_chips; i++, chip++) { + if (chip->config == NULL) { + chip->config = &gpio_cfg; + chip->group = gpioint_group++; } - } else if (chip->config == &gpio_cfg_eint) { - chip->chip.to_irq = s5pc100_gpiolib_to_eint; + if (chip->base == NULL) + chip->base = S5PC100_BANK_BASE(i); } -} - -static __init int s5pc100_gpiolib_init(void) -{ - struct s3c_gpio_chip *chip; - int nr_chips; - - chip = s5pc100_gpio_chips; - nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); - - for (; nr_chips > 0; nr_chips--, chip++) - s5pc100_gpiolib_link(chip); - - samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, - ARRAY_SIZE(s5pc100_gpio_chips)); - /* Interrupt */ - set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler); + samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips); return 0; } |