diff options
Diffstat (limited to 'arch/arm')
625 files changed, 12412 insertions, 17068 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7bbb035..611c98d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -3,7 +3,7 @@ config ARM default y select HAVE_AOUT select HAVE_DMA_API_DEBUG - select HAVE_IDE + select HAVE_IDE if PCI || ISA || PCMCIA select HAVE_MEMBLOCK select RTC_LIB select SYS_SUPPORTS_APM_EMULATION @@ -226,6 +226,10 @@ config PHYS_OFFSET Please provide the physical address corresponding to the location of main memory in your system. +config GENERIC_BUG + def_bool y + depends on BUG + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -359,7 +363,6 @@ config ARCH_GEMINI config ARCH_PRIMA2 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" select CPU_V7 - select GENERIC_TIME select NO_IOPORT select GENERIC_CLOCKEVENTS select CLKDEV_LOOKUP @@ -391,7 +394,7 @@ config ARCH_EP93XX select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_USES_GETTIMEOFFSET - select NEED_MEMORY_H + select NEED_MACH_MEMORY_H help This enables support for the Cirrus EP93xx series of CPUs. @@ -400,6 +403,7 @@ config ARCH_FOOTBRIDGE select CPU_SA110 select FOOTBRIDGE select GENERIC_CLOCKEVENTS + select HAVE_IDE select NEED_MACH_MEMORY_H help Support for systems based on the DC21285 companion chip @@ -538,7 +542,6 @@ config ARCH_LPC32XX select ARM_AMBA select USB_ARCH_HAS_OHCI select CLKDEV_LOOKUP - select GENERIC_TIME select GENERIC_CLOCKEVENTS help Support for the NXP LPC32XX family of processors @@ -606,19 +609,10 @@ config ARCH_W90X900 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> -config ARCH_NUC93X - bool "Nuvoton NUC93X CPU" - select CPU_ARM926T - select CLKDEV_LOOKUP - help - Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a - low-power and high performance MPEG-4/JPEG multimedia controller chip. - config ARCH_TEGRA bool "NVIDIA Tegra" select CLKDEV_LOOKUP select CLKSRC_MMIO - select GENERIC_TIME select GENERIC_CLOCKEVENTS select GENERIC_GPIO select HAVE_CLK @@ -651,6 +645,8 @@ config ARCH_PXA select SPARSE_IRQ select AUTO_ZRELADDR select MULTI_IRQ_HANDLER + select ARM_CPU_SUSPEND if PM + select HAVE_IDE help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. @@ -692,6 +688,7 @@ config ARCH_RPC select NO_IOPORT select ARCH_SPARSEMEM_ENABLE select ARCH_USES_GETTIMEOFFSET + select HAVE_IDE select NEED_MACH_MEMORY_H help On the Acorn Risc-PC, Linux can support the internal IDE disk and @@ -711,6 +708,7 @@ config ARCH_SA1100 select HAVE_SCHED_CLOCK select TICK_ONESHOT select ARCH_REQUIRE_GPIOLIB + select HAVE_IDE select NEED_MACH_MEMORY_H help Support for StrongARM 11x0 based boards. @@ -745,7 +743,6 @@ config ARCH_S3C64XX select ARCH_REQUIRE_GPIOLIB select SAMSUNG_CLKSRC select SAMSUNG_IRQ_VIC_TIMER - select SAMSUNG_IRQ_UART select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX @@ -856,6 +853,7 @@ config ARCH_U300 select HAVE_SCHED_CLOCK select HAVE_TCM select ARM_AMBA + select ARM_PATCH_PHYS_VIRT select ARM_VIC select GENERIC_CLOCKEVENTS select CLKDEV_LOOKUP @@ -938,7 +936,6 @@ config ARCH_VT8500 config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" select CPU_V7 - select GENERIC_TIME select GENERIC_CLOCKEVENTS select CLKDEV_LOOKUP select ARM_GIC @@ -1007,8 +1004,6 @@ source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" source "arch/arm/plat-nomadik/Kconfig" -source "arch/arm/mach-nuc93x/Kconfig" - source "arch/arm/plat-omap/Kconfig" source "arch/arm/mach-omap1/Kconfig" @@ -1403,6 +1398,7 @@ config SMP MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE + depends on MMU select USE_GENERIC_SMP_HELPERS select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP help @@ -1416,7 +1412,7 @@ config SMP processor machines. On a single processor machine, the kernel will run faster if you say N here. - See also <file:Documentation/i386/IO-APIC.txt>, + See also <file:Documentation/x86/i386/IO-APIC.txt>, <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at <http://tldp.org/HOWTO/SMP-HOWTO.html>. @@ -1535,6 +1531,7 @@ config THUMB2_KERNEL depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL select AEABI select ARM_ASM_UNIFIED + select ARM_UNWIND help By enabling this option, the kernel will be compiled in Thumb-2 mode. A compiler/assembler that understand the unified @@ -2038,6 +2035,7 @@ config CPU_FREQ_PXA bool depends on CPU_FREQ && ARCH_PXA && PXA25x default y + select CPU_FREQ_TABLE select CPU_FREQ_DEFAULT_GOV_USERSPACE config CPU_FREQ_S3C @@ -2186,6 +2184,9 @@ config ARCH_SUSPEND_POSSIBLE CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE def_bool y +config ARM_CPU_SUSPEND + def_bool PM_SLEEP + endmenu source "net/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index be3a0f7..f283938 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -65,13 +65,71 @@ config DEBUG_USER # These options are only for real kernel hackers who want to get their hands dirty. config DEBUG_LL - bool "Kernel low-level debugging functions" + bool "Kernel low-level debugging functions (read help!)" depends on DEBUG_KERNEL help Say Y here to include definitions of printascii, printch, printhex in the kernel. This is helpful if you are debugging code that executes before the console is initialized. + Note that selecting this option will limit the kernel to a single + UART definition, as specified below. Attempting to boot the kernel + image on a different platform *will not work*, so this option should + not be enabled for kernels that are intended to be portable. + +choice + prompt "Kernel low-level debugging port" + depends on DEBUG_LL + + config DEBUG_LL_UART_NONE + bool "No low-level debugging UART" + help + Say Y here if your platform doesn't provide a UART option + below. This relies on your platform choosing the right UART + definition internally in order for low-level debugging to + work. + + config DEBUG_ICEDCC + bool "Kernel low-level debugging via EmbeddedICE DCC channel" + help + Say Y here if you want the debug print routines to direct + their output to the EmbeddedICE macrocell's DCC channel using + co-processor 14. This is known to work on the ARM9 style ICE + channel and on the XScale with the PEEDI. + + Note that the system will appear to hang during boot if there + is nothing connected to read from the DCC. + + config DEBUG_FOOTBRIDGE_COM1 + bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" + depends on FOOTBRIDGE + help + Say Y here if you want the debug print routines to direct + their output to the 8250 at PCI COM1. + + config DEBUG_DC21285_PORT + bool "Kernel low-level debugging messages via footbridge serial port" + depends on FOOTBRIDGE + help + Say Y here if you want the debug print routines to direct + their output to the serial port in the DC21285 (Footbridge). + + config DEBUG_CLPS711X_UART1 + bool "Kernel low-level debugging messages via UART1" + depends on ARCH_CLPS711X + help + Say Y here if you want the debug print routines to direct + their output to the first serial port on these devices. + + config DEBUG_CLPS711X_UART2 + bool "Kernel low-level debugging messages via UART2" + depends on ARCH_CLPS711X + help + Say Y here if you want the debug print routines to direct + their output to the second serial port on these devices. + +endchoice + config EARLY_PRINTK bool "Early printk" depends on DEBUG_LL @@ -80,43 +138,14 @@ config EARLY_PRINTK kernel low-level debugging functions. Add earlyprintk to your kernel parameters to enable this console. -config DEBUG_ICEDCC - bool "Kernel low-level debugging via EmbeddedICE DCC channel" - depends on DEBUG_LL - help - Say Y here if you want the debug print routines to direct their - output to the EmbeddedICE macrocell's DCC channel using - co-processor 14. This is known to work on the ARM9 style ICE - channel and on the XScale with the PEEDI. - - It does include a timeout to ensure that the system does not - totally freeze when there is nothing connected to read. - config OC_ETM bool "On-chip ETM and ETB" - select ARM_AMBA + depends on ARM_AMBA help Enables the on-chip embedded trace macrocell and embedded trace buffer driver that will allow you to collect traces of the kernel code. -config DEBUG_DC21285_PORT - bool "Kernel low-level debugging messages via footbridge serial port" - depends on DEBUG_LL && FOOTBRIDGE - help - Say Y here if you want the debug print routines to direct their - output to the serial port in the DC21285 (Footbridge). Saying N - will cause the debug messages to appear on the first 16550 - serial port. - -config DEBUG_CLPS711X_UART2 - bool "Kernel low-level debugging messages via UART2" - depends on DEBUG_LL && ARCH_CLPS711X - help - Say Y here if you want the debug print routines to direct their - output to the second serial port on these devices. Saying N will - cause the debug messages to appear on the first serial port. - config DEBUG_S3C_UART depends on PLAT_SAMSUNG int "S3C UART to use for low-level debug" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5665c2a..a5aac16 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -192,7 +192,6 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_VEXPRESS) := vexpress machine-$(CONFIG_ARCH_VT8500) := vt8500 machine-$(CONFIG_ARCH_W90X900) := w90x900 -machine-$(CONFIG_ARCH_NUC93X) := nuc93x machine-$(CONFIG_FOOTBRIDGE) := footbridge machine-$(CONFIG_MACH_SPEAR300) := spear3xx machine-$(CONFIG_MACH_SPEAR310) := spear3xx diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index a1edfd5..176062a 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -78,7 +78,16 @@ endif $(obj)/uImage: STARTADDR=$(LOADADDR) +check_for_multiple_loadaddr = \ +if [ $(words $(LOADADDR)) -gt 1 ]; then \ + echo 'multiple load addresses: $(LOADADDR)'; \ + echo 'This is incompatible with uImages'; \ + echo 'Specify LOADADDR on the commandline to build an uImage'; \ + false; \ +fi + $(obj)/uImage: $(obj)/zImage FORCE + @$(check_for_multiple_loadaddr) $(call if_changed,uimage) @echo ' Image $@ is ready' diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index e4f32a8..21f56ff 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -163,8 +163,16 @@ bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \ ( echo "following symbols must have non local/private scope:" >&2; \ echo "$$bad_syms" >&2; rm -f $@; false ) +check_for_multiple_zreladdr = \ +if [ $(words $(ZRELADDR)) -gt 1 -a "$(CONFIG_AUTO_ZRELADDR)" = "" ]; then \ + echo 'multiple zreladdrs: $(ZRELADDR)'; \ + echo 'This needs CONFIG_AUTO_ZRELADDR to be set'; \ + false; \ +fi + $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE + @$(check_for_multiple_zreladdr) $(call if_changed,ld) @$(check_for_bad_syms) diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts index 6fecc88..34ae3a6 100644 --- a/arch/arm/boot/dts/prima2-cb.dts +++ b/arch/arm/boot/dts/prima2-cb.dts @@ -39,9 +39,12 @@ ranges = <0x40000000 0x40000000 0x80000000>; l2-cache-controller@80040000 { - compatible = "arm,pl310-cache"; + compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; reg = <0x80040000 0x1000>; interrupts = <59>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0 0x40000000>; }; intc: interrupt-controller@80020000 { @@ -67,6 +70,11 @@ compatible = "sirf,prima2-rstc"; reg = <0x88010000 0x1000>; }; + + rsc-controller@88020000 { + compatible = "sirf,prima2-rsc"; + reg = <0x88020000 0x1000>; + }; }; mem-iobg { @@ -274,7 +282,7 @@ gpio: gpio-controller@b0120000 { #gpio-cells = <2>; #interrupt-cells = <2>; - compatible = "sirf,prima2-gpio"; + compatible = "sirf,prima2-gpio-pinmux"; reg = <0xb0120000 0x10000>; gpio-controller; interrupt-controller; @@ -358,7 +366,7 @@ }; rtc-iobg { - compatible = "sirf,prima2-rtciobg", "simple-bus"; + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x80030000 0x10000>; diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index e581866..0e225b8 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -66,5 +66,6 @@ cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ + support-8bit; }; }; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index 64cedca..a72299b 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -25,4 +25,8 @@ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ }; + + sdhci@c8000600 { + support-8bit; + }; }; diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 016c1ae..a8fc6b2 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -37,7 +37,7 @@ #include <asm/mach/irq.h> #include <asm/hardware/gic.h> -static DEFINE_SPINLOCK(irq_controller_lock); +static DEFINE_RAW_SPINLOCK(irq_controller_lock); /* Address of GIC 0 CPU interface */ void __iomem *gic_cpu_base_addr __read_mostly; @@ -86,30 +86,30 @@ static void gic_mask_irq(struct irq_data *d) { u32 mask = 1 << (d->irq % 32); - spin_lock(&irq_controller_lock); + raw_spin_lock(&irq_controller_lock); writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); if (gic_arch_extn.irq_mask) gic_arch_extn.irq_mask(d); - spin_unlock(&irq_controller_lock); + raw_spin_unlock(&irq_controller_lock); } static void gic_unmask_irq(struct irq_data *d) { u32 mask = 1 << (d->irq % 32); - spin_lock(&irq_controller_lock); + raw_spin_lock(&irq_controller_lock); if (gic_arch_extn.irq_unmask) gic_arch_extn.irq_unmask(d); writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); - spin_unlock(&irq_controller_lock); + raw_spin_unlock(&irq_controller_lock); } static void gic_eoi_irq(struct irq_data *d) { if (gic_arch_extn.irq_eoi) { - spin_lock(&irq_controller_lock); + raw_spin_lock(&irq_controller_lock); gic_arch_extn.irq_eoi(d); - spin_unlock(&irq_controller_lock); + raw_spin_unlock(&irq_controller_lock); } writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); @@ -133,7 +133,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) return -EINVAL; - spin_lock(&irq_controller_lock); + raw_spin_lock(&irq_controller_lock); if (gic_arch_extn.irq_set_type) gic_arch_extn.irq_set_type(d, type); @@ -158,7 +158,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) if (enabled) writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); - spin_unlock(&irq_controller_lock); + raw_spin_unlock(&irq_controller_lock); return 0; } @@ -186,10 +186,10 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, mask = 0xff << shift; bit = 1 << (cpu_logical_map(cpu) + shift); - spin_lock(&irq_controller_lock); + raw_spin_lock(&irq_controller_lock); val = readl_relaxed(reg) & ~mask; writel_relaxed(val | bit, reg); - spin_unlock(&irq_controller_lock); + raw_spin_unlock(&irq_controller_lock); return IRQ_SET_MASK_OK; } @@ -219,9 +219,9 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) chained_irq_enter(chip, desc); - spin_lock(&irq_controller_lock); + raw_spin_lock(&irq_controller_lock); status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); - spin_unlock(&irq_controller_lock); + raw_spin_unlock(&irq_controller_lock); gic_irq = (status & 0x3ff); if (gic_irq == 1023) diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index 97912fa..7129cfb 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c @@ -1546,7 +1546,7 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) /* Start the next */ case PL330_OP_START: - if (!_start(thrd)) + if (!_thrd_active(thrd) && !_start(thrd)) ret = -EIO; break; diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 0569de6..61691cd 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -718,6 +718,10 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) goto err_free; } + ret = clk_prepare(sachip->clk); + if (ret) + goto err_clkput; + spin_lock_init(&sachip->lock); sachip->dev = me; @@ -733,7 +737,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) sachip->base = ioremap(mem->start, PAGE_SIZE * 2); if (!sachip->base) { ret = -ENOMEM; - goto err_clkput; + goto err_clk_unprep; } /* @@ -809,6 +813,8 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) err_unmap: iounmap(sachip->base); + err_clk_unprep: + clk_unprepare(sachip->clk); err_clkput: clk_put(sachip->clk); err_free: @@ -835,6 +841,7 @@ static void __sa1111_remove(struct sa1111 *sachip) sa1111_writel(0, irqbase + SA1111_WAKEEN1); clk_disable(sachip->clk); + clk_unprepare(sachip->clk); if (sachip->irq != NO_IRQ) { irq_set_chained_handler(sachip->irq, NULL); diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c index 41df478..2393b5b 100644 --- a/arch/arm/common/timer-sp.c +++ b/arch/arm/common/timer-sp.c @@ -41,9 +41,17 @@ static long __init sp804_get_clock_rate(const char *name) return PTR_ERR(clk); } + err = clk_prepare(clk); + if (err) { + pr_err("sp804: %s clock failed to prepare: %d\n", name, err); + clk_put(clk); + return err; + } + err = clk_enable(clk); if (err) { pr_err("sp804: %s clock failed to enable: %d\n", name, err); + clk_unprepare(clk); clk_put(clk); return err; } @@ -52,6 +60,7 @@ static long __init sp804_get_clock_rate(const char *name) if (rate < 0) { pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); clk_disable(clk); + clk_unprepare(clk); clk_put(clk); } diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 7aa4262..01f18a4 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -259,7 +259,6 @@ static void __init vic_disable(void __iomem *base) writel(0, base + VIC_INT_SELECT); writel(0, base + VIC_INT_ENABLE); writel(~0, base + VIC_INT_ENABLE_CLEAR); - writel(0, base + VIC_IRQ_STATUS); writel(0, base + VIC_ITCR); writel(~0, base + VIC_INT_SOFT_CLEAR); } @@ -347,7 +346,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, /* Identify which VIC cell this one is, by reading the ID */ for (i = 0; i < 4; i++) { - u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); + void __iomem *addr; + addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); cellid |= (readl(addr) & 0xff) << (8 * i); } vendor = (cellid >> 12) & 0xff; diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig new file mode 100644 index 0000000..c5876d2 --- /dev/null +++ b/arch/arm/configs/at91sam9g45_defconfig @@ -0,0 +1,214 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91SAM9G45=y +CONFIG_MACH_AT91SAM9M10G45EK=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_AT91_SLOW_CLOCK=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw" +CONFIG_AUTO_ZRELADDR=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT_6RD=y +CONFIG_CFG80211=y +CONFIG_LIB80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_MISC_DEVICES=y +CONFIG_ATMEL_PWM=y +CONFIG_ATMEL_TCLIB=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_DAVICOM_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_MACB=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_AT76C50X_USB=m +CONFIG_USB_ZD1201=m +CONFIG_RTL8187=m +CONFIG_ATH_COMMON=m +CONFIG_ATH9K=m +CONFIG_CARL9170=m +CONFIG_B43=m +CONFIG_B43_PHY_N=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8192CU=m +CONFIG_WL1251=m +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX_MENU=m +CONFIG_WL12XX=m +CONFIG_WL12XX_SDIO=m +CONFIG_ZD1211RW=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y +# CONFIG_SERIO is not set +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_SPI=y +CONFIG_SPI_ATMEL=y +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_FB=y +CONFIG_FB_ATMEL=y +CONFIG_FB_UDL=m +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_ATMEL_LCDC=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_ATMEL_AC97C=y +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +# CONFIG_USB_HID is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_ATMEL_USBA=m +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_MMC=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_SDIO_UART=m +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_ATMELMCI_DMA=y +CONFIG_LEDS_ATMEL_PWM=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_DMADEVICES=y +CONFIG_AT_HDMAC=y +CONFIG_DMATEST=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_FANOTIFY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig index 7196ade..1103f62 100644 --- a/arch/arm/configs/integrator_defconfig +++ b/arch/arm/configs/integrator_defconfig @@ -1,5 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y +CONFIG_TINY_RCU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -8,20 +9,29 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_AP=y +CONFIG_ARCH_INTEGRATOR_CP=y CONFIG_CPU_ARM720T=y CONFIG_CPU_ARM920T=y +CONFIG_CPU_ARM922T=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_ARM1020=y +CONFIG_CPU_ARM1022=y +CONFIG_CPU_ARM1026=y CONFIG_PCI=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y CONFIG_LEDS=y CONFIG_LEDS_CPU=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp mem=32M" +CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp" CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_FPE_NWFPE=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -32,7 +42,6 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_AFS_PARTS=y CONFIG_MTD_CHAR=y @@ -40,6 +49,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 @@ -56,6 +66,8 @@ CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PL030=y CONFIG_EXT2_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y @@ -68,4 +80,3 @@ CONFIG_NFSD_V3=y CONFIG_PARTITION_ADVANCED=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_ERRORS=y diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index 7c4b30b..cb0717f 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y @@ -13,20 +12,21 @@ CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_MXC=y CONFIG_MACH_MX31ADS_WM1133_EV1=y +CONFIG_MACH_MX31LILLY=y +CONFIG_MACH_MX31LITE=y CONFIG_MACH_PCM037=y CONFIG_MACH_PCM037_EET=y -CONFIG_MACH_MX31LITE=y CONFIG_MACH_MX31_3DS=y CONFIG_MACH_MX31MOBOARD=y -CONFIG_MACH_MX31LILLY=y CONFIG_MACH_QONG=y -CONFIG_MACH_PCM043=y CONFIG_MACH_ARMADILLO5X0=y -CONFIG_MACH_MX35_3DS=y CONFIG_MACH_KZM_ARM11_01=y +CONFIG_MACH_PCM043=y +CONFIG_MACH_MX35_3DS=y CONFIG_MACH_EUKREA_CPUIMX35=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y +CONFIG_ARM_ERRATA_411920=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y @@ -35,7 +35,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off" CONFIG_VFP=y -CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_NET=y CONFIG_PACKET=y @@ -52,7 +51,6 @@ CONFIG_IP_PNP_DHCP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_FW_LOADER=m CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y @@ -62,24 +60,27 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_MXC=y CONFIG_MTD_UBI=y # CONFIG_BLK_DEV is not set +CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT24=y CONFIG_NETDEVICES=y CONFIG_SMSC_PHY=y CONFIG_NET_ETHERNET=y CONFIG_SMSC911X=y CONFIG_DNET=y -CONFIG_FEC=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_IMX=y +# CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=m CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y @@ -89,12 +90,15 @@ CONFIG_W1=y CONFIG_W1_MASTER_MXC=y CONFIG_W1_SLAVE_THERM=y # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y CONFIG_MFD_WM8350_I2C=y CONFIG_REGULATOR=y CONFIG_REGULATOR_WM8350=y CONFIG_MEDIA_SUPPORT=y CONFIG_VIDEO_DEV=y -# CONFIG_VIDEO_ALLOW_V4L1 is not set +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set CONFIG_SOC_CAMERA=y CONFIG_SOC_CAMERA_MT9M001=y CONFIG_SOC_CAMERA_MT9M111=y @@ -105,9 +109,26 @@ CONFIG_SOC_CAMERA_OV772X=y CONFIG_VIDEO_MX3=y # CONFIG_RADIO_ADAPTERS is not set CONFIG_FB=y -# CONFIG_USB_SUPPORT is not set +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_MXC_SOC_WM1133_EV1=y +CONFIG_SND_SOC_PHYCORE_AC97=y +CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_GADGET=m +CONFIG_USB_FSL_USB2=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_ULPI=y CONFIG_MMC=y CONFIG_MMC_MXC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_MXC=y CONFIG_DMADEVICES=y # CONFIG_DNOTIFY is not set CONFIG_TMPFS=y @@ -119,6 +140,5 @@ CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 6550db3..960abce 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -1,3 +1,20 @@ include include/asm-generic/Kbuild.asm header-y += hwcap.h + +generic-y += auxvec.h +generic-y += bitsperlong.h +generic-y += cputime.h +generic-y += emergency-restart.h +generic-y += errno.h +generic-y += ioctl.h +generic-y += irq_regs.h +generic-y += kdebug.h +generic-y += local.h +generic-y += local64.h +generic-y += percpu.h +generic-y += poll.h +generic-y += resource.h +generic-y += sections.h +generic-y += siginfo.h +generic-y += sizes.h diff --git a/arch/arm/include/asm/auxvec.h b/arch/arm/include/asm/auxvec.h deleted file mode 100644 index c0536f6..0000000 --- a/arch/arm/include/asm/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASMARM_AUXVEC_H -#define __ASMARM_AUXVEC_H - -#endif diff --git a/arch/arm/include/asm/bitsperlong.h b/arch/arm/include/asm/bitsperlong.h deleted file mode 100644 index 6dc0bb0..0000000 --- a/arch/arm/include/asm/bitsperlong.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/bitsperlong.h> diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h index 4d88425..9abe7a0 100644 --- a/arch/arm/include/asm/bug.h +++ b/arch/arm/include/asm/bug.h @@ -3,21 +3,58 @@ #ifdef CONFIG_BUG -#ifdef CONFIG_DEBUG_BUGVERBOSE -extern void __bug(const char *file, int line) __attribute__((noreturn)); - -/* give file/line information */ -#define BUG() __bug(__FILE__, __LINE__) +/* + * Use a suitable undefined instruction to use for ARM/Thumb2 bug handling. + * We need to be careful not to conflict with those used by other modules and + * the register_undef_hook() system. + */ +#ifdef CONFIG_THUMB2_KERNEL +#define BUG_INSTR_VALUE 0xde02 +#define BUG_INSTR_TYPE ".hword " #else +#define BUG_INSTR_VALUE 0xe7f001f2 +#define BUG_INSTR_TYPE ".word " +#endif -/* this just causes an oops */ -#define BUG() do { *(int *)0 = 0; } while (1) -#endif +#define BUG() _BUG(__FILE__, __LINE__, BUG_INSTR_VALUE) +#define _BUG(file, line, value) __BUG(file, line, value) + +#ifdef CONFIG_DEBUG_BUGVERBOSE + +/* + * The extra indirection is to ensure that the __FILE__ string comes through + * OK. Many version of gcc do not support the asm %c parameter which would be + * preferable to this unpleasantness. We use mergeable string sections to + * avoid multiple copies of the string appearing in the kernel image. + */ + +#define __BUG(__file, __line, __value) \ +do { \ + BUILD_BUG_ON(sizeof(struct bug_entry) != 12); \ + asm volatile("1:\t" BUG_INSTR_TYPE #__value "\n" \ + ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \ + "2:\t.asciz " #__file "\n" \ + ".popsection\n" \ + ".pushsection __bug_table,\"a\"\n" \ + "3:\t.word 1b, 2b\n" \ + "\t.hword " #__line ", 0\n" \ + ".popsection"); \ + unreachable(); \ +} while (0) + +#else /* not CONFIG_DEBUG_BUGVERBOSE */ + +#define __BUG(__file, __line, __value) \ +do { \ + asm volatile(BUG_INSTR_TYPE #__value); \ + unreachable(); \ +} while (0) +#endif /* CONFIG_DEBUG_BUGVERBOSE */ #define HAVE_ARCH_BUG -#endif +#endif /* CONFIG_BUG */ #include <asm-generic/bug.h> diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index c023db0..7ea7814 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -7,6 +7,7 @@ #define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING) #define CACHEID_ASID_TAGGED (1 << 3) #define CACHEID_VIPT_I_ALIASING (1 << 4) +#define CACHEID_PIPT (1 << 5) extern unsigned int cacheid; @@ -16,6 +17,7 @@ extern unsigned int cacheid; #define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING) #define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED) #define icache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_I_ALIASING) +#define icache_is_pipt() cacheid_is(CACHEID_PIPT) /* * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture @@ -26,7 +28,8 @@ extern unsigned int cacheid; #if __LINUX_ARM_ARCH__ >= 7 #define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING |\ CACHEID_ASID_TAGGED |\ - CACHEID_VIPT_I_ALIASING) + CACHEID_VIPT_I_ALIASING |\ + CACHEID_PIPT) #elif __LINUX_ARM_ARCH__ >= 6 #define __CACHEID_ARCH_MIN (~CACHEID_VIVT) #else diff --git a/arch/arm/include/asm/cputime.h b/arch/arm/include/asm/cputime.h deleted file mode 100644 index 3a8002a..0000000 --- a/arch/arm/include/asm/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ARM_CPUTIME_H -#define __ARM_CPUTIME_H - -#include <asm-generic/cputime.h> - -#endif /* __ARM_CPUTIME_H */ diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h index 9f390ce..7aa3680 100644 --- a/arch/arm/include/asm/device.h +++ b/arch/arm/include/asm/device.h @@ -10,9 +10,17 @@ struct dev_archdata { #ifdef CONFIG_DMABOUNCE struct dmabounce_device_info *dmabounce; #endif +#ifdef CONFIG_IOMMU_API + void *iommu; /* private IOMMU data */ +#endif }; +struct omap_device; + struct pdev_archdata { +#ifdef CONFIG_ARCH_OMAP + struct omap_device *od; +#endif }; #endif diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 7f27fab..cb3b7c9 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -32,7 +32,7 @@ static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr) static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) { - return (void *)__bus_to_virt(addr); + return (void *)__bus_to_virt((unsigned long)addr); } static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index 628670e..69a5b0b 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h @@ -34,18 +34,18 @@ #define DMA_MODE_CASCADE 0xc0 #define DMA_AUTOINIT 0x10 -extern spinlock_t dma_spin_lock; +extern raw_spinlock_t dma_spin_lock; static inline unsigned long claim_dma_lock(void) { unsigned long flags; - spin_lock_irqsave(&dma_spin_lock, flags); + raw_spin_lock_irqsave(&dma_spin_lock, flags); return flags; } static inline void release_dma_lock(unsigned long flags) { - spin_unlock_irqrestore(&dma_spin_lock, flags); + raw_spin_unlock_irqrestore(&dma_spin_lock, flags); } /* Clear the 'DMA Pointer Flip Flop'. diff --git a/arch/arm/include/asm/ecard.h b/arch/arm/include/asm/ecard.h index 29f2610..eaea146 100644 --- a/arch/arm/include/asm/ecard.h +++ b/arch/arm/include/asm/ecard.h @@ -161,7 +161,6 @@ struct expansion_card { /* Private internal data */ const char *card_desc; /* Card description */ - CONST unsigned int podaddr; /* Base Linux address for card */ CONST loader_t loader; /* loader program */ u64 dma_mask; }; diff --git a/arch/arm/include/asm/emergency-restart.h b/arch/arm/include/asm/emergency-restart.h deleted file mode 100644 index 108d8c4..0000000 --- a/arch/arm/include/asm/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include <asm-generic/emergency-restart.h> - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/arch/arm/include/asm/errno.h b/arch/arm/include/asm/errno.h deleted file mode 100644 index 6e60f06..0000000 --- a/arch/arm/include/asm/errno.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ARM_ERRNO_H -#define _ARM_ERRNO_H - -#include <asm-generic/errno.h> - -#endif diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 99a6ed7..434edcc 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -52,6 +52,8 @@ #define L2X0_LOCKDOWN_WAY_D_BASE 0x900 #define L2X0_LOCKDOWN_WAY_I_BASE 0x904 #define L2X0_LOCKDOWN_STRIDE 0x08 +#define L2X0_ADDR_FILTER_START 0xC00 +#define L2X0_ADDR_FILTER_END 0xC04 #define L2X0_TEST_OPERATION 0xF00 #define L2X0_LINE_DATA 0xF10 #define L2X0_LINE_TAG 0xF30 @@ -65,8 +67,23 @@ #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L210 (1 << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) +#define L2X0_CACHE_ID_RTL_MASK 0x3f +#define L2X0_CACHE_ID_RTL_R0P0 0x0 +#define L2X0_CACHE_ID_RTL_R1P0 0x2 +#define L2X0_CACHE_ID_RTL_R2P0 0x4 +#define L2X0_CACHE_ID_RTL_R3P0 0x5 +#define L2X0_CACHE_ID_RTL_R3P1 0x6 +#define L2X0_CACHE_ID_RTL_R3P2 0x8 #define L2X0_AUX_CTRL_MASK 0xc0000fff +#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 +#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 +#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 +#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3) +#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 +#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6) +#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 +#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9) #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 #define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) @@ -77,8 +94,33 @@ #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 +#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0 +#define L2X0_LATENCY_CTRL_RD_SHIFT 4 +#define L2X0_LATENCY_CTRL_WR_SHIFT 8 + +#define L2X0_ADDR_FILTER_EN 1 + #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); +extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask); + +struct l2x0_regs { + unsigned long phy_base; + unsigned long aux_ctrl; + /* + * Whether the following registers need to be saved/restored + * depends on platform + */ + unsigned long tag_latency; + unsigned long data_latency; + unsigned long filter_start; + unsigned long filter_end; + unsigned long prefetch_ctrl; + unsigned long pwr_ctrl; +}; + +extern struct l2x0_regs l2x0_saved_regs; + #endif #endif diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h index b3fea38..43cab49 100644 --- a/arch/arm/include/asm/hardware/it8152.h +++ b/arch/arm/include/asm/hardware/it8152.h @@ -9,7 +9,7 @@ #ifndef __ASM_HARDWARE_IT8152_H #define __ASM_HARDWARE_IT8152_H -extern unsigned long it8152_base_address; +extern void __iomem *it8152_base_address; #define IT8152_IO_BASE (it8152_base_address + 0x03e00000) #define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index d66605de..065d100 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -80,6 +80,7 @@ extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int, extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int); +extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached); extern void __iounmap(volatile void __iomem *addr); /* @@ -110,6 +111,27 @@ static inline void __iomem *__typesafe_io(unsigned long addr) #include <mach/io.h> /* + * This is the limit of PC card/PCI/ISA IO space, which is by default + * 64K if we have PC card, PCI or ISA support. Otherwise, default to + * zero to prevent ISA/PCI drivers claiming IO space (and potentially + * oopsing.) + * + * Only set this larger if you really need inb() et.al. to operate over + * a larger address space. Note that SOC_COMMON ioremaps each sockets + * IO space area, and so inb() et.al. must be defined to operate as per + * readb() et.al. on such platforms. + */ +#ifndef IO_SPACE_LIMIT +#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE) +#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff) +#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD) +#define IO_SPACE_LIMIT ((resource_size_t)0xffff) +#else +#define IO_SPACE_LIMIT ((resource_size_t)0) +#endif +#endif + +/* * IO port access primitives * ------------------------- * @@ -189,11 +211,11 @@ extern void _memset_io(volatile void __iomem *, int, size_t); * IO port primitives for more information. */ #ifdef __mem_pci -#define readb_relaxed(c) ({ u8 __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \ - __raw_readw(__mem_pci(c))); __v; }) -#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \ - __raw_readl(__mem_pci(c))); __v; }) +#define readb_relaxed(c) ({ u8 __r = __raw_readb(__mem_pci(c)); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ + __raw_readw(__mem_pci(c))); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ + __raw_readl(__mem_pci(c))); __r; }) #define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c))) #define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \ @@ -238,7 +260,7 @@ extern void _memset_io(volatile void __iomem *, int, size_t); * ioremap and friends. * * ioremap takes a PCI memory address, as specified in - * Documentation/IO-mapping.txt. + * Documentation/io-mapping.txt. * */ #ifndef __arch_ioremap @@ -260,10 +282,16 @@ extern void _memset_io(volatile void __iomem *, int, size_t); #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; }) #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; }) +#define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) +#define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) + #define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); }) #define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); }) #define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); }) +#define iowrite16be(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_be16(v), p); }) +#define iowrite32be(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_be32(v), p); }) + #define ioread8_rep(p,d,c) __raw_readsb(p,d,c) #define ioread16_rep(p,d,c) __raw_readsw(p,d,c) #define ioread32_rep(p,d,c) __raw_readsl(p,d,c) diff --git a/arch/arm/include/asm/ioctl.h b/arch/arm/include/asm/ioctl.h deleted file mode 100644 index b279fe0..0000000 --- a/arch/arm/include/asm/ioctl.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ioctl.h> diff --git a/arch/arm/include/asm/irq_regs.h b/arch/arm/include/asm/irq_regs.h deleted file mode 100644 index 3dd9c0b..0000000 --- a/arch/arm/include/asm/irq_regs.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/irq_regs.h> diff --git a/arch/arm/include/asm/kdebug.h b/arch/arm/include/asm/kdebug.h deleted file mode 100644 index 6ece1b0..0000000 --- a/arch/arm/include/asm/kdebug.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/kdebug.h> diff --git a/arch/arm/include/asm/local.h b/arch/arm/include/asm/local.h deleted file mode 100644 index c11c530..0000000 --- a/arch/arm/include/asm/local.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/local.h> diff --git a/arch/arm/include/asm/local64.h b/arch/arm/include/asm/local64.h deleted file mode 100644 index 36c93b5..0000000 --- a/arch/arm/include/asm/local64.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/local64.h> diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h index f5e1cec..c6a1842 100644 --- a/arch/arm/include/asm/localtimer.h +++ b/arch/arm/include/asm/localtimer.h @@ -10,6 +10,7 @@ #ifndef __ASM_ARM_LOCALTIMER_H #define __ASM_ARM_LOCALTIMER_H +#include <linux/errno.h> #include <linux/interrupt.h> struct clock_event_device; diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index 727da11..7d19425 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -34,8 +34,7 @@ struct machine_desc { unsigned int reserve_lp1 :1; /* never has lp1 */ unsigned int reserve_lp2 :1; /* never has lp2 */ unsigned int soft_reboot :1; /* soft reboot */ - void (*fixup)(struct machine_desc *, - struct tag *, char **, + void (*fixup)(struct tag *, char **, struct meminfo *); void (*reserve)(void);/* reserve mem blocks */ void (*map_io)(void);/* IO mapping function */ diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index b4ffe9d..1496565 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h @@ -6,7 +6,7 @@ typedef struct { #ifdef CONFIG_CPU_HAS_ASID unsigned int id; - spinlock_t id_lock; + raw_spinlock_t id_lock; #endif unsigned int kvm_seq; } mm_context_t; @@ -16,7 +16,7 @@ typedef struct { /* init_mm.context.id_lock should be initialized. */ #define INIT_MM_CONTEXT(name) \ - .context.id_lock = __SPIN_LOCK_UNLOCKED(name.context.id_lock), + .context.id_lock = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock), #else #define ASID(mm) (0) #endif diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index d838743..53426c6 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -34,6 +34,7 @@ struct outer_cache_fns { void (*sync)(void); #endif void (*set_debug)(unsigned long); + void (*resume)(void); }; #ifdef CONFIG_OUTER_CACHE @@ -74,6 +75,12 @@ static inline void outer_disable(void) outer_cache.disable(); } +static inline void outer_resume(void) +{ + if (outer_cache.resume) + outer_cache.resume(); +} + #else static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index ac75d08..ca94653 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -151,47 +151,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from, #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) extern void copy_page(void *to, const void *from); -typedef unsigned long pteval_t; - -#undef STRICT_MM_TYPECHECKS - -#ifdef STRICT_MM_TYPECHECKS -/* - * These are used to make use of C type-checking.. - */ -typedef struct { pteval_t pte; } pte_t; -typedef struct { unsigned long pmd; } pmd_t; -typedef struct { unsigned long pgd[2]; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((x).pmd) -#define pgd_val(x) ((x).pgd[0]) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -#else -/* - * .. while these make it easier on the compiler - */ -typedef pteval_t pte_t; -typedef unsigned long pmd_t; -typedef unsigned long pgd_t[2]; -typedef unsigned long pgprot_t; - -#define pte_val(x) (x) -#define pmd_val(x) (x) -#define pgd_val(x) ((x)[0]) -#define pgprot_val(x) (x) - -#define __pte(x) (x) -#define __pmd(x) (x) -#define __pgprot(x) (x) - -#endif /* STRICT_MM_TYPECHECKS */ +#include <asm/pgtable-2level-types.h> #endif /* CONFIG_MMU */ diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h deleted file mode 100644 index b4e32d8..0000000 --- a/arch/arm/include/asm/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ARM_PERCPU -#define __ARM_PERCPU - -#include <asm-generic/percpu.h> - -#endif diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index 22de005..3e08fd3 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h @@ -105,9 +105,9 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t pte) } static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte, - unsigned long prot) + pmdval_t prot) { - unsigned long pmdval = (pte + PTE_HWTABLE_OFF) | prot; + pmdval_t pmdval = (pte + PTE_HWTABLE_OFF) | prot; pmdp[0] = __pmd(pmdval); pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); flush_pmd_entry(pmdp); diff --git a/arch/arm/include/asm/pgtable-2level-hwdef.h b/arch/arm/include/asm/pgtable-2level-hwdef.h new file mode 100644 index 0000000..5cfba15 --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level-hwdef.h @@ -0,0 +1,93 @@ +/* + * arch/arm/include/asm/pgtable-2level-hwdef.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ASM_PGTABLE_2LEVEL_HWDEF_H +#define _ASM_PGTABLE_2LEVEL_HWDEF_H + +/* + * Hardware page table definitions. + * + * + Level 1 descriptor (PMD) + * - common + */ +#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) +#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) +#define PMD_TYPE_TABLE (_AT(pmdval_t, 1) << 0) +#define PMD_TYPE_SECT (_AT(pmdval_t, 2) << 0) +#define PMD_BIT4 (_AT(pmdval_t, 1) << 4) +#define PMD_DOMAIN(x) (_AT(pmdval_t, (x)) << 5) +#define PMD_PROTECTION (_AT(pmdval_t, 1) << 9) /* v5 */ +/* + * - section + */ +#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) +#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) +#define PMD_SECT_XN (_AT(pmdval_t, 1) << 4) /* v6 */ +#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 1) << 10) +#define PMD_SECT_AP_READ (_AT(pmdval_t, 1) << 11) +#define PMD_SECT_TEX(x) (_AT(pmdval_t, (x)) << 12) /* v5 */ +#define PMD_SECT_APX (_AT(pmdval_t, 1) << 15) /* v6 */ +#define PMD_SECT_S (_AT(pmdval_t, 1) << 16) /* v6 */ +#define PMD_SECT_nG (_AT(pmdval_t, 1) << 17) /* v6 */ +#define PMD_SECT_SUPER (_AT(pmdval_t, 1) << 18) /* v6 */ +#define PMD_SECT_AF (_AT(pmdval_t, 0)) + +#define PMD_SECT_UNCACHED (_AT(pmdval_t, 0)) +#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) +#define PMD_SECT_WT (PMD_SECT_CACHEABLE) +#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) +#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) + +/* + * - coarse table (not used) + */ + +/* + * + Level 2 descriptor (PTE) + * - common + */ +#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) +#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) +#define PTE_TYPE_LARGE (_AT(pteval_t, 1) << 0) +#define PTE_TYPE_SMALL (_AT(pteval_t, 2) << 0) +#define PTE_TYPE_EXT (_AT(pteval_t, 3) << 0) /* v5 */ +#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) +#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) + +/* + * - extended small page/tiny page + */ +#define PTE_EXT_XN (_AT(pteval_t, 1) << 0) /* v6 */ +#define PTE_EXT_AP_MASK (_AT(pteval_t, 3) << 4) +#define PTE_EXT_AP0 (_AT(pteval_t, 1) << 4) +#define PTE_EXT_AP1 (_AT(pteval_t, 2) << 4) +#define PTE_EXT_AP_UNO_SRO (_AT(pteval_t, 0) << 4) +#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) +#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) +#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) +#define PTE_EXT_TEX(x) (_AT(pteval_t, (x)) << 6) /* v5 */ +#define PTE_EXT_APX (_AT(pteval_t, 1) << 9) /* v6 */ +#define PTE_EXT_COHERENT (_AT(pteval_t, 1) << 9) /* XScale3 */ +#define PTE_EXT_SHARED (_AT(pteval_t, 1) << 10) /* v6 */ +#define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* v6 */ + +/* + * - small page + */ +#define PTE_SMALL_AP_MASK (_AT(pteval_t, 0xff) << 4) +#define PTE_SMALL_AP_UNO_SRO (_AT(pteval_t, 0x00) << 4) +#define PTE_SMALL_AP_UNO_SRW (_AT(pteval_t, 0x55) << 4) +#define PTE_SMALL_AP_URO_SRW (_AT(pteval_t, 0xaa) << 4) +#define PTE_SMALL_AP_URW_SRW (_AT(pteval_t, 0xff) << 4) + +#define PHYS_MASK (~0UL) + +#endif diff --git a/arch/arm/include/asm/pgtable-2level-types.h b/arch/arm/include/asm/pgtable-2level-types.h new file mode 100644 index 0000000..66cb5b0 --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level-types.h @@ -0,0 +1,67 @@ +/* + * arch/arm/include/asm/pgtable-2level-types.h + * + * Copyright (C) 1995-2003 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _ASM_PGTABLE_2LEVEL_TYPES_H +#define _ASM_PGTABLE_2LEVEL_TYPES_H + +#include <asm/types.h> + +typedef u32 pteval_t; +typedef u32 pmdval_t; + +#undef STRICT_MM_TYPECHECKS + +#ifdef STRICT_MM_TYPECHECKS +/* + * These are used to make use of C type-checking.. + */ +typedef struct { pteval_t pte; } pte_t; +typedef struct { pmdval_t pmd; } pmd_t; +typedef struct { pmdval_t pgd[2]; } pgd_t; +typedef struct { pteval_t pgprot; } pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((x).pmd) +#define pgd_val(x) ((x).pgd[0]) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +#else +/* + * .. while these make it easier on the compiler + */ +typedef pteval_t pte_t; +typedef pmdval_t pmd_t; +typedef pmdval_t pgd_t[2]; +typedef pteval_t pgprot_t; + +#define pte_val(x) (x) +#define pmd_val(x) (x) +#define pgd_val(x) ((x)[0]) +#define pgprot_val(x) (x) + +#define __pte(x) (x) +#define __pmd(x) (x) +#define __pgprot(x) (x) + +#endif /* STRICT_MM_TYPECHECKS */ + +#endif /* _ASM_PGTABLE_2LEVEL_TYPES_H */ diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h new file mode 100644 index 0000000..470457e --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level.h @@ -0,0 +1,143 @@ +/* + * arch/arm/include/asm/pgtable-2level.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ASM_PGTABLE_2LEVEL_H +#define _ASM_PGTABLE_2LEVEL_H + +/* + * Hardware-wise, we have a two level page table structure, where the first + * level has 4096 entries, and the second level has 256 entries. Each entry + * is one 32-bit word. Most of the bits in the second level entry are used + * by hardware, and there aren't any "accessed" and "dirty" bits. + * + * Linux on the other hand has a three level page table structure, which can + * be wrapped to fit a two level page table structure easily - using the PGD + * and PTE only. However, Linux also expects one "PTE" table per page, and + * at least a "dirty" bit. + * + * Therefore, we tweak the implementation slightly - we tell Linux that we + * have 2048 entries in the first level, each of which is 8 bytes (iow, two + * hardware pointers to the second level.) The second level contains two + * hardware PTE tables arranged contiguously, preceded by Linux versions + * which contain the state information Linux needs. We, therefore, end up + * with 512 entries in the "PTE" level. + * + * This leads to the page tables having the following layout: + * + * pgd pte + * | | + * +--------+ + * | | +------------+ +0 + * +- - - - + | Linux pt 0 | + * | | +------------+ +1024 + * +--------+ +0 | Linux pt 1 | + * | |-----> +------------+ +2048 + * +- - - - + +4 | h/w pt 0 | + * | |-----> +------------+ +3072 + * +--------+ +8 | h/w pt 1 | + * | | +------------+ +4096 + * + * See L_PTE_xxx below for definitions of bits in the "Linux pt", and + * PTE_xxx for definitions of bits appearing in the "h/w pt". + * + * PMD_xxx definitions refer to bits in the first level page table. + * + * The "dirty" bit is emulated by only granting hardware write permission + * iff the page is marked "writable" and "dirty" in the Linux PTE. This + * means that a write to a clean page will cause a permission fault, and + * the Linux MM layer will mark the page dirty via handle_pte_fault(). + * For the hardware to notice the permission change, the TLB entry must + * be flushed, and ptep_set_access_flags() does that for us. + * + * The "accessed" or "young" bit is emulated by a similar method; we only + * allow accesses to the page if the "young" bit is set. Accesses to the + * page will cause a fault, and handle_pte_fault() will set the young bit + * for us as long as the page is marked present in the corresponding Linux + * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is + * up to date. + * + * However, when the "young" bit is cleared, we deny access to the page + * by clearing the hardware PTE. Currently Linux does not flush the TLB + * for us in this case, which means the TLB will retain the transation + * until either the TLB entry is evicted under pressure, or a context + * switch which changes the user space mapping occurs. + */ +#define PTRS_PER_PTE 512 +#define PTRS_PER_PMD 1 +#define PTRS_PER_PGD 2048 + +#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) +#define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) +#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) + +/* + * PMD_SHIFT determines the size of the area a second-level page table can map + * PGDIR_SHIFT determines what a third-level page table entry can map + */ +#define PMD_SHIFT 21 +#define PGDIR_SHIFT 21 + +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * section address mask and size definitions. + */ +#define SECTION_SHIFT 20 +#define SECTION_SIZE (1UL << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) + +/* + * ARMv6 supersection address mask and size definitions. + */ +#define SUPERSECTION_SHIFT 24 +#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) +#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) + +#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) + +/* + * "Linux" PTE definitions. + * + * We keep two sets of PTEs - the hardware and the linux version. + * This allows greater flexibility in the way we map the Linux bits + * onto the hardware tables, and allows us to have YOUNG and DIRTY + * bits. + * + * The PTE table pointer refers to the hardware entries; the "Linux" + * entries are stored 1024 bytes below. + */ +#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) +#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) +#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ +#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) +#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) +#define L_PTE_USER (_AT(pteval_t, 1) << 8) +#define L_PTE_XN (_AT(pteval_t, 1) << 9) +#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */ + +/* + * These are the memory types, defined to be compatible with + * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB + */ +#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */ +#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ +#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ +#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ +#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ +#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ +#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ +#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ +#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ +#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) + +#endif /* _ASM_PGTABLE_2LEVEL_H */ diff --git a/arch/arm/include/asm/pgtable-hwdef.h b/arch/arm/include/asm/pgtable-hwdef.h index fd1521d..1831111 100644 --- a/arch/arm/include/asm/pgtable-hwdef.h +++ b/arch/arm/include/asm/pgtable-hwdef.h @@ -10,81 +10,6 @@ #ifndef _ASMARM_PGTABLE_HWDEF_H #define _ASMARM_PGTABLE_HWDEF_H -/* - * Hardware page table definitions. - * - * + Level 1 descriptor (PMD) - * - common - */ -#define PMD_TYPE_MASK (3 << 0) -#define PMD_TYPE_FAULT (0 << 0) -#define PMD_TYPE_TABLE (1 << 0) -#define PMD_TYPE_SECT (2 << 0) -#define PMD_BIT4 (1 << 4) -#define PMD_DOMAIN(x) ((x) << 5) -#define PMD_PROTECTION (1 << 9) /* v5 */ -/* - * - section - */ -#define PMD_SECT_BUFFERABLE (1 << 2) -#define PMD_SECT_CACHEABLE (1 << 3) -#define PMD_SECT_XN (1 << 4) /* v6 */ -#define PMD_SECT_AP_WRITE (1 << 10) -#define PMD_SECT_AP_READ (1 << 11) -#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ -#define PMD_SECT_APX (1 << 15) /* v6 */ -#define PMD_SECT_S (1 << 16) /* v6 */ -#define PMD_SECT_nG (1 << 17) /* v6 */ -#define PMD_SECT_SUPER (1 << 18) /* v6 */ - -#define PMD_SECT_UNCACHED (0) -#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) -#define PMD_SECT_WT (PMD_SECT_CACHEABLE) -#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) -#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) - -/* - * - coarse table (not used) - */ - -/* - * + Level 2 descriptor (PTE) - * - common - */ -#define PTE_TYPE_MASK (3 << 0) -#define PTE_TYPE_FAULT (0 << 0) -#define PTE_TYPE_LARGE (1 << 0) -#define PTE_TYPE_SMALL (2 << 0) -#define PTE_TYPE_EXT (3 << 0) /* v5 */ -#define PTE_BUFFERABLE (1 << 2) -#define PTE_CACHEABLE (1 << 3) - -/* - * - extended small page/tiny page - */ -#define PTE_EXT_XN (1 << 0) /* v6 */ -#define PTE_EXT_AP_MASK (3 << 4) -#define PTE_EXT_AP0 (1 << 4) -#define PTE_EXT_AP1 (2 << 4) -#define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) -#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) -#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) -#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ -#define PTE_EXT_APX (1 << 9) /* v6 */ -#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */ -#define PTE_EXT_SHARED (1 << 10) /* v6 */ -#define PTE_EXT_NG (1 << 11) /* v6 */ - -/* - * - small page - */ -#define PTE_SMALL_AP_MASK (0xff << 4) -#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) -#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) -#define PTE_SMALL_AP_URO_SRW (0xaa << 4) -#define PTE_SMALL_AP_URW_SRW (0xff << 4) +#include <asm/pgtable-2level-hwdef.h> #endif diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index f1956b2..9451dce 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -24,6 +24,8 @@ #include <mach/vmalloc.h> #include <asm/pgtable-hwdef.h> +#include <asm/pgtable-2level.h> + /* * Just any arbitrary offset to the start of the vmalloc VM area: the * current 8MB value just means that there will be a 8MB "hole" after the @@ -41,79 +43,6 @@ #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #endif -/* - * Hardware-wise, we have a two level page table structure, where the first - * level has 4096 entries, and the second level has 256 entries. Each entry - * is one 32-bit word. Most of the bits in the second level entry are used - * by hardware, and there aren't any "accessed" and "dirty" bits. - * - * Linux on the other hand has a three level page table structure, which can - * be wrapped to fit a two level page table structure easily - using the PGD - * and PTE only. However, Linux also expects one "PTE" table per page, and - * at least a "dirty" bit. - * - * Therefore, we tweak the implementation slightly - we tell Linux that we - * have 2048 entries in the first level, each of which is 8 bytes (iow, two - * hardware pointers to the second level.) The second level contains two - * hardware PTE tables arranged contiguously, preceded by Linux versions - * which contain the state information Linux needs. We, therefore, end up - * with 512 entries in the "PTE" level. - * - * This leads to the page tables having the following layout: - * - * pgd pte - * | | - * +--------+ - * | | +------------+ +0 - * +- - - - + | Linux pt 0 | - * | | +------------+ +1024 - * +--------+ +0 | Linux pt 1 | - * | |-----> +------------+ +2048 - * +- - - - + +4 | h/w pt 0 | - * | |-----> +------------+ +3072 - * +--------+ +8 | h/w pt 1 | - * | | +------------+ +4096 - * - * See L_PTE_xxx below for definitions of bits in the "Linux pt", and - * PTE_xxx for definitions of bits appearing in the "h/w pt". - * - * PMD_xxx definitions refer to bits in the first level page table. - * - * The "dirty" bit is emulated by only granting hardware write permission - * iff the page is marked "writable" and "dirty" in the Linux PTE. This - * means that a write to a clean page will cause a permission fault, and - * the Linux MM layer will mark the page dirty via handle_pte_fault(). - * For the hardware to notice the permission change, the TLB entry must - * be flushed, and ptep_set_access_flags() does that for us. - * - * The "accessed" or "young" bit is emulated by a similar method; we only - * allow accesses to the page if the "young" bit is set. Accesses to the - * page will cause a fault, and handle_pte_fault() will set the young bit - * for us as long as the page is marked present in the corresponding Linux - * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is - * up to date. - * - * However, when the "young" bit is cleared, we deny access to the page - * by clearing the hardware PTE. Currently Linux does not flush the TLB - * for us in this case, which means the TLB will retain the transation - * until either the TLB entry is evicted under pressure, or a context - * switch which changes the user space mapping occurs. - */ -#define PTRS_PER_PTE 512 -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD 2048 - -#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) -#define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) -#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) - -/* - * PMD_SHIFT determines the size of the area a second-level page table can map - * PGDIR_SHIFT determines what a third-level page table entry can map - */ -#define PMD_SHIFT 21 -#define PGDIR_SHIFT 21 - #define LIBRARY_TEXT_START 0x0c000000 #ifndef __ASSEMBLY__ @@ -124,12 +53,6 @@ extern void __pgd_error(const char *file, int line, pgd_t); #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte) #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd) #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd) -#endif /* !__ASSEMBLY__ */ - -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) /* * This is the lowest virtual address we can permit any user space @@ -138,60 +61,6 @@ extern void __pgd_error(const char *file, int line, pgd_t); */ #define FIRST_USER_ADDRESS PAGE_SIZE -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) - -/* - * section address mask and size definitions. - */ -#define SECTION_SHIFT 20 -#define SECTION_SIZE (1UL << SECTION_SHIFT) -#define SECTION_MASK (~(SECTION_SIZE-1)) - -/* - * ARMv6 supersection address mask and size definitions. - */ -#define SUPERSECTION_SHIFT 24 -#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) -#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) - -/* - * "Linux" PTE definitions. - * - * We keep two sets of PTEs - the hardware and the linux version. - * This allows greater flexibility in the way we map the Linux bits - * onto the hardware tables, and allows us to have YOUNG and DIRTY - * bits. - * - * The PTE table pointer refers to the hardware entries; the "Linux" - * entries are stored 1024 bytes below. - */ -#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) -#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) -#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ -#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) -#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) -#define L_PTE_USER (_AT(pteval_t, 1) << 8) -#define L_PTE_XN (_AT(pteval_t, 1) << 9) -#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */ - -/* - * These are the memory types, defined to be compatible with - * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB - */ -#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */ -#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ -#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ -#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ -#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ -#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ -#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ -#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ -#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ -#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ -#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) - -#ifndef __ASSEMBLY__ - /* * The pgprot_* and protection_map entries will be fixed up in runtime * to include the cachable and bufferable bits based on memory policy, @@ -330,10 +199,10 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; static inline pte_t *pmd_page_vaddr(pmd_t pmd) { - return __va(pmd_val(pmd) & PAGE_MASK); + return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); } -#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) +#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) /* we don't need complex calculations here as the pmd is folded into the pgd */ #define pmd_addr_end(addr,end) (end) @@ -354,7 +223,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) #define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr)) #define pte_unmap(pte) __pte_unmap(pte) -#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) +#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) #define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot)) #define pte_page(pte) pfn_to_page(pte_pfn(pte)) diff --git a/arch/arm/include/asm/poll.h b/arch/arm/include/asm/poll.h deleted file mode 100644 index c98509d..0000000 --- a/arch/arm/include/asm/poll.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/poll.h> diff --git a/arch/arm/include/asm/resource.h b/arch/arm/include/asm/resource.h deleted file mode 100644 index 734b581..0000000 --- a/arch/arm/include/asm/resource.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ARM_RESOURCE_H -#define _ARM_RESOURCE_H - -#include <asm-generic/resource.h> - -#endif diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h deleted file mode 100644 index 2b8c516..0000000 --- a/arch/arm/include/asm/sections.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/sections.h> diff --git a/arch/arm/include/asm/siginfo.h b/arch/arm/include/asm/siginfo.h deleted file mode 100644 index 5e21852..0000000 --- a/arch/arm/include/asm/siginfo.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASMARM_SIGINFO_H -#define _ASMARM_SIGINFO_H - -#include <asm-generic/siginfo.h> - -#endif diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h deleted file mode 100644 index 154b89b..0000000 --- a/arch/arm/include/asm/sizes.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size definitions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ -#include <asm-generic/sizes.h> - -#define SZ_48M (SZ_32M + SZ_16M) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index ed6b049..984014b 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -57,6 +57,7 @@ #ifndef __ASSEMBLY__ +#include <linux/compiler.h> #include <linux/linkage.h> #include <linux/irqflags.h> @@ -90,14 +91,13 @@ void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, #define xchg(ptr,x) \ ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -extern asmlinkage void __backtrace(void); extern asmlinkage void c_backtrace(unsigned long fp, int pmode); struct mm_struct; extern void show_pte(struct mm_struct *mm, unsigned long addr); extern void __show_regs(struct pt_regs *); -extern int cpu_architecture(void); +extern int __pure cpu_architecture(void); extern void cpu_init(void); void arm_machine_restart(char mode, const char *cmd); diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 8077145..02b2f82 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -471,7 +471,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) * these operations. This is typically used when we are removing * PMD entries. */ -static inline void flush_pmd_entry(pmd_t *pmd) +static inline void flush_pmd_entry(void *pmd) { const unsigned int __tlb_flag = __cpu_tlb_flags; @@ -487,7 +487,7 @@ static inline void flush_pmd_entry(pmd_t *pmd) dsb(); } -static inline void clean_pmd_entry(pmd_t *pmd) +static inline void clean_pmd_entry(void *pmd) { const unsigned int __tlb_flag = __cpu_tlb_flags; diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 7cac26c..16eed6a 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o obj-$(CONFIG_ARTHUR) += arthur.o obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o -obj-$(CONFIG_PM_SLEEP) += sleep.o suspend.o +obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o obj-$(CONFIG_SMP) += smp.o smp_tlb.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index aeef960..8e3c6f1 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -49,9 +49,6 @@ extern void __aeabi_ulcmp(void); extern void fpundefinstr(void); - -EXPORT_SYMBOL(__backtrace); - /* platform dependent support */ EXPORT_SYMBOL(__udelay); EXPORT_SYMBOL(__const_udelay); diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 16baba2..1429d89 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -20,6 +20,7 @@ #include <asm/thread_info.h> #include <asm/memory.h> #include <asm/procinfo.h> +#include <asm/hardware/cache-l2x0.h> #include <linux/kbuild.h> /* @@ -92,6 +93,17 @@ int main(void) DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); BLANK(); +#ifdef CONFIG_CACHE_L2X0 + DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base)); + DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl)); + DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency)); + DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency)); + DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start)); + DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end)); + DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl)); + DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl)); + BLANK(); +#endif #ifdef CONFIG_CPU_HAS_ASID DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); BLANK(); diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index d6df359..c0d9203 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -412,6 +412,9 @@ void pcibios_fixup_bus(struct pci_bus *bus) printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n", bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); } +#ifdef CONFIG_HOTPLUG +EXPORT_SYMBOL(pcibios_fixup_bus); +#endif /* * Convert from Linux-centric to bus-centric addresses for bridge devices. @@ -431,6 +434,7 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, region->start = res->start - offset; region->end = res->end - offset; } +EXPORT_SYMBOL(pcibios_resource_to_bus); void __devinit pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, @@ -447,12 +451,7 @@ pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, res->start = region->start + offset; res->end = region->end + offset; } - -#ifdef CONFIG_HOTPLUG -EXPORT_SYMBOL(pcibios_fixup_bus); -EXPORT_SYMBOL(pcibios_resource_to_bus); EXPORT_SYMBOL(pcibios_bus_to_resource); -#endif /* * Swizzle the device pin each time we cross a bridge. diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index b7685f1..204e216 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -151,6 +151,8 @@ printhex: adr r2, hexbuf b printascii ENDPROC(printhex2) +hexbuf: .space 16 + .ltorg ENTRY(printascii) @@ -175,5 +177,3 @@ ENTRY(printch) mov r0, #0 b 1b ENDPROC(printch) - -hexbuf: .space 16 diff --git a/arch/arm/kernel/dma.c b/arch/arm/kernel/dma.c index 2c4a185..7b829d9 100644 --- a/arch/arm/kernel/dma.c +++ b/arch/arm/kernel/dma.c @@ -23,7 +23,7 @@ #include <asm/mach/dma.h> -DEFINE_SPINLOCK(dma_spin_lock); +DEFINE_RAW_SPINLOCK(dma_spin_lock); EXPORT_SYMBOL(dma_spin_lock); static dma_t *dma_chan[MAX_DMA_CHANNELS]; diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index d165001..4dd0eda 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -237,7 +237,7 @@ static void ecard_init_pgtables(struct mm_struct *mm) memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (IO_SIZE / PGDIR_SIZE)); - src_pgd = pgd_offset(mm, EASI_BASE); + src_pgd = pgd_offset(mm, (unsigned long)EASI_BASE); dst_pgd = pgd_offset(mm, EASI_START); memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE)); @@ -674,44 +674,37 @@ static int __init ecard_probeirqhw(void) #define ecard_probeirqhw() (0) #endif -#ifndef IO_EC_MEMC8_BASE -#define IO_EC_MEMC8_BASE 0 -#endif - -static unsigned int __ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed) +static void __iomem *__ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed) { - unsigned long address = 0; + void __iomem *address = NULL; int slot = ec->slot_no; if (ec->slot_no == 8) - return IO_EC_MEMC8_BASE; + return ECARD_MEMC8_BASE; ectcr &= ~(1 << slot); switch (type) { case ECARD_MEMC: if (slot < 4) - address = IO_EC_MEMC_BASE + (slot << 12); + address = ECARD_MEMC_BASE + (slot << 14); break; case ECARD_IOC: if (slot < 4) - address = IO_EC_IOC_BASE + (slot << 12); -#ifdef IO_EC_IOC4_BASE + address = ECARD_IOC_BASE + (slot << 14); else - address = IO_EC_IOC4_BASE + ((slot - 4) << 12); -#endif + address = ECARD_IOC4_BASE + ((slot - 4) << 14); if (address) - address += speed << 17; + address += speed << 19; break; -#ifdef IO_EC_EASI_BASE case ECARD_EASI: - address = IO_EC_EASI_BASE + (slot << 22); + address = ECARD_EASI_BASE + (slot << 24); if (speed == ECARD_FAST) ectcr |= 1 << slot; break; -#endif + default: break; } @@ -990,6 +983,7 @@ ecard_probe(int slot, card_type_t type) ecard_t **ecp; ecard_t *ec; struct ex_ecid cid; + void __iomem *addr; int i, rc; ec = ecard_alloc_card(type, slot); @@ -999,7 +993,7 @@ ecard_probe(int slot, card_type_t type) } rc = -ENODEV; - if ((ec->podaddr = __ecard_address(ec, type, ECARD_SYNC)) == 0) + if ((addr = __ecard_address(ec, type, ECARD_SYNC)) == NULL) goto nodev; cid.r_zero = 1; @@ -1019,7 +1013,7 @@ ecard_probe(int slot, card_type_t type) ec->cid.fiqmask = cid.r_fiqmask; ec->cid.fiqoff = ecard_gets24(cid.r_fiqoff); ec->fiqaddr = - ec->irqaddr = (void __iomem *)ioaddr(ec->podaddr); + ec->irqaddr = addr; if (ec->cid.is) { ec->irqmask = ec->cid.irqmask; @@ -1048,10 +1042,8 @@ ecard_probe(int slot, card_type_t type) set_irq_flags(ec->irq, IRQF_VALID); } -#ifdef IO_EC_MEMC8_BASE if (slot == 8) ec->irq = 11; -#endif #ifdef CONFIG_ARCH_RPC /* On RiscPC, only first two slots have DMA capability */ if (slot < 2) @@ -1097,9 +1089,7 @@ static int __init ecard_init(void) ecard_probe(slot, ECARD_IOC); } -#ifdef IO_EC_MEMC8_BASE ecard_probe(8, ECARD_IOC); -#endif irqhw = ecard_probeirqhw(); diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index a87cbf8..9ad50c4 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -24,6 +24,7 @@ #include <asm/unwind.h> #include <asm/unistd.h> #include <asm/tls.h> +#include <asm/system.h> #include "entry-header.S" #include <asm/entry-macro-multi.S> @@ -262,8 +263,7 @@ __und_svc: ldr r0, [r4, #-4] #else ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 - and r9, r0, #0xf800 - cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 + cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 ldrhhs r9, [r4] @ bottom 16 bits orrhs r0, r9, r0, lsl #16 #endif @@ -440,18 +440,46 @@ __und_usr: #endif beq call_fpe @ Thumb instruction -#if __LINUX_ARM_ARCH__ >= 7 +#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 +/* + * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms + * can never be supported in a single kernel, this code is not applicable at + * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be + * made about .arch directives. + */ +#if __LINUX_ARM_ARCH__ < 7 +/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ +#define NEED_CPU_ARCHITECTURE + ldr r5, .LCcpu_architecture + ldr r5, [r5] + cmp r5, #CPU_ARCH_ARMv7 + blo __und_usr_unknown +/* + * The following code won't get run unless the running CPU really is v7, so + * coding round the lack of ldrht on older arches is pointless. Temporarily + * override the assembler target arch with the minimum required instead: + */ + .arch armv6t2 +#endif 2: ARM( ldrht r5, [r4], #2 ) THUMB( ldrht r5, [r4] ) THUMB( add r4, r4, #2 ) - and r0, r5, #0xf800 @ mask bits 111x x... .... .... - cmp r0, #0xe800 @ 32bit instruction if xx != 0 + cmp r5, #0xe800 @ 32bit instruction if xx != 0 blo __und_usr_unknown 3: ldrht r0, [r4] add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 orr r0, r0, r5, lsl #16 + +#if __LINUX_ARM_ARCH__ < 7 +/* If the target arch was overridden, change it back: */ +#ifdef CONFIG_CPU_32v6K + .arch armv6k #else + .arch armv6 +#endif +#endif /* __LINUX_ARM_ARCH__ < 7 */ +#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ b __und_usr_unknown #endif UNWIND(.fnend ) @@ -578,6 +606,12 @@ call_fpe: movw_pc lr @ CP#14 (Debug) movw_pc lr @ CP#15 (Control) +#ifdef NEED_CPU_ARCHITECTURE + .align 2 +.LCcpu_architecture: + .word __cpu_architecture +#endif + #ifdef CONFIG_NEON .align 6 diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 673c806..566c54c 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -21,6 +21,7 @@ #include <asm/memory.h> #include <asm/thread_info.h> #include <asm/system.h> +#include <asm/pgtable.h> #ifdef CONFIG_DEBUG_LL #include <mach/debug-macro.S> @@ -38,11 +39,14 @@ #error KERNEL_RAM_VADDR must start at 0xXXXX8000 #endif +#define PG_DIR_SIZE 0x4000 +#define PMD_ORDER 2 + .globl swapper_pg_dir - .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 + .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE .macro pgtbl, rd, phys - add \rd, \phys, #TEXT_OFFSET - 0x4000 + add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE .endm #ifdef CONFIG_XIP_KERNEL @@ -148,11 +152,11 @@ __create_page_tables: pgtbl r4, r8 @ page table address /* - * Clear the 16K level 1 swapper page table + * Clear the swapper page table */ mov r0, r4 mov r3, #0 - add r6, r0, #0x4000 + add r6, r0, #PG_DIR_SIZE 1: str r3, [r0], #4 str r3, [r0], #4 str r3, [r0], #4 @@ -171,30 +175,30 @@ __create_page_tables: sub r0, r0, r3 @ virt->phys offset add r5, r5, r0 @ phys __enable_mmu add r6, r6, r0 @ phys __enable_mmu_end - mov r5, r5, lsr #20 - mov r6, r6, lsr #20 + mov r5, r5, lsr #SECTION_SHIFT + mov r6, r6, lsr #SECTION_SHIFT -1: orr r3, r7, r5, lsl #20 @ flags + kernel base - str r3, [r4, r5, lsl #2] @ identity mapping - teq r5, r6 - addne r5, r5, #1 @ next section - bne 1b +1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base + str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping + cmp r5, r6 + addlo r5, r5, #1 @ next section + blo 1b /* * Now setup the pagetables for our kernel direct * mapped region. */ mov r3, pc - mov r3, r3, lsr #20 - orr r3, r7, r3, lsl #20 - add r0, r4, #(KERNEL_START & 0xff000000) >> 18 - str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! + mov r3, r3, lsr #SECTION_SHIFT + orr r3, r7, r3, lsl #SECTION_SHIFT + add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) + str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! ldr r6, =(KERNEL_END - 1) - add r0, r0, #4 - add r6, r4, r6, lsr #18 + add r0, r0, #1 << PMD_ORDER + add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 1: cmp r0, r6 - add r3, r3, #1 << 20 - strls r3, [r0], #4 + add r3, r3, #1 << SECTION_SHIFT + strls r3, [r0], #1 << PMD_ORDER bls 1b #ifdef CONFIG_XIP_KERNEL @@ -203,11 +207,11 @@ __create_page_tables: */ add r3, r8, #TEXT_OFFSET orr r3, r3, r7 - add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 - str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! + add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) + str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]! ldr r6, =(_end - 1) add r0, r0, #4 - add r6, r4, r6, lsr #18 + add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 1: cmp r0, r6 add r3, r3, #1 << 20 strls r3, [r0], #4 @@ -218,12 +222,12 @@ __create_page_tables: * Then map boot params address in r2 or * the first 1MB of ram if boot params address is not specified. */ - mov r0, r2, lsr #20 - movs r0, r0, lsl #20 + mov r0, r2, lsr #SECTION_SHIFT + movs r0, r0, lsl #SECTION_SHIFT moveq r0, r8 sub r3, r0, r8 add r3, r3, #PAGE_OFFSET - add r3, r4, r3, lsr #18 + add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) orr r6, r7, r0 str r6, [r3] @@ -236,21 +240,21 @@ __create_page_tables: */ addruart r7, r3, r0 - mov r3, r3, lsr #20 - mov r3, r3, lsl #2 + mov r3, r3, lsr #SECTION_SHIFT + mov r3, r3, lsl #PMD_ORDER add r0, r4, r3 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) cmp r3, #0x0800 @ limit to 512MB movhi r3, #0x0800 add r6, r0, r3 - mov r3, r7, lsr #20 + mov r3, r7, lsr #SECTION_SHIFT ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags - orr r3, r7, r3, lsl #20 + orr r3, r7, r3, lsl #SECTION_SHIFT 1: str r3, [r0], #4 - add r3, r3, #1 << 20 - teq r0, r6 - bne 1b + add r3, r3, #1 << SECTION_SHIFT + cmp r0, r6 + blo 1b #else /* CONFIG_DEBUG_ICEDCC */ /* we don't need any serial debugging mappings for ICEDCC */ @@ -262,7 +266,7 @@ __create_page_tables: * If we're using the NetWinder or CATS, we also need to map * in the 16550-type serial port for the debug messages */ - add r0, r4, #0xff000000 >> 18 + add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) orr r3, r7, #0x7c000000 str r3, [r0] #endif @@ -272,10 +276,10 @@ __create_page_tables: * Similar reasons here - for debug. This is * only for Acorn RiscPC architectures. */ - add r0, r4, #0x02000000 >> 18 + add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) orr r3, r7, #0x02000000 str r3, [r0] - add r0, r4, #0xd8000000 >> 18 + add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) str r3, [r0] #endif #endif diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index e59bbd4..c1b4463 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -32,6 +32,24 @@ static atomic_t waiting_for_crash_ipi; int machine_kexec_prepare(struct kimage *image) { + unsigned long page_list; + void *reboot_code_buffer; + page_list = image->head & PAGE_MASK; + + reboot_code_buffer = page_address(image->control_code_page); + + /* Prepare parameters for reboot_code_buffer*/ + kexec_start_address = image->start; + kexec_indirection_page = page_list; + kexec_mach_type = machine_arch_type; + kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET; + + /* copy our kernel relocation code to the control code page */ + memcpy(reboot_code_buffer, + relocate_new_kernel, relocate_new_kernel_size); + + flush_icache_range((unsigned long) reboot_code_buffer, + (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); return 0; } @@ -82,31 +100,14 @@ void (*kexec_reinit)(void); void machine_kexec(struct kimage *image) { - unsigned long page_list; unsigned long reboot_code_buffer_phys; void *reboot_code_buffer; - - page_list = image->head & PAGE_MASK; - /* we need both effective and real address here */ reboot_code_buffer_phys = page_to_pfn(image->control_code_page) << PAGE_SHIFT; reboot_code_buffer = page_address(image->control_code_page); - /* Prepare parameters for reboot_code_buffer*/ - kexec_start_address = image->start; - kexec_indirection_page = page_list; - kexec_mach_type = machine_arch_type; - kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET; - - /* copy our kernel relocation code to the control code page */ - memcpy(reboot_code_buffer, - relocate_new_kernel, relocate_new_kernel_size); - - - flush_icache_range((unsigned long) reboot_code_buffer, - (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); printk(KERN_INFO "Bye!\n"); if (kexec_reinit) diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index cc2020c..1e9be5d 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -33,7 +33,7 @@ * recompiling the whole kernel when CONFIG_XIP_KERNEL is turned on/off. */ #undef MODULES_VADDR -#define MODULES_VADDR (((unsigned long)_etext + ~PGDIR_MASK) & PGDIR_MASK) +#define MODULES_VADDR (((unsigned long)_etext + ~PMD_MASK) & PMD_MASK) #endif #ifdef CONFIG_MMU diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 98b7573..1ef6d00 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -324,8 +324,8 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE, - [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT, - [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS, + [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS, + [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 1a347f4..fd08140 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -319,7 +319,7 @@ void show_regs(struct pt_regs * regs) printk("\n"); printk("Pid: %d, comm: %20s\n", task_pid_nr(current), current->comm); __show_regs(regs); - __backtrace(); + dump_stack(); } ATOMIC_NOTIFIER_HEAD(thread_notify_head); diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 6136144..bda0a21 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -29,6 +29,8 @@ #include <linux/fs.h> #include <linux/proc_fs.h> #include <linux/memblock.h> +#include <linux/bug.h> +#include <linux/compiler.h> #include <asm/unified.h> #include <asm/cpu.h> @@ -42,6 +44,7 @@ #include <asm/cacheflush.h> #include <asm/cachetype.h> #include <asm/tlbflush.h> +#include <asm/system.h> #include <asm/prom.h> #include <asm/mach/arch.h> @@ -115,6 +118,13 @@ struct outer_cache_fns outer_cache __read_mostly; EXPORT_SYMBOL(outer_cache); #endif +/* + * Cached cpu_architecture() result for use by assembler code. + * C code should use the cpu_architecture() function instead of accessing this + * variable directly. + */ +int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN; + struct stack { u32 irq[3]; u32 abt[3]; @@ -210,7 +220,7 @@ static const char *proc_arch[] = { "?(17)", }; -int cpu_architecture(void) +static int __get_cpu_architecture(void) { int cpu_arch; @@ -243,11 +253,22 @@ int cpu_architecture(void) return cpu_arch; } +int __pure cpu_architecture(void) +{ + BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN); + + return __cpu_architecture; +} + static int cpu_has_aliasing_icache(unsigned int arch) { int aliasing_icache; unsigned int id_reg, num_sets, line_size; + /* PIPT caches never alias. */ + if (icache_is_pipt()) + return 0; + /* arch specifies the register format */ switch (arch) { case CPU_ARCH_ARMv7: @@ -282,8 +303,14 @@ static void __init cacheid_init(void) /* ARMv7 register format */ arch = CPU_ARCH_ARMv7; cacheid = CACHEID_VIPT_NONALIASING; - if ((cachetype & (3 << 14)) == 1 << 14) + switch (cachetype & (3 << 14)) { + case (1 << 14): cacheid |= CACHEID_ASID_TAGGED; + break; + case (3 << 14): + cacheid |= CACHEID_PIPT; + break; + } } else { arch = CPU_ARCH_ARMv6; if (cachetype & (1 << 23)) @@ -300,10 +327,11 @@ static void __init cacheid_init(void) printk("CPU: %s data cache, %s instruction cache\n", cache_is_vivt() ? "VIVT" : cache_is_vipt_aliasing() ? "VIPT aliasing" : - cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown", + cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown", cache_is_vivt() ? "VIVT" : icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" : icache_is_vipt_aliasing() ? "VIPT aliasing" : + icache_is_pipt() ? "PIPT" : cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown"); } @@ -414,6 +442,7 @@ static void __init setup_processor(void) } cpu_name = list->cpu_name; + __cpu_architecture = __get_cpu_architecture(); #ifdef MULTI_CPU processor = *list->proc; @@ -844,7 +873,7 @@ static struct machine_desc * __init setup_machine_tags(unsigned int nr) } if (mdesc->fixup) - mdesc->fixup(mdesc, tags, &from, &meminfo); + mdesc->fixup(tags, &from, &meminfo); if (tags->hdr.tag == ATAG_CORE) { if (meminfo.nr_banks != 0) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index a96c08c..ef5640b 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -319,17 +319,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void) */ platform_secondary_init(cpu); - /* - * Enable local interrupts. - */ notify_cpu_starting(cpu); - local_irq_enable(); - local_fiq_enable(); - - /* - * Setup the percpu timer for this CPU. - */ - percpu_timer_setup(); calibrate_delay(); @@ -341,10 +331,23 @@ asmlinkage void __cpuinit secondary_start_kernel(void) * before we continue. */ set_cpu_online(cpu, true); + + /* + * Setup the percpu timer for this CPU. + */ + percpu_timer_setup(); + while (!cpu_active(cpu)) cpu_relax(); /* + * cpu_active bit is set, so it's safe to enalbe interrupts + * now. + */ + local_irq_enable(); + local_fiq_enable(); + + /* * OK, it's off to the idle thread for us */ cpu_idle(); @@ -527,7 +530,7 @@ static void percpu_timer_stop(void) } #endif -static DEFINE_SPINLOCK(stop_lock); +static DEFINE_RAW_SPINLOCK(stop_lock); /* * ipi_cpu_stop - handle IPI from smp_send_stop() @@ -536,10 +539,10 @@ static void ipi_cpu_stop(unsigned int cpu) { if (system_state == SYSTEM_BOOTING || system_state == SYSTEM_RUNNING) { - spin_lock(&stop_lock); + raw_spin_lock(&stop_lock); printk(KERN_CRIT "CPU%u: stopping\n", cpu); dump_stack(); - spin_unlock(&stop_lock); + raw_spin_unlock(&stop_lock); } set_cpu_online(cpu, false); diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index cb634c3..5a54b95 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -39,13 +39,11 @@ */ static struct sys_timer *system_timer; -#if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) +#if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) || \ + defined(CONFIG_NVRAM) || defined(CONFIG_NVRAM_MODULE) /* this needs a better home */ DEFINE_SPINLOCK(rtc_lock); - -#ifdef CONFIG_RTC_DRV_CMOS_MODULE EXPORT_SYMBOL(rtc_lock); -#endif #endif /* pc-style 'CMOS' RTC support */ /* change this if you have some constant time drift */ diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 2103825..99a5727 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -21,6 +21,7 @@ #include <linux/kdebug.h> #include <linux/module.h> #include <linux/kexec.h> +#include <linux/bug.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/sched.h> @@ -256,7 +257,7 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt return ret; } -static DEFINE_SPINLOCK(die_lock); +static DEFINE_RAW_SPINLOCK(die_lock); /* * This function is protected against re-entrancy. @@ -268,9 +269,11 @@ void die(const char *str, struct pt_regs *regs, int err) oops_enter(); - spin_lock_irq(&die_lock); + raw_spin_lock_irq(&die_lock); console_verbose(); bust_spinlocks(1); + if (!user_mode(regs)) + report_bug(regs->ARM_pc, regs); ret = __die(str, err, thread, regs); if (regs && kexec_should_crash(thread->task)) @@ -278,7 +281,7 @@ void die(const char *str, struct pt_regs *regs, int err) bust_spinlocks(0); add_taint(TAINT_DIE); - spin_unlock_irq(&die_lock); + raw_spin_unlock_irq(&die_lock); oops_exit(); if (in_interrupt()) @@ -302,25 +305,43 @@ void arm_notify_die(const char *str, struct pt_regs *regs, } } +#ifdef CONFIG_GENERIC_BUG + +int is_valid_bugaddr(unsigned long pc) +{ +#ifdef CONFIG_THUMB2_KERNEL + unsigned short bkpt; +#else + unsigned long bkpt; +#endif + + if (probe_kernel_address((unsigned *)pc, bkpt)) + return 0; + + return bkpt == BUG_INSTR_VALUE; +} + +#endif + static LIST_HEAD(undef_hook); -static DEFINE_SPINLOCK(undef_lock); +static DEFINE_RAW_SPINLOCK(undef_lock); void register_undef_hook(struct undef_hook *hook) { unsigned long flags; - spin_lock_irqsave(&undef_lock, flags); + raw_spin_lock_irqsave(&undef_lock, flags); list_add(&hook->node, &undef_hook); - spin_unlock_irqrestore(&undef_lock, flags); + raw_spin_unlock_irqrestore(&undef_lock, flags); } void unregister_undef_hook(struct undef_hook *hook) { unsigned long flags; - spin_lock_irqsave(&undef_lock, flags); + raw_spin_lock_irqsave(&undef_lock, flags); list_del(&hook->node); - spin_unlock_irqrestore(&undef_lock, flags); + raw_spin_unlock_irqrestore(&undef_lock, flags); } static int call_undef_hook(struct pt_regs *regs, unsigned int instr) @@ -329,12 +350,12 @@ static int call_undef_hook(struct pt_regs *regs, unsigned int instr) unsigned long flags; int (*fn)(struct pt_regs *regs, unsigned int instr) = NULL; - spin_lock_irqsave(&undef_lock, flags); + raw_spin_lock_irqsave(&undef_lock, flags); list_for_each_entry(hook, &undef_hook, node) if ((instr & hook->instr_mask) == hook->instr_val && (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val) fn = hook->fn; - spin_unlock_irqrestore(&undef_lock, flags); + raw_spin_unlock_irqrestore(&undef_lock, flags); return fn ? fn(regs, instr) : 1; } @@ -707,16 +728,6 @@ baddataabort(int code, unsigned long instr, struct pt_regs *regs) arm_notify_die("unknown data abort code", regs, &info, instr, 0); } -void __attribute__((noreturn)) __bug(const char *file, int line) -{ - printk(KERN_CRIT"kernel BUG at %s:%d!\n", file, line); - *(int *)0 = 0; - - /* Avoid "noreturn function does return" */ - for (;;); -} -EXPORT_SYMBOL(__bug); - void __readwrite_bug(const char *fn) { printk("%s called, but not implemented\n", fn); diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 4e66f62..20b3041 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -21,7 +21,8 @@ #define ARM_CPU_KEEP(x) #endif -#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK) +#if (defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)) || \ + defined(CONFIG_GENERIC_BUG) #define ARM_EXIT_KEEP(x) x #define ARM_EXIT_DISCARD(x) #else diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S index a673297..cd07b58 100644 --- a/arch/arm/lib/backtrace.S +++ b/arch/arm/lib/backtrace.S @@ -22,15 +22,10 @@ #define mask r7 #define offset r8 -ENTRY(__backtrace) - mov r1, #0x10 - mov r0, fp - ENTRY(c_backtrace) #if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK) mov pc, lr -ENDPROC(__backtrace) ENDPROC(c_backtrace) #else stmfd sp!, {r4 - r8, lr} @ Save an extra register so we have a location... @@ -107,7 +102,6 @@ for_each_frame: tst frame, mask @ Check for address exceptions mov r1, frame bl printk no_frame: ldmfd sp!, {r4 - r8, pc} -ENDPROC(__backtrace) ENDPROC(c_backtrace) .pushsection __ex_table,"a" diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S index faa7748..e55c484 100644 --- a/arch/arm/lib/div64.S +++ b/arch/arm/lib/div64.S @@ -13,6 +13,7 @@ */ #include <linux/linkage.h> +#include <asm/unwind.h> #ifdef __ARMEB__ #define xh r0 @@ -44,6 +45,7 @@ */ ENTRY(__do_div64) +UNWIND(.fnstart) @ Test for easy paths first. subs ip, r4, #1 @@ -189,7 +191,12 @@ ENTRY(__do_div64) moveq yh, xh moveq xh, #0 moveq pc, lr +UNWIND(.fnend) +UNWIND(.fnstart) +UNWIND(.pad #4) +UNWIND(.save {lr}) +Ldiv0_64: @ Division by 0: str lr, [sp, #-8]! bl __div0 @@ -200,4 +207,5 @@ ENTRY(__do_div64) mov xh, #0 ldr pc, [sp], #8 +UNWIND(.fnend) ENDPROC(__do_div64) diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c index 8b9b136..025f742 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -17,6 +17,7 @@ #include <linux/sched.h> #include <linux/hardirq.h> /* for in_atomic() */ #include <linux/gfp.h> +#include <linux/highmem.h> #include <asm/current.h> #include <asm/page.h> diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot index 3462b81..9ab5a3e 100644 --- a/arch/arm/mach-at91/Makefile.boot +++ b/arch/arm/mach-at91/Makefile.boot @@ -4,15 +4,15 @@ # INITRD_PHYS must be in RAM ifeq ($(CONFIG_ARCH_AT91CAP9),y) - zreladdr-y := 0x70008000 + zreladdr-y += 0x70008000 params_phys-y := 0x70000100 initrd_phys-y := 0x70410000 else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y) - zreladdr-y := 0x70008000 + zreladdr-y += 0x70008000 params_phys-y := 0x70000100 initrd_phys-y := 0x70410000 else - zreladdr-y := 0x20008000 + zreladdr-y += 0x20008000 params_phys-y := 0x20000100 initrd_phys-y := 0x20410000 endif diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index a53b3de..3c2b580 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -319,7 +319,7 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) if (!data) return; - for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { + for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { if (data->slot[i].bus_width) { /* input/irq */ if (data->slot[i].detect_pin) { diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 1532b50..00c0a78 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -54,6 +54,11 @@ static struct clk pioDE_clk = { .pmc_mask = 1 << AT91SAM9G45_ID_PIODE, .type = CLK_TYPE_PERIPHERAL, }; +static struct clk trng_clk = { + .name = "trng_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_TRNG, + .type = CLK_TYPE_PERIPHERAL, +}; static struct clk usart0_clk = { .name = "usart0_clk", .pmc_mask = 1 << AT91SAM9G45_ID_US0, @@ -177,6 +182,7 @@ static struct clk *periph_clocks[] __initdata = { &pioB_clk, &pioC_clk, &pioDE_clk, + &trng_clk, &usart0_clk, &usart1_clk, &usart2_clk, @@ -216,6 +222,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), + CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index c3dfb1b..2d6d57f 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -1095,6 +1095,34 @@ static void __init at91_add_device_rtt(void) /* -------------------------------------------------------------------- + * TRNG + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE) +static struct resource trng_resources[] = { + { + .start = AT91SAM9G45_BASE_TRNG, + .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device at91sam9g45_trng_device = { + .name = "atmel-trng", + .id = -1, + .resource = trng_resources, + .num_resources = ARRAY_SIZE(trng_resources), +}; + +static void __init at91_add_device_trng(void) +{ + platform_device_register(&at91sam9g45_trng_device); +} +#else +static void __init at91_add_device_trng(void) {} +#endif + +/* -------------------------------------------------------------------- * Watchdog * -------------------------------------------------------------------- */ @@ -1583,6 +1611,7 @@ static int __init at91_add_standard_devices(void) at91_add_device_hdmac(); at91_add_device_rtc(); at91_add_device_rtt(); + at91_add_device_trng(); at91_add_device_watchdog(); at91_add_device_tc(); return 0; diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig index 457b438..9170d16 100644 --- a/arch/arm/mach-bcmring/Kconfig +++ b/arch/arm/mach-bcmring/Kconfig @@ -17,5 +17,3 @@ config BCM_ZRELADDR hex "Compressed ZREL ADDR" endmenu - -# source "drivers/char/bcmring/Kconfig" diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot index fb53b28..aef2467 100644 --- a/arch/arm/mach-bcmring/Makefile.boot +++ b/arch/arm/mach-bcmring/Makefile.boot @@ -1,6 +1,6 @@ # Address where decompressor will be written and eventually executed. # # default to SDRAM -zreladdr-y := $(CONFIG_BCM_ZRELADDR) +zreladdr-y += $(CONFIG_BCM_ZRELADDR) params_phys-y := 0x00000800 diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c index a604b9e..31a1435 100644 --- a/arch/arm/mach-bcmring/arch.c +++ b/arch/arm/mach-bcmring/arch.c @@ -136,8 +136,8 @@ static void __init bcmring_init_machine(void) * *****************************************************************************/ -static void __init bcmring_fixup(struct machine_desc *desc, - struct tag *t, char **cmdline, struct meminfo *mi) { +static void __init bcmring_fixup(struct tag *t, char **cmdline, + struct meminfo *mi) { #ifdef CONFIG_BLK_DEV_INITRD printk(KERN_NOTICE "bcmring_fixup\n"); t->hdr.tag = ATAG_CORE; diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c index c48feaf..437fa68 100644 --- a/arch/arm/mach-bcmring/irq.c +++ b/arch/arm/mach-bcmring/irq.c @@ -20,7 +20,6 @@ #include <linux/stddef.h> #include <linux/list.h> #include <linux/timer.h> -#include <linux/version.h> #include <linux/io.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c index 2d415d2..af9c3d7 100644 --- a/arch/arm/mach-bcmring/timer.c +++ b/arch/arm/mach-bcmring/timer.c @@ -12,7 +12,6 @@ * consent. *****************************************************************************/ -#include <linux/version.h> #include <linux/types.h> #include <linux/module.h> #include <csp/tmrHw.h> diff --git a/arch/arm/mach-clps711x/Makefile.boot b/arch/arm/mach-clps711x/Makefile.boot index a51fcef..9398e85 100644 --- a/arch/arm/mach-clps711x/Makefile.boot +++ b/arch/arm/mach-clps711x/Makefile.boot @@ -1,5 +1,5 @@ # The standard locations for stuff on CLPS711x type processors - zreladdr-y := 0xc0028000 + zreladdr-y += 0xc0028000 params_phys-y := 0xc0000100 # Should probably have some agreement on these... initrd_phys-$(CONFIG_ARCH_P720T) := 0xc0400000 diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c index 06c8abd..80496c0 100644 --- a/arch/arm/mach-clps711x/clep7312.c +++ b/arch/arm/mach-clps711x/clep7312.c @@ -26,8 +26,7 @@ #include "common.h" static void __init -fixup_clep7312(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi) { mi->nr_banks=1; mi->bank[0].start = 0xc0000000; diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c index abf522d..9721f61 100644 --- a/arch/arm/mach-clps711x/edb7211-arch.c +++ b/arch/arm/mach-clps711x/edb7211-arch.c @@ -37,8 +37,7 @@ static void __init edb7211_reserve(void) } static void __init -fixup_edb7211(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi) { /* * Bank start addresses are not present in the information diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c index b6f7d86..d992566 100644 --- a/arch/arm/mach-clps711x/fortunet.c +++ b/arch/arm/mach-clps711x/fortunet.c @@ -57,8 +57,7 @@ typedef struct tag_IMAGE_PARAMS #define IMAGE_PARAMS_PHYS 0xC01F0000 static void __init -fortunet_fixup(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +fortunet_fixup(struct tag *tags, char **cmdline, struct meminfo *mi) { IMAGE_PARAMS *ip = phys_to_virt(IMAGE_PARAMS_PHYS); *cmdline = phys_to_virt(ip->command_line); diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c index e7f75ae..6ecea95 100644 --- a/arch/arm/mach-clps711x/p720t.c +++ b/arch/arm/mach-clps711x/p720t.c @@ -56,8 +56,7 @@ static struct map_desc p720t_io_desc[] __initdata = { }; static void __init -fixup_p720t(struct machine_desc *desc, struct tag *tag, - char **cmdline, struct meminfo *mi) +fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi) { /* * Our bootloader doesn't setup any tags (yet). diff --git a/arch/arm/mach-cns3xxx/Makefile.boot b/arch/arm/mach-cns3xxx/Makefile.boot index 7770128..d079de0 100644 --- a/arch/arm/mach-cns3xxx/Makefile.boot +++ b/arch/arm/mach-cns3xxx/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00C00000 diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot index db97ef2..04a6c4e 100644 --- a/arch/arm/mach-davinci/Makefile.boot +++ b/arch/arm/mach-davinci/Makefile.boot @@ -2,12 +2,12 @@ ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y) ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y) $(error Cannot enable DaVinci and DA8XX platforms concurrently) else - zreladdr-y := 0xc0008000 + zreladdr-y += 0xc0008000 params_phys-y := 0xc0000100 initrd_phys-y := 0xc0800000 endif else - zreladdr-y := 0x80008000 + zreladdr-y += 0x80008000 params_phys-y := 0x80000100 initrd_phys-y := 0x80800000 endif diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 2f7e719..68def71 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -136,6 +136,7 @@ static struct edma_soc_info da830_edma_cc0_info = { .n_cc = 1, .queue_tc_mapping = da8xx_queue_tc_mapping, .queue_priority_mapping = da8xx_queue_priority_mapping, + .default_queue = EVENTQ_1, }; static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { @@ -151,6 +152,7 @@ static struct edma_soc_info da850_edma_cc_info[] = { .n_cc = 1, .queue_tc_mapping = da8xx_queue_tc_mapping, .queue_priority_mapping = da8xx_queue_priority_mapping, + .default_queue = EVENTQ_1, }, { .n_channel = 32, @@ -160,6 +162,7 @@ static struct edma_soc_info da850_edma_cc_info[] = { .n_cc = 1, .queue_tc_mapping = da850_queue_tc_mapping, .queue_priority_mapping = da850_queue_priority_mapping, + .default_queue = EVENTQ_0, }, }; diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index 6162cae..29b17f7 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -80,6 +80,7 @@ static struct edma_soc_info edma_cc0_info = { .n_cc = 1, .queue_tc_mapping = edma_tc_mapping, .queue_priority_mapping = edma_priority_mapping, + .default_queue = EVENTQ_1, }; static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = { diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index c143f43..fe520d4 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -591,6 +591,7 @@ static struct edma_soc_info edma_cc0_info = { .n_cc = 1, .queue_tc_mapping = queue_tc_mapping, .queue_priority_mapping = queue_priority_mapping, + .default_queue = EVENTQ_1, }; static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = { diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 9a27466..3470983 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -514,6 +514,7 @@ static struct edma_soc_info edma_cc0_info = { .n_cc = 1, .queue_tc_mapping = queue_tc_mapping, .queue_priority_mapping = queue_priority_mapping, + .default_queue = EVENTQ_1, }; static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = { diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 03e5f49..0b68ed5 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -555,6 +555,7 @@ static struct edma_soc_info edma_cc0_info = { .n_cc = 1, .queue_tc_mapping = dm646x_queue_tc_mapping, .queue_priority_mapping = dm646x_queue_priority_mapping, + .default_queue = EVENTQ_1, }; static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = { diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 6b96698..da90103 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -1435,12 +1435,11 @@ static int __init edma_probe(struct platform_device *pdev) goto fail1; } - edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); + edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL); if (!edma_cc[j]) { status = -ENOMEM; goto fail1; } - memset(edma_cc[j], 0, sizeof(struct edma)); edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel, EDMA_MAX_DMACH); @@ -1450,8 +1449,6 @@ static int __init edma_probe(struct platform_device *pdev) EDMA_MAX_CC); edma_cc[j]->default_queue = info[j]->default_queue; - if (!edma_cc[j]->default_queue) - edma_cc[j]->default_queue = EVENTQ_1; dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[j]); diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot index 67039c3..760a0ef 100644 --- a/arch/arm/mach-dove/Makefile.boot +++ b/arch/arm/mach-dove/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-ebsa110/Makefile.boot b/arch/arm/mach-ebsa110/Makefile.boot index 2321260..83cf07c 100644 --- a/arch/arm/mach-ebsa110/Makefile.boot +++ b/arch/arm/mach-ebsa110/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000400 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h index f68daa63..44679db 100644 --- a/arch/arm/mach-ebsa110/include/mach/io.h +++ b/arch/arm/mach-ebsa110/include/mach/io.h @@ -13,8 +13,6 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#define IO_SPACE_LIMIT 0xffff - u8 __inb8(unsigned int port); void __outb8(u8 val, unsigned int port); diff --git a/arch/arm/mach-ep93xx/Makefile.boot b/arch/arm/mach-ep93xx/Makefile.boot index 0ad33f1..d3113a7 100644 --- a/arch/arm/mach-ep93xx/Makefile.boot +++ b/arch/arm/mach-ep93xx/Makefile.boot @@ -1,14 +1,14 @@ - zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) := 0x00008000 + zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) += 0x00008000 params_phys-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) := 0x00000100 - zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) := 0xc0008000 + zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) += 0xc0008000 params_phys-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) := 0xc0000100 - zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) := 0xd0008000 + zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) += 0xd0008000 params_phys-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) := 0xd0000100 - zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) := 0xe0008000 + zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) += 0xe0008000 params_phys-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) := 0xe0000100 - zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) := 0xf0008000 + zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) += 0xf0008000 params_phys-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) := 0xf0000100 diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index c63a5ec..70ef8c5 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -160,6 +160,11 @@ static void __init edb93xx_register_spi(void) /************************************************************************* * EDB93xx I2S *************************************************************************/ +static struct platform_device edb93xx_audio_device = { + .name = "edb93xx-audio", + .id = -1, +}; + static int __init edb93xx_has_audio(void) { return (machine_is_edb9301() || machine_is_edb9302() || @@ -171,6 +176,7 @@ static void __init edb93xx_register_i2s(void) { if (edb93xx_has_audio()) { ep93xx_register_i2s(); + platform_device_register(&edb93xx_audio_device); } } diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-ep93xx/include/mach/gpio.h new file mode 100644 index 0000000..40a8c17 --- /dev/null +++ b/arch/arm/mach-ep93xx/include/mach/gpio.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index d6f286b..52e090d 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -53,6 +53,17 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = { }, }; +static struct platform_device simone_audio_device = { + .name = "simone-audio", + .id = -1, +}; + +static void __init simone_register_audio(void) +{ + ep93xx_register_ac97(); + platform_device_register(&simone_audio_device); +} + static void __init simone_init_machine(void) { ep93xx_init_devices(); @@ -61,7 +72,7 @@ static void __init simone_init_machine(void) ep93xx_register_fb(&simone_fb_info); ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info, ARRAY_SIZE(simone_i2c_board_info)); - ep93xx_register_ac97(); + simone_register_audio(); } MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index 2b4d4b0..8121e3a 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -150,6 +150,17 @@ static struct ep93xxfb_mach_info __initdata snappercl15_fb_info = { .bpp = 16, }; +static struct platform_device snappercl15_audio_device = { + .name = "snappercl15-audio", + .id = -1, +}; + +static void __init snappercl15_register_audio(void) +{ + ep93xx_register_i2s(); + platform_device_register(&snappercl15_audio_device); +} + static void __init snappercl15_init_machine(void) { ep93xx_init_devices(); @@ -157,7 +168,7 @@ static void __init snappercl15_init_machine(void) ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data, ARRAY_SIZE(snappercl15_i2c_data)); ep93xx_register_fb(&snappercl15_fb_info); - ep93xx_register_i2s(); + snappercl15_register_audio(); platform_device_register(&snappercl15_nand_device); } diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index fec2385..a652735 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -12,6 +12,7 @@ if ARCH_EXYNOS4 config CPU_EXYNOS4210 bool select S3C_PL330_DMA + select ARM_CPU_SUSPEND if PM help Enable EXYNOS4210 CPU support diff --git a/arch/arm/mach-exynos4/Makefile.boot b/arch/arm/mach-exynos4/Makefile.boot index d65956f..b9862e2 100644 --- a/arch/arm/mach-exynos4/Makefile.boot +++ b/arch/arm/mach-exynos4/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x40008000 + zreladdr-y += 0x40008000 params_phys-y := 0x40000100 diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index c8e7afc..f643ef8 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -4,8 +4,8 @@ menu "Footbridge Implementations" config ARCH_CATS bool "CATS" - select CLKSRC_I8253 select CLKEVT_I8253 + select CLKSRC_I8253 select FOOTBRIDGE_HOST select ISA select ISA_DMA @@ -61,8 +61,8 @@ config ARCH_EBSA285_HOST config ARCH_NETWINDER bool "NetWinder" - select CLKSRC_I8253 select CLKEVT_I8253 + select CLKSRC_I8253 select FOOTBRIDGE_HOST select ISA select ISA_DMA diff --git a/arch/arm/mach-footbridge/Makefile.boot b/arch/arm/mach-footbridge/Makefile.boot index c7e75ac..ff0a4b5 100644 --- a/arch/arm/mach-footbridge/Makefile.boot +++ b/arch/arm/mach-footbridge/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c index a3da5d1..d5f1785 100644 --- a/arch/arm/mach-footbridge/cats-hw.c +++ b/arch/arm/mach-footbridge/cats-hw.c @@ -76,8 +76,7 @@ __initcall(cats_hw_init); * hard reboots fail on early boards. */ static void __init -fixup_cats(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi) { screen_info.orig_video_lines = 25; screen_info.orig_video_points = 16; diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h index 15d5498..e3d6cca 100644 --- a/arch/arm/mach-footbridge/include/mach/hardware.h +++ b/arch/arm/mach-footbridge/include/mach/hardware.h @@ -93,7 +93,7 @@ #define CPLD_FLASH_WR_ENABLE 1 #ifndef __ASSEMBLY__ -extern spinlock_t nw_gpio_lock; +extern raw_spinlock_t nw_gpio_lock; extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); extern unsigned int nw_gpio_read(void); diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h index 32e4cc3..15a7039 100644 --- a/arch/arm/mach-footbridge/include/mach/io.h +++ b/arch/arm/mach-footbridge/include/mach/io.h @@ -23,8 +23,6 @@ #define PCIO_SIZE 0x00100000 #define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) -#define IO_SPACE_LIMIT 0xffff - /* * Translation of various region addresses to virtual addresses */ diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c index d8c1c92..0d3846f 100644 --- a/arch/arm/mach-footbridge/netwinder-hw.c +++ b/arch/arm/mach-footbridge/netwinder-hw.c @@ -68,7 +68,7 @@ static inline void wb977_ww(int reg, int val) /* * This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE */ -DEFINE_SPINLOCK(nw_gpio_lock); +DEFINE_RAW_SPINLOCK(nw_gpio_lock); EXPORT_SYMBOL(nw_gpio_lock); static unsigned int current_gpio_op; @@ -327,9 +327,9 @@ static inline void wb977_init_gpio(void) /* * Set Group1/Group2 outputs */ - spin_lock_irqsave(&nw_gpio_lock, flags); + raw_spin_lock_irqsave(&nw_gpio_lock, flags); nw_gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN); - spin_unlock_irqrestore(&nw_gpio_lock, flags); + raw_spin_unlock_irqrestore(&nw_gpio_lock, flags); } /* @@ -390,9 +390,9 @@ static void __init cpld_init(void) { unsigned long flags; - spin_lock_irqsave(&nw_gpio_lock, flags); + raw_spin_lock_irqsave(&nw_gpio_lock, flags); nw_cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE); - spin_unlock_irqrestore(&nw_gpio_lock, flags); + raw_spin_unlock_irqrestore(&nw_gpio_lock, flags); } static unsigned char rwa_unlock[] __initdata = @@ -616,9 +616,9 @@ static int __init nw_hw_init(void) cpld_init(); rwa010_init(); - spin_lock_irqsave(&nw_gpio_lock, flags); + raw_spin_lock_irqsave(&nw_gpio_lock, flags); nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS); - spin_unlock_irqrestore(&nw_gpio_lock, flags); + raw_spin_unlock_irqrestore(&nw_gpio_lock, flags); } return 0; } @@ -631,8 +631,7 @@ __initcall(nw_hw_init); * the parameter page. */ static void __init -fixup_netwinder(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi) { #ifdef CONFIG_ISAPNP extern int isapnp_disable; diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c index 00269fe..e57102e 100644 --- a/arch/arm/mach-footbridge/netwinder-leds.c +++ b/arch/arm/mach-footbridge/netwinder-leds.c @@ -31,13 +31,13 @@ static char led_state; static char hw_led_state; -static DEFINE_SPINLOCK(leds_lock); +static DEFINE_RAW_SPINLOCK(leds_lock); static void netwinder_leds_event(led_event_t evt) { unsigned long flags; - spin_lock_irqsave(&leds_lock, flags); + raw_spin_lock_irqsave(&leds_lock, flags); switch (evt) { case led_start: @@ -117,12 +117,12 @@ static void netwinder_leds_event(led_event_t evt) break; } - spin_unlock_irqrestore(&leds_lock, flags); + raw_spin_unlock_irqrestore(&leds_lock, flags); if (led_state & LED_STATE_ENABLED) { - spin_lock_irqsave(&nw_gpio_lock, flags); + raw_spin_lock_irqsave(&nw_gpio_lock, flags); nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state); - spin_unlock_irqrestore(&nw_gpio_lock, flags); + raw_spin_unlock_irqrestore(&nw_gpio_lock, flags); } } diff --git a/arch/arm/mach-gemini/Makefile.boot b/arch/arm/mach-gemini/Makefile.boot index 22a52c2..683f52b 100644 --- a/arch/arm/mach-gemini/Makefile.boot +++ b/arch/arm/mach-gemini/Makefile.boot @@ -1,9 +1,9 @@ ifeq ($(CONFIG_GEMINI_MEM_SWAP),y) - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 else - zreladdr-y := 0x10008000 + zreladdr-y += 0x10008000 params_phys-y := 0x10000100 initrd_phys-y := 0x10800000 endif diff --git a/arch/arm/mach-h720x/Makefile.boot b/arch/arm/mach-h720x/Makefile.boot index 5298401..d875a70 100644 --- a/arch/arm/mach-h720x/Makefile.boot +++ b/arch/arm/mach-h720x/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-$(CONFIG_ARCH_H720X) := 0x40008000 + zreladdr-$(CONFIG_ARCH_H720X) += 0x40008000 diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 0519dd7..e9c2968 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -449,6 +449,7 @@ config MACH_MX31_3DS select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IPU_CORE select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e9eb36d..6cc8213 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,16 +1,15 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o -obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o -obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o +obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o +obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o -obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o +obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o -obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o -obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o +obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o +obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o -obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o -obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o -obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o +obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o +obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o # Support for CMOS sensor interface obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index ebee18b..dbe6120 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -1,19 +1,19 @@ -zreladdr-$(CONFIG_ARCH_MX1) := 0x08008000 +zreladdr-$(CONFIG_ARCH_MX1) += 0x08008000 params_phys-$(CONFIG_ARCH_MX1) := 0x08000100 initrd_phys-$(CONFIG_ARCH_MX1) := 0x08800000 -zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 +zreladdr-$(CONFIG_MACH_MX21) += 0xC0008000 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 -zreladdr-$(CONFIG_ARCH_MX25) := 0x80008000 +zreladdr-$(CONFIG_ARCH_MX25) += 0x80008000 params_phys-$(CONFIG_ARCH_MX25) := 0x80000100 initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000 -zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 +zreladdr-$(CONFIG_MACH_MX27) += 0xA0008000 params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 -zreladdr-$(CONFIG_ARCH_MX3) := 0x80008000 +zreladdr-$(CONFIG_ARCH_MX3) += 0x80008000 params_phys-$(CONFIG_ARCH_MX3) := 0x80000100 initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000 diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c deleted file mode 100644 index 69d1322..0000000 --- a/arch/arm/mach-imx/cache-l2x0.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Sascha Hauer <s.hauer@pengutronix.de> - * Juergen Beisert <j.beisert@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/err.h> -#include <linux/kernel.h> - -#include <asm/hardware/cache-l2x0.h> - -#include <mach/hardware.h> - -static int mxc_init_l2x0(void) -{ - void __iomem *l2x0_base; - void __iomem *clkctl_base; - - if (!cpu_is_mx31() && !cpu_is_mx35()) - return 0; - -/* - * First of all, we must repair broken chip settings. There are some - * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These - * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. - * Workaraound is to setup the correct register setting prior enabling the - * L2 cache. This should not hurt already working CPUs, as they are using the - * same value. - */ -#define L2_MEM_VAL 0x10 - - clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); - if (clkctl_base != NULL) { - writel(0x00000515, clkctl_base + L2_MEM_VAL); - iounmap(clkctl_base); - } else { - pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); - } - - l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); - if (IS_ERR(l2x0_base)) { - printk(KERN_ERR "remapping L2 cache area failed with %ld\n", - PTR_ERR(l2x0_base)); - return 0; - } - - l2x0_init(l2x0_base, 0x00030024, 0x00000000); - - return 0; -} -arch_initcall(mxc_init_l2x0); diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 6912b82..becc92e 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -583,7 +583,7 @@ DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk); DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk); DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk); DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk); -DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk); +DEFINE_CLOCK(pata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk); DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk); DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk); DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk); @@ -666,7 +666,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk) _REGISTER_CLOCK(NULL, "emi", emi_clk) _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) - _REGISTER_CLOCK(NULL, "ata", ata_clk) + _REGISTER_CLOCK("pata_imx", NULL, pata_clk) _REGISTER_CLOCK(NULL, "mstick", mstick_clk) _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "gpio", gpio_clk) diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c index d973770..58ea0a85 100644 --- a/arch/arm/mach-imx/clock-imx31.c +++ b/arch/arm/mach-imx/clock-imx31.c @@ -476,7 +476,7 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk); DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk); DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk); DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk); -DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); +DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk); DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk); DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk); @@ -562,7 +562,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK(NULL, "firi", firi_clk) - _REGISTER_CLOCK(NULL, "ata", ata_clk) + _REGISTER_CLOCK("pata_imx", NULL, pata_clk) _REGISTER_CLOCK(NULL, "rtic", rtic_clk) _REGISTER_CLOCK(NULL, "rng", rng_clk) _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1) diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c index 88b62a0..c39f5c3 100644 --- a/arch/arm/mach-imx/clock-imx35.c +++ b/arch/arm/mach-imx/clock-imx35.c @@ -354,7 +354,7 @@ static void clk_cgr_disable(struct clk *clk) } DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); -DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); +DEFINE_CLOCK(pata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); /* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */ DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); @@ -447,7 +447,7 @@ static struct clk nfc_clk = { static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "asrc", asrc_clk) - _REGISTER_CLOCK(NULL, "ata", ata_clk) + _REGISTER_CLOCK("pata_imx", NULL, pata_clk) _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 7f97a3c..2f727d7 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -76,3 +76,7 @@ extern const struct imx_spi_imx_data imx27_cspi_data[]; #define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) #define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata) #define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata) + +extern const struct imx_pata_imx_data imx27_pata_imx_data; +#define imx27_add_pata_imx() \ + imx_add_pata_imx(&imx27_pata_imx_data) diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h index dbe940d..488e241 100644 --- a/arch/arm/mach-imx/devices-imx31.h +++ b/arch/arm/mach-imx/devices-imx31.h @@ -78,3 +78,7 @@ extern const struct imx_spi_imx_data imx31_cspi_data[]; #define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) #define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata) #define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata) + +extern const struct imx_pata_imx_data imx31_pata_imx_data; +#define imx31_add_pata_imx() \ + imx_add_pata_imx(&imx31_pata_imx_data) diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h index 234cbd3..7b99ef0 100644 --- a/arch/arm/mach-imx/devices-imx35.h +++ b/arch/arm/mach-imx/devices-imx35.h @@ -81,3 +81,7 @@ extern const struct imx_spi_imx_data imx35_cspi_data[]; imx_add_spi_imx(&imx35_cspi_data[id], pdata) #define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) #define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) + +extern const struct imx_pata_imx_data imx35_pata_imx_data; +#define imx35_add_pata_imx() \ + imx_add_pata_imx(&imx35_pata_imx_data) diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index 2152590..fa2b97d 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c @@ -314,25 +314,19 @@ static struct mtd_partition armadillo5x0_nor_flash_partitions[] = { }, }; -static struct physmap_flash_data armadillo5x0_nor_flash_pdata = { +static const struct physmap_flash_data + armadillo5x0_nor_flash_pdata __initconst = { .width = 2, .parts = armadillo5x0_nor_flash_partitions, .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions), }; -static struct resource armadillo5x0_nor_flash_resource = { +static const struct resource armadillo5x0_nor_flash_resource __initconst = { .flags = IORESOURCE_MEM, .start = MX31_CS0_BASE_ADDR, .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, }; -static struct platform_device armadillo5x0_nor_flash = { - .name = "physmap-flash", - .id = -1, - .num_resources = 1, - .resource = &armadillo5x0_nor_flash_resource, -}; - /* * FB support */ @@ -514,8 +508,10 @@ static void __init armadillo5x0_init(void) imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* Register NOR Flash */ - mxc_register_device(&armadillo5x0_nor_flash, - &armadillo5x0_nor_flash_pdata); + platform_device_register_resndata(NULL, "physmap-flash", -1, + &armadillo5x0_nor_flash_resource, 1, + &armadillo5x0_nor_flash_pdata, + sizeof(armadillo5x0_nor_flash_pdata)); /* Register NAND Flash */ imx31_add_mxc_nand(&armadillo5x0_nand_board_info); diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 470b654..ea6c9c3 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c @@ -66,7 +66,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { I2C_BOARD_INFO("tsc2007", 0x48), .type = "tsc2007", .platform_data = &tsc2007_info, - .irq = gpio_to_irq(TSC2007_IRQGPIO), + .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO), }, }; diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c index 7c20e9e..4e030ac 100644 --- a/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c @@ -36,6 +36,7 @@ #include <mach/clock.h> #include <mach/common.h> +#include <mach/hardware.h> #include <mach/iomux-mx3.h> #include "devices-imx31.h" diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 530ea08..b4a5e03 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -68,23 +68,16 @@ static const struct imxuart_platform_data uart1_pdata __initconst = { * Physmap flash */ -static struct physmap_flash_data mx1ads_flash_data = { +static const struct physmap_flash_data mx1ads_flash_data __initconst = { .width = 4, /* bankwidth in bytes */ }; -static struct resource flash_resource = { +static const struct resource flash_resource __initconst = { .start = MX1_CS0_PHYS, .end = MX1_CS0_PHYS + SZ_32M - 1, .flags = IORESOURCE_MEM, }; -static struct platform_device flash_device = { - .name = "physmap-flash", - .id = 0, - .resource = &flash_resource, - .num_resources = 1, -}; - /* * I2C */ @@ -125,7 +118,9 @@ static void __init mx1ads_init(void) imx1_add_imx_uart1(&uart1_pdata); /* Physmap flash */ - mxc_register_device(&flash_device, &mx1ads_flash_data); + platform_device_register_resndata(NULL, "physmap-flash", 0, + &flash_resource, 1, + &mx1ads_flash_data, sizeof(mx1ads_flash_data)); /* I2C */ i2c_register_board_info(0, mx1ads_i2c_devices, diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 2eafbac..04bc86d 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -241,7 +241,7 @@ static struct regulator_init_data gpo_init = { }; static struct regulator_consumer_supply vmmc1_consumers[] = { - REGULATOR_SUPPLY("lcd_2v8", NULL), + REGULATOR_SUPPLY("vcore", "spi0.0"), }; static struct regulator_init_data vmmc1_init = { @@ -257,7 +257,7 @@ static struct regulator_init_data vmmc1_init = { }; static struct regulator_consumer_supply vgen_consumers[] = { - REGULATOR_SUPPLY("vdd_lcdio", NULL), + REGULATOR_SUPPLY("vdd", "spi0.0"), }; static struct regulator_init_data vgen_init = { @@ -348,8 +348,6 @@ static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = { static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = { .reset_gpio = LCD_RESET, .data_enable_gpio = LCD_ENABLE, - .core_supply = "lcd_2v8", - .io_supply = "vdd_lcdio", }; static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { @@ -359,7 +357,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { .bus_num = 1, .chip_select = 0, /* SS0 */ .platform_data = &mc13783_pdata, - .irq = gpio_to_irq(PMIC_INT), + .irq = IMX_GPIO_TO_IRQ(PMIC_INT), .mode = SPI_CS_HIGH, }, { .modalias = "l4f00242t03", diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 589066f..0de4d18 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -285,8 +285,6 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = { static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = { .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1), .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS), - .core_supply = "lcd_2v8", - .io_supply = "vdd_lcdio", }; /* @@ -411,7 +409,7 @@ static struct regulator_init_data vmmc2_init = { }; static struct regulator_consumer_supply vmmc1_consumers[] = { - REGULATOR_SUPPLY("lcd_2v8", NULL), + REGULATOR_SUPPLY("vcore", "spi0.0"), REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), }; @@ -428,7 +426,7 @@ static struct regulator_init_data vmmc1_init = { }; static struct regulator_consumer_supply vgen_consumers[] = { - REGULATOR_SUPPLY("vdd_lcdio", NULL), + REGULATOR_SUPPLY("vdd", "spi0.0"), }; static struct regulator_init_data vgen_init = { @@ -542,7 +540,7 @@ static const struct mxc_nand_platform_data mx31_3ds_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, -#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT +#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT .flash_bbt = 1, #endif }; diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 091bcf8..a497a29 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -176,7 +176,9 @@ static struct platform_device *platform_devices[] __initdata = { * setup other stuffs to access the sram. */ static void __init pcm038_init_sram(void) { - mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); + __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1))); + __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1))); + __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1))); } static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = { diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c index 9e11359..c33ab00 100644 --- a/arch/arm/mach-imx/mach-qong.c +++ b/arch/arm/mach-imx/mach-qong.c @@ -190,7 +190,10 @@ static struct platform_device qong_nand_device = { static void __init qong_init_nand_mtd(void) { /* init CS */ - mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800); + __raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); + __raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); + __raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); + mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); /* enable pin */ diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 7d8e012..5250283 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = { }, { I2C_BOARD_INFO("mc13892", 0x08), .platform_data = &vpr200_pmic, - .irq = gpio_to_irq(GPIO_PMIC_INT), + .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT), } }; diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c new file mode 100644 index 0000000..9f0e82e --- /dev/null +++ b/arch/arm/mach-imx/mm-imx3.c @@ -0,0 +1,256 @@ +/* + * Copyright (C) 1999,2000 Arm Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * - add MX31 specific definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/err.h> + +#include <asm/pgtable.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/mach/map.h> + +#include <mach/common.h> +#include <mach/devices-common.h> +#include <mach/hardware.h> +#include <mach/iomux-v3.h> +#include <mach/irqs.h> + +static void imx3_idle(void) +{ + unsigned long reg = 0; + __asm__ __volatile__( + /* disable I and D cache */ + "mrc p15, 0, %0, c1, c0, 0\n" + "bic %0, %0, #0x00001000\n" + "bic %0, %0, #0x00000004\n" + "mcr p15, 0, %0, c1, c0, 0\n" + /* invalidate I cache */ + "mov %0, #0\n" + "mcr p15, 0, %0, c7, c5, 0\n" + /* clear and invalidate D cache */ + "mov %0, #0\n" + "mcr p15, 0, %0, c7, c14, 0\n" + /* WFI */ + "mov %0, #0\n" + "mcr p15, 0, %0, c7, c0, 4\n" + "nop\n" "nop\n" "nop\n" "nop\n" + "nop\n" "nop\n" "nop\n" + /* enable I and D cache */ + "mrc p15, 0, %0, c1, c0, 0\n" + "orr %0, %0, #0x00001000\n" + "orr %0, %0, #0x00000004\n" + "mcr p15, 0, %0, c1, c0, 0\n" + : "=r" (reg)); +} + +static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, + unsigned int mtype) +{ + if (mtype == MT_DEVICE) { + /* + * Access all peripherals below 0x80000000 as nonshared device + * on mx3, but leave l2cc alone. Otherwise cache corruptions + * can occur. + */ + if (phys_addr < 0x80000000 && + !addr_in_module(phys_addr, MX3x_L2CC)) + mtype = MT_DEVICE_NONSHARED; + } + + return __arm_ioremap(phys_addr, size, mtype); +} + +void imx3_init_l2x0(void) +{ + void __iomem *l2x0_base; + void __iomem *clkctl_base; + +/* + * First of all, we must repair broken chip settings. There are some + * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These + * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. + * Workaraound is to setup the correct register setting prior enabling the + * L2 cache. This should not hurt already working CPUs, as they are using the + * same value. + */ +#define L2_MEM_VAL 0x10 + + clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); + if (clkctl_base != NULL) { + writel(0x00000515, clkctl_base + L2_MEM_VAL); + iounmap(clkctl_base); + } else { + pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); + } + + l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); + if (IS_ERR(l2x0_base)) { + printk(KERN_ERR "remapping L2 cache area failed with %ld\n", + PTR_ERR(l2x0_base)); + return; + } + + l2x0_init(l2x0_base, 0x00030024, 0x00000000); +} + +static struct map_desc mx31_io_desc[] __initdata = { + imx_map_entry(MX31, X_MEMC, MT_DEVICE), + imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mx31_map_io(void) +{ + iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); +} + +static struct map_desc mx35_io_desc[] __initdata = { + imx_map_entry(MX35, X_MEMC, MT_DEVICE), + imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), +}; + +void __init mx35_map_io(void) +{ + iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); +} + +void __init imx31_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX31); + mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); + imx_idle = imx3_idle; + imx_ioremap = imx3_ioremap; +} + +void __init imx35_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX35); + mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); + imx_idle = imx3_idle; + imx_ioremap = imx3_ioremap; +} + +void __init mx31_init_irq(void) +{ + mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); +} + +void __init mx35_init_irq(void) +{ + mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); +} + +static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { + .per_2_per_addr = 1677, +}; + +static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { + .ap_2_ap_addr = 423, + .ap_2_bp_addr = 829, + .bp_2_ap_addr = 1029, +}; + +static struct sdma_platform_data imx31_sdma_pdata __initdata = { + .fw_name = "sdma-imx31-to2.bin", + .script_addrs = &imx31_to2_sdma_script, +}; + +void __init imx31_soc_init(void) +{ + int to_version = mx31_revision() >> 4; + + imx3_init_l2x0(); + + mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); + mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); + mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); + + if (to_version == 1) { + strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", + strlen(imx31_sdma_pdata.fw_name)); + imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; + } + + imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); +} + +static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .uartsh_2_mcu_addr = 1183, + .per_2_shp_addr = 1033, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1333, + .mcu_2_ata_addr = 1252, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1111, + .shp_2_mcu_addr = 892, +}; + +static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1597, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1270, + .per_2_shp_addr = 1120, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1429, + .mcu_2_ata_addr = 1339, + .app_2_per_addr = 1531, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1198, + .shp_2_mcu_addr = 979, +}; + +static struct sdma_platform_data imx35_sdma_pdata __initdata = { + .fw_name = "sdma-imx35-to2.bin", + .script_addrs = &imx35_to2_sdma_script, +}; + +void __init imx35_soc_init(void) +{ + int to_version = mx35_revision() >> 4; + + imx3_init_l2x0(); + + /* i.mx35 has the i.mx31 type gpio */ + mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); + mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); + mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); + + if (to_version == 1) { + strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", + strlen(imx35_sdma_pdata.fw_name)); + imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; + } + + imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); +} diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c deleted file mode 100644 index b7c55e7..0000000 --- a/arch/arm/mach-imx/mm-imx31.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 1999,2000 Arm Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - add MX31 specific definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/err.h> - -#include <asm/pgtable.h> -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/devices-common.h> -#include <mach/hardware.h> -#include <mach/iomux-v3.h> -#include <mach/irqs.h> - -static struct map_desc mx31_io_desc[] __initdata = { - imx_map_entry(MX31, X_MEMC, MT_DEVICE), - imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx31_map_io(void) -{ - iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); -} - -void __init imx31_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX31); - mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); -} - -void __init mx31_init_irq(void) -{ - mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { - .per_2_per_addr = 1677, -}; - -static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { - .ap_2_ap_addr = 423, - .ap_2_bp_addr = 829, - .bp_2_ap_addr = 1029, -}; - -static struct sdma_platform_data imx31_sdma_pdata __initdata = { - .fw_name = "sdma-imx31-to2.bin", - .script_addrs = &imx31_to2_sdma_script, -}; - -void __init imx31_soc_init(void) -{ - int to_version = mx31_revision() >> 4; - - mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); - mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); - mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); - - if (to_version == 1) { - strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", - strlen(imx31_sdma_pdata.fw_name)); - imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; - } - - imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); -} diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c deleted file mode 100644 index f49bac7..0000000 --- a/arch/arm/mach-imx/mm-imx35.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (C) 1999,2000 Arm Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - add MX31 specific definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/err.h> - -#include <asm/pgtable.h> -#include <asm/mach/map.h> -#include <asm/hardware/cache-l2x0.h> - -#include <mach/common.h> -#include <mach/devices-common.h> -#include <mach/hardware.h> -#include <mach/iomux-v3.h> -#include <mach/irqs.h> - -static struct map_desc mx35_io_desc[] __initdata = { - imx_map_entry(MX35, X_MEMC, MT_DEVICE), - imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), -}; - -void __init mx35_map_io(void) -{ - iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); -} - -void __init imx35_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX35); - mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); -} - -void __init mx35_init_irq(void) -{ - mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .uart_2_mcu_addr = 817, - .mcu_2_app_addr = 747, - .uartsh_2_mcu_addr = 1183, - .per_2_shp_addr = 1033, - .mcu_2_shp_addr = 961, - .ata_2_mcu_addr = 1333, - .mcu_2_ata_addr = 1252, - .app_2_mcu_addr = 683, - .shp_2_per_addr = 1111, - .shp_2_mcu_addr = 892, -}; - -static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { - .ap_2_ap_addr = 729, - .uart_2_mcu_addr = 904, - .per_2_app_addr = 1597, - .mcu_2_app_addr = 834, - .uartsh_2_mcu_addr = 1270, - .per_2_shp_addr = 1120, - .mcu_2_shp_addr = 1048, - .ata_2_mcu_addr = 1429, - .mcu_2_ata_addr = 1339, - .app_2_per_addr = 1531, - .app_2_mcu_addr = 770, - .shp_2_per_addr = 1198, - .shp_2_mcu_addr = 979, -}; - -static struct sdma_platform_data imx35_sdma_pdata __initdata = { - .fw_name = "sdma-imx35-to2.bin", - .script_addrs = &imx35_to2_sdma_script, -}; - -void __init imx35_soc_init(void) -{ - int to_version = mx35_revision() >> 4; - - /* i.mx35 has the i.mx31 type gpio */ - mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); - mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); - mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); - - if (to_version == 1) { - strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", - strlen(imx35_sdma_pdata.fw_name)); - imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; - } - - imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); -} diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c index acf1769..e455d2f 100644 --- a/arch/arm/mach-imx/pm-imx27.c +++ b/arch/arm/mach-imx/pm-imx27.c @@ -11,7 +11,7 @@ #include <linux/suspend.h> #include <linux/io.h> #include <mach/system.h> -#include <mach/mx27.h> +#include <mach/hardware.h> static int mx27_suspend_enter(suspend_state_t state) { diff --git a/arch/arm/mach-integrator/Makefile.boot b/arch/arm/mach-integrator/Makefile.boot index c7e75ac..ff0a4b5 100644 --- a/arch/arm/mach-integrator/Makefile.boot +++ b/arch/arm/mach-integrator/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 77315b9..4b38e13 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -126,6 +126,10 @@ static struct clk_lookup lookups[] = { { /* Bus clock */ .con_id = "apb_pclk", .clk = &dummy_apb_pclk, + }, { + /* Integrator/AP timer frequency */ + .dev_id = "ap_timer", + .clk = &clk24mhz, }, { /* UART0 */ .dev_id = "mb:16", .clk = &uartclk, @@ -205,7 +209,7 @@ static struct amba_pl010_data integrator_uart_data = { #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL) -static DEFINE_SPINLOCK(cm_lock); +static DEFINE_RAW_SPINLOCK(cm_lock); /** * cm_control - update the CM_CTRL register. @@ -217,10 +221,10 @@ void cm_control(u32 mask, u32 set) unsigned long flags; u32 val; - spin_lock_irqsave(&cm_lock, flags); + raw_spin_lock_irqsave(&cm_lock, flags); val = readl(CM_CTRL) & ~mask; writel(val | set, CM_CTRL); - spin_unlock_irqrestore(&cm_lock, flags); + raw_spin_unlock_irqrestore(&cm_lock, flags); } EXPORT_SYMBOL(cm_control); diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h index f21bb54..37beed3 100644 --- a/arch/arm/mach-integrator/include/mach/io.h +++ b/arch/arm/mach-integrator/include/mach/io.h @@ -20,8 +20,6 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#define IO_SPACE_LIMIT 0xffff - /* * WARNING: this has to mirror definitions in platform.h */ diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index 5e6ea5c..ec467ba 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -13,9 +13,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ /************************************************************************** * * Copyright © ARM Limited 1998. All rights reserved. * ***********************************************************************/ @@ -399,15 +396,6 @@ #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) -#define TICKS_PER_uSEC 24 - -/* - * These are useconds NOT ticks. - * - */ -#define mSEC_1 1000 -#define mSEC_10 (mSEC_1 * 10) - #define INTEGRATOR_CSR_BASE 0x10000000 #define INTEGRATOR_CSR_SIZE 0x10000000 diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index a20fb3f..a1769f3 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -32,6 +32,7 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/mtd/physmap.h> +#include <linux/clk.h> #include <video/vga.h> #include <mach/hardware.h> @@ -322,27 +323,16 @@ static void __init ap_init(void) #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) -/* - * How long is the timer interval? - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) -#if TIMER_INTERVAL >= 0x100000 -#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) -#elif TIMER_INTERVAL >= 0x10000 -#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) -#else -#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) -#endif - static unsigned long timer_reload; -static void integrator_clocksource_init(u32 khz) +static void integrator_clocksource_init(unsigned long inrate) { void __iomem *base = (void __iomem *)TIMER2_VA_BASE; u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; + unsigned long rate = inrate; - if (khz >= 1500) { - khz /= 16; + if (rate >= 1500000) { + rate /= 16; ctrl |= TIMER_CTRL_DIV16; } @@ -350,7 +340,7 @@ static void integrator_clocksource_init(u32 khz) writel(ctrl, base + TIMER_CTRL); clocksource_mmio_init(base + TIMER_VALUE, "timer2", - khz * 1000, 200, 16, clocksource_mmio_readl_down); + rate, 200, 16, clocksource_mmio_readl_down); } static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; @@ -374,15 +364,29 @@ static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_devic { u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; - BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT); + /* Disable timer */ + writel(ctrl, clkevt_base + TIMER_CTRL); - if (mode == CLOCK_EVT_MODE_PERIODIC) { - writel(ctrl, clkevt_base + TIMER_CTRL); + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* Enable the timer and start the periodic tick */ writel(timer_reload, clkevt_base + TIMER_LOAD); ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; + writel(ctrl, clkevt_base + TIMER_CTRL); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* Leave the timer disabled, .set_next_event will enable it */ + ctrl &= ~TIMER_CTRL_PERIODIC; + writel(ctrl, clkevt_base + TIMER_CTRL); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + default: + /* Just leave in disabled state */ + break; } - writel(ctrl, clkevt_base + TIMER_CTRL); } static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) @@ -398,12 +402,10 @@ static int clkevt_set_next_event(unsigned long next, struct clock_event_device * static struct clock_event_device integrator_clockevent = { .name = "timer1", - .shift = 34, - .features = CLOCK_EVT_FEAT_PERIODIC, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = clkevt_set_mode, .set_next_event = clkevt_set_next_event, .rating = 300, - .cpumask = cpu_all_mask, }; static struct irqaction integrator_timer_irq = { @@ -413,29 +415,27 @@ static struct irqaction integrator_timer_irq = { .dev_id = &integrator_clockevent, }; -static void integrator_clockevent_init(u32 khz) +static void integrator_clockevent_init(unsigned long inrate) { - struct clock_event_device *evt = &integrator_clockevent; + unsigned long rate = inrate; unsigned int ctrl = 0; - if (khz * 1000 > 0x100000 * HZ) { - khz /= 256; + /* Calculate and program a divisor */ + if (rate > 0x100000 * HZ) { + rate /= 256; ctrl |= TIMER_CTRL_DIV256; - } else if (khz * 1000 > 0x10000 * HZ) { - khz /= 16; + } else if (rate > 0x10000 * HZ) { + rate /= 16; ctrl |= TIMER_CTRL_DIV16; } - - timer_reload = khz * 1000 / HZ; + timer_reload = rate / HZ; writel(ctrl, clkevt_base + TIMER_CTRL); - evt->irq = IRQ_TIMERINT1; - evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift); - evt->max_delta_ns = clockevent_delta2ns(0xffff, evt); - evt->min_delta_ns = clockevent_delta2ns(0xf, evt); - setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); - clockevents_register_device(evt); + clockevents_config_and_register(&integrator_clockevent, + rate, + 1, + 0xffffU); } /* @@ -443,14 +443,20 @@ static void integrator_clockevent_init(u32 khz) */ static void __init ap_init_timer(void) { - u32 khz = TICKS_PER_uSEC * 1000; + struct clk *clk; + unsigned long rate; + + clk = clk_get_sys("ap_timer", NULL); + BUG_ON(IS_ERR(clk)); + clk_enable(clk); + rate = clk_get_rate(clk); writel(0, TIMER0_VA_BASE + TIMER_CTRL); writel(0, TIMER1_VA_BASE + TIMER_CTRL); writel(0, TIMER2_VA_BASE + TIMER_CTRL); - integrator_clocksource_init(khz); - integrator_clockevent_init(khz); + integrator_clocksource_init(rate); + integrator_clockevent_init(rate); } static struct sys_timer ap_timer = { diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 11b86e5..b4d8f8b 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -163,7 +163,7 @@ * 7:2 register number * */ -static DEFINE_SPINLOCK(v3_lock); +static DEFINE_RAW_SPINLOCK(v3_lock); #define PCI_BUS_NONMEM_START 0x00000000 #define PCI_BUS_NONMEM_SIZE SZ_256M @@ -284,7 +284,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, unsigned long flags; u32 v; - spin_lock_irqsave(&v3_lock, flags); + raw_spin_lock_irqsave(&v3_lock, flags); addr = v3_open_config_window(bus, devfn, where); switch (size) { @@ -302,7 +302,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, } v3_close_config_window(); - spin_unlock_irqrestore(&v3_lock, flags); + raw_spin_unlock_irqrestore(&v3_lock, flags); *val = v; return PCIBIOS_SUCCESSFUL; @@ -314,7 +314,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, unsigned long addr; unsigned long flags; - spin_lock_irqsave(&v3_lock, flags); + raw_spin_lock_irqsave(&v3_lock, flags); addr = v3_open_config_window(bus, devfn, where); switch (size) { @@ -335,7 +335,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, } v3_close_config_window(); - spin_unlock_irqrestore(&v3_lock, flags); + raw_spin_unlock_irqrestore(&v3_lock, flags); return PCIBIOS_SUCCESSFUL; } @@ -513,7 +513,7 @@ void __init pci_v3_preinit(void) hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); - spin_lock_irqsave(&v3_lock, flags); + raw_spin_lock_irqsave(&v3_lock, flags); /* * Unlock V3 registers, but only if they were previously locked. @@ -586,7 +586,7 @@ void __init pci_v3_preinit(void) printk(KERN_ERR "PCI: unable to grab PCI error " "interrupt: %d\n", ret); - spin_unlock_irqrestore(&v3_lock, flags); + raw_spin_unlock_irqrestore(&v3_lock, flags); } void __init pci_v3_postinit(void) diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot index 0b0e19f..3a8c38c 100644 --- a/arch/arm/mach-iop13xx/Makefile.boot +++ b/arch/arm/mach-iop13xx/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-iop32x/Makefile.boot b/arch/arm/mach-iop32x/Makefile.boot index 47000dc..0a833b1 100644 --- a/arch/arm/mach-iop32x/Makefile.boot +++ b/arch/arm/mach-iop32x/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0xa0008000 + zreladdr-y += 0xa0008000 params_phys-y := 0xa0000100 initrd_phys-y := 0xa0800000 diff --git a/arch/arm/mach-iop33x/Makefile.boot b/arch/arm/mach-iop33x/Makefile.boot index 67039c3..760a0ef 100644 --- a/arch/arm/mach-iop33x/Makefile.boot +++ b/arch/arm/mach-iop33x/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-ixp2000/Makefile.boot b/arch/arm/mach-ixp2000/Makefile.boot index d84c580..9c7af91 100644 --- a/arch/arm/mach-ixp2000/Makefile.boot +++ b/arch/arm/mach-ixp2000/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot index d5561ad..44fb4a71 100644 --- a/arch/arm/mach-ixp23xx/Makefile.boot +++ b/arch/arm/mach-ixp23xx/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 diff --git a/arch/arm/mach-ixp4xx/Makefile.boot b/arch/arm/mach-ixp4xx/Makefile.boot index d84c580..9c7af91 100644 --- a/arch/arm/mach-ixp4xx/Makefile.boot +++ b/arch/arm/mach-ixp4xx/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index 2131832..f72a3a8 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -54,7 +54,7 @@ unsigned long ixp4xx_pci_reg_base = 0; * these transactions are atomic or we will end up * with corrupt data on the bus or in a driver. */ -static DEFINE_SPINLOCK(ixp4xx_pci_lock); +static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock); /* * Read from PCI config space @@ -62,10 +62,10 @@ static DEFINE_SPINLOCK(ixp4xx_pci_lock); static void crp_read(u32 ad_cbe, u32 *data) { unsigned long flags; - spin_lock_irqsave(&ixp4xx_pci_lock, flags); + raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_CRP_AD_CBE = ad_cbe; *data = *PCI_CRP_RDATA; - spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); } /* @@ -74,10 +74,10 @@ static void crp_read(u32 ad_cbe, u32 *data) static void crp_write(u32 ad_cbe, u32 data) { unsigned long flags; - spin_lock_irqsave(&ixp4xx_pci_lock, flags); + raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe; *PCI_CRP_WDATA = data; - spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); } static inline int check_master_abort(void) @@ -101,7 +101,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data) int retval = 0; int i; - spin_lock_irqsave(&ixp4xx_pci_lock, flags); + raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_NP_AD = addr; @@ -118,7 +118,7 @@ int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data) if(check_master_abort()) retval = 1; - spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); return retval; } @@ -127,7 +127,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data) unsigned long flags; int retval = 0; - spin_lock_irqsave(&ixp4xx_pci_lock, flags); + raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_NP_AD = addr; @@ -140,7 +140,7 @@ int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data) if(check_master_abort()) retval = 1; - spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); return retval; } @@ -149,7 +149,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data) unsigned long flags; int retval = 0; - spin_lock_irqsave(&ixp4xx_pci_lock, flags); + raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); *PCI_NP_AD = addr; @@ -162,7 +162,7 @@ int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data) if(check_master_abort()) retval = 1; - spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); + raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); return retval; } @@ -397,7 +397,8 @@ void __init ixp4xx_pci_preinit(void) local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); - local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M); + local_write_config(PCI_BASE_ADDRESS_3, 4, + PHYS_OFFSET + SZ_32M + SZ_16M); /* * Enable CSR window at 64 MiB to allow PCI masters diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 57b5410..ffb9d6a 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -17,8 +17,6 @@ #include <mach/hardware.h> -#define IO_SPACE_LIMIT 0x0000ffff - extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot index 67039c3..760a0ef 100644 --- a/arch/arm/mach-kirkwood/Makefile.boot +++ b/arch/arm/mach-kirkwood/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-ks8695/Makefile.boot b/arch/arm/mach-ks8695/Makefile.boot index 48eb2cb..c9b0beb 100644 --- a/arch/arm/mach-ks8695/Makefile.boot +++ b/arch/arm/mach-ks8695/Makefile.boot @@ -3,6 +3,6 @@ # PARAMS_PHYS must be within 4MB of ZRELADDR # INITRD_PHYS must be in RAM - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot index b796b41..2cfe0ee 100644 --- a/arch/arm/mach-lpc32xx/Makefile.boot +++ b/arch/arm/mach-lpc32xx/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x80008000 + zreladdr-y += 0x80008000 params_phys-y := 0x80000100 initrd_phys-y := 0x82000000 diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h index e69de29..40a8c17 100644 --- a/arch/arm/mach-lpc32xx/include/mach/gpio.h +++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 56ef5f6..323d4c9 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -77,7 +77,7 @@ config MACH_TETON_BGA Say 'Y' here if you want to support the Marvell PXA168-based Teton BGA Development Board. -config MACH_SHEEVAD +config MACH_GPLUGD bool "Marvell's PXA168 GuruPlug Display (gplugD) Board" select CPU_PXA168 help diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index b0ac942..8f948f9 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -19,4 +19,4 @@ obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o obj-$(CONFIG_MACH_FLINT) += flint.o obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o -obj-$(CONFIG_MACH_SHEEVAD) += gplugd.o +obj-$(CONFIG_MACH_GPLUGD) += gplugd.o diff --git a/arch/arm/mach-mmp/Makefile.boot b/arch/arm/mach-mmp/Makefile.boot index 574a4aa..5edf03e 100644 --- a/arch/arm/mach-mmp/Makefile.boot +++ b/arch/arm/mach-mmp/Makefile.boot @@ -1 +1 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index 833c3a2..06b5ad7 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -160,7 +160,7 @@ static struct mtd_partition aspenite_nand_partitions[] = { }, { .name = "filesystem", .offset = MTDPART_OFS_APPEND, - .size = SZ_48M, + .size = SZ_32M + SZ_16M, .mask_flags = 0, } }; diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h index 3143e99..149b30c 100644 --- a/arch/arm/mach-mmp/clock.h +++ b/arch/arm/mach-mmp/clock.h @@ -30,7 +30,7 @@ extern struct clkops apmu_clk_ops; #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ struct clk clk_##_name = { \ - .clk_rst = (void __iomem *)APBC_##_reg, \ + .clk_rst = APBC_##_reg, \ .fnclksel = _fnclksel, \ .rate = _rate, \ .ops = &apbc_clk_ops, \ @@ -38,7 +38,7 @@ struct clk clk_##_name = { \ #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ struct clk clk_##_name = { \ - .clk_rst = (void __iomem *)APBC_##_reg, \ + .clk_rst = APBC_##_reg, \ .fnclksel = _fnclksel, \ .rate = _rate, \ .ops = _ops, \ @@ -46,7 +46,7 @@ struct clk clk_##_name = { \ #define APMU_CLK(_name, _reg, _eval, _rate) \ struct clk clk_##_name = { \ - .clk_rst = (void __iomem *)APMU_##_reg, \ + .clk_rst = APMU_##_reg, \ .enable_val = _eval, \ .rate = _rate, \ .ops = &apmu_clk_ops, \ @@ -54,7 +54,7 @@ struct clk clk_##_name = { \ #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ struct clk clk_##_name = { \ - .clk_rst = (void __iomem *)APMU_##_reg, \ + .clk_rst = APMU_##_reg, \ .enable_val = _eval, \ .rate = _rate, \ .ops = _ops, \ diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c index 0ec0ca8..5720674 100644 --- a/arch/arm/mach-mmp/common.c +++ b/arch/arm/mach-mmp/common.c @@ -27,12 +27,12 @@ EXPORT_SYMBOL(mmp_chip_id); static struct map_desc standard_io_desc[] __initdata = { { .pfn = __phys_to_pfn(APB_PHYS_BASE), - .virtual = APB_VIRT_BASE, + .virtual = (unsigned long)APB_VIRT_BASE, .length = APB_PHYS_SIZE, .type = MT_DEVICE, }, { .pfn = __phys_to_pfn(AXI_PHYS_BASE), - .virtual = AXI_VIRT_BASE, + .virtual = (unsigned long)AXI_VIRT_BASE, .length = AXI_PHYS_SIZE, .type = MT_DEVICE, }, diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c index 32776f3..6915656 100644 --- a/arch/arm/mach-mmp/gplugd.c +++ b/arch/arm/mach-mmp/gplugd.c @@ -188,7 +188,7 @@ static void __init gplugd_init(void) pxa168_add_eth(&gplugd_eth_platform_data); } -MACHINE_START(SHEEVAD, "PXA168-based GuruPlug Display (gplugD) Platform") +MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform") .map_io = mmp_map_io, .nr_irqs = IRQ_BOARD_START, .init_irq = pxa168_init_irq, diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h index 3254089..3e404ac 100644 --- a/arch/arm/mach-mmp/include/mach/addr-map.h +++ b/arch/arm/mach-mmp/include/mach/addr-map.h @@ -11,6 +11,12 @@ #ifndef __ASM_MACH_ADDR_MAP_H #define __ASM_MACH_ADDR_MAP_H +#ifndef __ASSEMBLER__ +#define IOMEM(x) ((void __iomem *)(x)) +#else +#define IOMEM(x) (x) +#endif + /* APB - Application Subsystem Peripheral Bus * * NOTE: the DMA controller registers are actually on the AXI fabric #1 @@ -18,11 +24,11 @@ * peripherals on APB, let's count it into the ABP mapping area. */ #define APB_PHYS_BASE 0xd4000000 -#define APB_VIRT_BASE 0xfe000000 +#define APB_VIRT_BASE IOMEM(0xfe000000) #define APB_PHYS_SIZE 0x00200000 #define AXI_PHYS_BASE 0xd4200000 -#define AXI_VIRT_BASE 0xfe200000 +#define AXI_VIRT_BASE IOMEM(0xfe200000) #define AXI_PHYS_SIZE 0x00200000 /* Static Memory Controller - Chip Select 0 and 1 */ diff --git a/arch/arm/mach-mmp/include/mach/gpio-pxa.h b/arch/arm/mach-mmp/include/mach/gpio-pxa.h index c017a98..d14eeaf 100644 --- a/arch/arm/mach-mmp/include/mach/gpio-pxa.h +++ b/arch/arm/mach-mmp/include/mach/gpio-pxa.h @@ -7,7 +7,7 @@ #define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) -#define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) +#define GPIO_REG(x) (GPIO_REGS_VIRT + (x)) #define NR_BUILTIN_GPIO IRQ_GPIO_NUM diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 7f00584..7fb568d 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -35,6 +35,13 @@ extern struct pxa_device_desc pxa168_device_fb; extern struct pxa_device_desc pxa168_device_keypad; extern struct pxa_device_desc pxa168_device_eth; +struct pxa168_usb_pdata { + /* If NULL, default phy init routine for PXA168 would be called */ + int (*phy_init)(void __iomem *usb_phy_reg_base); +}; +/* pdata can be NULL */ +int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata); + static inline int pxa168_add_uart(int id) { struct pxa_device_desc *d = NULL; diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 65d8689e..7a7e8e4 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -86,7 +86,8 @@ static struct mfp_addr_map mmp2_addr_map[] __initdata = { void mmp2_clear_pmic_int(void) { - unsigned long mfpr_pmic, data; + void __iomem *mfpr_pmic; + unsigned long data; mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; data = __raw_readl(mfpr_pmic); diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 50c1763..76ca15c 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -24,6 +24,9 @@ #include <mach/dma.h> #include <mach/devices.h> #include <mach/mfp.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <mach/pxa168.h> #include "common.h" #include "clock.h" @@ -82,6 +85,7 @@ static APBC_CLK(keypad, PXA168_KPC, 0, 32000); static APMU_CLK(nand, NAND, 0x19b, 156000000); static APMU_CLK(lcd, LCD, 0x7f, 312000000); static APMU_CLK(eth, ETH, 0x09, 0); +static APMU_CLK(usb, USB, 0x12, 0); /* device and clock bindings */ static struct clk_lookup pxa168_clkregs[] = { @@ -103,6 +107,7 @@ static struct clk_lookup pxa168_clkregs[] = { INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), + INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"), }; static int __init pxa168_init(void) @@ -168,3 +173,44 @@ PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8); PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c); PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff); + +struct resource pxa168_usb_host_resources[] = { + /* USB Host conroller register base */ + [0] = { + .start = 0xd4209000, + .end = 0xd4209000 + 0x200, + .flags = IORESOURCE_MEM, + .name = "pxa168-usb-host", + }, + /* USB PHY register base */ + [1] = { + .start = 0xd4206000, + .end = 0xd4206000 + 0xff, + .flags = IORESOURCE_MEM, + .name = "pxa168-usb-phy", + }, + [2] = { + .start = IRQ_PXA168_USB2, + .end = IRQ_PXA168_USB2, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 pxa168_usb_host_dmamask = DMA_BIT_MASK(32); +struct platform_device pxa168_device_usb_host = { + .name = "pxa168-ehci", + .id = -1, + .dev = { + .dma_mask = &pxa168_usb_host_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + + .num_resources = ARRAY_SIZE(pxa168_usb_host_resources), + .resource = pxa168_usb_host_resources, +}; + +int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata) +{ + pxa168_device_usb_host.dev.platform_data = pdata; + return platform_device_register(&pxa168_device_usb_host); +} diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index 6bd37a2..176515a 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -93,7 +93,7 @@ static struct mtd_partition ttc_dkb_onenand_partitions[] = { }, { .name = "filesystem", .offset = MTDPART_OFS_APPEND, - .size = SZ_48M, + .size = SZ_32M + SZ_16M, .mask_flags = 0, } }; diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot index 24dfbf8..9b803a5 100644 --- a/arch/arm/mach-msm/Makefile.boot +++ b/arch/arm/mach-msm/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x10008000 + zreladdr-y += 0x10008000 params_phys-y := 0x10000100 initrd_phys-y := 0x10800000 diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 16c86f8..a60ab6d 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -78,8 +78,8 @@ static void __init halibut_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); } -static void __init halibut_fixup(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +static void __init halibut_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { mi->nr_banks=1; mi->bank[0].start = PHYS_OFFSET; diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index 8a1672e..5a4882f 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c @@ -53,8 +53,8 @@ static void __init mahimahi_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); } -static void __init mahimahi_fixup(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +static void __init mahimahi_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { mi->nr_banks = 2; mi->bank[0].start = PHYS_OFFSET; diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index afa9293..32b4657 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -76,8 +76,8 @@ static struct map_desc sapphire_io_desc[] __initdata = { } }; -static void __init sapphire_fixup(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +static void __init sapphire_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { int smi_sz = parse_tag_smi((const struct tag *)tags); diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 22d5694..6b9b227 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -48,8 +48,8 @@ static void __init trout_init_irq(void) msm_init_irq(); } -static void __init trout_fixup(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +static void __init trout_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { mi->nr_banks = 1; mi->bank[0].start = PHYS_OFFSET; diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index 22a5376..d9145df 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -18,7 +18,7 @@ #include <linux/list.h> #include <linux/err.h> #include <linux/spinlock.h> -#include <linux/pm_qos_params.h> +#include <linux/pm_qos.h> #include <linux/mutex.h> #include <linux/clk.h> #include <linux/string.h> diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index c4f5e26..993780f 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -176,12 +176,6 @@ static struct resource resources_sdc1[] = { .name = "cmd_irq", }, { - .start = INT_SDC1_1, - .end = INT_SDC1_1, - .flags = IORESOURCE_IRQ, - .name = "pio_irq", - }, - { .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, .name = "status_irq" }, @@ -204,12 +198,6 @@ static struct resource resources_sdc2[] = { .flags = IORESOURCE_IRQ, .name = "cmd_irq", }, - { - .start = INT_SDC2_1, - .end = INT_SDC2_1, - .flags = IORESOURCE_IRQ, - .name = "pio_irq", - }, { .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, .name = "status_irq" @@ -233,12 +221,6 @@ static struct resource resources_sdc3[] = { .flags = IORESOURCE_IRQ, .name = "cmd_irq", }, - { - .start = INT_SDC3_1, - .end = INT_SDC3_1, - .flags = IORESOURCE_IRQ, - .name = "pio_irq", - }, { .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, .name = "status_irq" @@ -262,12 +244,6 @@ static struct resource resources_sdc4[] = { .flags = IORESOURCE_IRQ, .name = "cmd_irq", }, - { - .start = INT_SDC4_1, - .end = INT_SDC4_1, - .flags = IORESOURCE_IRQ, - .name = "pio_irq", - }, { .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, .name = "status_irq" diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index 12d8deb..131633b 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -140,12 +140,6 @@ static struct resource resources_sdc1[] = { .name = "cmd_irq", }, { - .start = INT_SDC1_1, - .end = INT_SDC1_1, - .flags = IORESOURCE_IRQ, - .name = "pio_irq", - }, - { .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, .name = "status_irq" }, @@ -168,12 +162,6 @@ static struct resource resources_sdc2[] = { .flags = IORESOURCE_IRQ, .name = "cmd_irq", }, - { - .start = INT_SDC2_1, - .end = INT_SDC2_1, - .flags = IORESOURCE_IRQ, - .name = "pio_irq", - }, { .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, .name = "status_irq" @@ -197,12 +185,6 @@ static struct resource resources_sdc3[] = { .flags = IORESOURCE_IRQ, .name = "cmd_irq", }, - { - .start = INT_SDC3_1, - .end = INT_SDC3_1, - .flags = IORESOURCE_IRQ, - .name = "pio_irq", - }, { .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, .name = "status_irq" @@ -226,12 +208,6 @@ static struct resource resources_sdc4[] = { .flags = IORESOURCE_IRQ, .name = "cmd_irq", }, - { - .start = INT_SDC4_1, - .end = INT_SDC4_1, - .flags = IORESOURCE_IRQ, - .name = "pio_irq", - }, { .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, .name = "status_irq" diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h index 5631b51..ffcd9e3 100644 --- a/arch/arm/mach-msm/include/mach/mmc.h +++ b/arch/arm/mach-msm/include/mach/mmc.h @@ -8,13 +8,6 @@ #include <linux/mmc/card.h> #include <linux/mmc/sdio_func.h> -struct embedded_sdio_data { - struct sdio_cis cis; - struct sdio_cccr cccr; - struct sdio_embedded_func *funcs; - int num_funcs; -}; - struct msm_mmc_gpio { unsigned no; const char *name; @@ -29,9 +22,9 @@ struct msm_mmc_platform_data { unsigned int ocr_mask; /* available voltages */ u32 (*translate_vdd)(struct device *, unsigned int); unsigned int (*status)(struct device *); - struct embedded_sdio_data *embedded_sdio; int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); struct msm_mmc_gpio_data *gpio_data; + void (*init_card)(struct mmc_card *card); }; #endif diff --git a/arch/arm/mach-mv78xx0/Makefile.boot b/arch/arm/mach-mv78xx0/Makefile.boot index 67039c3..760a0ef 100644 --- a/arch/arm/mach-mv78xx0/Makefile.boot +++ b/arch/arm/mach-mv78xx0/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index b4e7c58..5e42c73 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -52,7 +52,6 @@ config MACH_MX50_RDP select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX - select IMX_HAVE_PLATFORM_FEC help Include support for MX50 reference design platform (RDP) board. This includes specific configurations for the board and its peripherals. @@ -65,9 +64,11 @@ comment "i.MX51 machines:" config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" select SOC_IMX51 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX help @@ -91,8 +92,10 @@ config MACH_MX51_3DS config MACH_EUKREA_CPUIMX51 bool "Support Eukrea CPUIMX51 module" select SOC_IMX51 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX help @@ -119,10 +122,12 @@ endchoice config MACH_EUKREA_CPUIMX51SD bool "Support Eukrea CPUIMX51SD module" select SOC_IMX51 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_SPI_IMX select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for Eukrea CPUIMX51SD platform. This includes specific configurations for the module and its peripherals. @@ -147,6 +152,8 @@ config MX51_EFIKA_COMMON bool select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_PATA_IMX select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 383e7cd..9565304 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -3,8 +3,7 @@ # # Object file lists. -obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o -obj-$(CONFIG_SOC_IMX50) += mm-mx50.o +obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o obj-$(CONFIG_PM) += pm-imx5.o obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot index e928be1..ca207ca 100644 --- a/arch/arm/mach-mx5/Makefile.boot +++ b/arch/arm/mach-mx5/Makefile.boot @@ -1,9 +1,9 @@ - zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000 + zreladdr-$(CONFIG_ARCH_MX50) += 0x70008000 params_phys-$(CONFIG_ARCH_MX50) := 0x70000100 initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000 - zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000 + zreladdr-$(CONFIG_ARCH_MX51) += 0x90008000 params_phys-$(CONFIG_ARCH_MX51) := 0x90000100 initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000 - zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000 + zreladdr-$(CONFIG_ARCH_MX53) += 0x70008000 params_phys-$(CONFIG_ARCH_MX53) := 0x70000100 initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000 diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index e01af94..190a6e7 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -22,21 +22,18 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/interrupt.h> -#include <linux/irq.h> #include <mach/eukrea-baseboards.h> #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <asm/irq.h> #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include "devices-imx51.h" -#include "devices.h" #define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) #define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) @@ -57,7 +54,7 @@ static struct plat_serial8250_port serial_platform_data[] = { { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), - .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO), + .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO), .irqflags = IRQF_TRIGGER_HIGH, .uartclk = CPUIMX51_QUART_XTAL, .regshift = CPUIMX51_QUART_REGSHIFT, @@ -65,7 +62,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), - .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO), + .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO), .irqflags = IRQF_TRIGGER_HIGH, .uartclk = CPUIMX51_QUART_XTAL, .regshift = CPUIMX51_QUART_REGSHIFT, @@ -73,7 +70,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), - .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO), + .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO), .irqflags = IRQF_TRIGGER_HIGH, .uartclk = CPUIMX51_QUART_XTAL, .regshift = CPUIMX51_QUART_REGSHIFT, @@ -81,7 +78,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), - .irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO), + .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO), .irqflags = IRQF_TRIGGER_HIGH, .uartclk = CPUIMX51_QUART_XTAL, .regshift = CPUIMX51_QUART_REGSHIFT, @@ -167,7 +164,7 @@ static int initialize_otg_port(struct platform_device *pdev) void __iomem *usb_base; void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -190,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) void __iomem *usb_base; void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -206,17 +203,17 @@ static int initialize_usbh1_port(struct platform_device *pdev) MXC_EHCI_ITC_NO_THRESHOLD); } -static struct mxc_usbh_platform_data dr_utmi_config = { +static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { .init = initialize_otg_port, .portsc = MXC_EHCI_UTMI_16BIT, }; -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; -static struct mxc_usbh_platform_data usbh1_config = { +static const struct mxc_usbh_platform_data usbh1_config __initconst = { .init = initialize_usbh1_port, .portsc = MXC_EHCI_MODE_ULPI, }; @@ -270,12 +267,12 @@ static void __init eukrea_cpuimx51_init(void) ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); if (otg_mode_host) - mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + imx51_add_mxc_ehci_otg(&dr_utmi_config); else { initialize_otg_port(NULL); - mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); + imx51_add_fsl_usb2_udc(&usb_pdata); } - mxc_register_device(&mxc_usbh1_device, &usbh1_config); + imx51_add_mxc_ehci_hs(1, &usbh1_config); #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD eukrea_mbimx51_baseboard_init(); diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index b41fc27..72410d2 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -22,7 +22,6 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/interrupt.h> -#include <linux/irq.h> #include <linux/i2c-gpio.h> #include <linux/spi/spi.h> #include <linux/can/platform/mcp251x.h> @@ -32,14 +31,12 @@ #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <asm/irq.h> #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include "devices-imx51.h" -#include "devices.h" #include "cpu_op-mx51.h" #define USBH1_RST IMX_GPIO_NR(2, 28) @@ -108,7 +105,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = { /* Touchscreen */ /* IRQ */ - _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | + NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), }; @@ -129,7 +126,7 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = { I2C_BOARD_INFO("tsc2007", 0x49), .type = "tsc2007", .platform_data = &tsc2007_info, - .irq = gpio_to_irq(TSC2007_IRQGPIO), + .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO), }, }; @@ -149,7 +146,7 @@ static int initialize_otg_port(struct platform_device *pdev) void __iomem *usb_base; void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -172,7 +169,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) void __iomem *usb_base; void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -189,17 +186,17 @@ static int initialize_usbh1_port(struct platform_device *pdev) MXC_EHCI_ITC_NO_THRESHOLD); } -static struct mxc_usbh_platform_data dr_utmi_config = { +static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { .init = initialize_otg_port, .portsc = MXC_EHCI_UTMI_16BIT, }; -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; -static struct mxc_usbh_platform_data usbh1_config = { +static const struct mxc_usbh_platform_data usbh1_config __initconst = { .init = initialize_usbh1_port, .portsc = MXC_EHCI_MODE_ULPI, }; @@ -245,7 +242,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = { .mode = SPI_MODE_0, .chip_select = 0, .platform_data = &mcp251x_info, - .irq = gpio_to_irq(CAN_IRQGPIO) + .irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO) }, }; @@ -303,17 +300,17 @@ static void __init eukrea_cpuimx51sd_init(void) platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); if (otg_mode_host) - mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + imx51_add_mxc_ehci_otg(&dr_utmi_config); else { initialize_otg_port(NULL); - mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); + imx51_add_fsl_usb2_udc(&usb_pdata); } gpio_request(USBH1_RST, "usb_rst"); gpio_direction_output(USBH1_RST, 0); msleep(20); gpio_set_value(USBH1_RST, 1); - mxc_register_device(&mxc_usbh1_device, &usbh1_config); + imx51_add_mxc_ehci_hs(1, &usbh1_config); #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD eukrea_mbimxsd51_baseboard_init(); diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index a50174e..f988be7 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -25,7 +25,6 @@ #include <mach/3ds_debugboard.h> #include "devices-imx51.h" -#include "devices.h" #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6)) #define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 468926a..622b2de 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -24,14 +24,12 @@ #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <asm/irq.h> #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include "devices-imx51.h" -#include "devices.h" #include "cpu_op-mx51.h" #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) @@ -176,7 +174,7 @@ static const struct imxi2c_platform_data babbage_i2c_data __initconst = { .bitrate = 100000, }; -static struct imxi2c_platform_data babbage_hsi2c_data = { +static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = { .bitrate = 400000, }; @@ -249,7 +247,7 @@ static int initialize_otg_port(struct platform_device *pdev) void __iomem *usb_base; void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -272,7 +270,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) void __iomem *usb_base; void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -288,17 +286,17 @@ static int initialize_usbh1_port(struct platform_device *pdev) MXC_EHCI_ITC_NO_THRESHOLD); } -static struct mxc_usbh_platform_data dr_utmi_config = { +static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { .init = initialize_otg_port, .portsc = MXC_EHCI_UTMI_16BIT, }; -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; -static struct mxc_usbh_platform_data usbh1_config = { +static const struct mxc_usbh_platform_data usbh1_config __initconst = { .init = initialize_usbh1_port, .portsc = MXC_EHCI_MODE_ULPI, }; @@ -357,8 +355,8 @@ static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = { static void __init mx51_babbage_init(void) { iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | - MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP); + iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21, + PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP); imx51_soc_init(); @@ -381,17 +379,17 @@ static void __init mx51_babbage_init(void) imx51_add_imx_i2c(0, &babbage_i2c_data); imx51_add_imx_i2c(1, &babbage_i2c_data); - mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); + imx51_add_hsi2c(&babbage_hsi2c_data); if (otg_mode_host) - mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + imx51_add_mxc_ehci_otg(&dr_utmi_config); else { initialize_otg_port(NULL); - mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); + imx51_add_fsl_usb2_udc(&usb_pdata); } gpio_usbh1_active(); - mxc_register_device(&mxc_usbh1_device, &usbh1_config); + imx51_add_mxc_ehci_hs(1, &usbh1_config); /* setback USBH1_STP to be function */ mxc_iomux_v3_setup_pad(usbh1stp); babbage_usbhub_reset(); diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index c36880d..d231b3e 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -32,14 +32,12 @@ #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <asm/irq.h> #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include "devices-imx51.h" -#include "devices.h" #include "efika.h" #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c index ba5436a..d4e98f0 100644 --- a/arch/arm/mach-mx5/board-mx51_efikasb.c +++ b/arch/arm/mach-mx5/board-mx51_efikasb.c @@ -35,14 +35,12 @@ #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <asm/irq.h> #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include "devices-imx51.h" -#include "devices.h" #include "efika.h" #define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) @@ -119,7 +117,7 @@ static int initialize_usbh2_port(struct platform_device *pdev) return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); } -static struct mxc_usbh_platform_data usbh2_config = { +static struct mxc_usbh_platform_data usbh2_config __initdata = { .init = initialize_usbh2_port, .portsc = MXC_EHCI_MODE_ULPI, }; @@ -129,7 +127,7 @@ static void __init mx51_efikasb_usb(void) usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); if (usbh2_config.otg) - mxc_register_device(&mxc_usbh2_device, &usbh2_config); + imx51_add_mxc_ehci_hs(2, &usbh2_config); } static const struct gpio_led mx51_efikasb_leds[] __initconst = { diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c index 76a67c4..9d844f1 100644 --- a/arch/arm/mach-mx5/board-mx53_ard.c +++ b/arch/arm/mach-mx5/board-mx53_ard.c @@ -134,8 +134,8 @@ static struct resource ard_smsc911x_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = gpio_to_irq(ARD_ETHERNET_INT_B), - .end = gpio_to_irq(ARD_ETHERNET_INT_B), + .start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B), + .end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B), .flags = IORESOURCE_IRQ, }, }; @@ -234,6 +234,7 @@ static void __init mx53_ard_board_init(void) imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); imx_add_gpio_keys(&ard_button_data); + imx53_add_ahci_imx(); } static void __init mx53_ard_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 4e1d51d..940aac9 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -273,6 +273,7 @@ static void __init mx53_loco_board_init(void) imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); imx_add_gpio_keys(&loco_button_data); gpio_led_register_device(-1, &mx53loco_leds_data); + imx53_add_ahci_imx(); } static void __init mx53_loco_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index bc02894..efcab68 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -35,6 +35,7 @@ #include "devices-imx53.h" #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, @@ -111,6 +112,19 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { .bitrate = 100000, }; +static inline void mx53_smd_ahci_pwr_on(void) +{ + int ret; + + /* Enable SATA PWR */ + ret = gpio_request_one(MX53_SMD_SATA_PWR_EN, + GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr"); + if (ret) { + pr_err("failed to enable SATA_PWR_EN: %d\n", ret); + return; + } +} + static void __init mx53_smd_board_init(void) { imx53_soc_init(); @@ -125,6 +139,8 @@ static void __init mx53_smd_board_init(void) imx53_add_sdhci_esdhc_imx(0, NULL); imx53_add_sdhci_esdhc_imx(1, NULL); imx53_add_sdhci_esdhc_imx(2, NULL); + mx53_smd_ahci_pwr_on(); + imx53_add_ahci_imx(); } static void __init mx53_smd_timer_init(void) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index f7bf996..c2dafe4 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1401,6 +1401,22 @@ static struct clk esdhc4_mx53_clk = { .secondary = &esdhc4_ipg_clk, }; +static struct clk sata_clk = { + .parent = &ipg_clk, + .enable = _clk_max_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_max_disable, +}; + +static struct clk ahci_phy_clk = { + .parent = &usb_phy1_clk, +}; + +static struct clk ahci_dma_clk = { + .parent = &ahb_clk, +}; + DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); @@ -1418,6 +1434,10 @@ DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET, DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, NULL, NULL, &pll3_sw_clk, NULL); +/* PATA */ +DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET, + NULL, NULL, &ipg_clk, &spba_clk); + #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@ -1474,6 +1494,7 @@ static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) + _REGISTER_CLOCK("pata_imx", NULL, pata_clk) }; static struct clk_lookup mx53_lookups[] = { @@ -1507,6 +1528,10 @@ static struct clk_lookup mx53_lookups[] = { _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) + _REGISTER_CLOCK("pata_imx", NULL, pata_clk) + _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk) + _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk) + _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk) }; static void clk_tree_init(void) @@ -1568,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, /* System timer */ mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), - MX51_MXC_INT_GPT); + MX51_INT_GPT); return 0; } diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index e11bc0e..af488bc 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -13,9 +13,15 @@ extern const struct imx_fec_data imx51_fec_data; #define imx51_add_fec(pdata) \ imx_add_fec(&imx51_fec_data, pdata) +extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data; +#define imx51_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata) + extern const struct imx_imx_i2c_data imx51_imx_i2c_data[]; #define imx51_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) +#define imx51_add_hsi2c(pdata) \ + imx51_add_imx_i2c(2, pdata) extern const struct imx_imx_ssi_data imx51_imx_ssi_data[]; #define imx51_add_imx_ssi(id, pdata) \ @@ -25,6 +31,13 @@ extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[]; #define imx51_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) +extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data; +#define imx51_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[]; +#define imx51_add_mxc_ehci_hs(id, pdata) \ + imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata) + extern const struct imx_mxc_nand_data imx51_mxc_nand_data; #define imx51_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) @@ -52,3 +65,7 @@ extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; extern const struct imx_imx_keypad_data imx51_imx_keypad_data; #define imx51_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) + +extern const struct imx_pata_imx_data imx51_pata_imx_data; +#define imx51_add_pata_imx() \ + imx_add_pata_imx(&imx51_pata_imx_data) diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index c27fe8b..7fe5e46 100644 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h @@ -40,3 +40,8 @@ extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; extern const struct imx_imx_keypad_data imx53_imx_keypad_data; #define imx53_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) + +extern const struct imx_pata_imx_data imx53_pata_imx_data; +#define imx53_add_pata_imx() \ + imx_add_pata_imx(&imx53_pata_imx_data) +extern struct platform_device *__init imx53_add_ahci_imx(void); diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c deleted file mode 100644 index 371ca8c..0000000 --- a/arch/arm/mach-mx5/devices.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <mach/hardware.h> -#include <mach/imx-uart.h> -#include <mach/irqs.h> - -static struct resource mxc_hsi2c_resources[] = { - { - .start = MX51_HSI2C_DMA_BASE_ADDR, - .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MX51_MXC_INT_HS_I2C, - .end = MX51_MXC_INT_HS_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_hsi2c_device = { - .name = "imx-i2c", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_hsi2c_resources), - .resource = mxc_hsi2c_resources -}; - -static u64 usb_dma_mask = DMA_BIT_MASK(32); - -static struct resource usbotg_resources[] = { - { - .start = MX51_OTG_BASE_ADDR, - .end = MX51_OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX51_MXC_INT_USB_OTG, - .flags = IORESOURCE_IRQ, - }, -}; - -/* OTG gadget device */ -struct platform_device mxc_usbdr_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .num_resources = ARRAY_SIZE(usbotg_resources), - .resource = usbotg_resources, - .dev = { - .dma_mask = &usb_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device mxc_usbdr_host_device = { - .name = "mxc-ehci", - .id = 0, - .num_resources = ARRAY_SIZE(usbotg_resources), - .resource = usbotg_resources, - .dev = { - .dma_mask = &usb_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource usbh1_resources[] = { - { - .start = MX51_OTG_BASE_ADDR + 0x200, - .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX51_MXC_INT_USB_H1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh1_device = { - .name = "mxc-ehci", - .id = 1, - .num_resources = ARRAY_SIZE(usbh1_resources), - .resource = usbh1_resources, - .dev = { - .dma_mask = &usb_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource usbh2_resources[] = { - { - .start = MX51_OTG_BASE_ADDR + 0x400, - .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX51_MXC_INT_USB_H2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh2_device = { - .name = "mxc-ehci", - .id = 2, - .num_resources = ARRAY_SIZE(usbh2_resources), - .resource = usbh2_resources, - .dev = { - .dma_mask = &usb_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h deleted file mode 100644 index 55a5129..0000000 --- a/arch/arm/mach-mx5/devices.h +++ /dev/null @@ -1,5 +0,0 @@ -extern struct platform_device mxc_usbdr_host_device; -extern struct platform_device mxc_usbh1_device; -extern struct platform_device mxc_usbh2_device; -extern struct platform_device mxc_usbdr_udc_device; -extern struct platform_device mxc_hsi2c_device; diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c index 7ce12c8..c17fa13 100644 --- a/arch/arm/mach-mx5/ehci.c +++ b/arch/arm/mach-mx5/ehci.c @@ -52,7 +52,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) void __iomem *usbother_base; int ret = 0; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) { printk(KERN_ERR "%s(): ioremap failed\n", __func__); return -ENOMEM; diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index bbf4564..a6a3ab8 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -28,7 +28,6 @@ #include <asm/mach/arch.h> #include "devices-imx51.h" -#include "devices.h" #define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30) #define MBIMX51_LED0 IMX_GPIO_NR(3, 5) @@ -160,7 +159,7 @@ struct tsc2007_platform_data tsc2007_data = { static struct i2c_board_info mbimx51_i2c_devices[] = { { I2C_BOARD_INFO("tsc2007", 0x49), - .irq = gpio_to_irq(MBIMX51_TSC2007_GPIO), + .irq = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO), .platform_data = &tsc2007_data, }, { I2C_BOARD_INFO("tlv320aic23", 0x1a), diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index 2619239..d817fc8 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c @@ -24,7 +24,6 @@ #include <linux/gpio.h> #include <linux/interrupt.h> -#include <linux/irq.h> #include <linux/leds.h> #include <linux/platform_device.h> #include <linux/input.h> @@ -41,13 +40,12 @@ #include <mach/audmux.h> #include "devices-imx51.h" -#include "devices.h" static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { /* LED */ MX51_PAD_NANDF_D10__GPIO3_30, /* SWITCH */ - _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | + NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), /* UART2 */ @@ -66,7 +64,7 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { MX51_PAD_SD1_DATA2__SD1_DATA2, MX51_PAD_SD1_DATA3__SD1_DATA3, /* SD1 CD */ - _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | + NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), }; diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c deleted file mode 100644 index 77e374c..0000000 --- a/arch/arm/mach-mx5/mm-mx50.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Create static mapping between physical to virtual memory. - */ - -#include <linux/mm.h> -#include <linux/init.h> - -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/iomux-v3.h> -#include <mach/irqs.h> - -/* - * Define the MX50 memory map. - */ -static struct map_desc mx50_io_desc[] __initdata = { - imx_map_entry(MX50, TZIC, MT_DEVICE), - imx_map_entry(MX50, SPBA0, MT_DEVICE), - imx_map_entry(MX50, AIPS1, MT_DEVICE), - imx_map_entry(MX50, AIPS2, MT_DEVICE), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx50_map_io(void) -{ - iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); -} - -void __init imx50_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX50); - mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); -} - -void __init mx50_init_irq(void) -{ - tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); -} - -void __init imx50_soc_init(void) -{ - /* i.mx50 has the i.mx31 type gpio */ - mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); - mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); - mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); - mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); - mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); - mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); -} diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index baea6e5..26eacc9 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -21,12 +21,27 @@ #include <mach/devices-common.h> #include <mach/iomux-v3.h> +static void imx5_idle(void) +{ + mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); +} + +/* + * Define the MX50 memory map. + */ +static struct map_desc mx50_io_desc[] __initdata = { + imx_map_entry(MX50, TZIC, MT_DEVICE), + imx_map_entry(MX50, SPBA0, MT_DEVICE), + imx_map_entry(MX50, AIPS1, MT_DEVICE), + imx_map_entry(MX50, AIPS2, MT_DEVICE), +}; + /* * Define the MX51 memory map. */ static struct map_desc mx51_io_desc[] __initdata = { + imx_map_entry(MX51, TZIC, MT_DEVICE), imx_map_entry(MX51, IRAM, MT_DEVICE), - imx_map_entry(MX51, DEBUG, MT_DEVICE), imx_map_entry(MX51, AIPS1, MT_DEVICE), imx_map_entry(MX51, SPBA0, MT_DEVICE), imx_map_entry(MX51, AIPS2, MT_DEVICE), @@ -36,6 +51,7 @@ static struct map_desc mx51_io_desc[] __initdata = { * Define the MX53 memory map. */ static struct map_desc mx53_io_desc[] __initdata = { + imx_map_entry(MX53, TZIC, MT_DEVICE), imx_map_entry(MX53, AIPS1, MT_DEVICE), imx_map_entry(MX53, SPBA0, MT_DEVICE), imx_map_entry(MX53, AIPS2, MT_DEVICE), @@ -46,21 +62,34 @@ static struct map_desc mx53_io_desc[] __initdata = { * system startup to create static physical to virtual memory mappings * for the IO modules. */ +void __init mx50_map_io(void) +{ + iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); +} + void __init mx51_map_io(void) { iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); } +void __init mx53_map_io(void) +{ + iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); +} + +void __init imx50_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX50); + mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); +} + void __init imx51_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX51); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); -} - -void __init mx53_map_io(void) -{ - iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); + imx_idle = imx5_idle; } void __init imx53_init_early(void) @@ -70,35 +99,19 @@ void __init imx53_init_early(void) mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); } -void __init mx51_init_irq(void) +void __init mx50_init_irq(void) { - unsigned long tzic_addr; - void __iomem *tzic_virt; - - if (mx51_revision() < IMX_CHIP_REVISION_2_0) - tzic_addr = MX51_TZIC_BASE_ADDR_TO1; - else - tzic_addr = MX51_TZIC_BASE_ADDR; - - tzic_virt = ioremap(tzic_addr, SZ_16K); - if (!tzic_virt) - panic("unable to map TZIC interrupt controller\n"); + tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); +} - tzic_init_irq(tzic_virt); +void __init mx51_init_irq(void) +{ + tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); } void __init mx53_init_irq(void) { - unsigned long tzic_addr; - void __iomem *tzic_virt; - - tzic_addr = MX53_TZIC_BASE_ADDR; - - tzic_virt = ioremap(tzic_addr, SZ_16K); - if (!tzic_virt) - panic("unable to map TZIC interrupt controller\n"); - - tzic_init_irq(tzic_virt); + tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); } static struct sdma_script_start_addrs imx51_sdma_script __initdata = { @@ -138,13 +151,24 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = { .script_addrs = &imx53_sdma_script, }; +void __init imx50_soc_init(void) +{ + /* i.mx50 has the i.mx31 type gpio */ + mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); + mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); + mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); + mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); + mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); + mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); +} + void __init imx51_soc_init(void) { /* i.mx51 has the i.mx31 type gpio */ - mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH); - mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH); - mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH); - mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH); + mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); + mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); + mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH); + mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH); /* i.mx51 has the i.mx35 type sdma */ imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index c920945..83c5702 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -34,14 +34,12 @@ #include <linux/usb/ulpi.h> #include <mach/ulpi.h> -#include <asm/irq.h> #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include "devices-imx51.h" -#include "devices.h" #include "efika.h" #include "cpu_op-mx51.h" @@ -133,7 +131,7 @@ static int initialize_otg_port(struct platform_device *pdev) u32 v; void __iomem *usb_base; void __iomem *usbother_base; - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); @@ -150,7 +148,7 @@ static int initialize_otg_port(struct platform_device *pdev) return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); } -static struct mxc_usbh_platform_data dr_utmi_config = { +static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { .init = initialize_otg_port, .portsc = MXC_EHCI_UTMI_16BIT, }; @@ -170,7 +168,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) gpio_set_value(EFIKAMX_USBH1_STP, 1); msleep(1); - usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); /* The clock for the USBH1 ULPI port will come externally */ @@ -189,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); } -static struct mxc_usbh_platform_data usbh1_config = { +static struct mxc_usbh_platform_data usbh1_config __initdata = { .init = initialize_usbh1_port, .portsc = MXC_EHCI_MODE_ULPI, }; @@ -217,9 +215,9 @@ static void __init mx51_efika_usb(void) usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); - mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); + imx51_add_mxc_ehci_otg(&dr_utmi_config); if (usbh1_config.otg) - mxc_register_device(&mxc_usbh1_device, &usbh1_config); + imx51_add_mxc_ehci_hs(1, &usbh1_config); } static struct mtd_partition mx51_efika_spi_nor_partitions[] = { @@ -589,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { .bus_num = 0, .chip_select = 0, .platform_data = &mx51_efika_mc13892_data, - .irq = gpio_to_irq(EFIKAMX_PMIC), + .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC), }, }; @@ -627,8 +625,9 @@ void __init efika_board_common_init(void) ARRAY_SIZE(mx51_efika_spi_board_info)); imx51_add_ecspi(0, &mx51_efika_spi_pdata); + imx51_add_pata_imx(); + #if defined(CONFIG_CPU_FREQ_IMX) get_cpu_op = mx51_get_cpu_op; #endif } - diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c index e4529af..98052fc 100644 --- a/arch/arm/mach-mx5/pm-imx5.c +++ b/arch/arm/mach-mx5/pm-imx5.c @@ -14,14 +14,19 @@ #include <linux/err.h> #include <asm/cacheflush.h> #include <asm/tlbflush.h> -#include <mach/system.h> +#include <mach/common.h> +#include <mach/hardware.h> #include "crm_regs.h" static struct clk *gpc_dvfs_clk; +static int mx5_suspend_prepare(void) +{ + return clk_enable(gpc_dvfs_clk); +} + static int mx5_suspend_enter(suspend_state_t state) { - clk_enable(gpc_dvfs_clk); switch (state) { case PM_SUSPEND_MEM: mx5_cpu_lp_set(STOP_POWER_OFF); @@ -42,11 +47,14 @@ static int mx5_suspend_enter(suspend_state_t state) __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); } cpu_do_idle(); - clk_disable(gpc_dvfs_clk); - return 0; } +static void mx5_suspend_finish(void) +{ + clk_disable(gpc_dvfs_clk); +} + static int mx5_pm_valid(suspend_state_t state) { return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); @@ -54,7 +62,9 @@ static int mx5_pm_valid(suspend_state_t state) static const struct platform_suspend_ops mx5_suspend_ops = { .valid = mx5_pm_valid, + .prepare = mx5_suspend_prepare, .enter = mx5_suspend_enter, + .finish = mx5_suspend_finish, }; static int __init mx5_pm_init(void) diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c index 76ae8dc..144ebeb 100644 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-mx5/system.c @@ -13,6 +13,7 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <mach/hardware.h> +#include <mach/common.h> #include "crm_regs.h" /* set cpu low power mode before WFI instruction. This function is called diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index adcfb4e..8c93b24 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -1,11 +1,11 @@ # Common support -obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o +obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o obj-$(CONFIG_MXS_OCOTP) += ocotp.o obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o -obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o +obj-$(CONFIG_SOC_IMX23) += clock-mx23.o +obj-$(CONFIG_SOC_IMX28) += clock-mx28.o obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot index eb541e0..07b11fe 100644 --- a/arch/arm/mach-mxs/Makefile.boot +++ b/arch/arm/mach-mxs/Makefile.boot @@ -1 +1 @@ -zreladdr-y := 0x40008000 +zreladdr-y += 0x40008000 diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 3122310..7fa1ac4 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -349,7 +349,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ \ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \ - reg |= frac; \ + reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC; \ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ } \ \ diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h index bb11e63..40a8c17 100644 --- a/arch/arm/mach-mxs/include/mach/gpio.h +++ b/arch/arm/mach-mxs/include/mach/gpio.h @@ -1,27 +1 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MXS_GPIO_H__ -#define __MACH_MXS_GPIO_H__ - -#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) - -#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START) - -#endif /* __MACH_MXS_GPIO_H__ */ +/* empty */ diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h index 0582318..0d2d2b4 100644 --- a/arch/arm/mach-mxs/include/mach/mxs.h +++ b/arch/arm/mach-mxs/include/mach/mxs.h @@ -87,6 +87,8 @@ .type = _type, \ } +#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) + #define MXS_SET_ADDR 0x4 #define MXS_CLR_ADDR 0x8 #define MXS_TOG_ADDR 0xc diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c index 3c2de33..69e218d 100644 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ b/arch/arm/mach-mxs/mach-mx23evk.c @@ -15,7 +15,6 @@ #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/gpio.h> -#include <linux/irq.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -182,6 +181,6 @@ MACHINE_START(MX23EVK, "Freescale MX23 EVK") /* Maintainer: Freescale Semiconductor, Inc. */ .map_io = mx23_map_io, .init_irq = mx23_init_irq, - .init_machine = mx23evk_init, .timer = &mx23evk_timer, + .init_machine = mx23evk_init, MACHINE_END diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index eaaf6ff..0173c3b 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -16,7 +16,6 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/leds.h> -#include <linux/irq.h> #include <linux/clk.h> #include <asm/mach-types.h> @@ -352,6 +351,11 @@ static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { }, }; +static struct gpio mx28evk_lcd_gpios[] = { + { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" }, + { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" }, +}; + static void __init mx28evk_init(void) { int ret; @@ -378,19 +382,12 @@ static void __init mx28evk_init(void) mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); } - ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); - if (ret) - pr_warn("failed to request gpio lcd-enable: %d\n", ret); - else - gpio_set_value(MX28EVK_LCD_ENABLE, 1); - - ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable"); + ret = gpio_request_array(mx28evk_lcd_gpios, + ARRAY_SIZE(mx28evk_lcd_gpios)); if (ret) - pr_warn("failed to request gpio bl-enable: %d\n", ret); + pr_warn("failed to request gpio pins for lcd: %d\n", ret); else - gpio_set_value(MX28EVK_BL_ENABLE, 1); - - mx28_add_mxsfb(&mx28evk_mxsfb_pdata); + mx28_add_mxsfb(&mx28evk_mxsfb_pdata); /* power on mmc slot by writing 0 to the gpio */ ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, @@ -403,7 +400,8 @@ static void __init mx28evk_init(void) "mmc1-slot-power"); if (ret) pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); - mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); + else + mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); gpio_led_register_device(0, &mx28evk_led_data); } @@ -421,6 +419,6 @@ MACHINE_START(MX28EVK, "Freescale MX28 EVK") /* Maintainer: Freescale Semiconductor, Inc. */ .map_io = mx28_map_io, .init_irq = mx28_init_irq, - .init_machine = mx28evk_init, .timer = &mx28evk_timer, + .init_machine = mx28evk_init, MACHINE_END diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c index 7f38d82..3fe5dd5 100644 --- a/arch/arm/mach-mxs/mach-stmp378x_devb.c +++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c @@ -19,7 +19,6 @@ #include <linux/platform_device.h> #include <linux/gpio.h> -#include <linux/irq.h> #include <linux/spi/spi.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c index 515a423..9555938 100644 --- a/arch/arm/mach-mxs/mach-tx28.c +++ b/arch/arm/mach-mxs/mach-tx28.c @@ -175,6 +175,6 @@ static struct sys_timer tx28_timer = { MACHINE_START(TX28, "Ka-Ro electronics TX28 module") .map_io = mx28_map_io, .init_irq = mx28_init_irq, - .init_machine = tx28_stk5v3_init, .timer = &tx28_timer, + .init_machine = tx28_stk5v3_init, MACHINE_END diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c deleted file mode 100644 index b6e18dd..0000000 --- a/arch/arm/mach-mxs/mm-mx28.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Create static mapping between physical to virtual memory. - */ - -#include <linux/mm.h> -#include <linux/init.h> - -#include <asm/mach/map.h> - -#include <mach/mx28.h> -#include <mach/common.h> -#include <mach/iomux.h> - -/* - * Define the MX28 memory map. - */ -static struct map_desc mx28_io_desc[] __initdata = { - mxs_map_entry(MX28, OCRAM, MT_DEVICE), - mxs_map_entry(MX28, IO, MT_DEVICE), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx28_map_io(void) -{ - iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); -} - -void __init mx28_init_irq(void) -{ - icoll_init_irq(); -} diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm.c index 1b2345a..50af5ce 100644 --- a/arch/arm/mach-mxs/mm-mx23.c +++ b/arch/arm/mach-mxs/mm.c @@ -17,6 +17,7 @@ #include <asm/mach/map.h> #include <mach/mx23.h> +#include <mach/mx28.h> #include <mach/common.h> #include <mach/iomux.h> @@ -29,6 +30,14 @@ static struct map_desc mx23_io_desc[] __initdata = { }; /* + * Define the MX28 memory map. + */ +static struct map_desc mx28_io_desc[] __initdata = { + mxs_map_entry(MX28, OCRAM, MT_DEVICE), + mxs_map_entry(MX28, IO, MT_DEVICE), +}; + +/* * This function initializes the memory map. It is called during the * system startup to create static physical to virtual memory mappings * for the IO modules. @@ -42,3 +51,13 @@ void __init mx23_init_irq(void) { icoll_init_irq(); } + +void __init mx28_map_io(void) +{ + iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); +} + +void __init mx28_init_irq(void) +{ + icoll_init_irq(); +} diff --git a/arch/arm/mach-netx/Makefile.boot b/arch/arm/mach-netx/Makefile.boot index b81cf6a..534a4d2 100644 --- a/arch/arm/mach-netx/Makefile.boot +++ b/arch/arm/mach-netx/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x80008000 + zreladdr-y += 0x80008000 diff --git a/arch/arm/mach-nomadik/Makefile.boot b/arch/arm/mach-nomadik/Makefile.boot index c7e75ac..ff0a4b5 100644 --- a/arch/arm/mach-nomadik/Makefile.boot +++ b/arch/arm/mach-nomadik/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-nuc93x/Kconfig b/arch/arm/mach-nuc93x/Kconfig deleted file mode 100644 index 2bc40a2..0000000 --- a/arch/arm/mach-nuc93x/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if ARCH_NUC93X - -config CPU_NUC932 - bool - help - Support for NUC932 of Nuvoton NUC93X CPUs. - -menu "NUC932 Machines" - -config MACH_NUC932EVB - bool "Nuvoton NUC932 Evaluation Board" - default y - select CPU_NUC932 - help - Say Y here if you are using the Nuvoton NUC932EVB - -endmenu - -endif diff --git a/arch/arm/mach-nuc93x/Makefile b/arch/arm/mach-nuc93x/Makefile deleted file mode 100644 index 440e2de..0000000 --- a/arch/arm/mach-nuc93x/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := irq.o time.o dev.o cpu.o clock.o -# NUC932 CPU support files - -obj-$(CONFIG_CPU_NUC932) += nuc932.o - -# machine support - -obj-$(CONFIG_MACH_NUC932EVB) += mach-nuc932evb.o diff --git a/arch/arm/mach-nuc93x/Makefile.boot b/arch/arm/mach-nuc93x/Makefile.boot deleted file mode 100644 index a057b54..0000000 --- a/arch/arm/mach-nuc93x/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ -zreladdr-y := 0x00008000 -params_phys-y := 0x00000100 - diff --git a/arch/arm/mach-nuc93x/clock.c b/arch/arm/mach-nuc93x/clock.c deleted file mode 100644 index 0521efb..0000000 --- a/arch/arm/mach-nuc93x/clock.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * linux/arch/arm/mach-nuc93x/clock.c - * - * Copyright (c) 2008 Nuvoton technology corporation - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <mach/hardware.h> - -#include "clock.h" - -static DEFINE_SPINLOCK(clocks_lock); - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clocks_lock, flags); - if (clk->enabled++ == 0) - (clk->enable)(clk, 1); - spin_unlock_irqrestore(&clocks_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - WARN_ON(clk->enabled == 0); - - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->enabled == 0) - (clk->enable)(clk, 0); - spin_unlock_irqrestore(&clocks_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return 27000000; -} -EXPORT_SYMBOL(clk_get_rate); - -void nuc93x_clk_enable(struct clk *clk, int enable) -{ - unsigned int clocks = clk->cken; - unsigned long clken; - - clken = __raw_readl(NUC93X_VA_CLKPWR); - - if (enable) - clken |= clocks; - else - clken &= ~clocks; - - __raw_writel(clken, NUC93X_VA_CLKPWR); -} - -void clks_register(struct clk_lookup *clks, size_t num) -{ - int i; - - for (i = 0; i < num; i++) - clkdev_add(&clks[i]); -} diff --git a/arch/arm/mach-nuc93x/clock.h b/arch/arm/mach-nuc93x/clock.h deleted file mode 100644 index 4de1f1d..0000000 --- a/arch/arm/mach-nuc93x/clock.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * linux/arch/arm/mach-nuc93x/clock.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. - */ - -#include <linux/clkdev.h> - -void nuc93x_clk_enable(struct clk *clk, int enable); -void clks_register(struct clk_lookup *clks, size_t num); - -struct clk { - unsigned long cken; - unsigned int enabled; - void (*enable)(struct clk *, int enable); -}; - -#define DEFINE_CLK(_name, _ctrlbit) \ -struct clk clk_##_name = { \ - .enable = nuc93x_clk_enable, \ - .cken = (1 << _ctrlbit), \ - } - -#define DEF_CLKLOOK(_clk, _devname, _conname) \ - { \ - .clk = _clk, \ - .dev_id = _devname, \ - .con_id = _conname, \ - } - diff --git a/arch/arm/mach-nuc93x/cpu.c b/arch/arm/mach-nuc93x/cpu.c deleted file mode 100644 index f6ff5d8..0000000 --- a/arch/arm/mach-nuc93x/cpu.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * linux/arch/arm/mach-nuc93x/cpu.c - * - * Copyright (c) 2009 Nuvoton corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * NUC93x series cpu common support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation;version 2 of the License. - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/serial_8250.h> -#include <linux/delay.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/irq.h> - -#include <mach/hardware.h> -#include <mach/regs-serial.h> -#include <mach/regs-clock.h> -#include <mach/regs-ebi.h> - -#include "cpu.h" -#include "clock.h" - -/* Initial IO mappings */ - -static struct map_desc nuc93x_iodesc[] __initdata = { - IODESC_ENT(IRQ), - IODESC_ENT(GCR), - IODESC_ENT(UART), - IODESC_ENT(TIMER), - IODESC_ENT(EBI), -}; - -/* Initial nuc932 clock declarations. */ -static DEFINE_CLK(audio, 2); -static DEFINE_CLK(sd, 3); -static DEFINE_CLK(jpg, 4); -static DEFINE_CLK(video, 5); -static DEFINE_CLK(vpost, 6); -static DEFINE_CLK(2d, 7); -static DEFINE_CLK(gpu, 8); -static DEFINE_CLK(gdma, 9); -static DEFINE_CLK(adc, 10); -static DEFINE_CLK(uart, 11); -static DEFINE_CLK(spi, 12); -static DEFINE_CLK(pwm, 13); -static DEFINE_CLK(timer, 14); -static DEFINE_CLK(wdt, 15); -static DEFINE_CLK(ac97, 16); -static DEFINE_CLK(i2s, 16); -static DEFINE_CLK(usbck, 17); -static DEFINE_CLK(usb48, 18); -static DEFINE_CLK(usbh, 19); -static DEFINE_CLK(i2c, 20); -static DEFINE_CLK(ext, 0); - -static struct clk_lookup nuc932_clkregs[] = { - DEF_CLKLOOK(&clk_audio, "nuc932-audio", NULL), - DEF_CLKLOOK(&clk_sd, "nuc932-sd", NULL), - DEF_CLKLOOK(&clk_jpg, "nuc932-jpg", "NULL"), - DEF_CLKLOOK(&clk_video, "nuc932-video", "NULL"), - DEF_CLKLOOK(&clk_vpost, "nuc932-vpost", NULL), - DEF_CLKLOOK(&clk_2d, "nuc932-2d", NULL), - DEF_CLKLOOK(&clk_gpu, "nuc932-gpu", NULL), - DEF_CLKLOOK(&clk_gdma, "nuc932-gdma", "NULL"), - DEF_CLKLOOK(&clk_adc, "nuc932-adc", NULL), - DEF_CLKLOOK(&clk_uart, NULL, "uart"), - DEF_CLKLOOK(&clk_spi, "nuc932-spi", NULL), - DEF_CLKLOOK(&clk_pwm, "nuc932-pwm", NULL), - DEF_CLKLOOK(&clk_timer, NULL, "timer"), - DEF_CLKLOOK(&clk_wdt, "nuc932-wdt", NULL), - DEF_CLKLOOK(&clk_ac97, "nuc932-ac97", NULL), - DEF_CLKLOOK(&clk_i2s, "nuc932-i2s", NULL), - DEF_CLKLOOK(&clk_usbck, "nuc932-usbck", NULL), - DEF_CLKLOOK(&clk_usb48, "nuc932-usb48", NULL), - DEF_CLKLOOK(&clk_usbh, "nuc932-usbh", NULL), - DEF_CLKLOOK(&clk_i2c, "nuc932-i2c", NULL), - DEF_CLKLOOK(&clk_ext, NULL, "ext"), -}; - -/* Initial serial platform data */ - -struct plat_serial8250_port nuc93x_uart_data[] = { - NUC93X_8250PORT(UART0), - {}, -}; - -struct platform_device nuc93x_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = nuc93x_uart_data, - }, -}; - -/*Init NUC93x evb io*/ - -void __init nuc93x_map_io(struct map_desc *mach_desc, int mach_size) -{ - unsigned long idcode = 0x0; - - iotable_init(mach_desc, mach_size); - iotable_init(nuc93x_iodesc, ARRAY_SIZE(nuc93x_iodesc)); - - idcode = __raw_readl(NUC93XPDID); - if (idcode == NUC932_CPUID) - printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode); - else - printk(KERN_ERR "CPU type detect error!\n"); - -} - -/*Init NUC93x clock*/ - -void __init nuc93x_init_clocks(void) -{ - clks_register(nuc932_clkregs, ARRAY_SIZE(nuc932_clkregs)); -} - diff --git a/arch/arm/mach-nuc93x/cpu.h b/arch/arm/mach-nuc93x/cpu.h deleted file mode 100644 index 9def28197..0000000 --- a/arch/arm/mach-nuc93x/cpu.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * arch/arm/mach-nuc93x/cpu.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Header file for NUC93X CPU support - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#define IODESC_ENT(y) \ -{ \ - .virtual = (unsigned long)NUC93X_VA_##y, \ - .pfn = __phys_to_pfn(NUC93X_PA_##y), \ - .length = NUC93X_SZ_##y, \ - .type = MT_DEVICE, \ -} - -#define NUC93X_8250PORT(name) \ -{ \ - .membase = name##_BA, \ - .mapbase = name##_PA, \ - .irq = IRQ_##name, \ - .uartclk = 57139200, \ - .regshift = 2, \ - .iotype = UPIO_MEM, \ - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ -} - -/*Cpu identifier register*/ - -#define NUC93XPDID NUC93X_VA_GCR -#define NUC932_CPUID 0x29550091 - -/* extern file from cpu.c */ - -extern void nuc93x_clock_source(struct device *dev, unsigned char *src); -extern void nuc93x_init_clocks(void); -extern void nuc93x_map_io(struct map_desc *mach_desc, int mach_size); -extern void nuc93x_board_init(struct platform_device **device, int size); -extern struct platform_device nuc93x_serial_device; - diff --git a/arch/arm/mach-nuc93x/dev.c b/arch/arm/mach-nuc93x/dev.c deleted file mode 100644 index a962ae9..0000000 --- a/arch/arm/mach-nuc93x/dev.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * linux/arch/arm/mach-nuc93x/dev.c - * - * Copyright (C) 2009 Nuvoton corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation;version 2 of the License. - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/platform_device.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach-types.h> - -#include "cpu.h" - -/*Here should be your evb resourse,such as LCD*/ - -static struct platform_device *nuc93x_public_dev[] __initdata = { - &nuc93x_serial_device, -}; - -/* Provide adding specific CPU platform devices API */ - -void __init nuc93x_board_init(struct platform_device **device, int size) -{ - platform_add_devices(device, size); - platform_add_devices(nuc93x_public_dev, ARRAY_SIZE(nuc93x_public_dev)); -} - diff --git a/arch/arm/mach-nuc93x/include/mach/entry-macro.S b/arch/arm/mach-nuc93x/include/mach/entry-macro.S deleted file mode 100644 index 1352cbd..0000000 --- a/arch/arm/mach-nuc93x/include/mach/entry-macro.S +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/entry-macro.S - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - */ - -#include <mach/hardware.h> -#include <mach/regs-irq.h> - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #AIC_BA - - ldr \irqnr, [ \base, #AIC_IPER] - ldr \irqnr, [ \base, #AIC_ISNR] - cmp \irqnr, #0 - - .endm - - /* currently don't need an disable_fiq macro */ - - .macro disable_fiq - .endm diff --git a/arch/arm/mach-nuc93x/include/mach/hardware.h b/arch/arm/mach-nuc93x/include/mach/hardware.h deleted file mode 100644 index fb5c6fc..0000000 --- a/arch/arm/mach-nuc93x/include/mach/hardware.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/hardware.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> -#include <mach/map.h> - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h deleted file mode 100644 index 72e5051..0000000 --- a/arch/arm/mach-nuc93x/include/mach/io.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/io.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * 1:1 mapping for ioremapped regions. - */ - -#define __mem_pci(a) (a) -#define __io(a) __typesafe_io(a) - -#endif diff --git a/arch/arm/mach-nuc93x/include/mach/irqs.h b/arch/arm/mach-nuc93x/include/mach/irqs.h deleted file mode 100644 index 7c4aa71..0000000 --- a/arch/arm/mach-nuc93x/include/mach/irqs.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/irqs.h - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation;version 2 of the License. - * - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define NUC93X_IRQ(x) (x) - -/* Main cpu interrupts */ - -#define IRQ_WDT NUC93X_IRQ(1) -#define IRQ_IRQ0 NUC93X_IRQ(2) -#define IRQ_IRQ1 NUC93X_IRQ(3) -#define IRQ_IRQ2 NUC93X_IRQ(4) -#define IRQ_IRQ3 NUC93X_IRQ(5) -#define IRQ_USBH NUC93X_IRQ(6) -#define IRQ_APU NUC93X_IRQ(7) -#define IRQ_VPOST NUC93X_IRQ(8) -#define IRQ_ADC NUC93X_IRQ(9) -#define IRQ_UART0 NUC93X_IRQ(10) -#define IRQ_TIMER0 NUC93X_IRQ(11) -#define IRQ_GPU0 NUC93X_IRQ(12) -#define IRQ_GPU1 NUC93X_IRQ(13) -#define IRQ_GPU2 NUC93X_IRQ(14) -#define IRQ_GPU3 NUC93X_IRQ(15) -#define IRQ_GPU4 NUC93X_IRQ(16) -#define IRQ_VIN NUC93X_IRQ(17) -#define IRQ_USBD NUC93X_IRQ(18) -#define IRQ_VRAMLD NUC93X_IRQ(19) -#define IRQ_GDMA0 NUC93X_IRQ(20) -#define IRQ_GDMA1 NUC93X_IRQ(21) -#define IRQ_SDIO NUC93X_IRQ(22) -#define IRQ_FMI NUC93X_IRQ(22) -#define IRQ_JPEG NUC93X_IRQ(23) -#define IRQ_SPI0 NUC93X_IRQ(24) -#define IRQ_SPI1 NUC93X_IRQ(25) -#define IRQ_RTC NUC93X_IRQ(26) -#define IRQ_PWM0 NUC93X_IRQ(27) -#define IRQ_PWM1 NUC93X_IRQ(28) -#define IRQ_PWM2 NUC93X_IRQ(29) -#define IRQ_PWM3 NUC93X_IRQ(30) -#define IRQ_I2SAC97 NUC93X_IRQ(31) -#define IRQ_CAP0 IRQ_PWM0 -#define IRQ_CAP1 IRQ_PWM1 -#define IRQ_CAP2 IRQ_PWM2 -#define IRQ_CAP3 IRQ_PWM3 -#define NR_IRQS (IRQ_I2SAC97 + 1) - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/map.h b/arch/arm/mach-nuc93x/include/mach/map.h deleted file mode 100644 index fd0b5e8..0000000 --- a/arch/arm/mach-nuc93x/include/mach/map.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/map.h - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation;version 2 of the License. - * - */ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H - -#define MAP_OFFSET (0xfff00000) -#define CLK_OFFSET (0x10) - -#ifndef __ASSEMBLY__ -#define NUC93X_ADDR(x) ((void __iomem *)(0xF0000000 + ((x)&(~MAP_OFFSET)))) -#else -#define NUC93X_ADDR(x) (0xF0000000 + ((x)&(~MAP_OFFSET))) -#endif - - /* - * nuc932 hardware register definition - */ - -#define NUC93X_PA_IRQ (0xFFF83000) -#define NUC93X_PA_GCR (0xFFF00000) -#define NUC93X_PA_EBI (0xFFF01000) -#define NUC93X_PA_UART (0xFFF80000) -#define NUC93X_PA_TIMER (0xFFF81000) -#define NUC93X_PA_GPIO (0xFFF84000) -#define NUC93X_PA_GDMA (0xFFF03000) -#define NUC93X_PA_USBHOST (0xFFF0d000) -#define NUC93X_PA_I2C (0xFFF89000) -#define NUC93X_PA_LCD (0xFFF06000) -#define NUC93X_PA_GE (0xFFF05000) -#define NUC93X_PA_ADC (0xFFF85000) -#define NUC93X_PA_RTC (0xFFF87000) -#define NUC93X_PA_PWM (0xFFF82000) -#define NUC93X_PA_ACTL (0xFFF0a000) -#define NUC93X_PA_USBDEV (0xFFF0C000) -#define NUC93X_PA_JEPEG (0xFFF0e000) -#define NUC93X_PA_CACHE_T (0xFFF60000) -#define NUC93X_PA_VRAM (0xFFF0b000) -#define NUC93X_PA_DMAC (0xFFF09000) -#define NUC93X_PA_I2SM (0xFFF08000) -#define NUC93X_PA_CACHE (0xFFF02000) -#define NUC93X_PA_GPU (0xFFF04000) -#define NUC93X_PA_VIDEOIN (0xFFF07000) -#define NUC93X_PA_SPI0 (0xFFF86000) -#define NUC93X_PA_SPI1 (0xFFF88000) - - /* - * nuc932 virtual address mapping. - * interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ - -#define NUC93X_VA_IRQ NUC93X_ADDR(0x00000000) -#define NUC93X_SZ_IRQ SZ_4K - -#define NUC93X_VA_GCR NUC93X_ADDR(NUC93X_PA_IRQ) -#define NUC93X_VA_CLKPWR (NUC93X_VA_GCR+CLK_OFFSET) -#define NUC93X_SZ_GCR SZ_4K - -/* EBI management */ - -#define NUC93X_VA_EBI NUC93X_ADDR(NUC93X_PA_EBI) -#define NUC93X_SZ_EBI SZ_4K - -/* UARTs */ - -#define NUC93X_VA_UART NUC93X_ADDR(NUC93X_PA_UART) -#define NUC93X_SZ_UART SZ_4K - -/* Timers */ - -#define NUC93X_VA_TIMER NUC93X_ADDR(NUC93X_PA_TIMER) -#define NUC93X_SZ_TIMER SZ_4K - -/* GPIO ports */ - -#define NUC93X_VA_GPIO NUC93X_ADDR(NUC93X_PA_GPIO) -#define NUC93X_SZ_GPIO SZ_4K - -/* GDMA control */ - -#define NUC93X_VA_GDMA NUC93X_ADDR(NUC93X_PA_GDMA) -#define NUC93X_SZ_GDMA SZ_4K - -/* I2C hardware controller */ - -#define NUC93X_VA_I2C NUC93X_ADDR(NUC93X_PA_I2C) -#define NUC93X_SZ_I2C SZ_4K - -/* LCD controller*/ - -#define NUC93X_VA_LCD NUC93X_ADDR(NUC93X_PA_LCD) -#define NUC93X_SZ_LCD SZ_4K - -/* 2D controller*/ - -#define NUC93X_VA_GE NUC93X_ADDR(NUC93X_PA_GE) -#define NUC93X_SZ_GE SZ_4K - -/* ADC */ - -#define NUC93X_VA_ADC NUC93X_ADDR(NUC93X_PA_ADC) -#define NUC93X_SZ_ADC SZ_4K - -/* RTC */ - -#define NUC93X_VA_RTC NUC93X_ADDR(NUC93X_PA_RTC) -#define NUC93X_SZ_RTC SZ_4K - -/* Pulse Width Modulation(PWM) Registers */ - -#define NUC93X_VA_PWM NUC93X_ADDR(NUC93X_PA_PWM) -#define NUC93X_SZ_PWM SZ_4K - -/* Audio Controller controller */ - -#define NUC93X_VA_ACTL NUC93X_ADDR(NUC93X_PA_ACTL) -#define NUC93X_SZ_ACTL SZ_4K - -/* USB Device port */ - -#define NUC93X_VA_USBDEV NUC93X_ADDR(NUC93X_PA_USBDEV) -#define NUC93X_SZ_USBDEV SZ_4K - -/* USB host controller*/ -#define NUC93X_VA_USBHOST NUC93X_ADDR(NUC93X_PA_USBHOST) -#define NUC93X_SZ_USBHOST SZ_4K - -#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/regs-clock.h b/arch/arm/mach-nuc93x/include/mach/regs-clock.h deleted file mode 100644 index 5cb2954..0000000 --- a/arch/arm/mach-nuc93x/include/mach/regs-clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/regs-clock.h - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation;version 2 of the License. - * - */ - -#ifndef __ASM_ARCH_REGS_CLOCK_H -#define __ASM_ARCH_REGS_CLOCK_H - -/* Clock Control Registers */ -#define CLK_BA NUC93X_VA_CLKPWR -#define REG_CLKEN (CLK_BA + 0x00) -#define REG_CLKSEL (CLK_BA + 0x04) -#define REG_CLKDIV (CLK_BA + 0x08) -#define REG_PLLCON0 (CLK_BA + 0x0C) -#define REG_PLLCON1 (CLK_BA + 0x10) -#define REG_PMCON (CLK_BA + 0x14) -#define REG_IRQWAKECON (CLK_BA + 0x18) -#define REG_IRQWAKEFLAG (CLK_BA + 0x1C) -#define REG_IPSRST (CLK_BA + 0x20) -#define REG_CLKEN1 (CLK_BA + 0x24) -#define REG_CLKDIV1 (CLK_BA + 0x28) - -/* Define PLL freq setting */ -#define PLL_DISABLE 0x12B63 -#define PLL_66MHZ 0x2B63 -#define PLL_100MHZ 0x4F64 -#define PLL_120MHZ 0x4F63 -#define PLL_166MHZ 0x4124 -#define PLL_200MHZ 0x4F24 - -/* Define AHB:CPUFREQ ratio */ -#define AHB_CPUCLK_1_1 0x00 -#define AHB_CPUCLK_1_2 0x01 -#define AHB_CPUCLK_1_4 0x02 -#define AHB_CPUCLK_1_8 0x03 - -/* Define APB:AHB ratio */ -#define APB_AHB_1_2 0x01 -#define APB_AHB_1_4 0x02 -#define APB_AHB_1_8 0x03 - -/* Define clock skew */ -#define DEFAULTSKEW 0x48 - -#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/regs-ebi.h b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h deleted file mode 100644 index 3c72550..0000000 --- a/arch/arm/mach-nuc93x/include/mach/regs-ebi.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/regs-ebi.h - * - * Copyright (c) 2009 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation;version 2 of the License. - * - */ - -#ifndef __ASM_ARCH_REGS_EBI_H -#define __ASM_ARCH_REGS_EBI_H - -/* EBI Control Registers */ - -#define EBI_BA NUC93X_VA_EBI -#define REG_EBICON (EBI_BA + 0x00) -#define REG_ROMCON (EBI_BA + 0x04) -#define REG_SDCONF0 (EBI_BA + 0x08) -#define REG_SDCONF1 (EBI_BA + 0x0C) -#define REG_SDTIME0 (EBI_BA + 0x10) -#define REG_SDTIME1 (EBI_BA + 0x14) -#define REG_EXT0CON (EBI_BA + 0x18) -#define REG_EXT1CON (EBI_BA + 0x1C) -#define REG_EXT2CON (EBI_BA + 0x20) -#define REG_EXT3CON (EBI_BA + 0x24) -#define REG_EXT4CON (EBI_BA + 0x28) -#define REG_CKSKEW (EBI_BA + 0x2C) - -#endif /* __ASM_ARCH_REGS_EBI_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/regs-irq.h b/arch/arm/mach-nuc93x/include/mach/regs-irq.h deleted file mode 100644 index 2302159..0000000 --- a/arch/arm/mach-nuc93x/include/mach/regs-irq.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/regs-irq.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef ___ASM_ARCH_REGS_IRQ_H -#define ___ASM_ARCH_REGS_IRQ_H - -/* Advance Interrupt Controller (AIC) Registers */ - -#define AIC_BA NUC93X_VA_IRQ - -#define REG_AIC_IRQSC (AIC_BA+0x80) -#define REG_AIC_GEN (AIC_BA+0x84) -#define REG_AIC_GASR (AIC_BA+0x88) -#define REG_AIC_GSCR (AIC_BA+0x8C) -#define REG_AIC_IRSR (AIC_BA+0x100) -#define REG_AIC_IASR (AIC_BA+0x104) -#define REG_AIC_ISR (AIC_BA+0x108) -#define REG_AIC_IPER (AIC_BA+0x10C) -#define REG_AIC_ISNR (AIC_BA+0x110) -#define REG_AIC_IMR (AIC_BA+0x114) -#define REG_AIC_OISR (AIC_BA+0x118) -#define REG_AIC_MECR (AIC_BA+0x120) -#define REG_AIC_MDCR (AIC_BA+0x124) -#define REG_AIC_SSCR (AIC_BA+0x128) -#define REG_AIC_SCCR (AIC_BA+0x12C) -#define REG_AIC_EOSCR (AIC_BA+0x130) -#define AIC_IPER (0x10C) -#define AIC_ISNR (0x110) - -#endif /* ___ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/regs-serial.h b/arch/arm/mach-nuc93x/include/mach/regs-serial.h deleted file mode 100644 index 767a047..0000000 --- a/arch/arm/mach-nuc93x/include/mach/regs-serial.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/regs-serial.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARM_REGS_SERIAL_H -#define __ASM_ARM_REGS_SERIAL_H - -#define UART0_BA NUC93X_VA_UART -#define UART1_BA (NUC93X_VA_UART+0x100) - -#define UART0_PA NUC93X_PA_UART -#define UART1_PA (NUC93X_PA_UART+0x100) - - -#ifndef __ASSEMBLY__ - -struct nuc93x_uart_clksrc { - const char *name; - unsigned int divisor; - unsigned int min_baud; - unsigned int max_baud; -}; - -struct nuc93x_uartcfg { - unsigned char hwport; - unsigned char unused; - unsigned short flags; - unsigned long uart_flags; - - unsigned long ucon; - unsigned long ulcon; - unsigned long ufcon; - - struct nuc93x_uart_clksrc *clocks; - unsigned int clocks_size; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARM_REGS_SERIAL_H */ - diff --git a/arch/arm/mach-nuc93x/include/mach/regs-timer.h b/arch/arm/mach-nuc93x/include/mach/regs-timer.h deleted file mode 100644 index 394be96..0000000 --- a/arch/arm/mach-nuc93x/include/mach/regs-timer.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/regs-timer.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_REGS_TIMER_H -#define __ASM_ARCH_REGS_TIMER_H - -/* Timer Registers */ - -#define TMR_BA NUC93X_VA_TIMER -#define REG_TCSR0 (TMR_BA+0x00) -#define REG_TICR0 (TMR_BA+0x08) -#define REG_TDR0 (TMR_BA+0x10) -#define REG_TISR (TMR_BA+0x18) -#define REG_WTCR (TMR_BA+0x1C) - -#endif /* __ASM_ARCH_REGS_TIMER_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/system.h b/arch/arm/mach-nuc93x/include/mach/system.h deleted file mode 100644 index d26bd9a..0000000 --- a/arch/arm/mach-nuc93x/include/mach/system.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/machnuc93x/include/mach/system.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/system.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#include <asm/proc-fns.h> - -static void arch_idle(void) -{ -} - -static void arch_reset(char mode, const char *cmd) -{ - cpu_reset(0); -} - diff --git a/arch/arm/mach-nuc93x/include/mach/timex.h b/arch/arm/mach-nuc93x/include/mach/timex.h deleted file mode 100644 index 0c719cc..0000000 --- a/arch/arm/mach-nuc93x/include/mach/timex.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/timex.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/timex.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* CLOCK_TICK_RATE Now, I don't use it. */ - -#define CLOCK_TICK_RATE 27000000 - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h deleted file mode 100644 index 381cb9b..0000000 --- a/arch/arm/mach-nuc93x/include/mach/uncompress.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/uncompress.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/uncompress.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -/* Defines for UART registers */ - -#include <mach/regs-serial.h> -#include <mach/map.h> -#include <linux/serial_reg.h> - -#define arch_decomp_wdog() - -#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) -static u32 * const uart_base = (u32 *)UART0_PA; - -static void putc(int ch) -{ - /* Check THRE and TEMT bits before we transmit the character. - */ - while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) - barrier(); - - *uart_base = ch; -} - -static inline void flush(void) -{ -} - -static void arch_decomp_setup(void) -{ -} - -#endif/* __ASM_NUC93X_UNCOMPRESS_H */ diff --git a/arch/arm/mach-nuc93x/include/mach/vmalloc.h b/arch/arm/mach-nuc93x/include/mach/vmalloc.h deleted file mode 100644 index 7d11a5f..0000000 --- a/arch/arm/mach-nuc93x/include/mach/vmalloc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * arch/arm/mach-nuc93x/include/mach/vmalloc.h - * - * Copyright (c) 2008 Nuvoton technology corporation - * All rights reserved. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END 0xE0000000UL - -#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c deleted file mode 100644 index aa279f2..0000000 --- a/arch/arm/mach-nuc93x/irq.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * linux/arch/arm/mach-nuc93x/irq.c - * - * Copyright (c) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation;version 2 of the License. - * - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/ptrace.h> -#include <linux/sysdev.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/regs-irq.h> - -static void nuc93x_irq_mask(struct irq_data *d) -{ - __raw_writel(1 << d->irq, REG_AIC_MDCR); -} - -/* - * By the w90p910 spec,any irq,only write 1 - * to REG_AIC_EOSCR for ACK - */ - -static void nuc93x_irq_ack(struct irq_data *d) -{ - __raw_writel(0x01, REG_AIC_EOSCR); -} - -static void nuc93x_irq_unmask(struct irq_data *d) -{ - __raw_writel(1 << d->irq, REG_AIC_MECR); - -} - -static struct irq_chip nuc93x_irq_chip = { - .irq_ack = nuc93x_irq_ack, - .irq_mask = nuc93x_irq_mask, - .irq_unmask = nuc93x_irq_unmask, -}; - -void __init nuc93x_init_irq(void) -{ - int irqno; - - __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); - - for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { - irq_set_chip_and_handler(irqno, &nuc93x_irq_chip, - handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } -} diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c deleted file mode 100644 index 1f741b1..0000000 --- a/arch/arm/mach-nuc93x/mach-nuc932evb.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * linux/arch/arm/mach-w90x900/mach-nuc910evb.c - * - * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche - * - * Copyright (C) 2008 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation;version 2 of the License. - * - */ - -#include <linux/platform_device.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach-types.h> -#include <mach/map.h> - -#include "nuc932.h" - -static void __init nuc932evb_map_io(void) -{ - nuc932_map_io(); - nuc932_init_clocks(); - nuc932_init_uartclk(); -} - -static void __init nuc932evb_init(void) -{ - nuc932_board_init(); -} - -MACHINE_START(NUC932EVB, "NUC932EVB") - /* Maintainer: Wan ZongShun */ - .map_io = nuc932evb_map_io, - .init_irq = nuc93x_init_irq, - .init_machine = nuc932evb_init, - .timer = &nuc93x_timer, -MACHINE_END diff --git a/arch/arm/mach-nuc93x/nuc932.c b/arch/arm/mach-nuc93x/nuc932.c deleted file mode 100644 index 3966ead..0000000 --- a/arch/arm/mach-nuc93x/nuc932.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * linux/arch/arm/mach-nuc93x/nuc932.c - * - * Copyright (c) 2009 Nuvoton corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * NUC932 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation;version 2 of the License. - * - */ - -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/err.h> - -#include <asm/mach/map.h> -#include <mach/hardware.h> - -#include "cpu.h" -#include "clock.h" - -/* define specific CPU platform device */ - -static struct platform_device *nuc932_dev[] __initdata = { -}; - -/* define specific CPU platform io map */ - -static struct map_desc nuc932evb_iodesc[] __initdata = { -}; - -/*Init NUC932 evb io*/ - -void __init nuc932_map_io(void) -{ - nuc93x_map_io(nuc932evb_iodesc, ARRAY_SIZE(nuc932evb_iodesc)); -} - -/*Init NUC932 clock*/ - -void __init nuc932_init_clocks(void) -{ - nuc93x_init_clocks(); -} - -/*enable NUC932 uart clock*/ - -void __init nuc932_init_uartclk(void) -{ - struct clk *ck_uart = clk_get(NULL, "uart"); - BUG_ON(IS_ERR(ck_uart)); - - clk_enable(ck_uart); -} - -/*Init NUC932 board info*/ - -void __init nuc932_board_init(void) -{ - nuc93x_board_init(nuc932_dev, ARRAY_SIZE(nuc932_dev)); -} diff --git a/arch/arm/mach-nuc93x/nuc932.h b/arch/arm/mach-nuc93x/nuc932.h deleted file mode 100644 index 9a66edd..0000000 --- a/arch/arm/mach-nuc93x/nuc932.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-nuc93x/nuc932.h - * - * Copyright (c) 2008 Nuvoton corporation - * - * Header file for NUC93x CPU support - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -struct map_desc; -struct sys_timer; - -/* core initialisation functions */ - -extern void nuc93x_init_irq(void); -extern struct sys_timer nuc93x_timer; - -/* extern file from nuc932.c */ - -extern void nuc932_board_init(void); -extern void nuc932_init_clocks(void); -extern void nuc932_map_io(void); -extern void nuc932_init_uartclk(void); diff --git a/arch/arm/mach-nuc93x/time.c b/arch/arm/mach-nuc93x/time.c deleted file mode 100644 index 2f90f9d..0000000 --- a/arch/arm/mach-nuc93x/time.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * linux/arch/arm/mach-nuc93x/time.c - * - * Copyright (c) 2009 Nuvoton technology corporation. - * - * Wan ZongShun <mcuos.com@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/leds.h> - -#include <asm/mach-types.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> - -#include <mach/system.h> -#include <mach/map.h> -#include <mach/regs-timer.h> - -#define RESETINT 0x01 -#define PERIOD (0x01 << 27) -#define ONESHOT (0x00 << 27) -#define COUNTEN (0x01 << 30) -#define INTEN (0x01 << 29) - -#define TICKS_PER_SEC 100 -#define PRESCALE 0x63 /* Divider = prescale + 1 */ - -unsigned int timer0_load; - -static unsigned long nuc93x_gettimeoffset(void) -{ - return 0; -} - -/*IRQ handler for the timer*/ - -static irqreturn_t nuc93x_timer_interrupt(int irq, void *dev_id) -{ - timer_tick(); - __raw_writel(0x01, REG_TISR); /* clear TIF0 */ - return IRQ_HANDLED; -} - -static struct irqaction nuc93x_timer_irq = { - .name = "nuc93x Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = nuc93x_timer_interrupt, -}; - -/*Set up timer reg.*/ - -static void nuc93x_timer_setup(void) -{ - struct clk *ck_ext = clk_get(NULL, "ext"); - struct clk *ck_timer = clk_get(NULL, "timer"); - unsigned int rate, val = 0; - - BUG_ON(IS_ERR(ck_ext) || IS_ERR(ck_timer)); - - clk_enable(ck_timer); - rate = clk_get_rate(ck_ext); - clk_put(ck_ext); - rate = rate / (PRESCALE + 0x01); - - /* set a known state */ - __raw_writel(0x00, REG_TCSR0); - __raw_writel(RESETINT, REG_TISR); - - timer0_load = (rate / TICKS_PER_SEC); - __raw_writel(timer0_load, REG_TICR0); - - val |= (PERIOD | COUNTEN | INTEN | PRESCALE);; - __raw_writel(val, REG_TCSR0); - -} - -static void __init nuc93x_timer_init(void) -{ - nuc93x_timer_setup(); - setup_irq(IRQ_TIMER0, &nuc93x_timer_irq); -} - -struct sys_timer nuc93x_timer = { - .init = nuc93x_timer_init, - .offset = nuc93x_gettimeoffset, - .resume = nuc93x_timer_setup -}; diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 5b114d1..11c85cd2 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o -obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o +obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o diff --git a/arch/arm/mach-omap1/Makefile.boot b/arch/arm/mach-omap1/Makefile.boot index 292d56c..13bda8d 100644 --- a/arch/arm/mach-omap1/Makefile.boot +++ b/arch/arm/mach-omap1/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x10008000 + zreladdr-y += 0x10008000 params_phys-y := 0x10000100 initrd_phys-y := 0x10800000 diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index ab7395d..91f9abb 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -31,6 +31,7 @@ static int dsp_use; static struct clk *api_clk; static struct clk *dsp_clk; +static struct platform_device **omap_mcbsp_devices; static void omap1_mcbsp_request(unsigned int id) { @@ -78,6 +79,17 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = { .free = omap1_mcbsp_free, }; +#define OMAP7XX_MCBSP1_BASE 0xfffb1000 +#define OMAP7XX_MCBSP2_BASE 0xfffb1800 + +#define OMAP1510_MCBSP1_BASE 0xe1011800 +#define OMAP1510_MCBSP2_BASE 0xfffb1000 +#define OMAP1510_MCBSP3_BASE 0xe1017000 + +#define OMAP1610_MCBSP1_BASE 0xe1011800 +#define OMAP1610_MCBSP2_BASE 0xfffb1000 +#define OMAP1610_MCBSP3_BASE 0xe1017000 + #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) struct resource omap7xx_mcbsp_res[][6] = { { @@ -369,6 +381,39 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { #define OMAP16XX_MCBSP_COUNT 0 #endif +static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, + struct omap_mcbsp_platform_data *config, int size) +{ + int i; + + omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *), + GFP_KERNEL); + if (!omap_mcbsp_devices) { + printk(KERN_ERR "Could not register McBSP devices\n"); + return; + } + + for (i = 0; i < size; i++) { + struct platform_device *new_mcbsp; + int ret; + + new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1); + if (!new_mcbsp) + continue; + platform_device_add_resources(new_mcbsp, &res[i * res_count], + res_count); + config[i].reg_size = 2; + config[i].reg_step = 2; + new_mcbsp->dev.platform_data = &config[i]; + ret = platform_device_add(new_mcbsp); + if (ret) { + platform_device_put(new_mcbsp); + continue; + } + omap_mcbsp_devices[i] = new_mcbsp; + } +} + static int __init omap1_mcbsp_init(void) { if (!cpu_class_is_omap1()) diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c index 943072d..7868e75 100644 --- a/arch/arm/mach-omap1/pm_bus.c +++ b/arch/arm/mach-omap1/pm_bus.c @@ -13,6 +13,7 @@ #include <linux/kernel.h> #include <linux/io.h> #include <linux/pm_runtime.h> +#include <linux/pm_clock.h> #include <linux/platform_device.h> #include <linux/mutex.h> #include <linux/clk.h> diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c new file mode 100644 index 0000000..6e90665 --- /dev/null +++ b/arch/arm/mach-omap1/timer.c @@ -0,0 +1,173 @@ +/** + * OMAP1 Dual-Mode Timers - platform device registration + * + * Contains first level initialization routines which internally + * generates timer device information and registers with linux + * device model. It also has low level function to chnage the timer + * input clock source. + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Tarun Kanti DebBarma <tarun.kanti@ti.com> + * Thara Gopinath <thara@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> + +#include <plat/dmtimer.h> + +#define OMAP1610_GPTIMER1_BASE 0xfffb1400 +#define OMAP1610_GPTIMER2_BASE 0xfffb1c00 +#define OMAP1610_GPTIMER3_BASE 0xfffb2400 +#define OMAP1610_GPTIMER4_BASE 0xfffb2c00 +#define OMAP1610_GPTIMER5_BASE 0xfffb3400 +#define OMAP1610_GPTIMER6_BASE 0xfffb3c00 +#define OMAP1610_GPTIMER7_BASE 0xfffb7400 +#define OMAP1610_GPTIMER8_BASE 0xfffbd400 + +#define OMAP1_DM_TIMER_COUNT 8 + +static int omap1_dm_timer_set_src(struct platform_device *pdev, + int source) +{ + int n = (pdev->id - 1) << 1; + u32 l; + + l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); + l |= source << n; + __raw_writel(l, MOD_CONF_CTRL_1); + + return 0; +} + + +int __init omap1_dm_timer_init(void) +{ + int i; + int ret; + struct dmtimer_platform_data *pdata; + struct platform_device *pdev; + + if (!cpu_is_omap16xx()) + return 0; + + for (i = 1; i <= OMAP1_DM_TIMER_COUNT; i++) { + struct resource res[2]; + u32 base, irq; + + switch (i) { + case 1: + base = OMAP1610_GPTIMER1_BASE; + irq = INT_1610_GPTIMER1; + break; + case 2: + base = OMAP1610_GPTIMER2_BASE; + irq = INT_1610_GPTIMER2; + break; + case 3: + base = OMAP1610_GPTIMER3_BASE; + irq = INT_1610_GPTIMER3; + break; + case 4: + base = OMAP1610_GPTIMER4_BASE; + irq = INT_1610_GPTIMER4; + break; + case 5: + base = OMAP1610_GPTIMER5_BASE; + irq = INT_1610_GPTIMER5; + break; + case 6: + base = OMAP1610_GPTIMER6_BASE; + irq = INT_1610_GPTIMER6; + break; + case 7: + base = OMAP1610_GPTIMER7_BASE; + irq = INT_1610_GPTIMER7; + break; + case 8: + base = OMAP1610_GPTIMER8_BASE; + irq = INT_1610_GPTIMER8; + break; + default: + /* + * not supposed to reach here. + * this is to remove warning. + */ + return -EINVAL; + } + + pdev = platform_device_alloc("omap_timer", i); + if (!pdev) { + pr_err("%s: Failed to device alloc for dmtimer%d\n", + __func__, i); + return -ENOMEM; + } + + memset(res, 0, 2 * sizeof(struct resource)); + res[0].start = base; + res[0].end = base + 0x46; + res[0].flags = IORESOURCE_MEM; + res[1].start = irq; + res[1].end = irq; + res[1].flags = IORESOURCE_IRQ; + ret = platform_device_add_resources(pdev, res, + ARRAY_SIZE(res)); + if (ret) { + dev_err(&pdev->dev, "%s: Failed to add resources.\n", + __func__); + goto err_free_pdev; + } + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + dev_err(&pdev->dev, "%s: Failed to allocate pdata.\n", + __func__); + ret = -ENOMEM; + goto err_free_pdata; + } + + pdata->set_timer_src = omap1_dm_timer_set_src; + pdata->needs_manual_reset = 1; + + ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (ret) { + dev_err(&pdev->dev, "%s: Failed to add platform data.\n", + __func__); + goto err_free_pdata; + } + + ret = platform_device_add(pdev); + if (ret) { + dev_err(&pdev->dev, "%s: Failed to add platform device.\n", + __func__); + goto err_free_pdata; + } + + dev_dbg(&pdev->dev, " Registered.\n"); + } + + return 0; + +err_free_pdata: + kfree(pdata); + +err_free_pdev: + platform_device_unregister(pdev); + + return ret; +} +arch_initcall(omap1_dm_timer_init); diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 57b66d5..89bfb49 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -36,6 +36,7 @@ config ARCH_OMAP3 select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 select ARCH_HAS_OPP select PM_OPP if PM + select ARM_CPU_SUSPEND if PM config ARCH_OMAP4 bool "TI OMAP4" @@ -50,6 +51,7 @@ config ARCH_OMAP4 select ARCH_HAS_OPP select PM_OPP if PM select USB_ARCH_HAS_EHCI + select ARM_CPU_SUSPEND if PM comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index f343365..69ab1c0 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -89,14 +89,13 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \ vp44xx_data.o # OMAP voltage domains -ifeq ($(CONFIG_PM),y) -voltagedomain-common := voltage.o -obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) +voltagedomain-common := voltage.o vc.o vp.o +obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \ + voltagedomains2xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \ voltagedomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \ voltagedomains44xx_data.o -endif # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o @@ -116,9 +115,12 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \ obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ clockdomain2xxx_3xxx.o \ clockdomains2xxx_3xxx_data.o +obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o +obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ clockdomain2xxx_3xxx.o \ - clockdomains2xxx_3xxx_data.o + clockdomains2xxx_3xxx_data.o \ + clockdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ clockdomain44xx.o \ clockdomains44xx_data.o @@ -185,81 +187,67 @@ endif # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o -obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \ - hsmmc.o +obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o -obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ - hsmmc.o -obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ - board-flash.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o \ - hsmmc.o -obj-$(CONFIG_MACH_OVERO) += board-overo.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ - hsmmc.o \ - board-flash.o +obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o +obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o +obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o +obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o +obj-$(CONFIG_MACH_OVERO) += board-overo.o +obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o +obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o +obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \ - sdram-nokia.o \ - hsmmc.o + sdram-nokia.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ sdram-nokia.o \ board-rx51-peripherals.o \ - board-rx51-video.o \ - hsmmc.o + board-rx51-video.o obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \ board-zoom-peripherals.o \ board-zoom-display.o \ - board-flash.o \ - hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \ board-zoom-peripherals.o \ board-zoom-display.o \ - board-flash.o \ - hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ board-zoom-peripherals.o \ - board-zoom-display.o \ - board-flash.o \ - hsmmc.o -obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ - hsmmc.o + board-zoom-display.o +obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o -obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ - hsmmc.o -obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ - hsmmc.o \ - omap_phy_internal.o -obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ - hsmmc.o \ - omap_phy_internal.o - -obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \ - omap_phy_internal.o \ +obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o +obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o +obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o +obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o + +obj-$(CONFIG_MACH_PCM049) += board-omap4pcm049.o + +obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o -obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ - hsmmc.o +obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o + # Platform specific device init code + +omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o +omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o +obj-y += $(omap-flash-y) $(omap-flash-m) + +omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o +obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) + + usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o obj-y += $(usbfs-m) $(usbfs-y) obj-y += usb-musb.o +obj-y += omap_phy_internal.o + obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o obj-y += usb-host.o diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot index 565aff7..b03e562 100644 --- a/arch/arm/mach-omap2/Makefile.boot +++ b/arch/arm/mach-omap2/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x80008000 + zreladdr-y += 0x80008000 params_phys-y := 0x80000100 initrd_phys-y := 0x80800000 diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 195157d..d704f0a 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -39,6 +39,9 @@ #include <plat/usb.h> #include <plat/gpmc-smc91x.h> +#include <video/omapdss.h> +#include <video/omap-panel-generic-dpi.h> + #include "mux.h" #include "hsmmc.h" #include "common-board-devices.h" @@ -99,20 +102,72 @@ static struct platform_device sdp2430_flash_device = { .resource = &sdp2430_flash_resource, }; -static struct platform_device sdp2430_lcd_device = { - .name = "sdp2430_lcd", - .id = -1, -}; - static struct platform_device *sdp2430_devices[] __initdata = { &sdp2430_flash_device, +}; + +/* LCD */ +#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91 +#define SDP2430_LCD_PANEL_ENABLE_GPIO 154 + +static int sdp2430_panel_enable_lcd(struct omap_dss_device *dssdev) +{ + gpio_direction_output(SDP2430_LCD_PANEL_ENABLE_GPIO, 1); + gpio_direction_output(SDP2430_LCD_PANEL_BACKLIGHT_GPIO, 1); + + return 0; +} + +static void sdp2430_panel_disable_lcd(struct omap_dss_device *dssdev) +{ + gpio_direction_output(SDP2430_LCD_PANEL_ENABLE_GPIO, 0); + gpio_direction_output(SDP2430_LCD_PANEL_BACKLIGHT_GPIO, 0); +} + +static struct panel_generic_dpi_data sdp2430_panel_data = { + .name = "nec_nl2432dr22-11b", + .platform_enable = sdp2430_panel_enable_lcd, + .platform_disable = sdp2430_panel_disable_lcd, +}; + +static struct omap_dss_device sdp2430_lcd_device = { + .name = "lcd", + .driver_name = "generic_dpi_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 16, + .data = &sdp2430_panel_data, +}; + +static struct omap_dss_device *sdp2430_dss_devices[] = { &sdp2430_lcd_device, }; -static struct omap_lcd_config sdp2430_lcd_config __initdata = { - .ctrl_name = "internal", +static struct omap_dss_board_info sdp2430_dss_data = { + .num_devices = ARRAY_SIZE(sdp2430_dss_devices), + .devices = sdp2430_dss_devices, + .default_device = &sdp2430_lcd_device, }; +static void __init sdp2430_display_init(void) +{ + int r; + + static struct gpio gpios[] __initdata = { + { SDP2430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, + "LCD reset" }, + { SDP2430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, + "LCD Backlight" }, + }; + + r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); + if (r) { + pr_err("Cannot request LCD GPIOs, error %d\n", r); + return; + } + + omap_display_init(&sdp2430_dss_data); +} + #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) static struct omap_smc91x_platform_data board_smc91x_data = { @@ -137,16 +192,6 @@ static inline void board_smc91x_init(void) #endif -static struct omap_board_config_kernel sdp2430_config[] __initdata = { - {OMAP_TAG_LCD, &sdp2430_lcd_config}, -}; - -static void __init omap_2430sdp_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = { REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), }; @@ -193,7 +238,8 @@ static int __init omap2430_i2c_init(void) { omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, ARRAY_SIZE(sdp2430_i2c1_boardinfo)); - omap2_pmic_init("twl4030", &sdp2430_twldata); + omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ, + &sdp2430_twldata); return 0; } @@ -228,13 +274,11 @@ static void __init omap_2430sdp_init(void) { omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); - omap_board_config = sdp2430_config; - omap_board_config_size = ARRAY_SIZE(sdp2430_config); - omap2430_i2c_init(); platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); omap_serial_init(); + omap_sdrc_init(NULL, NULL); omap2_hsmmc_init(mmc); omap2_usbfs_init(&sdp2430_usb_config); @@ -246,20 +290,16 @@ static void __init omap_2430sdp_init(void) /* Turn off secondary LCD backlight */ gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW, "Secondary LCD backlight"); -} -static void __init omap_2430sdp_map_io(void) -{ - omap2_set_globals_243x(); - omap243x_map_common_io(); + sdp2430_display_init(); } MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") /* Maintainer: Syed Khasim - Texas Instruments Inc */ .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = omap_2430sdp_map_io, - .init_early = omap_2430sdp_init_early, + .map_io = omap243x_map_io, + .init_early = omap2430_init_early, .init_irq = omap2_init_irq, .init_machine = omap_2430sdp_init, .timer = &omap2_timer, diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 2430531..77142c1 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -37,7 +37,7 @@ #include <plat/dma.h> #include <plat/gpmc.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include <plat/gpmc-smc91x.h> @@ -186,8 +186,7 @@ static struct omap_dss_device sdp3430_lcd_device = { .platform_disable = sdp3430_panel_disable_lcd, }; -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = sdp3430_panel_enable_dvi, .platform_disable = sdp3430_panel_disable_dvi, }; @@ -195,7 +194,7 @@ static struct panel_generic_dpi_data dvi_panel = { static struct omap_dss_device sdp3430_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -225,12 +224,6 @@ static struct omap_dss_board_info sdp3430_dss_data = { static struct omap_board_config_kernel sdp3430_config[] __initdata = { }; -static void __init omap_3430sdp_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); -} - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -719,6 +712,7 @@ static void __init omap_3430sdp_init(void) gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1; omap_ads7846_init(1, gpio_pendown, 310, NULL); board_serial_init(); + omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL); usb_musb_init(NULL); board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); @@ -732,7 +726,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = omap_3430sdp_init_early, + .init_early = omap3430_init_early, .init_irq = omap3_init_irq, .init_machine = omap_3430sdp_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 8b5b5aa..f552305 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -70,13 +70,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = { static struct omap_board_config_kernel sdp_config[] __initdata = { }; -static void __init omap_sdp_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, - h8mbx00u0mer0em_sdrc_params); -} - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, @@ -207,6 +200,8 @@ static void __init omap_sdp_init(void) omap_board_config = sdp_config; omap_board_config_size = ARRAY_SIZE(sdp_config); zoom_peripherals_init(); + omap_sdrc_init(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); zoom_display_init(); board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16); @@ -218,7 +213,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = omap_sdp_init_early, + .init_early = omap3630_init_early, .init_irq = omap3_init_irq, .init_machine = omap_sdp_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index be93110..5156468 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -38,6 +38,8 @@ #include <plat/mmc.h> #include <plat/omap4-keypad.h> #include <video/omapdss.h> +#include <video/omap-panel-nokia-dsi.h> +#include <video/omap-panel-picodlp.h> #include <linux/wl12xx.h> #include "mux.h" @@ -52,6 +54,8 @@ #define OMAP4_SFH7741_ENABLE_GPIO 188 #define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ +#define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */ +#define DLP_POWER_ON_GPIO 40 #define GPIO_WIFI_PMENA 54 #define GPIO_WIFI_IRQ 53 @@ -129,7 +133,7 @@ static const int sdp4430_keymap[] = { KEY(7, 6, KEY_OK), KEY(7, 7, KEY_DOWN), }; -static struct omap_device_pad keypad_pads[] __initdata = { +static struct omap_device_pad keypad_pads[] = { { .name = "kpd_col1.kpd_col1", .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, }, @@ -340,11 +344,6 @@ static int __init omap_ethernet_init(void) return status; } -static struct platform_device sdp4430_lcd_device = { - .name = "sdp4430_lcd", - .id = -1, -}; - static struct regulator_consumer_supply sdp4430_vbat_supply[] = { REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"), REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"), @@ -374,27 +373,12 @@ static struct platform_device sdp4430_vbat = { }; static struct platform_device *sdp4430_devices[] __initdata = { - &sdp4430_lcd_device, &sdp4430_gpio_keys_device, &sdp4430_leds_gpio, &sdp4430_leds_pwm, &sdp4430_vbat, }; -static struct omap_lcd_config sdp4430_lcd_config __initdata = { - .ctrl_name = "internal", -}; - -static struct omap_board_config_kernel sdp4430_config[] __initdata = { - { OMAP_TAG_LCD, &sdp4430_lcd_config }, -}; - -static void __init omap_4430sdp_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, .mode = MUSB_OTG, @@ -648,37 +632,202 @@ static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) gpio_free(HDMI_GPIO_HPD); } -static struct omap_dss_device sdp4430_hdmi_device = { - .name = "hdmi", - .driver_name = "hdmi_panel", - .type = OMAP_DISPLAY_TYPE_HDMI, - .clocks = { - .dispc = { +static struct nokia_dsi_panel_data dsi1_panel = { + .name = "taal", + .reset_gpio = 102, + .use_ext_te = false, + .ext_te_gpio = 101, + .esd_interval = 0, +}; + +static struct omap_dss_device sdp4430_lcd_device = { + .name = "lcd", + .driver_name = "taal", + .type = OMAP_DISPLAY_TYPE_DSI, + .data = &dsi1_panel, + .phy.dsi = { + .clk_lane = 1, + .clk_pol = 0, + .data1_lane = 2, + .data1_pol = 0, + .data2_lane = 3, + .data2_pol = 0, + + .module = 0, + }, + + .clocks = { + .dispc = { + .channel = { + /* Logic Clock = 172.8 MHz */ + .lck_div = 1, + /* Pixel Clock = 34.56 MHz */ + .pck_div = 5, + .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, + }, + .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, + }, + + .dsi = { + .regn = 16, /* Fint = 2.4 MHz */ + .regm = 180, /* DDR Clock = 216 MHz */ + .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */ + .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */ + + .lp_clk_div = 10, /* LP Clock = 8.64 MHz */ + .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, + }, + }, + .channel = OMAP_DSS_CHANNEL_LCD, +}; + +static struct nokia_dsi_panel_data dsi2_panel = { + .name = "taal", + .reset_gpio = 104, + .use_ext_te = false, + .ext_te_gpio = 103, + .esd_interval = 0, +}; + +static struct omap_dss_device sdp4430_lcd2_device = { + .name = "lcd2", + .driver_name = "taal", + .type = OMAP_DISPLAY_TYPE_DSI, + .data = &dsi2_panel, + .phy.dsi = { + .clk_lane = 1, + .clk_pol = 0, + .data1_lane = 2, + .data1_pol = 0, + .data2_lane = 3, + .data2_pol = 0, + + .module = 1, + }, + + .clocks = { + .dispc = { + .channel = { + /* Logic Clock = 172.8 MHz */ + .lck_div = 1, + /* Pixel Clock = 34.56 MHz */ + .pck_div = 5, + .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, + }, .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, }, - .hdmi = { - .regn = 15, - .regm2 = 1, + + .dsi = { + .regn = 16, /* Fint = 2.4 MHz */ + .regm = 180, /* DDR Clock = 216 MHz */ + .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */ + .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */ + + .lp_clk_div = 10, /* LP Clock = 8.64 MHz */ + .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, }, }, + .channel = OMAP_DSS_CHANNEL_LCD2, +}; + +static void sdp4430_lcd_init(void) +{ + int r; + + r = gpio_request_one(dsi1_panel.reset_gpio, GPIOF_DIR_OUT, + "lcd1_reset_gpio"); + if (r) + pr_err("%s: Could not get lcd1_reset_gpio\n", __func__); + + r = gpio_request_one(dsi2_panel.reset_gpio, GPIOF_DIR_OUT, + "lcd2_reset_gpio"); + if (r) + pr_err("%s: Could not get lcd2_reset_gpio\n", __func__); +} + +static struct omap_dss_device sdp4430_hdmi_device = { + .name = "hdmi", + .driver_name = "hdmi_panel", + .type = OMAP_DISPLAY_TYPE_HDMI, .platform_enable = sdp4430_panel_enable_hdmi, .platform_disable = sdp4430_panel_disable_hdmi, .channel = OMAP_DSS_CHANNEL_DIGIT, }; +static struct picodlp_panel_data sdp4430_picodlp_pdata = { + .picodlp_adapter_id = 2, + .emu_done_gpio = 44, + .pwrgood_gpio = 45, +}; + +static void sdp4430_picodlp_init(void) +{ + int r; + const struct gpio picodlp_gpios[] = { + {DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW, + "DLP POWER ON"}, + {sdp4430_picodlp_pdata.emu_done_gpio, GPIOF_IN, + "DLP EMU DONE"}, + {sdp4430_picodlp_pdata.pwrgood_gpio, GPIOF_OUT_INIT_LOW, + "DLP PWRGOOD"}, + }; + + r = gpio_request_array(picodlp_gpios, ARRAY_SIZE(picodlp_gpios)); + if (r) + pr_err("Cannot request PicoDLP GPIOs, error %d\n", r); +} + +static int sdp4430_panel_enable_picodlp(struct omap_dss_device *dssdev) +{ + gpio_set_value(DISPLAY_SEL_GPIO, 0); + gpio_set_value(DLP_POWER_ON_GPIO, 1); + + return 0; +} + +static void sdp4430_panel_disable_picodlp(struct omap_dss_device *dssdev) +{ + gpio_set_value(DLP_POWER_ON_GPIO, 0); + gpio_set_value(DISPLAY_SEL_GPIO, 1); +} + +static struct omap_dss_device sdp4430_picodlp_device = { + .name = "picodlp", + .driver_name = "picodlp_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 24, + .channel = OMAP_DSS_CHANNEL_LCD2, + .platform_enable = sdp4430_panel_enable_picodlp, + .platform_disable = sdp4430_panel_disable_picodlp, + .data = &sdp4430_picodlp_pdata, +}; + static struct omap_dss_device *sdp4430_dss_devices[] = { + &sdp4430_lcd_device, + &sdp4430_lcd2_device, &sdp4430_hdmi_device, + &sdp4430_picodlp_device, }; static struct omap_dss_board_info sdp4430_dss_data = { .num_devices = ARRAY_SIZE(sdp4430_dss_devices), .devices = sdp4430_dss_devices, - .default_device = &sdp4430_hdmi_device, + .default_device = &sdp4430_lcd_device, }; -void omap_4430sdp_display_init(void) +static void omap_4430sdp_display_init(void) { + int r; + + /* Enable LCD2 by default (instead of Pico DLP) */ + r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH, + "display_sel"); + if (r) + pr_err("%s: Could not get display_sel GPIO\n", __func__); + + sdp4430_lcd_init(); sdp4430_hdmi_mux_init(); + sdp4430_picodlp_init(); omap_display_init(&sdp4430_dss_data); } @@ -802,13 +951,11 @@ static void __init omap_4430sdp_init(void) package = OMAP_PACKAGE_CBL; omap4_mux_init(board_mux, NULL, package); - omap_board_config = sdp4430_config; - omap_board_config_size = ARRAY_SIZE(sdp4430_config); - omap4_i2c_init(); omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); board_serial_init(); + omap_sdrc_init(NULL, NULL); omap4_sdp4430_wifi_init(); omap4_twl6030_hsmmc_init(mmc); @@ -830,18 +977,12 @@ static void __init omap_4430sdp_init(void) omap_4430sdp_display_init(); } -static void __init omap_4430sdp_map_io(void) -{ - omap2_set_globals_443x(); - omap44xx_map_common_io(); -} - MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = omap_4430sdp_map_io, - .init_early = omap_4430sdp_init_early, + .map_io = omap4_map_io, + .init_early = omap4430_init_early, .init_irq = gic_init_irq, .init_machine = omap_4430sdp_init, .timer = &omap4_timer, diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index db110fd..7834536 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -47,12 +47,6 @@ static struct omap_board_mux board_mux[] __initdata = { }; #endif -static void __init am3517_crane_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - static struct usbhs_omap_board_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, @@ -70,6 +64,7 @@ static void __init am3517_crane_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); + omap_sdrc_init(NULL, NULL); omap_board_config = am3517_crane_config; omap_board_config_size = ARRAY_SIZE(am3517_crane_config); @@ -101,7 +96,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = am3517_crane_init_early, + .init_early = am35xx_init_early, .init_irq = omap3_init_irq, .init_machine = am3517_crane_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 1325085..d314f03 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -36,6 +36,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include "mux.h" #include "control.h" @@ -333,8 +334,7 @@ static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev) dvi_enabled = 0; } -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = am3517_evm_panel_enable_dvi, .platform_disable = am3517_evm_panel_disable_dvi, }; @@ -342,7 +342,7 @@ static struct panel_generic_dpi_data dvi_panel = { static struct omap_dss_device am3517_evm_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -362,11 +362,6 @@ static struct omap_dss_board_info am3517_evm_dss_data = { /* * Board initialization */ -static void __init am3517_evm_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_ULPI, @@ -469,6 +464,7 @@ static void __init am3517_evm_init(void) am3517_evm_i2c_init(); omap_display_init(&am3517_evm_dss_data); omap_serial_init(); + omap_sdrc_init(NULL, NULL); /* Configure GPIO for EHCI port */ omap_mux_init_gpio(57, OMAP_PIN_OUTPUT); @@ -493,7 +489,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = am3517_evm_init_early, + .init_early = am35xx_init_early, .init_irq = omap3_init_irq, .init_machine = am3517_evm_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 67800e6..de8134b 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -40,6 +40,9 @@ #include <plat/common.h> #include <plat/gpmc.h> +#include <video/omapdss.h> +#include <video/omap-panel-generic-dpi.h> + #include "mux.h" #include "control.h" @@ -149,11 +152,6 @@ static struct platform_device apollon_smc91x_device = { .resource = apollon_smc91x_resources, }; -static struct platform_device apollon_lcd_device = { - .name = "apollon_lcd", - .id = -1, -}; - static struct omap_led_config apollon_led_config[] = { { .cdev = { @@ -191,7 +189,6 @@ static struct platform_device apollon_led_device = { static struct platform_device *apollon_devices[] __initdata = { &apollon_onenand_device, &apollon_smc91x_device, - &apollon_lcd_device, &apollon_led_device, }; @@ -265,19 +262,27 @@ static struct omap_usb_config apollon_usb_config __initdata = { .pins[0] = 6, }; -static struct omap_lcd_config apollon_lcd_config __initdata = { - .ctrl_name = "internal", +static struct panel_generic_dpi_data apollon_panel_data = { + .name = "apollon", }; -static struct omap_board_config_kernel apollon_config[] __initdata = { - { OMAP_TAG_LCD, &apollon_lcd_config }, +static struct omap_dss_device apollon_lcd_device = { + .name = "lcd", + .driver_name = "generic_dpi_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 18, + .data = &apollon_panel_data, }; -static void __init omap_apollon_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} +static struct omap_dss_device *apollon_dss_devices[] = { + &apollon_lcd_device, +}; + +static struct omap_dss_board_info apollon_dss_data = { + .num_devices = ARRAY_SIZE(apollon_dss_devices), + .devices = apollon_dss_devices, + .default_device = &apollon_lcd_device, +}; static struct gpio apollon_gpio_leds[] __initdata = { { LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */ @@ -314,8 +319,6 @@ static void __init omap_apollon_init(void) u32 v; omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); - omap_board_config = apollon_config; - omap_board_config_size = ARRAY_SIZE(apollon_config); apollon_init_smc91x(); apollon_led_init(); @@ -340,20 +343,16 @@ static void __init omap_apollon_init(void) */ platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices)); omap_serial_init(); -} - -static void __init omap_apollon_map_io(void) -{ - omap2_set_globals_242x(); - omap242x_map_common_io(); + omap_sdrc_init(NULL, NULL); + omap_display_init(&apollon_dss_data); } MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = omap_apollon_map_io, - .init_early = omap_apollon_init_early, + .map_io = omap242x_map_io, + .init_early = omap2420_init_early, .init_irq = omap2_init_irq, .init_machine = omap_apollon_init, .timer = &omap2_timer, diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 38179c1..bd1bcac 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -43,6 +43,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include <plat/mcspi.h> #include <mach/hardware.h> @@ -242,8 +243,7 @@ static struct omap_dss_device cm_t35_lcd_device = { .phy.dpi.data_lines = 18, }; -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = cm_t35_panel_enable_dvi, .platform_disable = cm_t35_panel_disable_dvi, }; @@ -251,7 +251,7 @@ static struct panel_generic_dpi_data dvi_panel = { static struct omap_dss_device cm_t35_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -471,13 +471,6 @@ static void __init cm_t35_init_i2c(void) omap3_pmic_init("tps65930", &cm_t35_twldata); } -static void __init cm_t35_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -} - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { /* nCS and IRQ for CM-T35 ethernet */ @@ -610,6 +603,8 @@ static void __init cm_t3x_common_init(void) omap_board_config_size = ARRAY_SIZE(cm_t35_config); omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); cm_t35_init_i2c(); omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL); cm_t35_init_ethernet(); @@ -637,7 +632,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = cm_t35_init_early, + .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, .init_machine = cm_t35_init, .timer = &omap3_timer, @@ -647,7 +642,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = cm_t35_init_early, + .init_early = omap3630_init_early, .init_irq = omap3_init_irq, .init_machine = cm_t3730_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index aed9c29..3f4dc66 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -251,12 +251,6 @@ static inline void cm_t3517_init_nand(void) {} static struct omap_board_config_kernel cm_t3517_config[] __initdata = { }; -static void __init cm_t3517_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { /* GPIO186 - Green LED */ @@ -289,6 +283,7 @@ static void __init cm_t3517_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); + omap_sdrc_init(NULL, NULL); omap_board_config = cm_t3517_config; omap_board_config_size = ARRAY_SIZE(cm_t3517_config); cm_t3517_init_leds(); @@ -302,7 +297,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = cm_t3517_init_early, + .init_early = am35xx_init_early, .init_irq = omap3_init_irq, .init_machine = cm_t3517_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 99a4243..4291894 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -47,6 +47,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include <plat/mcspi.h> #include <linux/input/matrix_keypad.h> @@ -139,7 +140,7 @@ static struct regulator_consumer_supply devkit8000_vio_supply[] = { }; static struct panel_generic_dpi_data lcd_panel = { - .name = "generic", + .name = "innolux_at070tn83", .platform_enable = devkit8000_panel_enable_lcd, .platform_disable = devkit8000_panel_disable_lcd, }; @@ -152,8 +153,7 @@ static struct omap_dss_device devkit8000_lcd_device = { .phy.dpi.data_lines = 24, }; -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = devkit8000_panel_enable_dvi, .platform_disable = devkit8000_panel_disable_dvi, }; @@ -161,7 +161,7 @@ static struct panel_generic_dpi_data dvi_panel = { static struct omap_dss_device devkit8000_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -267,7 +267,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = { REGULATOR_SUPPLY("vdds_dsi", "omapdss"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), }; /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ @@ -397,19 +397,6 @@ static struct platform_device keys_gpio = { }, }; - -static void __init devkit8000_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -} - -static void __init devkit8000_init_irq(void) -{ - omap3_init_irq(); -} - #define OMAP_DM9000_BASE 0x2c000000 static struct resource omap_dm9000_resources[] = { @@ -645,6 +632,8 @@ static void __init devkit8000_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_dm9000_init(); @@ -670,8 +659,8 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = devkit8000_init_early, - .init_irq = devkit8000_init_irq, + .init_early = omap35xx_init_early, + .init_irq = omap3_init_irq, .init_machine = devkit8000_init, .timer = &omap3_secure_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index aa1b0cb..30a6f52 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -148,11 +148,6 @@ __init board_nand_init(struct mtd_partition *nand_parts, board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; gpmc_nand_init(&board_nand_data); } -#else -void -__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type) -{ -} #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ /** diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h index c240a3f..d25503a 100644 --- a/arch/arm/mach-omap2/board-flash.h +++ b/arch/arm/mach-omap2/board-flash.h @@ -24,7 +24,26 @@ struct flash_partitions { int nr_parts; }; +#if defined(CONFIG_MTD_NAND_OMAP2) || \ + defined(CONFIG_MTD_NAND_OMAP2_MODULE) || \ + defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) extern void board_flash_init(struct flash_partitions [], char chip_sel[][GPMC_CS_NUM], int nand_type); +#else +static inline void board_flash_init(struct flash_partitions part[], + char chip_sel[][GPMC_CS_NUM], int nand_type) +{ +} +#endif + +#if defined(CONFIG_MTD_NAND_OMAP2) || \ + defined(CONFIG_MTD_NAND_OMAP2_MODULE) extern void board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type); +#else +static inline void board_nand_init(struct mtd_partition *nand_parts, + u8 nr_parts, u8 cs, int nand_type) +{ +} +#endif diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 4431ad3..7ac5462 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -35,12 +35,12 @@ static struct omap_board_config_kernel generic_config[] = { static void __init omap_generic_init_early(void) { omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); } static void __init omap_generic_init(void) { omap_serial_init(); + omap_sdrc_init(NULL, NULL); omap_board_config = generic_config; omap_board_config_size = ARRAY_SIZE(generic_config); } diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 82421a4..c12666e 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -39,6 +39,9 @@ #include <plat/dma.h> #include <plat/gpmc.h> +#include <video/omapdss.h> +#include <video/omap-panel-generic-dpi.h> + #include "mux.h" #include "control.h" @@ -156,17 +159,33 @@ static struct platform_device h4_kp_device = { }, }; -static struct platform_device h4_lcd_device = { - .name = "lcd_h4", - .id = -1, -}; - static struct platform_device *h4_devices[] __initdata = { &h4_flash_device, &h4_kp_device, +}; + +static struct panel_generic_dpi_data h4_panel_data = { + .name = "h4", +}; + +static struct omap_dss_device h4_lcd_device = { + .name = "lcd", + .driver_name = "generic_dpi_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 16, + .data = &h4_panel_data, +}; + +static struct omap_dss_device *h4_dss_devices[] = { &h4_lcd_device, }; +static struct omap_dss_board_info h4_dss_data = { + .num_devices = ARRAY_SIZE(h4_dss_devices), + .devices = h4_dss_devices, + .default_device = &h4_lcd_device, +}; + /* 2420 Sysboot setup (2430 is different) */ static u32 get_sysboot_value(void) { @@ -270,10 +289,6 @@ static void __init h4_init_flash(void) h4_flash_resource.end = base + SZ_64M - 1; } -static struct omap_lcd_config h4_lcd_config __initdata = { - .ctrl_name = "internal", -}; - static struct omap_usb_config h4_usb_config __initdata = { /* S1.10 OFF -- usb "download port" * usb0 switched to Mini-B port and isp1105 transceiver; @@ -285,21 +300,6 @@ static struct omap_usb_config h4_usb_config __initdata = { .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ }; -static struct omap_board_config_kernel h4_config[] __initdata = { - { OMAP_TAG_LCD, &h4_lcd_config }, -}; - -static void __init omap_h4_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - -static void __init omap_h4_init_irq(void) -{ - omap2_init_irq(); -} - static struct at24_platform_data m24c01 = { .byte_len = SZ_1K / 8, .page_size = 16, @@ -330,9 +330,6 @@ static void __init omap_h4_init(void) { omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); - omap_board_config = h4_config; - omap_board_config_size = ARRAY_SIZE(h4_config); - /* * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on @@ -370,22 +367,19 @@ static void __init omap_h4_init(void) platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); omap2_usbfs_init(&h4_usb_config); omap_serial_init(); + omap_sdrc_init(NULL, NULL); h4_init_flash(); -} -static void __init omap_h4_map_io(void) -{ - omap2_set_globals_242x(); - omap242x_map_common_io(); + omap_display_init(&h4_dss_data); } MACHINE_START(OMAP_H4, "OMAP2420 H4 board") /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = omap_h4_map_io, - .init_early = omap_h4_init_early, - .init_irq = omap_h4_init_irq, + .map_io = omap242x_map_io, + .init_early = omap2420_init_early, + .init_irq = omap2_init_irq, .init_machine = omap_h4_init, .timer = &omap2_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 7040352..d0a3f78 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -32,7 +32,7 @@ #include <plat/gpmc.h> #include <plat/usb.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include <plat/onenand.h> #include "mux.h" @@ -455,16 +455,16 @@ static void igep2_disable_dvi(struct omap_dss_device *dssdev) gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0); } -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = igep2_enable_dvi, .platform_disable = igep2_disable_dvi, + .i2c_bus_num = 3, }; static struct omap_dss_device igep2_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -491,13 +491,6 @@ static struct platform_device *igep_devices[] __initdata = { &igep_vwlan_device, }; -static void __init igep_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(m65kxxxxam_sdrc_params, - m65kxxxxam_sdrc_params); -} - static int igep2_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_RIGHT), @@ -650,6 +643,8 @@ static void __init igep_init(void) igep_i2c_init(); platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices)); omap_serial_init(); + omap_sdrc_init(m65kxxxxam_sdrc_params, + m65kxxxxam_sdrc_params); usb_musb_init(NULL); igep_flash_init(); @@ -675,7 +670,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = igep_init_early, + .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, .init_machine = igep_init, .timer = &omap3_timer, @@ -685,7 +680,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = igep_init_early, + .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, .init_machine = igep_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index abe8c7e..e179da0 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -27,6 +27,7 @@ #include <linux/io.h> #include <linux/smsc911x.h> #include <linux/mmc/host.h> +#include <linux/gpio.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -43,6 +44,9 @@ #include <plat/usb.h> #include <plat/gpmc-smsc911x.h> +#include <video/omapdss.h> +#include <video/omap-panel-generic-dpi.h> + #include "board-flash.h" #include "mux.h" #include "hsmmc.h" @@ -179,29 +183,102 @@ static inline void __init ldp_init_smsc911x(void) gpmc_smsc911x_init(&smsc911x_cfg); } -static struct platform_device ldp_lcd_device = { - .name = "ldp_lcd", - .id = -1, +/* LCD */ + +static int ldp_backlight_gpio; +static int ldp_lcd_enable_gpio; + +#define LCD_PANEL_RESET_GPIO 55 +#define LCD_PANEL_QVGA_GPIO 56 + +static int ldp_panel_enable_lcd(struct omap_dss_device *dssdev) +{ + if (gpio_is_valid(ldp_lcd_enable_gpio)) + gpio_direction_output(ldp_lcd_enable_gpio, 1); + if (gpio_is_valid(ldp_backlight_gpio)) + gpio_direction_output(ldp_backlight_gpio, 1); + + return 0; +} + +static void ldp_panel_disable_lcd(struct omap_dss_device *dssdev) +{ + if (gpio_is_valid(ldp_lcd_enable_gpio)) + gpio_direction_output(ldp_lcd_enable_gpio, 0); + if (gpio_is_valid(ldp_backlight_gpio)) + gpio_direction_output(ldp_backlight_gpio, 0); +} + +static struct panel_generic_dpi_data ldp_panel_data = { + .name = "nec_nl2432dr22-11b", + .platform_enable = ldp_panel_enable_lcd, + .platform_disable = ldp_panel_disable_lcd, +}; + +static struct omap_dss_device ldp_lcd_device = { + .name = "lcd", + .driver_name = "generic_dpi_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 18, + .data = &ldp_panel_data, }; -static struct omap_lcd_config ldp_lcd_config __initdata = { - .ctrl_name = "internal", +static struct omap_dss_device *ldp_dss_devices[] = { + &ldp_lcd_device, }; -static struct omap_board_config_kernel ldp_config[] __initdata = { - { OMAP_TAG_LCD, &ldp_lcd_config }, +static struct omap_dss_board_info ldp_dss_data = { + .num_devices = ARRAY_SIZE(ldp_dss_devices), + .devices = ldp_dss_devices, + .default_device = &ldp_lcd_device, }; -static void __init omap_ldp_init_early(void) +static void __init ldp_display_init(void) +{ + int r; + + static struct gpio gpios[] __initdata = { + {LCD_PANEL_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "LCD RESET"}, + {LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "LCD QVGA"}, + }; + + r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); + if (r) { + pr_err("Cannot request LCD GPIOs, error %d\n", r); + return; + } + + omap_display_init(&ldp_dss_data); +} + +static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); + int r; + + struct gpio gpios[] = { + {gpio + 7 , GPIOF_OUT_INIT_LOW, "LCD ENABLE"}, + {gpio + 15, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT"}, + }; + + r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); + if (r) { + pr_err("Cannot request LCD GPIOs, error %d\n", r); + ldp_backlight_gpio = -EINVAL; + ldp_lcd_enable_gpio = -EINVAL; + return r; + } + + ldp_backlight_gpio = gpio + 15; + ldp_lcd_enable_gpio = gpio + 7; + + return 0; } static struct twl4030_gpio_platform_data ldp_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, + .setup = ldp_twl_gpio_setup, }; static struct regulator_consumer_supply ldp_vmmc1_supply[] = { @@ -243,10 +320,31 @@ static struct regulator_init_data ldp_vaux1 = { .consumer_supplies = ldp_vaux1_supplies, }; +static struct regulator_consumer_supply ldp_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), +}; + +static struct regulator_init_data ldp_vpll2 = { + .constraints = { + .name = "VDVI", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(ldp_vpll2_supplies), + .consumer_supplies = ldp_vpll2_supplies, +}; + static struct twl4030_platform_data ldp_twldata = { /* platform_data for children goes here */ .vmmc1 = &ldp_vmmc1, .vaux1 = &ldp_vaux1, + .vpll2 = &ldp_vpll2, .gpio = &ldp_gpio_data, .keypad = &ldp_kp_twl4030_data, }; @@ -272,7 +370,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = { }; static struct platform_device *ldp_devices[] __initdata = { - &ldp_lcd_device, &ldp_gpio_keys_device, }; @@ -317,25 +414,25 @@ static struct mtd_partition ldp_nand_partitions[] = { static void __init omap_ldp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_board_config = ldp_config; - omap_board_config_size = ARRAY_SIZE(ldp_config); ldp_init_smsc911x(); omap_i2c_init(); platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); omap_ads7846_init(1, 54, 310, NULL); omap_serial_init(); + omap_sdrc_init(NULL, NULL); usb_musb_init(NULL); board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0); omap2_hsmmc_init(mmc); + ldp_display_init(); } MACHINE_START(OMAP_LDP, "OMAP LDP board") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = omap_ldp_init_early, + .init_early = omap3430_init_early, .init_irq = omap3_init_irq, .init_machine = omap_ldp_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 6ce7481..e9d5f4a 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -616,18 +616,6 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { }, }; -static void __init n8x0_map_io(void) -{ - omap2_set_globals_242x(); - omap242x_map_common_io(); -} - -static void __init n8x0_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { /* I2S codec port pins for McBSP block */ @@ -689,6 +677,7 @@ static void __init n8x0_init_machine(void) i2c_register_board_info(2, n810_i2c_board_info_2, ARRAY_SIZE(n810_i2c_board_info_2)); board_serial_init(); + omap_sdrc_init(NULL, NULL); gpmc_onenand_init(board_onenand_data); n8x0_mmc_init(); n8x0_usb_init(); @@ -697,8 +686,8 @@ static void __init n8x0_init_machine(void) MACHINE_START(NOKIA_N800, "Nokia N800") .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = n8x0_map_io, - .init_early = n8x0_init_early, + .map_io = omap242x_map_io, + .init_early = omap2420_init_early, .init_irq = omap2_init_irq, .init_machine = n8x0_init_machine, .timer = &omap2_timer, @@ -707,8 +696,8 @@ MACHINE_END MACHINE_START(NOKIA_N810, "Nokia N810") .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = n8x0_map_io, - .init_early = n8x0_init_early, + .map_io = omap242x_map_io, + .init_early = omap2420_init_early, .init_irq = omap2_init_irq, .init_machine = n8x0_init_machine, .timer = &omap2_timer, @@ -717,8 +706,8 @@ MACHINE_END MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = n8x0_map_io, - .init_early = n8x0_init_early, + .map_io = omap242x_map_io, + .init_early = omap2420_init_early, .init_irq = omap2_init_irq, .init_machine = n8x0_init_machine, .timer = &omap2_timer, diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 1fde8a0..474a7e2 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -42,7 +42,7 @@ #include <plat/board.h> #include <plat/common.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> @@ -203,16 +203,16 @@ static void beagle_disable_dvi(struct omap_dss_device *dssdev) gpio_set_value(dssdev->reset_gpio, 0); } -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = beagle_enable_dvi, .platform_disable = beagle_disable_dvi, + .i2c_bus_num = 3, }; static struct omap_dss_device beagle_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, .reset_gpio = -EINVAL, @@ -447,13 +447,6 @@ static struct platform_device keys_gpio = { static void __init omap3_beagle_init_early(void) { omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -} - -static void __init omap3_beagle_init_irq(void) -{ - omap3_init_irq(); } static struct platform_device *omap3_beagle_devices[] __initdata = { @@ -534,6 +527,8 @@ static void __init omap3_beagle_init(void) ARRAY_SIZE(omap3_beagle_devices)); omap_display_init(&beagle_dss_data); omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_mux_init_gpio(170, OMAP_PIN_INPUT); /* REVISIT leave DVI powered down until it's needed ... */ @@ -561,7 +556,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") .reserve = omap_reserve, .map_io = omap3_map_io, .init_early = omap3_beagle_init_early, - .init_irq = omap3_beagle_init_irq, + .init_irq = omap3_init_irq, .init_machine = omap3_beagle_init, .timer = &omap3_secure_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 15c69a0..2d24e28 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -45,7 +45,7 @@ #include <plat/common.h> #include <plat/mcspi.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" @@ -247,8 +247,7 @@ static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) dvi_enabled = 0; } -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = omap3_evm_enable_dvi, .platform_disable = omap3_evm_disable_dvi, }; @@ -256,7 +255,7 @@ static struct panel_generic_dpi_data dvi_panel = { static struct omap_dss_device omap3_evm_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -520,12 +519,6 @@ static int __init omap3_evm_i2c_init(void) static struct omap_board_config_kernel omap3_evm_config[] __initdata = { }; -static void __init omap3_evm_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); -} - static struct usbhs_omap_board_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, @@ -640,6 +633,7 @@ static void __init omap3_evm_init(void) omap_display_init(&omap3_evm_dss_data); omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */ usb_nop_xceiv_register(); @@ -684,7 +678,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = omap3_evm_init_early, + .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, .init_machine = omap3_evm_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 01354a2..7c0f193 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -182,12 +182,6 @@ static inline void __init board_smsc911x_init(void) gpmc_smsc911x_init(&board_smsc911x_data); } -static void __init omap3logic_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, @@ -200,6 +194,7 @@ static void __init omap3logic_init(void) omap3torpedo_fix_pbias_voltage(); omap3logic_i2c_init(); omap_serial_init(); + omap_sdrc_init(NULL, NULL); board_mmc_init(); board_smsc911x_init(); @@ -211,7 +206,7 @@ static void __init omap3logic_init(void) MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") .atag_offset = 0x100, .map_io = omap3_map_io, - .init_early = omap3logic_init_early, + .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, .init_machine = omap3logic_init, .timer = &omap3_timer, @@ -220,7 +215,7 @@ MACHINE_END MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") .atag_offset = 0x100, .map_io = omap3_map_io, - .init_early = omap3logic_init_early, + .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, .init_machine = omap3logic_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index ace5693..f7811f4 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -335,7 +335,7 @@ static struct regulator_consumer_supply pandora_vmmc3_supply[] = { static struct regulator_consumer_supply pandora_vdds_supplies[] = { REGULATOR_SUPPLY("vdds_sdi", "omapdss"), REGULATOR_SUPPLY("vdds_dsi", "omapdss"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), }; static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = { @@ -525,13 +525,6 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { } }; -static void __init omap3pandora_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -} - static void __init pandora_wl1251_init(void) { struct wl12xx_platform_data pandora_wl1251_pdata; @@ -593,6 +586,8 @@ static void __init omap3pandora_init(void) ARRAY_SIZE(omap3pandora_devices)); omap_display_init(&pandora_dss_data); omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); spi_register_board_info(omap3pandora_spi_board_info, ARRAY_SIZE(omap3pandora_spi_board_info)); omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL); @@ -609,7 +604,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = omap3pandora_init_early, + .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, .init_machine = omap3pandora_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index ba13e1d..ddb7d66 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -41,6 +41,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include <plat/mcspi.h> #include <linux/input/matrix_keypad.h> @@ -107,39 +108,6 @@ static void __init omap3_stalker_display_init(void) return; } -static int omap3_stalker_enable_lcd(struct omap_dss_device *dssdev) -{ - if (dvi_enabled) { - printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); - return -EINVAL; - } - gpio_set_value(DSS_ENABLE_GPIO, 1); - gpio_set_value(LCD_PANEL_BKLIGHT_GPIO, 1); - lcd_enabled = 1; - return 0; -} - -static void omap3_stalker_disable_lcd(struct omap_dss_device *dssdev) -{ - gpio_set_value(DSS_ENABLE_GPIO, 0); - gpio_set_value(LCD_PANEL_BKLIGHT_GPIO, 0); - lcd_enabled = 0; -} - -static struct panel_generic_dpi_data lcd_panel = { - .name = "generic", - .platform_enable = omap3_stalker_enable_lcd, - .platform_disable = omap3_stalker_disable_lcd, -}; - -static struct omap_dss_device omap3_stalker_lcd_device = { - .name = "lcd", - .driver_name = "generic_dpi_panel", - .data = &lcd_panel, - .phy.dpi.data_lines = 24, - .type = OMAP_DISPLAY_TYPE_DPI, -}; - static int omap3_stalker_enable_tv(struct omap_dss_device *dssdev) { return 0; @@ -179,8 +147,7 @@ static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev) dvi_enabled = 0; } -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = omap3_stalker_enable_dvi, .platform_disable = omap3_stalker_disable_dvi, }; @@ -188,13 +155,12 @@ static struct panel_generic_dpi_data dvi_panel = { static struct omap_dss_device omap3_stalker_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; static struct omap_dss_device *omap3_stalker_dss_devices[] = { - &omap3_stalker_lcd_device, &omap3_stalker_tv_device, &omap3_stalker_dvi_device, }; @@ -428,17 +394,6 @@ static int __init omap3_stalker_i2c_init(void) static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { }; -static void __init omap3_stalker_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); -} - -static void __init omap3_stalker_init_irq(void) -{ - omap3_init_irq(); -} - static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, }; @@ -478,6 +433,7 @@ static void __init omap3_stalker_init(void) omap_display_init(&omap3_stalker_dss_data); omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); usb_musb_init(NULL); usbhs_init(&usbhs_bdata); omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL); @@ -496,8 +452,8 @@ MACHINE_START(SBC3530, "OMAP3 STALKER") /* Maintainer: Jason Lam -lzg@ema-tech.com */ .atag_offset = 0x100, .map_io = omap3_map_io, - .init_early = omap3_stalker_init_early, - .init_irq = omap3_stalker_init_irq, + .init_early = omap35xx_init_early, + .init_irq = omap3_init_irq, .init_machine = omap3_stalker_init, .timer = &omap3_secure_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 49e4bd2..a2d0d19 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -104,15 +104,6 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct platform_device omap3_touchbook_lcd_device = { - .name = "omap3touchbook_lcd", - .id = -1, -}; - -static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = { - .ctrl_name = "internal", -}; - static struct regulator_consumer_supply touchbook_vmmc1_supply[] = { REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), }; @@ -165,14 +156,12 @@ static struct twl4030_gpio_platform_data touchbook_gpio_data = { static struct regulator_consumer_supply touchbook_vdac_supply[] = { { .supply = "vdac", - .dev = &omap3_touchbook_lcd_device.dev, }, }; static struct regulator_consumer_supply touchbook_vdvi_supply[] = { { .supply = "vdvi", - .dev = &omap3_touchbook_lcd_device.dev, }, }; @@ -316,30 +305,13 @@ static struct platform_device keys_gpio = { }, }; -static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = { - { OMAP_TAG_LCD, &omap3_touchbook_lcd_config }, -}; - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; #endif -static void __init omap3_touchbook_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -} - -static void __init omap3_touchbook_init_irq(void) -{ - omap3_init_irq(); -} - static struct platform_device *omap3_touchbook_devices[] __initdata = { - &omap3_touchbook_lcd_device, &leds_gpio, &keys_gpio, }; @@ -376,8 +348,6 @@ early_param("tbr", early_touchbook_revision); static void __init omap3_touchbook_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_board_config = omap3_touchbook_config; - omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); pm_power_off = omap3_touchbook_poweroff; @@ -385,6 +355,8 @@ static void __init omap3_touchbook_init(void) platform_add_devices(omap3_touchbook_devices, ARRAY_SIZE(omap3_touchbook_devices)); omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_mux_init_gpio(170, OMAP_PIN_INPUT); /* REVISIT leave DVI powered down until it's needed ... */ @@ -407,8 +379,8 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = omap3_touchbook_init_early, - .init_irq = omap3_touchbook_init_irq, + .init_early = omap3430_init_early, + .init_irq = omap3_init_irq, .init_machine = omap3_touchbook_init, .timer = &omap3_secure_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 683bede..a8c2c42 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -40,7 +40,7 @@ #include <plat/common.h> #include <plat/usb.h> #include <plat/mmc.h> -#include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include "hsmmc.h" #include "control.h" @@ -95,12 +95,6 @@ static struct platform_device *panda_devices[] __initdata = { &wl1271_device, }; -static void __init omap4_panda_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - static const struct usbhs_omap_board_data usbhs_bdata __initconst = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, @@ -455,16 +449,16 @@ static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev) } /* Using generic display panel */ -static struct panel_generic_dpi_data omap4_dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data omap4_dvi_panel = { .platform_enable = omap4_panda_enable_dvi, .platform_disable = omap4_panda_disable_dvi, + .i2c_bus_num = 3, }; struct omap_dss_device omap4_panda_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &omap4_dvi_panel, .phy.dpi.data_lines = 24, .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, @@ -569,24 +563,19 @@ static void __init omap4_panda_init(void) platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); platform_device_register(&omap_vwlan_device); board_serial_init(); + omap_sdrc_init(NULL, NULL); omap4_twl6030_hsmmc_init(mmc); omap4_ehci_init(); usb_musb_init(&musb_board_data); omap4_panda_display_init(); } -static void __init omap4_panda_map_io(void) -{ - omap2_set_globals_443x(); - omap44xx_map_common_io(); -} - MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") /* Maintainer: David Anders - Texas Instruments Inc */ .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = omap4_panda_map_io, - .init_early = omap4_panda_init_early, + .map_io = omap4_map_io, + .init_early = omap4430_init_early, .init_irq = gic_init_irq, .init_machine = omap4_panda_init, .timer = &omap4_timer, diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index e592fb1..4cf7aea 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -46,6 +46,7 @@ #include <plat/common.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-dvi.h> #include <plat/gpmc.h> #include <mach/hardware.h> #include <plat/nand.h> @@ -182,16 +183,16 @@ static void overo_panel_disable_dvi(struct omap_dss_device *dssdev) dvi_enabled = 0; } -static struct panel_generic_dpi_data dvi_panel = { - .name = "generic", +static struct panel_dvi_platform_data dvi_panel = { .platform_enable = overo_panel_enable_dvi, .platform_disable = overo_panel_disable_dvi, + .i2c_bus_num = 3, }; static struct omap_dss_device overo_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", + .driver_name = "dvi", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -478,13 +479,6 @@ static int __init overo_spi_init(void) return 0; } -static void __init overo_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -} - static const struct usbhs_omap_board_data usbhs_bdata __initconst = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, @@ -514,6 +508,8 @@ static void __init overo_init(void) overo_i2c_init(); omap_display_init(&overo_dss_data); omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); omap_nand_flash_init(0, overo_nand_partitions, ARRAY_SIZE(overo_nand_partitions)); usb_musb_init(NULL); @@ -564,7 +560,7 @@ MACHINE_START(OVERO, "Gumstix Overo") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = overo_init_early, + .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, .init_machine = overo_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index 9a8ce23..616fb39 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c @@ -123,15 +123,6 @@ static void __init rm680_peripherals_init(void) omap2_hsmmc_init(mmc); } -static void __init rm680_init_early(void) -{ - struct omap_sdrc_params *sdrc_params; - - omap2_init_common_infrastructure(); - sdrc_params = nokia_get_sdram_timings(); - omap2_init_common_devices(sdrc_params, sdrc_params); -} - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, @@ -140,23 +131,23 @@ static struct omap_board_mux board_mux[] __initdata = { static void __init rm680_init(void) { + struct omap_sdrc_params *sdrc_params; + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); + + sdrc_params = nokia_get_sdram_timings(); + omap_sdrc_init(sdrc_params, sdrc_params); + usb_musb_init(NULL); rm680_peripherals_init(); } -static void __init rm680_map_io(void) -{ - omap2_set_globals_3xxx(); - omap34xx_map_common_io(); -} - MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") .atag_offset = 0x100, .reserve = omap_reserve, - .map_io = rm680_map_io, - .init_early = rm680_init_early, + .map_io = omap3_map_io, + .init_early = omap3630_init_early, .init_irq = omap3_init_irq, .init_machine = rm680_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 5a886cd..ba1aa07 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -900,7 +900,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = { }; static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = { - .id = TPA6130A2, .power_gpio = 98, }; diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index a6c473b..4af7c4b 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -79,38 +79,6 @@ static struct cpuidle_params rx51_cpuidle_params[] = { {7505 + 15274, 484329, 1}, }; -static struct omap_lcd_config rx51_lcd_config = { - .ctrl_name = "internal", -}; - -static struct omap_fbmem_config rx51_fbmem0_config = { - .size = 752 * 1024, -}; - -static struct omap_fbmem_config rx51_fbmem1_config = { - .size = 752 * 1024, -}; - -static struct omap_fbmem_config rx51_fbmem2_config = { - .size = 752 * 1024, -}; - -static struct omap_board_config_kernel rx51_config[] = { - { OMAP_TAG_FBMEM, &rx51_fbmem0_config }, - { OMAP_TAG_FBMEM, &rx51_fbmem1_config }, - { OMAP_TAG_FBMEM, &rx51_fbmem2_config }, - { OMAP_TAG_LCD, &rx51_lcd_config }, -}; - -static void __init rx51_init_early(void) -{ - struct omap_sdrc_params *sdrc_params; - - omap2_init_common_infrastructure(); - sdrc_params = nokia_get_sdram_timings(); - omap2_init_common_devices(sdrc_params, sdrc_params); -} - extern void __init rx51_peripherals_init(void); #ifdef CONFIG_OMAP_MUX @@ -127,11 +95,15 @@ static struct omap_musb_board_data musb_board_data = { static void __init rx51_init(void) { + struct omap_sdrc_params *sdrc_params; + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_board_config = rx51_config; - omap_board_config_size = ARRAY_SIZE(rx51_config); omap3_pm_init_cpuidle(rx51_cpuidle_params); omap_serial_init(); + + sdrc_params = nokia_get_sdram_timings(); + omap_sdrc_init(sdrc_params, sdrc_params); + usb_musb_init(&musb_board_data); rx51_peripherals_init(); @@ -142,12 +114,6 @@ static void __init rx51_init(void) platform_device_register(&leds_gpio); } -static void __init rx51_map_io(void) -{ - omap2_set_globals_3xxx(); - omap34xx_map_common_io(); -} - static void __init rx51_reserve(void) { rx51_video_mem_init(); @@ -158,8 +124,8 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ .atag_offset = 0x100, .reserve = rx51_reserve, - .map_io = rx51_map_io, - .init_early = rx51_init_early, + .map_io = omap3_map_io, + .init_early = omap3430_init_early, .init_irq = omap3_init_irq, .init_machine = rx51_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index e41958a..e26c79c 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -27,15 +27,10 @@ static struct omap_board_config_kernel ti8168_evm_config[] __initdata = { }; -static void __init ti8168_init_early(void) -{ - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -} - static void __init ti8168_evm_init(void) { omap_serial_init(); + omap_sdrc_init(NULL, NULL); omap_board_config = ti8168_evm_config; omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); } @@ -50,7 +45,7 @@ MACHINE_START(TI8168EVM, "ti8168evm") /* Maintainer: Texas Instruments */ .atag_offset = 0x100, .map_io = ti8168_evm_map_io, - .init_early = ti8168_init_early, + .init_early = ti816x_init_early, .init_irq = ti816x_init_irq, .timer = &omap3_timer, .init_machine = ti8168_evm_init, diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index 72f1db4..be6684d 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -34,17 +34,6 @@ #define ZOOM3_EHCI_RESET_GPIO 64 -static void __init omap_zoom_init_early(void) -{ - omap2_init_common_infrastructure(); - if (machine_is_omap_zoom2()) - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - else if (machine_is_omap_zoom3()) - omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, - h8mbx00u0mer0em_sdrc_params); -} - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { /* WLAN IRQ - GPIO 162 */ @@ -129,6 +118,14 @@ static void __init omap_zoom_init(void) ZOOM_NAND_CS, NAND_BUSWIDTH_16); zoom_debugboard_init(); zoom_peripherals_init(); + + if (machine_is_omap_zoom2()) + omap_sdrc_init(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); + else if (machine_is_omap_zoom3()) + omap_sdrc_init(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); + zoom_display_init(); } @@ -136,7 +133,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = omap_zoom_init_early, + .init_early = omap3430_init_early, .init_irq = omap3_init_irq, .init_machine = omap_zoom_init, .timer = &omap3_timer, @@ -146,7 +143,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_early = omap_zoom_init_early, + .init_early = omap3630_init_early, .init_irq = omap3_init_irq, .init_machine = omap_zoom_init, .timer = &omap3_timer, diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index debc040..14a6277 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1898,6 +1898,54 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb-hdrc", "fck", &osc_ck, CK_242X), + CLK("omap_timer.1", "fck", &gpt1_fck, CK_242X), + CLK("omap_timer.2", "fck", &gpt2_fck, CK_242X), + CLK("omap_timer.3", "fck", &gpt3_fck, CK_242X), + CLK("omap_timer.4", "fck", &gpt4_fck, CK_242X), + CLK("omap_timer.5", "fck", &gpt5_fck, CK_242X), + CLK("omap_timer.6", "fck", &gpt6_fck, CK_242X), + CLK("omap_timer.7", "fck", &gpt7_fck, CK_242X), + CLK("omap_timer.8", "fck", &gpt8_fck, CK_242X), + CLK("omap_timer.9", "fck", &gpt9_fck, CK_242X), + CLK("omap_timer.10", "fck", &gpt10_fck, CK_242X), + CLK("omap_timer.11", "fck", &gpt11_fck, CK_242X), + CLK("omap_timer.12", "fck", &gpt12_fck, CK_242X), + CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X), }; /* diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 96a942e..ea6717c 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1998,6 +1998,54 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), + CLK("omap_timer.1", "fck", &gpt1_fck, CK_243X), + CLK("omap_timer.2", "fck", &gpt2_fck, CK_243X), + CLK("omap_timer.3", "fck", &gpt3_fck, CK_243X), + CLK("omap_timer.4", "fck", &gpt4_fck, CK_243X), + CLK("omap_timer.5", "fck", &gpt5_fck, CK_243X), + CLK("omap_timer.6", "fck", &gpt6_fck, CK_243X), + CLK("omap_timer.7", "fck", &gpt7_fck, CK_243X), + CLK("omap_timer.8", "fck", &gpt8_fck, CK_243X), + CLK("omap_timer.9", "fck", &gpt9_fck, CK_243X), + CLK("omap_timer.10", "fck", &gpt10_fck, CK_243X), + CLK("omap_timer.11", "fck", &gpt11_fck, CK_243X), + CLK("omap_timer.12", "fck", &gpt12_fck, CK_243X), + CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X), + CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X), + CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X), + CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X), }; /* diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index b9b8446..65dd363 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3464,6 +3464,42 @@ static struct omap_clk omap3xxx_clks[] = { CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), + CLK("omap_timer.1", "fck", &gpt1_fck, CK_3XXX), + CLK("omap_timer.2", "fck", &gpt2_fck, CK_3XXX), + CLK("omap_timer.3", "fck", &gpt3_fck, CK_3XXX), + CLK("omap_timer.4", "fck", &gpt4_fck, CK_3XXX), + CLK("omap_timer.5", "fck", &gpt5_fck, CK_3XXX), + CLK("omap_timer.6", "fck", &gpt6_fck, CK_3XXX), + CLK("omap_timer.7", "fck", &gpt7_fck, CK_3XXX), + CLK("omap_timer.8", "fck", &gpt8_fck, CK_3XXX), + CLK("omap_timer.9", "fck", &gpt9_fck, CK_3XXX), + CLK("omap_timer.10", "fck", &gpt10_fck, CK_3XXX), + CLK("omap_timer.11", "fck", &gpt11_fck, CK_3XXX), + CLK("omap_timer.12", "fck", &gpt12_fck, CK_3XXX), + CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX), + CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX), + CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX), }; @@ -3472,7 +3508,16 @@ int __init omap3xxx_clk_init(void) struct omap_clk *c; u32 cpu_clkflg = 0; - if (cpu_is_omap3517()) { + /* + * 3505 must be tested before 3517, since 3517 returns true + * for both AM3517 chips and AM3517 family chips, which + * includes 3505. Unfortunately there's no obvious family + * test for 3517/3505 :-( + */ + if (cpu_is_omap3505()) { + cpu_mask = RATE_IN_34XX; + cpu_clkflg = CK_3505; + } else if (cpu_is_omap3517()) { cpu_mask = RATE_IN_34XX; cpu_clkflg = CK_3517; } else if (cpu_is_omap3505()) { diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index c0b6fbd..946bf04 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3363,6 +3363,39 @@ static struct omap_clk omap44xx_clks[] = { CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X), + CLK("omap_timer.1", "fck", &timer1_fck, CK_443X), + CLK("omap_timer.2", "fck", &timer2_fck, CK_443X), + CLK("omap_timer.3", "fck", &timer3_fck, CK_443X), + CLK("omap_timer.4", "fck", &timer4_fck, CK_443X), + CLK("omap_timer.5", "fck", &timer5_fck, CK_443X), + CLK("omap_timer.6", "fck", &timer6_fck, CK_443X), + CLK("omap_timer.7", "fck", &timer7_fck, CK_443X), + CLK("omap_timer.8", "fck", &timer8_fck, CK_443X), + CLK("omap_timer.9", "fck", &timer9_fck, CK_443X), + CLK("omap_timer.10", "fck", &timer10_fck, CK_443X), + CLK("omap_timer.11", "fck", &timer11_fck, CK_443X), + CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X), }; int __init omap4xxx_clk_init(void) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 8f08906..8480ee4 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -73,9 +73,6 @@ static int _clkdm_register(struct clockdomain *clkdm) if (!clkdm || !clkdm->name) return -EINVAL; - if (!omap_chip_is(clkdm->omap_chip)) - return -EINVAL; - pwrdm = pwrdm_lookup(clkdm->pwrdm.name); if (!pwrdm) { pr_err("clockdomain: %s: powerdomain %s does not exist\n", @@ -105,13 +102,10 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm, { struct clkdm_dep *cd; - if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip)) + if (!clkdm || !deps) return ERR_PTR(-EINVAL); for (cd = deps; cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; - if (!cd->clkdm && cd->clkdm_name) cd->clkdm = _clkdm_lookup(cd->clkdm_name); @@ -148,9 +142,6 @@ static void _autodep_lookup(struct clkdm_autodep *autodep) if (!autodep) return; - if (!omap_chip_is(autodep->omap_chip)) - return; - clkdm = clkdm_lookup(autodep->clkdm.name); if (!clkdm) { pr_err("clockdomain: autodeps: clockdomain %s does not exist\n", @@ -182,9 +173,6 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm) if (IS_ERR(autodep->clkdm.ptr)) continue; - if (!omap_chip_is(autodep->omap_chip)) - continue; - pr_debug("clockdomain: adding %s sleepdep/wkdep for " "clkdm %s\n", autodep->clkdm.ptr->name, clkdm->name); @@ -216,9 +204,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm) if (IS_ERR(autodep->clkdm.ptr)) continue; - if (!omap_chip_is(autodep->omap_chip)) - continue; - pr_debug("clockdomain: removing %s sleepdep/wkdep for " "clkdm %s\n", autodep->clkdm.ptr->name, clkdm->name); @@ -243,8 +228,6 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm, struct clkdm_dep *cd; for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; if (cd->clkdm) continue; cd->clkdm = _clkdm_lookup(cd->clkdm_name); @@ -257,43 +240,113 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm, /* Public functions */ /** - * clkdm_init - set up the clockdomain layer - * @clkdms: optional pointer to an array of clockdomains to register - * @init_autodeps: optional pointer to an array of autodeps to register - * @custom_funcs: func pointers for arch specific implementations - * - * Set up internal state. If a pointer to an array of clockdomains - * @clkdms was supplied, loop through the list of clockdomains, - * register all that are available on the current platform. Similarly, - * if a pointer to an array of clockdomain autodependencies - * @init_autodeps was provided, register those. No return value. + * clkdm_register_platform_funcs - register clockdomain implementation fns + * @co: func pointers for arch specific implementations + * + * Register the list of function pointers used to implement the + * clockdomain functions on different OMAP SoCs. Should be called + * before any other clkdm_register*() function. Returns -EINVAL if + * @co is null, -EEXIST if platform functions have already been + * registered, or 0 upon success. + */ +int clkdm_register_platform_funcs(struct clkdm_ops *co) +{ + if (!co) + return -EINVAL; + + if (arch_clkdm) + return -EEXIST; + + arch_clkdm = co; + + return 0; +}; + +/** + * clkdm_register_clkdms - register SoC clockdomains + * @cs: pointer to an array of struct clockdomain to register + * + * Register the clockdomains available on a particular OMAP SoC. Must + * be called after clkdm_register_platform_funcs(). May be called + * multiple times. Returns -EACCES if called before + * clkdm_register_platform_funcs(); -EINVAL if the argument @cs is + * null; or 0 upon success. */ -void clkdm_init(struct clockdomain **clkdms, - struct clkdm_autodep *init_autodeps, - struct clkdm_ops *custom_funcs) +int clkdm_register_clkdms(struct clockdomain **cs) { struct clockdomain **c = NULL; - struct clockdomain *clkdm; - struct clkdm_autodep *autodep = NULL; - if (!custom_funcs) - WARN(1, "No custom clkdm functions registered\n"); - else - arch_clkdm = custom_funcs; + if (!arch_clkdm) + return -EACCES; + + if (!cs) + return -EINVAL; + + for (c = cs; *c; c++) + _clkdm_register(*c); + + return 0; +} + +/** + * clkdm_register_autodeps - register autodeps (if required) + * @ia: pointer to a static array of struct clkdm_autodep to register + * + * Register clockdomain "automatic dependencies." These are + * clockdomain wakeup and sleep dependencies that are automatically + * added whenever the first clock inside a clockdomain is enabled, and + * removed whenever the last clock inside a clockdomain is disabled. + * These are currently only used on OMAP3 devices, and are deprecated, + * since they waste energy. However, until the OMAP2/3 IP block + * enable/disable sequence can be converted to match the OMAP4 + * sequence, they are needed. + * + * Must be called only after all of the SoC clockdomains are + * registered, since the function will resolve autodep clockdomain + * names into clockdomain pointers. + * + * The struct clkdm_autodep @ia array must be static, as this function + * does not copy the array elements. + * + * Returns -EACCES if called before any clockdomains have been + * registered, -EINVAL if called with a null @ia argument, -EEXIST if + * autodeps have already been registered, or 0 upon success. + */ +int clkdm_register_autodeps(struct clkdm_autodep *ia) +{ + struct clkdm_autodep *a = NULL; - if (clkdms) - for (c = clkdms; *c; c++) - _clkdm_register(*c); + if (list_empty(&clkdm_list)) + return -EACCES; + + if (!ia) + return -EINVAL; - autodeps = init_autodeps; if (autodeps) - for (autodep = autodeps; autodep->clkdm.ptr; autodep++) - _autodep_lookup(autodep); + return -EEXIST; + + autodeps = ia; + for (a = autodeps; a->clkdm.ptr; a++) + _autodep_lookup(a); + + return 0; +} + +/** + * clkdm_complete_init - set up the clockdomain layer + * + * Put all clockdomains into software-supervised mode; PM code should + * later enable hardware-supervised mode as appropriate. Must be + * called after clkdm_register_clkdms(). Returns -EACCES if called + * before clkdm_register_clkdms(), or 0 upon success. + */ +int clkdm_complete_init(void) +{ + struct clockdomain *clkdm; + + if (list_empty(&clkdm_list)) + return -EACCES; - /* - * Put all clockdomains into software-supervised mode; PM code - * should later enable hardware-supervised mode as appropriate - */ list_for_each_entry(clkdm, &clkdm_list, node) { if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) clkdm_wakeup(clkdm); @@ -306,6 +359,8 @@ void clkdm_init(struct clockdomain **clkdms, _resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs); clkdm_clear_all_sleepdeps(clkdm); } + + return 0; } /** diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 1e50c88..f7b58609 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -45,7 +45,6 @@ /** * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only - * @omap_chip: OMAP chip types that this autodep is valid on * * A clockdomain that should have wkdeps and sleepdeps added when a * clockdomain should stay active in hwsup mode; and conversely, @@ -60,14 +59,12 @@ struct clkdm_autodep { const char *name; struct clockdomain *ptr; } clkdm; - const struct omap_chip_id omap_chip; }; /** * struct clkdm_dep - encode dependencies between clockdomains * @clkdm_name: clockdomain name * @clkdm: pointer to the struct clockdomain of @clkdm_name - * @omap_chip: OMAP chip types that this dependency is valid on * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle * @@ -81,7 +78,6 @@ struct clkdm_dep { struct clockdomain *clkdm; atomic_t wkdep_usecount; atomic_t sleepdep_usecount; - const struct omap_chip_id omap_chip; }; /* Possible flags for struct clockdomain._flags */ @@ -101,7 +97,6 @@ struct clkdm_dep { * @clkdm_offs: (OMAP4 only) CM clockdomain register offset * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact - * @omap_chip: OMAP chip types that this clockdomain is valid on * @usecount: Usecount tracking * @node: list_head to link all clockdomains together * @@ -126,7 +121,6 @@ struct clockdomain { const u16 clkdm_offs; struct clkdm_dep *wkdep_srcs; struct clkdm_dep *sleepdep_srcs; - const struct omap_chip_id omap_chip; atomic_t usecount; struct list_head node; spinlock_t lock; @@ -166,8 +160,11 @@ struct clkdm_ops { int (*clkdm_clk_disable)(struct clockdomain *clkdm); }; -void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps, - struct clkdm_ops *custom_funcs); +int clkdm_register_platform_funcs(struct clkdm_ops *co); +int clkdm_register_autodeps(struct clkdm_autodep *ia); +int clkdm_register_clkdms(struct clockdomain **c); +int clkdm_complete_init(void); + struct clockdomain *clkdm_lookup(const char *name); int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), @@ -195,7 +192,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); -extern void __init omap2xxx_clockdomains_init(void); +extern void __init omap242x_clockdomains_init(void); +extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); extern void _clkdm_add_autodeps(struct clockdomain *clkdm); @@ -205,4 +203,10 @@ extern struct clkdm_ops omap2_clkdm_operations; extern struct clkdm_ops omap3_clkdm_operations; extern struct clkdm_ops omap4_clkdm_operations; +extern struct clkdm_dep gfx_24xx_wkdeps[]; +extern struct clkdm_dep dsp_24xx_wkdeps[]; +extern struct clockdomain wkup_common_clkdm; +extern struct clockdomain prm_common_clkdm; +extern struct clockdomain cm_common_clkdm; + #endif diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index f740edb..a0d68db 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -52,8 +52,6 @@ static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) u32 mask = 0; for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; if (!cd->clkdm) continue; /* only happens if data is erroneous */ @@ -98,8 +96,6 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) u32 mask = 0; for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; if (!cd->clkdm) continue; /* only happens if data is erroneous */ diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c index b43706a..935c7f0 100644 --- a/arch/arm/mach-omap2/clockdomain44xx.c +++ b/arch/arm/mach-omap2/clockdomain44xx.c @@ -52,8 +52,6 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) u32 mask = 0; for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; if (!cd->clkdm) continue; /* only happens if data is erroneous */ diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c new file mode 100644 index 0000000..0ab8e46 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains2420_data.c @@ -0,0 +1,154 @@ +/* + * OMAP2420 clockdomains + * + * Copyright (C) 2008-2011 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley, Jouni Högander + * + * This file contains clockdomains and clockdomain wakeup dependencies + * for OMAP2420 chips. Some notes: + * + * A useful validation rule for struct clockdomain: Any clockdomain + * referenced by a wkdep_srcs must have a dep_bit assigned. So + * wkdep_srcs are really just software-controllable dependencies. + * Non-software-controllable dependencies do exist, but they are not + * encoded below (yet). + * + * 24xx does not support programmable sleep dependencies (SLEEPDEP) + * + * The overly-specific dep_bit names are due to a bit name collision + * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift + * value are the same for all powerdomains: 2 + * + * XXX should dep_bit be a mask, so we can test to see if it is 0 as a + * sanity check? + * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE + */ + +/* + * To-Do List + * -> Port the Sleep/Wakeup dependencies for the domains + * from the Power domain framework + */ + +#include <linux/kernel.h> +#include <linux/io.h> + +#include "clockdomain.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" +#include "prm-regbits-24xx.h" + +/* + * Clockdomain dependencies for wkdeps + * + * XXX Hardware dependencies (e.g., dependencies that cannot be + * changed in software) are not included here yet, but should be. + */ + +/* Wakeup dependency source arrays */ + +/* 2420-specific possible wakeup dependencies */ + +/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */ +static struct clkdm_dep mpu_2420_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "dsp_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { NULL }, +}; + +/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */ +static struct clkdm_dep core_2420_wkdeps[] = { + { .clkdm_name = "dsp_clkdm" }, + { .clkdm_name = "gfx_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { NULL }, +}; + +/* + * 2420-only clockdomains + */ + +static struct clockdomain mpu_2420_clkdm = { + .name = "mpu_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .wkdep_srcs = mpu_2420_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, +}; + +static struct clockdomain iva1_2420_clkdm = { + .name = "iva1_clkdm", + .pwrdm = { .name = "dsp_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, + .wkdep_srcs = dsp_24xx_wkdeps, + .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, +}; + +static struct clockdomain dsp_2420_clkdm = { + .name = "dsp_clkdm", + .pwrdm = { .name = "dsp_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, +}; + +static struct clockdomain gfx_2420_clkdm = { + .name = "gfx_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .wkdep_srcs = gfx_24xx_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, +}; + +static struct clockdomain core_l3_2420_clkdm = { + .name = "core_l3_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .wkdep_srcs = core_2420_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, +}; + +static struct clockdomain core_l4_2420_clkdm = { + .name = "core_l4_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .wkdep_srcs = core_2420_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, +}; + +static struct clockdomain dss_2420_clkdm = { + .name = "dss_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, +}; + +static struct clockdomain *clockdomains_omap242x[] __initdata = { + &wkup_common_clkdm, + &cm_common_clkdm, + &prm_common_clkdm, + &mpu_2420_clkdm, + &iva1_2420_clkdm, + &dsp_2420_clkdm, + &gfx_2420_clkdm, + &core_l3_2420_clkdm, + &core_l4_2420_clkdm, + &dss_2420_clkdm, + NULL, +}; + +void __init omap242x_clockdomains_init(void) +{ + if (!cpu_is_omap242x()) + return; + + clkdm_register_platform_funcs(&omap2_clkdm_operations); + clkdm_register_clkdms(clockdomains_omap242x); + clkdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c new file mode 100644 index 0000000..3645ed0 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains2430_data.c @@ -0,0 +1,181 @@ +/* + * OMAP2xxx clockdomains + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley, Jouni Högander + * + * This file contains clockdomains and clockdomain wakeup dependencies + * for OMAP2xxx chips. Some notes: + * + * A useful validation rule for struct clockdomain: Any clockdomain + * referenced by a wkdep_srcs must have a dep_bit assigned. So + * wkdep_srcs are really just software-controllable dependencies. + * Non-software-controllable dependencies do exist, but they are not + * encoded below (yet). + * + * 24xx does not support programmable sleep dependencies (SLEEPDEP) + * + * The overly-specific dep_bit names are due to a bit name collision + * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift + * value are the same for all powerdomains: 2 + * + * XXX should dep_bit be a mask, so we can test to see if it is 0 as a + * sanity check? + * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE + */ + +/* + * To-Do List + * -> Port the Sleep/Wakeup dependencies for the domains + * from the Power domain framework + */ + +#include <linux/kernel.h> +#include <linux/io.h> + +#include "clockdomain.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" +#include "prm-regbits-24xx.h" + +/* + * Clockdomain dependencies for wkdeps + * + * XXX Hardware dependencies (e.g., dependencies that cannot be + * changed in software) are not included here yet, but should be. + */ + +/* Wakeup dependency source arrays */ + +/* 2430-specific possible wakeup dependencies */ + +/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */ +static struct clkdm_dep core_2430_wkdeps[] = { + { .clkdm_name = "dsp_clkdm" }, + { .clkdm_name = "gfx_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { .clkdm_name = "mdm_clkdm" }, + { NULL }, +}; + +/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */ +static struct clkdm_dep mpu_2430_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "dsp_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { .clkdm_name = "mdm_clkdm" }, + { NULL }, +}; + +/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ +static struct clkdm_dep mdm_2430_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { NULL }, +}; + +/* + * 2430-only clockdomains + */ + +static struct clockdomain mpu_2430_clkdm = { + .name = "mpu_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .wkdep_srcs = mpu_2430_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, +}; + +/* Another case of bit name collisions between several registers: EN_MDM */ +static struct clockdomain mdm_clkdm = { + .name = "mdm_clkdm", + .pwrdm = { .name = "mdm_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, + .wkdep_srcs = mdm_2430_wkdeps, + .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, +}; + +static struct clockdomain dsp_2430_clkdm = { + .name = "dsp_clkdm", + .pwrdm = { .name = "dsp_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, + .wkdep_srcs = dsp_24xx_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, +}; + +static struct clockdomain gfx_2430_clkdm = { + .name = "gfx_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .wkdep_srcs = gfx_24xx_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, +}; + +/* + * XXX add usecounting for clkdm dependencies, otherwise the presence + * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm + * could cause trouble + */ +static struct clockdomain core_l3_2430_clkdm = { + .name = "core_l3_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .dep_bit = OMAP24XX_EN_CORE_SHIFT, + .wkdep_srcs = core_2430_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, +}; + +/* + * XXX add usecounting for clkdm dependencies, otherwise the presence + * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm + * could cause trouble + */ +static struct clockdomain core_l4_2430_clkdm = { + .name = "core_l4_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .dep_bit = OMAP24XX_EN_CORE_SHIFT, + .wkdep_srcs = core_2430_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, +}; + +static struct clockdomain dss_2430_clkdm = { + .name = "dss_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, +}; + +static struct clockdomain *clockdomains_omap243x[] __initdata = { + &wkup_common_clkdm, + &cm_common_clkdm, + &prm_common_clkdm, + &mpu_2430_clkdm, + &mdm_clkdm, + &dsp_2430_clkdm, + &gfx_2430_clkdm, + &core_l3_2430_clkdm, + &core_l4_2430_clkdm, + &dss_2430_clkdm, + NULL, +}; + +void __init omap243x_clockdomains_init(void) +{ + if (!cpu_is_omap243x()) + return; + + clkdm_register_platform_funcs(&omap2_clkdm_operations); + clkdm_register_clkdms(clockdomains_omap243x); + clkdm_complete_init(); +} + diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 13bde95..0a6a048 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -1,7 +1,7 @@ /* - * OMAP2/3 clockdomains + * OMAP2/3 clockdomain common data * - * Copyright (C) 2008-2009 Texas Instruments, Inc. + * Copyright (C) 2008-2011 Texas Instruments, Inc. * Copyright (C) 2008-2010 Nokia Corporation * * Paul Walmsley, Jouni Högander @@ -51,374 +51,28 @@ * changed in software) are not included here yet, but should be. */ -/* OMAP2/3-common wakeup dependencies */ - -/* - * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP - * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE - * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE - * These can share data since they will never be present simultaneously - * on the same device. - */ -static struct clkdm_dep gfx_sgx_wkdeps[] = { - { - .clkdm_name = "core_l3_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "core_l4_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | - CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | - CHIP_IS_OMAP3430) - }, - { NULL }, -}; - - -/* 24XX-specific possible dependencies */ - -#ifdef CONFIG_ARCH_OMAP2 - /* Wakeup dependency source arrays */ -/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ -static struct clkdm_dep dsp_24xx_wkdeps[] = { - { - .clkdm_name = "core_l3_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "core_l4_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { NULL }, -}; - -/* - * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP - * 2430 adds MDM - */ -static struct clkdm_dep mpu_24xx_wkdeps[] = { - { - .clkdm_name = "core_l3_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "core_l4_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "dsp_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "mdm_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }, - { NULL }, -}; - -/* - * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP - * 2430 adds MDM - */ -static struct clkdm_dep core_24xx_wkdeps[] = { - { - .clkdm_name = "dsp_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "gfx_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "mdm_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }, - { NULL }, -}; - -#endif /* CONFIG_ARCH_OMAP2 */ - -/* 2430-specific possible wakeup dependencies */ +/* 2xxx-specific possible dependencies */ -#ifdef CONFIG_SOC_OMAP2430 - -/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ -static struct clkdm_dep mdm_2430_wkdeps[] = { - { - .clkdm_name = "core_l3_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "core_l4_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { NULL }, -}; - -#endif /* CONFIG_SOC_OMAP2430 */ - - -/* OMAP3-specific possible dependencies */ - -#ifdef CONFIG_ARCH_OMAP3 - -/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ -static struct clkdm_dep per_wkdeps[] = { - { - .clkdm_name = "core_l3_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "core_l4_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ -static struct clkdm_dep usbhost_wkdeps[] = { - { - .clkdm_name = "core_l3_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "core_l4_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, +/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */ +struct clkdm_dep gfx_24xx_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, { NULL }, }; -/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ -static struct clkdm_dep mpu_3xxx_wkdeps[] = { - { - .clkdm_name = "core_l3_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "core_l4_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "dss_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, +/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */ +struct clkdm_dep dsp_24xx_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, { NULL }, }; -/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ -static struct clkdm_dep iva2_wkdeps[] = { - { - .clkdm_name = "core_l3_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "core_l4_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "dss_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - - -/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */ -static struct clkdm_dep cam_wkdeps[] = { - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */ -static struct clkdm_dep dss_wkdeps[] = { - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* 3430: PM_WKDEP_NEON: MPU */ -static struct clkdm_dep neon_wkdeps[] = { - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - - -/* Sleep dependency source arrays for OMAP3-specific clkdms */ - -/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */ -static struct clkdm_dep dss_sleepdeps[] = { - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* 3430: CM_SLEEPDEP_PER: MPU, IVA */ -static struct clkdm_dep per_sleepdeps[] = { - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ -static struct clkdm_dep usbhost_sleepdeps[] = { - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm_name = "iva2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* 3430: CM_SLEEPDEP_CAM: MPU */ -static struct clkdm_dep cam_sleepdeps[] = { - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* - * 3430ES1: CM_SLEEPDEP_GFX: MPU - * 3430ES2: CM_SLEEPDEP_SGX: MPU - * These can share data since they will never be present simultaneously - * on the same device. - */ -static struct clkdm_dep gfx_sgx_sleepdeps[] = { - { - .clkdm_name = "mpu_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -#endif /* CONFIG_ARCH_OMAP3 */ - /* * OMAP2/3-common clockdomains @@ -430,439 +84,18 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = { */ /* This is an implicit clockdomain - it is never defined as such in TRM */ -static struct clockdomain wkup_clkdm = { +struct clockdomain wkup_common_clkdm = { .name = "wkup_clkdm", .pwrdm = { .name = "wkup_pwrdm" }, .dep_bit = OMAP_EN_WKUP_SHIFT, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), }; -static struct clockdomain prm_clkdm = { +struct clockdomain prm_common_clkdm = { .name = "prm_clkdm", .pwrdm = { .name = "wkup_pwrdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), }; -static struct clockdomain cm_clkdm = { +struct clockdomain cm_common_clkdm = { .name = "cm_clkdm", .pwrdm = { .name = "core_pwrdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), }; - -/* - * 2420-only clockdomains - */ - -#if defined(CONFIG_SOC_OMAP2420) - -static struct clockdomain mpu_2420_clkdm = { - .name = "mpu_clkdm", - .pwrdm = { .name = "mpu_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .wkdep_srcs = mpu_24xx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -static struct clockdomain iva1_2420_clkdm = { - .name = "iva1_clkdm", - .pwrdm = { .name = "dsp_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, - .wkdep_srcs = dsp_24xx_wkdeps, - .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -static struct clockdomain dsp_2420_clkdm = { - .name = "dsp_clkdm", - .pwrdm = { .name = "dsp_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -static struct clockdomain gfx_2420_clkdm = { - .name = "gfx_clkdm", - .pwrdm = { .name = "gfx_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .wkdep_srcs = gfx_sgx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -static struct clockdomain core_l3_2420_clkdm = { - .name = "core_l3_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .wkdep_srcs = core_24xx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -static struct clockdomain core_l4_2420_clkdm = { - .name = "core_l4_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .wkdep_srcs = core_24xx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -static struct clockdomain dss_2420_clkdm = { - .name = "dss_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -}; - -#endif /* CONFIG_SOC_OMAP2420 */ - - -/* - * 2430-only clockdomains - */ - -#if defined(CONFIG_SOC_OMAP2430) - -static struct clockdomain mpu_2430_clkdm = { - .name = "mpu_clkdm", - .pwrdm = { .name = "mpu_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .wkdep_srcs = mpu_24xx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -/* Another case of bit name collisions between several registers: EN_MDM */ -static struct clockdomain mdm_clkdm = { - .name = "mdm_clkdm", - .pwrdm = { .name = "mdm_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, - .wkdep_srcs = mdm_2430_wkdeps, - .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -static struct clockdomain dsp_2430_clkdm = { - .name = "dsp_clkdm", - .pwrdm = { .name = "dsp_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, - .wkdep_srcs = dsp_24xx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -static struct clockdomain gfx_2430_clkdm = { - .name = "gfx_clkdm", - .pwrdm = { .name = "gfx_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .wkdep_srcs = gfx_sgx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -/* - * XXX add usecounting for clkdm dependencies, otherwise the presence - * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm - * could cause trouble - */ -static struct clockdomain core_l3_2430_clkdm = { - .name = "core_l3_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .dep_bit = OMAP24XX_EN_CORE_SHIFT, - .wkdep_srcs = core_24xx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -/* - * XXX add usecounting for clkdm dependencies, otherwise the presence - * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm - * could cause trouble - */ -static struct clockdomain core_l4_2430_clkdm = { - .name = "core_l4_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .dep_bit = OMAP24XX_EN_CORE_SHIFT, - .wkdep_srcs = core_24xx_wkdeps, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -static struct clockdomain dss_2430_clkdm = { - .name = "dss_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -}; - -#endif /* CONFIG_SOC_OMAP2430 */ - - -/* - * OMAP3 clockdomains - */ - -#if defined(CONFIG_ARCH_OMAP3) - -static struct clockdomain mpu_3xxx_clkdm = { - .name = "mpu_clkdm", - .pwrdm = { .name = "mpu_pwrdm" }, - .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, - .dep_bit = OMAP3430_EN_MPU_SHIFT, - .wkdep_srcs = mpu_3xxx_wkdeps, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain neon_clkdm = { - .name = "neon_clkdm", - .pwrdm = { .name = "neon_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .wkdep_srcs = neon_wkdeps, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain iva2_clkdm = { - .name = "iva2_clkdm", - .pwrdm = { .name = "iva2_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, - .wkdep_srcs = iva2_wkdeps, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain gfx_3430es1_clkdm = { - .name = "gfx_clkdm", - .pwrdm = { .name = "gfx_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .wkdep_srcs = gfx_sgx_wkdeps, - .sleepdep_srcs = gfx_sgx_sleepdeps, - .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), -}; - -static struct clockdomain sgx_clkdm = { - .name = "sgx_clkdm", - .pwrdm = { .name = "sgx_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .wkdep_srcs = gfx_sgx_wkdeps, - .sleepdep_srcs = gfx_sgx_sleepdeps, - .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), -}; - -/* - * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but - * then that information was removed from the 34xx ES2+ TRM. It is - * unclear whether the core is still there, but the clockdomain logic - * is there, and must be programmed to an appropriate state if the - * CORE clockdomain is to become inactive. - */ -static struct clockdomain d2d_clkdm = { - .name = "d2d_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -/* - * XXX add usecounting for clkdm dependencies, otherwise the presence - * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm - * could cause trouble - */ -static struct clockdomain core_l3_3xxx_clkdm = { - .name = "core_l3_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .dep_bit = OMAP3430_EN_CORE_SHIFT, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -/* - * XXX add usecounting for clkdm dependencies, otherwise the presence - * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm - * could cause trouble - */ -static struct clockdomain core_l4_3xxx_clkdm = { - .name = "core_l4_clkdm", - .pwrdm = { .name = "core_pwrdm" }, - .flags = CLKDM_CAN_HWSUP, - .dep_bit = OMAP3430_EN_CORE_SHIFT, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -/* Another case of bit name collisions between several registers: EN_DSS */ -static struct clockdomain dss_3xxx_clkdm = { - .name = "dss_clkdm", - .pwrdm = { .name = "dss_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, - .wkdep_srcs = dss_wkdeps, - .sleepdep_srcs = dss_sleepdeps, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain cam_clkdm = { - .name = "cam_clkdm", - .pwrdm = { .name = "cam_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .wkdep_srcs = cam_wkdeps, - .sleepdep_srcs = cam_sleepdeps, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain usbhost_clkdm = { - .name = "usbhost_clkdm", - .pwrdm = { .name = "usbhost_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .wkdep_srcs = usbhost_wkdeps, - .sleepdep_srcs = usbhost_sleepdeps, - .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), -}; - -static struct clockdomain per_clkdm = { - .name = "per_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .flags = CLKDM_CAN_HWSUP_SWSUP, - .dep_bit = OMAP3430_EN_PER_SHIFT, - .wkdep_srcs = per_wkdeps, - .sleepdep_srcs = per_sleepdeps, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -/* - * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is - * switched of even if sdti is in use - */ -static struct clockdomain emu_clkdm = { - .name = "emu_clkdm", - .pwrdm = { .name = "emu_pwrdm" }, - .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, - .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain dpll1_clkdm = { - .name = "dpll1_clkdm", - .pwrdm = { .name = "dpll1_pwrdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain dpll2_clkdm = { - .name = "dpll2_clkdm", - .pwrdm = { .name = "dpll2_pwrdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain dpll3_clkdm = { - .name = "dpll3_clkdm", - .pwrdm = { .name = "dpll3_pwrdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain dpll4_clkdm = { - .name = "dpll4_clkdm", - .pwrdm = { .name = "dpll4_pwrdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -}; - -static struct clockdomain dpll5_clkdm = { - .name = "dpll5_clkdm", - .pwrdm = { .name = "dpll5_pwrdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), -}; - -#endif /* CONFIG_ARCH_OMAP3 */ - -/* - * Clockdomain hwsup dependencies (OMAP3 only) - */ - -static struct clkdm_autodep clkdm_autodeps[] = { - { - .clkdm = { .name = "mpu_clkdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm = { .name = "iva2_clkdm" }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .clkdm = { .name = NULL }, - } -}; - -static struct clockdomain *clockdomains_omap2[] __initdata = { - &wkup_clkdm, - &cm_clkdm, - &prm_clkdm, - -#ifdef CONFIG_SOC_OMAP2420 - &mpu_2420_clkdm, - &iva1_2420_clkdm, - &dsp_2420_clkdm, - &gfx_2420_clkdm, - &core_l3_2420_clkdm, - &core_l4_2420_clkdm, - &dss_2420_clkdm, -#endif - -#ifdef CONFIG_SOC_OMAP2430 - &mpu_2430_clkdm, - &mdm_clkdm, - &dsp_2430_clkdm, - &gfx_2430_clkdm, - &core_l3_2430_clkdm, - &core_l4_2430_clkdm, - &dss_2430_clkdm, -#endif - -#ifdef CONFIG_ARCH_OMAP3 - &mpu_3xxx_clkdm, - &neon_clkdm, - &iva2_clkdm, - &gfx_3430es1_clkdm, - &sgx_clkdm, - &d2d_clkdm, - &core_l3_3xxx_clkdm, - &core_l4_3xxx_clkdm, - &dss_3xxx_clkdm, - &cam_clkdm, - &usbhost_clkdm, - &per_clkdm, - &emu_clkdm, - &dpll1_clkdm, - &dpll2_clkdm, - &dpll3_clkdm, - &dpll4_clkdm, - &dpll5_clkdm, -#endif - NULL, -}; - -void __init omap2xxx_clockdomains_init(void) -{ - clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations); -} - -void __init omap3xxx_clockdomains_init(void) -{ - clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations); -} diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c new file mode 100644 index 0000000..b84e138 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c @@ -0,0 +1,398 @@ +/* + * OMAP3xxx clockdomains + * + * Copyright (C) 2008-2011 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley, Jouni Högander + * + * This file contains clockdomains and clockdomain wakeup/sleep + * dependencies for the OMAP3xxx chips. Some notes: + * + * A useful validation rule for struct clockdomain: Any clockdomain + * referenced by a wkdep_srcs or sleepdep_srcs array must have a + * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just + * software-controllable dependencies. Non-software-controllable + * dependencies do exist, but they are not encoded below (yet). + * + * The overly-specific dep_bit names are due to a bit name collision + * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift + * value are the same for all powerdomains: 2 + * + * XXX should dep_bit be a mask, so we can test to see if it is 0 as a + * sanity check? + * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE + */ + +/* + * To-Do List + * -> Port the Sleep/Wakeup dependencies for the domains + * from the Power domain framework + */ + +#include <linux/kernel.h> +#include <linux/io.h> + +#include "clockdomain.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-34xx.h" +#include "prm-regbits-34xx.h" + +/* + * Clockdomain dependencies for wkdeps/sleepdeps + * + * XXX Hardware dependencies (e.g., dependencies that cannot be + * changed in software) are not included here yet, but should be. + */ + +/* OMAP3-specific possible dependencies */ + +/* + * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE + * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE + */ +static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = { + { .clkdm_name = "iva2_clkdm", }, + { .clkdm_name = "mpu_clkdm", }, + { .clkdm_name = "wkup_clkdm", }, + { NULL }, +}; + +/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ +static struct clkdm_dep per_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "iva2_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { NULL }, +}; + +/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ +static struct clkdm_dep usbhost_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "iva2_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { NULL }, +}; + +/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ +static struct clkdm_dep mpu_3xxx_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "iva2_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "per_clkdm" }, + { NULL }, +}; + +/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ +static struct clkdm_dep iva2_wkdeps[] = { + { .clkdm_name = "core_l3_clkdm" }, + { .clkdm_name = "core_l4_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "per_clkdm" }, + { NULL }, +}; + +/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */ +static struct clkdm_dep cam_wkdeps[] = { + { .clkdm_name = "iva2_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { NULL }, +}; + +/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */ +static struct clkdm_dep dss_wkdeps[] = { + { .clkdm_name = "iva2_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, + { NULL }, +}; + +/* 3430: PM_WKDEP_NEON: MPU */ +static struct clkdm_dep neon_wkdeps[] = { + { .clkdm_name = "mpu_clkdm" }, + { NULL }, +}; + +/* Sleep dependency source arrays for OMAP3-specific clkdms */ + +/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */ +static struct clkdm_dep dss_sleepdeps[] = { + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "iva2_clkdm" }, + { NULL }, +}; + +/* 3430: CM_SLEEPDEP_PER: MPU, IVA */ +static struct clkdm_dep per_sleepdeps[] = { + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "iva2_clkdm" }, + { NULL }, +}; + +/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ +static struct clkdm_dep usbhost_sleepdeps[] = { + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "iva2_clkdm" }, + { NULL }, +}; + +/* 3430: CM_SLEEPDEP_CAM: MPU */ +static struct clkdm_dep cam_sleepdeps[] = { + { .clkdm_name = "mpu_clkdm" }, + { NULL }, +}; + +/* + * 3430ES1: CM_SLEEPDEP_GFX: MPU + * 3430ES2: CM_SLEEPDEP_SGX: MPU + * These can share data since they will never be present simultaneously + * on the same device. + */ +static struct clkdm_dep gfx_sgx_sleepdeps[] = { + { .clkdm_name = "mpu_clkdm" }, + { NULL }, +}; + +/* + * OMAP3 clockdomains + */ + +static struct clockdomain mpu_3xxx_clkdm = { + .name = "mpu_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, + .dep_bit = OMAP3430_EN_MPU_SHIFT, + .wkdep_srcs = mpu_3xxx_wkdeps, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, +}; + +static struct clockdomain neon_clkdm = { + .name = "neon_clkdm", + .pwrdm = { .name = "neon_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .wkdep_srcs = neon_wkdeps, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, +}; + +static struct clockdomain iva2_clkdm = { + .name = "iva2_clkdm", + .pwrdm = { .name = "iva2_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, + .wkdep_srcs = iva2_wkdeps, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, +}; + +static struct clockdomain gfx_3430es1_clkdm = { + .name = "gfx_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .wkdep_srcs = gfx_sgx_3xxx_wkdeps, + .sleepdep_srcs = gfx_sgx_sleepdeps, + .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, +}; + +static struct clockdomain sgx_clkdm = { + .name = "sgx_clkdm", + .pwrdm = { .name = "sgx_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .wkdep_srcs = gfx_sgx_3xxx_wkdeps, + .sleepdep_srcs = gfx_sgx_sleepdeps, + .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, +}; + +/* + * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but + * then that information was removed from the 34xx ES2+ TRM. It is + * unclear whether the core is still there, but the clockdomain logic + * is there, and must be programmed to an appropriate state if the + * CORE clockdomain is to become inactive. + */ +static struct clockdomain d2d_clkdm = { + .name = "d2d_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, +}; + +/* + * XXX add usecounting for clkdm dependencies, otherwise the presence + * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm + * could cause trouble + */ +static struct clockdomain core_l3_3xxx_clkdm = { + .name = "core_l3_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .dep_bit = OMAP3430_EN_CORE_SHIFT, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, +}; + +/* + * XXX add usecounting for clkdm dependencies, otherwise the presence + * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm + * could cause trouble + */ +static struct clockdomain core_l4_3xxx_clkdm = { + .name = "core_l4_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .dep_bit = OMAP3430_EN_CORE_SHIFT, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, +}; + +/* Another case of bit name collisions between several registers: EN_DSS */ +static struct clockdomain dss_3xxx_clkdm = { + .name = "dss_clkdm", + .pwrdm = { .name = "dss_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, + .wkdep_srcs = dss_wkdeps, + .sleepdep_srcs = dss_sleepdeps, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, +}; + +static struct clockdomain cam_clkdm = { + .name = "cam_clkdm", + .pwrdm = { .name = "cam_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .wkdep_srcs = cam_wkdeps, + .sleepdep_srcs = cam_sleepdeps, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, +}; + +static struct clockdomain usbhost_clkdm = { + .name = "usbhost_clkdm", + .pwrdm = { .name = "usbhost_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .wkdep_srcs = usbhost_wkdeps, + .sleepdep_srcs = usbhost_sleepdeps, + .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, +}; + +static struct clockdomain per_clkdm = { + .name = "per_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .dep_bit = OMAP3430_EN_PER_SHIFT, + .wkdep_srcs = per_wkdeps, + .sleepdep_srcs = per_sleepdeps, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, +}; + +/* + * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is + * switched of even if sdti is in use + */ +static struct clockdomain emu_clkdm = { + .name = "emu_clkdm", + .pwrdm = { .name = "emu_pwrdm" }, + .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, + .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, +}; + +static struct clockdomain dpll1_clkdm = { + .name = "dpll1_clkdm", + .pwrdm = { .name = "dpll1_pwrdm" }, +}; + +static struct clockdomain dpll2_clkdm = { + .name = "dpll2_clkdm", + .pwrdm = { .name = "dpll2_pwrdm" }, +}; + +static struct clockdomain dpll3_clkdm = { + .name = "dpll3_clkdm", + .pwrdm = { .name = "dpll3_pwrdm" }, +}; + +static struct clockdomain dpll4_clkdm = { + .name = "dpll4_clkdm", + .pwrdm = { .name = "dpll4_pwrdm" }, +}; + +static struct clockdomain dpll5_clkdm = { + .name = "dpll5_clkdm", + .pwrdm = { .name = "dpll5_pwrdm" }, +}; + +/* + * Clockdomain hwsup dependencies + */ + +static struct clkdm_autodep clkdm_autodeps[] = { + { + .clkdm = { .name = "mpu_clkdm" }, + }, + { + .clkdm = { .name = "iva2_clkdm" }, + }, + { + .clkdm = { .name = NULL }, + } +}; + +/* + * + */ + +static struct clockdomain *clockdomains_omap3430_common[] __initdata = { + &wkup_common_clkdm, + &cm_common_clkdm, + &prm_common_clkdm, + &mpu_3xxx_clkdm, + &neon_clkdm, + &iva2_clkdm, + &d2d_clkdm, + &core_l3_3xxx_clkdm, + &core_l4_3xxx_clkdm, + &dss_3xxx_clkdm, + &cam_clkdm, + &per_clkdm, + &emu_clkdm, + &dpll1_clkdm, + &dpll2_clkdm, + &dpll3_clkdm, + &dpll4_clkdm, + NULL +}; + +static struct clockdomain *clockdomains_omap3430es1[] __initdata = { + &gfx_3430es1_clkdm, + NULL, +}; + +static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = { + &sgx_clkdm, + &dpll5_clkdm, + &usbhost_clkdm, + NULL, +}; + +void __init omap3xxx_clockdomains_init(void) +{ + struct clockdomain **sc; + + if (!cpu_is_omap34xx()) + return; + + clkdm_register_platform_funcs(&omap3_clkdm_operations); + clkdm_register_clkdms(clockdomains_omap3430_common); + + sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 : + clockdomains_omap3430es2plus; + + clkdm_register_clkdms(sc); + + clkdm_register_autodeps(clkdm_autodeps); + clkdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index dccc651..9299ac2 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -34,350 +34,122 @@ /* Static Dependencies for OMAP4 Clock Domains */ static struct clkdm_dep d2d_wkup_sleep_deps[] = { - { - .clkdm_name = "abe_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_init_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_cfg_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_2_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, + { .clkdm_name = "l3_init_clkdm" }, + { .clkdm_name = "l4_cfg_clkdm" }, + { .clkdm_name = "l4_per_clkdm" }, { NULL }, }; static struct clkdm_dep ducati_wkup_sleep_deps[] = { - { - .clkdm_name = "abe_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_dss_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_gfx_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_init_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_cfg_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_secure_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "tesla_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_2_clkdm" }, + { .clkdm_name = "l3_dss_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, + { .clkdm_name = "l3_gfx_clkdm" }, + { .clkdm_name = "l3_init_clkdm" }, + { .clkdm_name = "l4_cfg_clkdm" }, + { .clkdm_name = "l4_per_clkdm" }, + { .clkdm_name = "l4_secure_clkdm" }, + { .clkdm_name = "l4_wkup_clkdm" }, + { .clkdm_name = "tesla_clkdm" }, { NULL }, }; static struct clkdm_dep iss_wkup_sleep_deps[] = { - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, { NULL }, }; static struct clkdm_dep ivahd_wkup_sleep_deps[] = { - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, { NULL }, }; static struct clkdm_dep l3_dma_wkup_sleep_deps[] = { - { - .clkdm_name = "abe_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "ducati_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_dss_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_init_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_cfg_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_secure_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "ducati_clkdm" }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_dss_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, + { .clkdm_name = "l3_init_clkdm" }, + { .clkdm_name = "l4_cfg_clkdm" }, + { .clkdm_name = "l4_per_clkdm" }, + { .clkdm_name = "l4_secure_clkdm" }, + { .clkdm_name = "l4_wkup_clkdm" }, { NULL }, }; static struct clkdm_dep l3_dss_wkup_sleep_deps[] = { - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_2_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, { NULL }, }; static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = { - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, { NULL }, }; static struct clkdm_dep l3_init_wkup_sleep_deps[] = { - { - .clkdm_name = "abe_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_cfg_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_secure_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, + { .clkdm_name = "l4_cfg_clkdm" }, + { .clkdm_name = "l4_per_clkdm" }, + { .clkdm_name = "l4_secure_clkdm" }, + { .clkdm_name = "l4_wkup_clkdm" }, { NULL }, }; static struct clkdm_dep l4_secure_wkup_sleep_deps[] = { - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, + { .clkdm_name = "l4_per_clkdm" }, { NULL }, }; static struct clkdm_dep mpu_wkup_sleep_deps[] = { - { - .clkdm_name = "abe_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "ducati_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_dss_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_gfx_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_init_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_cfg_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_secure_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "tesla_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "ducati_clkdm" }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_2_clkdm" }, + { .clkdm_name = "l3_dss_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, + { .clkdm_name = "l3_gfx_clkdm" }, + { .clkdm_name = "l3_init_clkdm" }, + { .clkdm_name = "l4_cfg_clkdm" }, + { .clkdm_name = "l4_per_clkdm" }, + { .clkdm_name = "l4_secure_clkdm" }, + { .clkdm_name = "l4_wkup_clkdm" }, + { .clkdm_name = "tesla_clkdm" }, { NULL }, }; static struct clkdm_dep tesla_wkup_sleep_deps[] = { - { - .clkdm_name = "abe_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "ivahd_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_1_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_2_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_emif_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l3_init_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_cfg_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_per_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, - { - .clkdm_name = "l4_wkup_clkdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) - }, + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "ivahd_clkdm" }, + { .clkdm_name = "l3_1_clkdm" }, + { .clkdm_name = "l3_2_clkdm" }, + { .clkdm_name = "l3_emif_clkdm" }, + { .clkdm_name = "l3_init_clkdm" }, + { .clkdm_name = "l4_cfg_clkdm" }, + { .clkdm_name = "l4_per_clkdm" }, + { .clkdm_name = "l4_wkup_clkdm" }, { NULL }, }; @@ -388,7 +160,6 @@ static struct clockdomain l4_cefuse_44xx_clkdm = { .cm_inst = OMAP4430_CM2_CEFUSE_INST, .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l4_cfg_44xx_clkdm = { @@ -399,7 +170,6 @@ static struct clockdomain l4_cfg_44xx_clkdm = { .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain tesla_44xx_clkdm = { @@ -412,7 +182,6 @@ static struct clockdomain tesla_44xx_clkdm = { .wkdep_srcs = tesla_wkup_sleep_deps, .sleepdep_srcs = tesla_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_gfx_44xx_clkdm = { @@ -425,7 +194,6 @@ static struct clockdomain l3_gfx_44xx_clkdm = { .wkdep_srcs = l3_gfx_wkup_sleep_deps, .sleepdep_srcs = l3_gfx_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain ivahd_44xx_clkdm = { @@ -438,7 +206,6 @@ static struct clockdomain ivahd_44xx_clkdm = { .wkdep_srcs = ivahd_wkup_sleep_deps, .sleepdep_srcs = ivahd_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l4_secure_44xx_clkdm = { @@ -451,7 +218,6 @@ static struct clockdomain l4_secure_44xx_clkdm = { .wkdep_srcs = l4_secure_wkup_sleep_deps, .sleepdep_srcs = l4_secure_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l4_per_44xx_clkdm = { @@ -462,7 +228,6 @@ static struct clockdomain l4_per_44xx_clkdm = { .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain abe_44xx_clkdm = { @@ -473,7 +238,6 @@ static struct clockdomain abe_44xx_clkdm = { .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, .dep_bit = OMAP4430_ABE_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_instr_44xx_clkdm = { @@ -482,7 +246,6 @@ static struct clockdomain l3_instr_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CORE_INST, .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_init_44xx_clkdm = { @@ -495,7 +258,6 @@ static struct clockdomain l3_init_44xx_clkdm = { .wkdep_srcs = l3_init_wkup_sleep_deps, .sleepdep_srcs = l3_init_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain d2d_44xx_clkdm = { @@ -507,7 +269,6 @@ static struct clockdomain d2d_44xx_clkdm = { .wkdep_srcs = d2d_wkup_sleep_deps, .sleepdep_srcs = d2d_wkup_sleep_deps, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain mpu0_44xx_clkdm = { @@ -517,7 +278,6 @@ static struct clockdomain mpu0_44xx_clkdm = { .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain mpu1_44xx_clkdm = { @@ -527,7 +287,6 @@ static struct clockdomain mpu1_44xx_clkdm = { .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_emif_44xx_clkdm = { @@ -538,7 +297,6 @@ static struct clockdomain l3_emif_44xx_clkdm = { .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l4_ao_44xx_clkdm = { @@ -548,7 +306,6 @@ static struct clockdomain l4_ao_44xx_clkdm = { .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST, .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain ducati_44xx_clkdm = { @@ -561,7 +318,6 @@ static struct clockdomain ducati_44xx_clkdm = { .wkdep_srcs = ducati_wkup_sleep_deps, .sleepdep_srcs = ducati_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain mpu_44xx_clkdm = { @@ -573,7 +329,6 @@ static struct clockdomain mpu_44xx_clkdm = { .wkdep_srcs = mpu_wkup_sleep_deps, .sleepdep_srcs = mpu_wkup_sleep_deps, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_2_44xx_clkdm = { @@ -584,7 +339,6 @@ static struct clockdomain l3_2_44xx_clkdm = { .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_1_44xx_clkdm = { @@ -595,7 +349,6 @@ static struct clockdomain l3_1_44xx_clkdm = { .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain iss_44xx_clkdm = { @@ -607,7 +360,6 @@ static struct clockdomain iss_44xx_clkdm = { .wkdep_srcs = iss_wkup_sleep_deps, .sleepdep_srcs = iss_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_dss_44xx_clkdm = { @@ -620,7 +372,6 @@ static struct clockdomain l3_dss_44xx_clkdm = { .wkdep_srcs = l3_dss_wkup_sleep_deps, .sleepdep_srcs = l3_dss_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l4_wkup_44xx_clkdm = { @@ -631,7 +382,6 @@ static struct clockdomain l4_wkup_44xx_clkdm = { .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain emu_sys_44xx_clkdm = { @@ -641,7 +391,6 @@ static struct clockdomain emu_sys_44xx_clkdm = { .cm_inst = OMAP4430_PRM_EMU_CM_INST, .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, .flags = CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct clockdomain l3_dma_44xx_clkdm = { @@ -653,7 +402,6 @@ static struct clockdomain l3_dma_44xx_clkdm = { .wkdep_srcs = l3_dma_wkup_sleep_deps, .sleepdep_srcs = l3_dma_wkup_sleep_deps, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* As clockdomains are added or removed above, this list must also be changed */ @@ -685,7 +433,10 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { NULL }; + void __init omap44xx_clockdomains_init(void) { - clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations); + clkdm_register_platform_funcs(&omap4_clkdm_operations); + clkdm_register_clkdms(clockdomains_omap44xx); + clkdm_complete_init(); } diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 3f20cbb..de61f15 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -56,6 +56,12 @@ void __init omap2_set_globals_242x(void) { __omap2_set_globals(&omap242x_globals); } + +void __init omap242x_map_io(void) +{ + omap2_set_globals_242x(); + omap242x_map_common_io(); +} #endif #if defined(CONFIG_SOC_OMAP2430) @@ -74,6 +80,12 @@ void __init omap2_set_globals_243x(void) { __omap2_set_globals(&omap243x_globals); } + +void __init omap243x_map_io(void) +{ + omap2_set_globals_243x(); + omap243x_map_common_io(); +} #endif #if defined(CONFIG_ARCH_OMAP3) @@ -138,5 +150,11 @@ void __init omap2_set_globals_443x(void) omap2_set_globals_control(&omap4_globals); omap2_set_globals_prcm(&omap4_globals); } + +void __init omap4_map_io(void) +{ + omap2_set_globals_443x(); + omap44xx_map_common_io(); +} #endif diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 5391079..406b56c 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -43,7 +43,7 @@ static int __init omap3_l3_init(void) { int l; struct omap_hwmod *oh; - struct omap_device *od; + struct platform_device *pdev; char oh_name[L3_MODULES_MAX_LEN]; /* @@ -60,12 +60,12 @@ static int __init omap3_l3_init(void) if (!oh) pr_err("could not look up %s\n", oh_name); - od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, + pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, NULL, 0, 0); - WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name); + WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); - return IS_ERR(od) ? PTR_ERR(od) : 0; + return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; } postcore_initcall(omap3_l3_init); @@ -73,7 +73,7 @@ static int __init omap4_l3_init(void) { int l, i; struct omap_hwmod *oh[3]; - struct omap_device *od; + struct platform_device *pdev; char oh_name[L3_MODULES_MAX_LEN]; /* @@ -91,12 +91,12 @@ static int __init omap4_l3_init(void) pr_err("could not look up %s\n", oh_name); } - od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, + pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, 0, NULL, 0, 0); - WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name); + WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); - return IS_ERR(od) ? PTR_ERR(od) : 0; + return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; } postcore_initcall(omap4_l3_init); @@ -231,7 +231,7 @@ struct omap_device_pm_latency omap_keyboard_latency[] = { int __init omap4_keyboard_init(struct omap4_keypad_platform_data *sdp4430_keypad_data, struct omap_board_data *bdata) { - struct omap_device *od; + struct platform_device *pdev; struct omap_hwmod *oh; struct omap4_keypad_platform_data *keypad_data; unsigned int id = -1; @@ -246,15 +246,15 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data keypad_data = sdp4430_keypad_data; - od = omap_device_build(name, id, oh, keypad_data, + pdev = omap_device_build(name, id, oh, keypad_data, sizeof(struct omap4_keypad_platform_data), omap_keyboard_latency, ARRAY_SIZE(omap_keyboard_latency), 0); - if (IS_ERR(od)) { + if (IS_ERR(pdev)) { WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); - return PTR_ERR(od); + return PTR_ERR(pdev); } oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); @@ -273,7 +273,7 @@ static struct omap_device_pm_latency mbox_latencies[] = { static inline void omap_init_mbox(void) { struct omap_hwmod *oh; - struct omap_device *od; + struct platform_device *pdev; oh = omap_hwmod_lookup("mailbox"); if (!oh) { @@ -281,10 +281,10 @@ static inline void omap_init_mbox(void) return; } - od = omap_device_build("omap-mailbox", -1, oh, NULL, 0, + pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, mbox_latencies, ARRAY_SIZE(mbox_latencies), 0); - WARN(IS_ERR(od), "%s: could not build device, err %ld\n", - __func__, PTR_ERR(od)); + WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", + __func__, PTR_ERR(pdev)); } #else static inline void omap_init_mbox(void) { } @@ -329,6 +329,38 @@ static void omap_init_audio(void) static inline void omap_init_audio(void) {} #endif +#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ + defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) + +static struct omap_device_pm_latency omap_mcpdm_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +static void omap_init_mcpdm(void) +{ + struct omap_hwmod *oh; + struct omap_device *od; + + oh = omap_hwmod_lookup("mcpdm"); + if (!oh) { + printk(KERN_ERR "Could not look up mcpdm hw_mod\n"); + return; + } + + od = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, + omap_mcpdm_latency, + ARRAY_SIZE(omap_mcpdm_latency), 0); + if (IS_ERR(od)) + printk(KERN_ERR "Could not build omap_device for omap-mcpdm-dai\n"); +} +#else +static inline void omap_init_mcpdm(void) {} +#endif + #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) #include <plat/mcspi.h> @@ -343,7 +375,7 @@ struct omap_device_pm_latency omap_mcspi_latency[] = { static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) { - struct omap_device *od; + struct platform_device *pdev; char *name = "omap2_mcspi"; struct omap2_mcspi_platform_config *pdata; static int spi_num; @@ -370,10 +402,10 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) } spi_num++; - od = omap_device_build(name, spi_num, oh, pdata, + pdev = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata), omap_mcspi_latency, ARRAY_SIZE(omap_mcspi_latency), 0); - WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n", + WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", name, oh->name); kfree(pdata); return 0; @@ -682,6 +714,7 @@ static int __init omap2_init_devices(void) * in alphabetical order so they're easier to sort through. */ omap_init_audio(); + omap_init_mcpdm(); omap_init_camera(); omap_init_mbox(); omap_init_mcspi(); @@ -708,7 +741,7 @@ static struct omap_device_pm_latency omap_wdt_latency[] = { static int __init omap_init_wdt(void) { int id = -1; - struct omap_device *od; + struct platform_device *pdev; struct omap_hwmod *oh; char *oh_name = "wd_timer2"; char *dev_name = "omap_wdt"; @@ -722,10 +755,10 @@ static int __init omap_init_wdt(void) return -EINVAL; } - od = omap_device_build(dev_name, id, oh, NULL, 0, + pdev = omap_device_build(dev_name, id, oh, NULL, 0, omap_wdt_latency, ARRAY_SIZE(omap_wdt_latency), 0); - WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n", + WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", dev_name, oh->name); return 0; } diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index a5b7a23..836f0f7 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -27,6 +27,8 @@ #include <plat/omap_device.h> #include <plat/omap-pm.h> +#include "control.h" + static struct platform_device omap_display_device = { .name = "omapdss", .id = -1, @@ -61,7 +63,7 @@ static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = { { "dss_dispc", "omapdss_dispc", -1 }, { "dss_rfbi", "omapdss_rfbi", -1 }, { "dss_venc", "omapdss_venc", -1 }, - { "dss_dsi1", "omapdss_dsi1", -1 }, + { "dss_dsi1", "omapdss_dsi", 0 }, }; static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = { @@ -69,16 +71,63 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = { { "dss_dispc", "omapdss_dispc", -1 }, { "dss_rfbi", "omapdss_rfbi", -1 }, { "dss_venc", "omapdss_venc", -1 }, - { "dss_dsi1", "omapdss_dsi1", -1 }, - { "dss_dsi2", "omapdss_dsi2", -1 }, + { "dss_dsi1", "omapdss_dsi", 0 }, + { "dss_dsi2", "omapdss_dsi", 1 }, { "dss_hdmi", "omapdss_hdmi", -1 }, }; +static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) +{ + u32 enable_mask, enable_shift; + u32 pipd_mask, pipd_shift; + u32 reg; + + if (dsi_id == 0) { + enable_mask = OMAP4_DSI1_LANEENABLE_MASK; + enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; + pipd_mask = OMAP4_DSI1_PIPD_MASK; + pipd_shift = OMAP4_DSI1_PIPD_SHIFT; + } else if (dsi_id == 1) { + enable_mask = OMAP4_DSI2_LANEENABLE_MASK; + enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; + pipd_mask = OMAP4_DSI2_PIPD_MASK; + pipd_shift = OMAP4_DSI2_PIPD_SHIFT; + } else { + return -ENODEV; + } + + reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); + + reg &= ~enable_mask; + reg &= ~pipd_mask; + + reg |= (lanes << enable_shift) & enable_mask; + reg |= (lanes << pipd_shift) & pipd_mask; + + omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); + + return 0; +} + +static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) +{ + if (cpu_is_omap44xx()) + return omap4_dsi_mux_pads(dsi_id, lane_mask); + + return 0; +} + +static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) +{ + if (cpu_is_omap44xx()) + omap4_dsi_mux_pads(dsi_id, 0); +} + int __init omap_display_init(struct omap_dss_board_info *board_data) { int r = 0; struct omap_hwmod *oh; - struct omap_device *od; + struct platform_device *pdev; int i, oh_count; struct omap_display_platform_data pdata; const struct omap_dss_hwmod_data *curr_dss_hwmod; @@ -96,6 +145,11 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) oh_count = ARRAY_SIZE(omap4_dss_hwmod_data); } + if (board_data->dsi_enable_pads == NULL) + board_data->dsi_enable_pads = omap_dsi_enable_pads; + if (board_data->dsi_disable_pads == NULL) + board_data->dsi_disable_pads = omap_dsi_disable_pads; + pdata.board_data = board_data; pdata.board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count; @@ -108,13 +162,13 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) return -ENODEV; } - od = omap_device_build(curr_dss_hwmod[i].dev_name, + pdev = omap_device_build(curr_dss_hwmod[i].dev_name, curr_dss_hwmod[i].id, oh, &pdata, sizeof(struct omap_display_platform_data), omap_dss_latency, ARRAY_SIZE(omap_dss_latency), 0); - if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n", + if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n", curr_dss_hwmod[i].oh_name)) return -ENODEV; } diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index c9ff0e7..ae8cb3f 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -228,7 +228,7 @@ static u32 configure_dma_errata(void) /* One time initializations */ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) { - struct omap_device *od; + struct platform_device *pdev; struct omap_system_dma_plat_info *p; struct resource *mem; char *name = "omap_dma_system"; @@ -258,23 +258,23 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) p->errata = configure_dma_errata(); - od = omap_device_build(name, 0, oh, p, sizeof(*p), + pdev = omap_device_build(name, 0, oh, p, sizeof(*p), omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); kfree(p); - if (IS_ERR(od)) { + if (IS_ERR(pdev)) { pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, name, oh->name); - return PTR_ERR(od); + return PTR_ERR(pdev); } - mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) { - dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__); + dev_err(&pdev->dev, "%s: no mem resource\n", __func__); return -EINVAL; } dma_base = ioremap(mem->start, resource_size(mem)); if (!dma_base) { - dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__); + dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); return -ENOMEM; } @@ -283,7 +283,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) (d->lch_count), GFP_KERNEL); if (!d->chan) { - dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__); + dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__); return -ENOMEM; } return 0; diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 2765cdc..652ccc5 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -34,7 +34,7 @@ static struct omap_device_pm_latency omap_gpio_latency[] = { static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) { - struct omap_device *od; + struct platform_device *pdev; struct omap_gpio_platform_data *pdata; struct omap_gpio_dev_attr *dev_attr; char *name = "omap_gpio"; @@ -107,19 +107,19 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) return -EINVAL; } - od = omap_device_build(name, id - 1, oh, pdata, + pdev = omap_device_build(name, id - 1, oh, pdata, sizeof(*pdata), omap_gpio_latency, ARRAY_SIZE(omap_gpio_latency), false); kfree(pdata); - if (IS_ERR(od)) { + if (IS_ERR(pdev)) { WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); - return PTR_ERR(od); + return PTR_ERR(pdev); } - omap_device_disable_idle_on_suspend(od); + omap_device_disable_idle_on_suspend(pdev); gpio_bank_count++; return 0; diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index a9b45c7..2dc002a 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -137,8 +137,7 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, */ reg = omap4_ctrl_pad_readl(control_pbias_offset); reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + OMAP4_MMC1_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); } @@ -156,8 +155,7 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, else reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + OMAP4_MMC1_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); timeout = jiffies + msecs_to_jiffies(5); @@ -171,16 +169,14 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { pr_err("Pbias Voltage is not same as LDO\n"); /* Caution : On VMODE_ERROR Power Down MMC IO */ - reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); } } else { reg = omap4_ctrl_pad_readl(control_pbias_offset); reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_MMC1_PBIASLITE_VMODE_MASK | - OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + OMAP4_MMC1_PBIASLITE_VMODE_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); } } @@ -430,7 +426,7 @@ static struct omap_device_pm_latency omap_hsmmc_latency[] = { void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) { struct omap_hwmod *oh; - struct omap_device *od; + struct platform_device *pdev; struct omap_device_pm_latency *ohl; char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; struct omap_mmc_platform_data *mmc_data; @@ -471,9 +467,9 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) mmc_data->controller_flags = mmc_dev_attr->flags; } - od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, + pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); - if (IS_ERR(od)) { + if (IS_ERR(pdev)) { WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); kfree(mmc_data->slots[0].name); goto done; @@ -482,7 +478,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) * return device handle to board setup code * required to populate for regulator framework structure */ - hsmmcinfo->dev = &od->pdev.dev; + hsmmcinfo->dev = &pdev->dev; done: kfree(mmc_data); diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c index 06d4a80..0b3ae9d 100644 --- a/arch/arm/mach-omap2/hwspinlock.c +++ b/arch/arm/mach-omap2/hwspinlock.c @@ -35,7 +35,7 @@ int __init hwspinlocks_init(void) { int retval = 0; struct omap_hwmod *oh; - struct omap_device *od; + struct platform_device *pdev; const char *oh_name = "spinlock"; const char *dev_name = "omap_hwspinlock"; @@ -48,13 +48,13 @@ int __init hwspinlocks_init(void) if (oh == NULL) return -EINVAL; - od = omap_device_build(dev_name, 0, oh, NULL, 0, + pdev = omap_device_build(dev_name, 0, oh, NULL, 0, omap_spinlock_latency, ARRAY_SIZE(omap_spinlock_latency), false); - if (IS_ERR(od)) { + if (IS_ERR(pdev)) { pr_err("Can't build omap_device for %s:%s\n", dev_name, oh_name); - retval = PTR_ERR(od); + retval = PTR_ERR(pdev); } return retval; diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37efb86..d27daf9 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -28,7 +28,6 @@ #include "control.h" -static struct omap_chip_id omap_chip; static unsigned int omap_revision; u32 omap_features; @@ -39,19 +38,6 @@ unsigned int omap_rev(void) } EXPORT_SYMBOL(omap_rev); -/** - * omap_chip_is - test whether currently running OMAP matches a chip type - * @oc: omap_chip_t to test against - * - * Test whether the currently-running OMAP chip matches the supplied - * chip type 'oc'. Returns 1 upon a match; 0 upon failure. - */ -int omap_chip_is(struct omap_chip_id oci) -{ - return (oci.oc & omap_chip.oc) ? 1 : 0; -} -EXPORT_SYMBOL(omap_chip_is); - int omap_type(void) { u32 val = 0; @@ -242,14 +228,12 @@ static void __init ti816x_check_features(void) omap_features = OMAP3_HAS_NEON; } -static void __init omap3_check_revision(void) +static void __init omap3_check_revision(const char **cpu_rev) { u32 cpuid, idcode; u16 hawkeye; u8 rev; - omap_chip.oc = CHIP_IS_OMAP3430; - /* * We cannot access revision registers on ES1.0. * If the processor type is Cortex-A8 and the revision is 0x0 @@ -258,7 +242,7 @@ static void __init omap3_check_revision(void) cpuid = read_cpuid(CPUID_ID); if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { omap_revision = OMAP3430_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP3430ES1; + *cpu_rev = "1.0"; return; } @@ -279,77 +263,85 @@ static void __init omap3_check_revision(void) case 0: /* Take care of early samples */ case 1: omap_revision = OMAP3430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP3430ES2; + *cpu_rev = "2.0"; break; case 2: omap_revision = OMAP3430_REV_ES2_1; - omap_chip.oc |= CHIP_IS_OMAP3430ES2; + *cpu_rev = "2.1"; break; case 3: omap_revision = OMAP3430_REV_ES3_0; - omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; + *cpu_rev = "3.0"; break; case 4: omap_revision = OMAP3430_REV_ES3_1; - omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; + *cpu_rev = "3.1"; break; case 7: /* FALLTHROUGH */ default: /* Use the latest known revision as default */ omap_revision = OMAP3430_REV_ES3_1_2; - - /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */ - omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; + *cpu_rev = "3.1.2"; } break; case 0xb868: - /* Handle OMAP35xx/AM35xx devices + /* + * Handle OMAP/AM 3505/3517 devices * - * Set the device to be OMAP3505 here. Actual device + * Set the device to be OMAP3517 here. Actual device * is identified later based on the features. - * - * REVISIT: AM3505/AM3517 should have their own CHIP_IS */ - omap_revision = OMAP3505_REV(rev); - omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; + switch (rev) { + case 0: + omap_revision = OMAP3517_REV_ES1_0; + *cpu_rev = "1.0"; + break; + case 1: + /* FALLTHROUGH */ + default: + omap_revision = OMAP3517_REV_ES1_1; + *cpu_rev = "1.1"; + } break; case 0xb891: /* Handle 36xx devices */ - omap_chip.oc |= CHIP_IS_OMAP3630ES1; switch(rev) { case 0: /* Take care of early samples */ omap_revision = OMAP3630_REV_ES1_0; + *cpu_rev = "1.0"; break; case 1: omap_revision = OMAP3630_REV_ES1_1; - omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + *cpu_rev = "1.1"; break; case 2: + /* FALLTHROUGH */ default: - omap_revision = OMAP3630_REV_ES1_2; - omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + omap_revision = OMAP3630_REV_ES1_2; + *cpu_rev = "1.2"; } break; case 0xb81e: - omap_chip.oc = CHIP_IS_TI816X; - switch (rev) { case 0: omap_revision = TI8168_REV_ES1_0; + *cpu_rev = "1.0"; break; case 1: + /* FALLTHROUGH */ + default: omap_revision = TI8168_REV_ES1_1; + *cpu_rev = "1.1"; break; - default: - omap_revision = TI8168_REV_ES1_1; } break; default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_2; - omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + /* Unknown default to latest silicon rev as default */ + omap_revision = OMAP3630_REV_ES1_2; + *cpu_rev = "1.2"; + pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); } } @@ -382,24 +374,20 @@ static void __init omap4_check_revision(void) switch (rev) { case 0: omap_revision = OMAP4430_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES1; break; case 1: default: omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; } break; case 0xb95c: switch (rev) { case 3: omap_revision = OMAP4430_REV_ES2_1; - omap_chip.oc |= CHIP_IS_OMAP4430ES2_1; break; case 4: default: omap_revision = OMAP4430_REV_ES2_2; - omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; } break; case 0xb94e: @@ -407,14 +395,12 @@ static void __init omap4_check_revision(void) case 0: default: omap_revision = OMAP4460_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP4460ES1_0; break; } break; default: /* Unknown default to latest silicon rev as default */ omap_revision = OMAP4430_REV_ES2_2; - omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; } pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, @@ -425,94 +411,33 @@ static void __init omap4_check_revision(void) if (omap3_has_ ##feat()) \ printk(#feat" "); -static void __init omap3_cpuinfo(void) +static void __init omap3_cpuinfo(const char *cpu_rev) { - u8 rev = GET_OMAP_REVISION(); - char cpu_name[16], cpu_rev[16]; + const char *cpu_name; - /* OMAP3430 and OMAP3530 are assumed to be same. + /* + * OMAP3430 and OMAP3530 are assumed to be same. * * OMAP3525, OMAP3515 and OMAP3503 can be detected only based * on available features. Upon detection, update the CPU id * and CPU class bits. */ if (cpu_is_omap3630()) { - strcpy(cpu_name, "OMAP3630"); - } else if (cpu_is_omap3505()) { - /* - * AM35xx devices - */ - if (omap3_has_sgx()) { - omap_revision = OMAP3517_REV(rev); - strcpy(cpu_name, "AM3517"); - } else { - /* Already set in omap3_check_revision() */ - strcpy(cpu_name, "AM3505"); - } + cpu_name = "OMAP3630"; + } else if (cpu_is_omap3517()) { + /* AM35xx devices */ + cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; } else if (cpu_is_ti816x()) { - strcpy(cpu_name, "TI816X"); + cpu_name = "TI816X"; } else if (omap3_has_iva() && omap3_has_sgx()) { /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ - strcpy(cpu_name, "OMAP3430/3530"); + cpu_name = "OMAP3430/3530"; } else if (omap3_has_iva()) { - omap_revision = OMAP3525_REV(rev); - strcpy(cpu_name, "OMAP3525"); + cpu_name = "OMAP3525"; } else if (omap3_has_sgx()) { - omap_revision = OMAP3515_REV(rev); - strcpy(cpu_name, "OMAP3515"); + cpu_name = "OMAP3515"; } else { - omap_revision = OMAP3503_REV(rev); - strcpy(cpu_name, "OMAP3503"); - } - - if (cpu_is_omap3630() || cpu_is_ti816x()) { - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); - break; - case OMAP_REVBITS_01: - strcpy(cpu_rev, "1.1"); - break; - case OMAP_REVBITS_02: - /* FALLTHROUGH */ - default: - /* Use the latest known revision as default */ - strcpy(cpu_rev, "1.2"); - } - } else if (cpu_is_omap3505() || cpu_is_omap3517()) { - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); - break; - case OMAP_REVBITS_01: - /* FALLTHROUGH */ - default: - /* Use the latest known revision as default */ - strcpy(cpu_rev, "1.1"); - } - } else { - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); - break; - case OMAP_REVBITS_01: - strcpy(cpu_rev, "2.0"); - break; - case OMAP_REVBITS_02: - strcpy(cpu_rev, "2.1"); - break; - case OMAP_REVBITS_03: - strcpy(cpu_rev, "3.0"); - break; - case OMAP_REVBITS_04: - strcpy(cpu_rev, "3.1"); - break; - case OMAP_REVBITS_05: - /* FALLTHROUGH */ - default: - /* Use the latest known revision as default */ - strcpy(cpu_rev, "3.1.2"); - } + cpu_name = "OMAP3503"; } /* Print verbose information */ @@ -533,6 +458,8 @@ static void __init omap3_cpuinfo(void) */ void __init omap2_check_revision(void) { + const char *cpu_rev; + /* * At this point we have an idea about the processor revision set * earlier with omap2_set_globals_tap(). @@ -540,7 +467,7 @@ void __init omap2_check_revision(void) if (cpu_is_omap24xx()) { omap24xx_check_revision(); } else if (cpu_is_omap34xx()) { - omap3_check_revision(); + omap3_check_revision(&cpu_rev); /* TI816X doesn't have feature register */ if (!cpu_is_ti816x()) @@ -548,7 +475,7 @@ void __init omap2_check_revision(void) else ti816x_check_features(); - omap3_cpuinfo(); + omap3_cpuinfo(cpu_rev); return; } else if (cpu_is_omap44xx()) { omap4_check_revision(); @@ -557,22 +484,6 @@ void __init omap2_check_revision(void) } else { pr_err("OMAP revision unknown, please fix!\n"); } - - /* - * OK, now we know the exact revision. Initialize omap_chip bits - * for powerdowmain and clockdomain code. - */ - if (cpu_is_omap243x()) { - /* Currently only supports 2430ES2.1 and 2430-all */ - omap_chip.oc |= CHIP_IS_OMAP2430; - return; - } else if (cpu_is_omap242x()) { - /* Currently only supports 2420ES2.1.1 and 2420-all */ - omap_chip.oc |= CHIP_IS_OMAP2420; - return; - } - - pr_err("Uninitialized omap_chip, please fix!\n"); } /* diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index d6d01cb..f012730 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -37,6 +37,7 @@ #include "io.h" #include <plat/omap-pm.h> +#include "voltage.h" #include "powerdomain.h" #include "clockdomain.h" @@ -341,18 +342,22 @@ void __init omap2_init_common_infrastructure(void) u8 postsetup_state; if (cpu_is_omap242x()) { - omap2xxx_powerdomains_init(); - omap2xxx_clockdomains_init(); + omap2xxx_voltagedomains_init(); + omap242x_powerdomains_init(); + omap242x_clockdomains_init(); omap2420_hwmod_init(); } else if (cpu_is_omap243x()) { - omap2xxx_powerdomains_init(); - omap2xxx_clockdomains_init(); + omap2xxx_voltagedomains_init(); + omap243x_powerdomains_init(); + omap243x_clockdomains_init(); omap2430_hwmod_init(); } else if (cpu_is_omap34xx()) { + omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); } else if (cpu_is_omap44xx()) { + omap44xx_voltagedomains_init(); omap44xx_powerdomains_init(); omap44xx_clockdomains_init(); omap44xx_hwmod_init(); @@ -376,7 +381,7 @@ void __init omap2_init_common_infrastructure(void) * omap_hwmod_late_init(), so boards that desire full watchdog * coverage of kernel initialization can reprogram the * postsetup_state between the calls to - * omap2_init_common_infra() and omap2_init_common_devices(). + * omap2_init_common_infra() and omap_sdrc_init(). * * XXX ideally we could detect whether the MPU WDT was currently * enabled here and make this conditional @@ -400,7 +405,47 @@ void __init omap2_init_common_infrastructure(void) pr_err("Could not init clock framework - unknown SoC\n"); } -void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, +void __init omap2420_init_early(void) +{ + omap2_init_common_infrastructure(); +} + +void __init omap2430_init_early(void) +{ + omap2_init_common_infrastructure(); +} + +void __init omap3430_init_early(void) +{ + omap2_init_common_infrastructure(); +} + +void __init omap35xx_init_early(void) +{ + omap2_init_common_infrastructure(); +} + +void __init omap3630_init_early(void) +{ + omap2_init_common_infrastructure(); +} + +void __init am35xx_init_early(void) +{ + omap2_init_common_infrastructure(); +} + +void __init ti816x_init_early(void) +{ + omap2_init_common_infrastructure(); +} + +void __init omap4430_init_early(void) +{ + omap2_init_common_infrastructure(); +} + +void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { if (cpu_is_omap24xx() || omap3_has_sdrc()) { diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index f286012..eefc379 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -66,7 +66,7 @@ ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) -static void __iommu_set_twl(struct iommu *obj, bool on) +static void __iommu_set_twl(struct omap_iommu *obj, bool on) { u32 l = iommu_read_reg(obj, MMU_CNTL); @@ -85,7 +85,7 @@ static void __iommu_set_twl(struct iommu *obj, bool on) } -static int omap2_iommu_enable(struct iommu *obj) +static int omap2_iommu_enable(struct omap_iommu *obj) { u32 l, pa; unsigned long timeout; @@ -127,7 +127,7 @@ static int omap2_iommu_enable(struct iommu *obj) return 0; } -static void omap2_iommu_disable(struct iommu *obj) +static void omap2_iommu_disable(struct omap_iommu *obj) { u32 l = iommu_read_reg(obj, MMU_CNTL); @@ -138,12 +138,12 @@ static void omap2_iommu_disable(struct iommu *obj) dev_dbg(obj->dev, "%s is shutting down\n", obj->name); } -static void omap2_iommu_set_twl(struct iommu *obj, bool on) +static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on) { __iommu_set_twl(obj, false); } -static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) +static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra) { u32 stat, da; u32 errs = 0; @@ -173,13 +173,13 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) return errs; } -static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) +static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) { cr->cam = iommu_read_reg(obj, MMU_READ_CAM); cr->ram = iommu_read_reg(obj, MMU_READ_RAM); } -static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr) +static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) { iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); iommu_write_reg(obj, cr->ram, MMU_RAM); @@ -193,7 +193,8 @@ static u32 omap2_cr_to_virt(struct cr_regs *cr) return cr->cam & mask; } -static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e) +static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj, + struct iotlb_entry *e) { struct cr_regs *cr; @@ -230,7 +231,8 @@ static u32 omap2_get_pte_attr(struct iotlb_entry *e) return attr; } -static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) +static ssize_t +omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf) { char *p = buf; @@ -254,7 +256,8 @@ static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) goto out; \ } while (0) -static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len) +static ssize_t +omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len) { char *p = buf; @@ -280,7 +283,7 @@ out: return p - buf; } -static void omap2_iommu_save_ctx(struct iommu *obj) +static void omap2_iommu_save_ctx(struct omap_iommu *obj) { int i; u32 *p = obj->ctx; @@ -293,7 +296,7 @@ static void omap2_iommu_save_ctx(struct iommu *obj) BUG_ON(p[0] != IOMMU_ARCH_VERSION); } -static void omap2_iommu_restore_ctx(struct iommu *obj) +static void omap2_iommu_restore_ctx(struct omap_iommu *obj) { int i; u32 *p = obj->ctx; @@ -343,13 +346,13 @@ static const struct iommu_functions omap2_iommu_ops = { static int __init omap2_iommu_init(void) { - return install_iommu_arch(&omap2_iommu_ops); + return omap_install_iommu_arch(&omap2_iommu_ops); } module_init(omap2_iommu_init); static void __exit omap2_iommu_exit(void) { - uninstall_iommu_arch(&omap2_iommu_ops); + omap_uninstall_iommu_arch(&omap2_iommu_ops); } module_exit(omap2_iommu_exit); diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 3a12f75..65f1be6 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -165,8 +165,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs) omap_irq_bank_init_one(bank); - for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20) - omap_alloc_gc(bank->base_reg + j, i, 32); + for (j = 0; j < bank->nr_irqs; j += 32) + omap_alloc_gc(bank->base_reg + j, j, 32); nr_of_irqs += bank->nr_irqs; nr_banks++; diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 4a6ef6a..5063f25 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -27,66 +27,69 @@ #include "control.h" -/* McBSP internal signal muxing functions */ +/* + * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle. + * Sidetone needs non-gated ICLK and sidetone autoidle is broken. + */ +#include "cm2xxx_3xxx.h" +#include "cm-regbits-34xx.h" -void omap2_mcbsp1_mux_clkr_src(u8 mux) +/* McBSP internal signal muxing function */ +static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal, + const char *src) { u32 v; v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - if (mux == CLKR_SRC_CLKR) - v &= ~OMAP2_MCBSP1_CLKR_MASK; - else if (mux == CLKR_SRC_CLKX) - v |= OMAP2_MCBSP1_CLKR_MASK; - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); -} -EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src); -void omap2_mcbsp1_mux_fsr_src(u8 mux) -{ - u32 v; + if (!strcmp(signal, "clkr")) { + if (!strcmp(src, "clkr")) + v &= ~OMAP2_MCBSP1_CLKR_MASK; + else if (!strcmp(src, "clkx")) + v |= OMAP2_MCBSP1_CLKR_MASK; + else + return -EINVAL; + } else if (!strcmp(signal, "fsr")) { + if (!strcmp(src, "fsr")) + v &= ~OMAP2_MCBSP1_FSR_MASK; + else if (!strcmp(src, "fsx")) + v |= OMAP2_MCBSP1_FSR_MASK; + else + return -EINVAL; + } else { + return -EINVAL; + } - v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - if (mux == FSR_SRC_FSR) - v &= ~OMAP2_MCBSP1_FSR_MASK; - else if (mux == FSR_SRC_FSX) - v |= OMAP2_MCBSP1_FSR_MASK; omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + + return 0; } -EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src); /* McBSP CLKS source switching function */ - -int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) +static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk, + const char *src) { - struct omap_mcbsp *mcbsp; struct clk *fck_src; char *fck_src_name; int r; - if (!omap_mcbsp_check_valid_id(id)) { - pr_err("%s: Invalid id (%d)\n", __func__, id + 1); - return -EINVAL; - } - mcbsp = id_to_mcbsp_ptr(id); - - if (fck_src_id == MCBSP_CLKS_PAD_SRC) + if (!strcmp(src, "clks_ext")) fck_src_name = "pad_fck"; - else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) + else if (!strcmp(src, "clks_fclk")) fck_src_name = "prcm_fck"; else return -EINVAL; - fck_src = clk_get(mcbsp->dev, fck_src_name); + fck_src = clk_get(dev, fck_src_name); if (IS_ERR_OR_NULL(fck_src)) { pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks", fck_src_name); return -EINVAL; } - pm_runtime_put_sync(mcbsp->dev); + pm_runtime_put_sync(dev); - r = clk_set_parent(mcbsp->fclk, fck_src); + r = clk_set_parent(clk, fck_src); if (IS_ERR_VALUE(r)) { pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n", "clks", fck_src_name); @@ -94,13 +97,30 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) return -EINVAL; } - pm_runtime_get_sync(mcbsp->dev); + pm_runtime_get_sync(dev); clk_put(fck_src); return 0; } -EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); + +static int omap3_enable_st_clock(unsigned int id, bool enable) +{ + unsigned int w; + + /* + * Sidetone uses McBSP ICLK - which must not idle when sidetones + * are enabled or sidetones start sounding ugly. + */ + w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); + if (enable) + w &= ~(1 << (id - 2)); + else + w |= 1 << (id - 2); + omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); + + return 0; +} struct omap_device_pm_latency omap2_mcbsp_latency[] = { { @@ -116,7 +136,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) char *name = "omap-mcbsp"; struct omap_hwmod *oh_device[2]; struct omap_mcbsp_platform_data *pdata = NULL; - struct omap_device *od; + struct platform_device *pdev; sscanf(oh->name, "mcbsp%d", &id); @@ -126,7 +146,13 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) return -ENOMEM; } - pdata->mcbsp_config_type = oh->class->rev; + pdata->reg_step = 4; + if (oh->class->rev < MCBSP_CONFIG_TYPE2) { + pdata->reg_size = 2; + } else { + pdata->reg_size = 4; + pdata->has_ccr = true; + } if (oh->class->rev == MCBSP_CONFIG_TYPE3) { if (id == 2) @@ -137,22 +163,29 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) pdata->buffer_size = 0x80; } + if (oh->class->rev >= MCBSP_CONFIG_TYPE3) + pdata->has_wakeup = true; + oh_device[0] = oh; if (oh->dev_attr) { oh_device[1] = omap_hwmod_lookup(( (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); + pdata->enable_st_clock = omap3_enable_st_clock; count++; } - od = omap_device_build_ss(name, id, oh_device, count, pdata, + pdev = omap_device_build_ss(name, id, oh_device, count, pdata, sizeof(*pdata), omap2_mcbsp_latency, ARRAY_SIZE(omap2_mcbsp_latency), false); kfree(pdata); - if (IS_ERR(od)) { + if (IS_ERR(pdev)) { pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, name, oh->name); - return PTR_ERR(od); + return PTR_ERR(pdev); } + pdata->set_clk_src = omap2_mcbsp_set_clk_src; + if (id == 1) + pdata->mux_signal = omap2_mcbsp1_mux_rx_clk; omap_mcbsp_count++; return 0; } diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 84cc0bd..d713807 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1954,9 +1954,6 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs) i = 0; do { - if (!omap_chip_is(ohs[i]->omap_chip)) - continue; - r = _register(ohs[i]); WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, r); diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a015c69..6d72062 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -100,7 +100,6 @@ static struct omap_hwmod omap2420_l3_main_hwmod = { .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), .slaves = omap2420_l3_main_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_NO_IDLEST, }; @@ -206,7 +205,6 @@ static struct omap_hwmod omap2420_l4_core_hwmod = { .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), .slaves = omap2420_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_NO_IDLEST, }; @@ -227,7 +225,6 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod = { .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), .slaves = omap2420_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_NO_IDLEST, }; @@ -243,7 +240,6 @@ static struct omap_hwmod omap2420_mpu_hwmod = { .main_clk = "mpu_ck", .masters = omap2420_mpu_masters, .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* @@ -271,7 +267,16 @@ static struct omap_hwmod omap2420_iva_hwmod = { .class = &iva_hwmod_class, .masters = omap2420_iva_masters, .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, +}; + +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, }; /* timer1 */ @@ -314,10 +319,10 @@ static struct omap_hwmod omap2420_timer1_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2420_timer1_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer2 */ @@ -351,10 +356,10 @@ static struct omap_hwmod omap2420_timer2_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2420_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer3 */ @@ -388,10 +393,10 @@ static struct omap_hwmod omap2420_timer3_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2420_timer3_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer4 */ @@ -425,10 +430,10 @@ static struct omap_hwmod omap2420_timer4_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2420_timer4_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer5 */ @@ -462,10 +467,10 @@ static struct omap_hwmod omap2420_timer5_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2420_timer5_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; @@ -500,10 +505,10 @@ static struct omap_hwmod omap2420_timer6_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2420_timer6_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer7 */ @@ -537,10 +542,10 @@ static struct omap_hwmod omap2420_timer7_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2420_timer7_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer8 */ @@ -574,10 +579,10 @@ static struct omap_hwmod omap2420_timer8_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2420_timer8_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer9 */ @@ -611,10 +616,10 @@ static struct omap_hwmod omap2420_timer9_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap2420_timer9_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer10 */ @@ -648,10 +653,10 @@ static struct omap_hwmod omap2420_timer10_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap2420_timer10_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer11 */ @@ -685,10 +690,10 @@ static struct omap_hwmod omap2420_timer11_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap2420_timer11_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* timer12 */ @@ -722,10 +727,10 @@ static struct omap_hwmod omap2420_timer12_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap2420_timer12_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; /* l4_wkup -> wd_timer2 */ @@ -766,7 +771,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = { }, .slaves = omap2420_wd_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* UART1 */ @@ -792,7 +796,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = { .slaves = omap2420_uart1_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* UART2 */ @@ -818,7 +821,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = { .slaves = omap2420_uart2_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* UART3 */ @@ -844,7 +846,6 @@ static struct omap_hwmod omap2420_uart3_hwmod = { .slaves = omap2420_uart3_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* dss */ @@ -898,7 +899,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), .masters = omap2420_dss_masters, .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_NO_IDLEST, }; @@ -938,7 +938,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = { }, .slaves = omap2420_dss_dispc_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_NO_IDLEST, }; @@ -975,7 +974,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = { }, .slaves = omap2420_dss_rfbi_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_NO_IDLEST, }; @@ -1013,7 +1011,6 @@ static struct omap_hwmod omap2420_dss_venc_hwmod = { }, .slaves = omap2420_dss_venc_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_NO_IDLEST, }; @@ -1064,7 +1061,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), .class = &i2c_class, .dev_attr = &i2c_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_16BIT_REG, }; @@ -1092,7 +1088,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), .class = &i2c_class, .dev_attr = &i2c_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_16BIT_REG, }; @@ -1197,7 +1192,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* gpio2 */ @@ -1223,7 +1217,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* gpio3 */ @@ -1249,7 +1242,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* gpio4 */ @@ -1275,7 +1267,6 @@ static struct omap_hwmod omap2420_gpio4_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* dma attributes */ @@ -1322,7 +1313,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { .masters = omap2420_dma_system_masters, .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), .dev_attr = &dma_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), .flags = HWMOD_NO_IDLEST, }; @@ -1363,7 +1353,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { }, .slaves = omap2420_mailbox_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* mcspi1 */ @@ -1393,7 +1382,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), .class = &omap2xxx_mcspi_class, .dev_attr = &omap_mcspi1_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* mcspi2 */ @@ -1423,7 +1411,6 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), .class = &omap2xxx_mcspi_class, .dev_attr = &omap_mcspi2_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* @@ -1473,7 +1460,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { }, .slaves = omap2420_mcbsp1_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; /* mcbsp2 */ @@ -1514,7 +1500,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { }, .slaves = omap2420_mcbsp2_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; static __initdata struct omap_hwmod *omap2420_hwmods[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 408193d..a2580d0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -110,7 +110,6 @@ static struct omap_hwmod omap2430_l3_main_hwmod = { .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), .slaves = omap2430_l3_main_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .flags = HWMOD_NO_IDLEST, }; @@ -250,7 +249,6 @@ static struct omap_hwmod omap2430_l4_core_hwmod = { .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), .slaves = omap2430_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .flags = HWMOD_NO_IDLEST, }; @@ -301,7 +299,6 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod = { .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), .slaves = omap2430_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .flags = HWMOD_NO_IDLEST, }; @@ -317,7 +314,6 @@ static struct omap_hwmod omap2430_mpu_hwmod = { .main_clk = "mpu_ck", .masters = omap2430_mpu_masters, .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* @@ -345,7 +341,16 @@ static struct omap_hwmod omap2430_iva_hwmod = { .class = &iva_hwmod_class, .masters = omap2430_iva_masters, .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, +}; + +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, }; /* timer1 */ @@ -388,10 +393,10 @@ static struct omap_hwmod omap2430_timer1_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2430_timer1_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer2 */ @@ -425,10 +430,10 @@ static struct omap_hwmod omap2430_timer2_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2430_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer3 */ @@ -462,10 +467,10 @@ static struct omap_hwmod omap2430_timer3_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2430_timer3_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer4 */ @@ -499,10 +504,10 @@ static struct omap_hwmod omap2430_timer4_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2430_timer4_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer5 */ @@ -536,10 +541,10 @@ static struct omap_hwmod omap2430_timer5_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2430_timer5_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer6 */ @@ -573,10 +578,10 @@ static struct omap_hwmod omap2430_timer6_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2430_timer6_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer7 */ @@ -610,10 +615,10 @@ static struct omap_hwmod omap2430_timer7_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2430_timer7_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer8 */ @@ -647,10 +652,10 @@ static struct omap_hwmod omap2430_timer8_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap2430_timer8_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer9 */ @@ -684,10 +689,10 @@ static struct omap_hwmod omap2430_timer9_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap2430_timer9_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer10 */ @@ -721,10 +726,10 @@ static struct omap_hwmod omap2430_timer10_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap2430_timer10_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer11 */ @@ -758,10 +763,10 @@ static struct omap_hwmod omap2430_timer11_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap2430_timer11_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* timer12 */ @@ -795,10 +800,10 @@ static struct omap_hwmod omap2430_timer12_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap2430_timer12_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), .class = &omap2xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* l4_wkup -> wd_timer2 */ @@ -839,7 +844,6 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = { }, .slaves = omap2430_wd_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* UART1 */ @@ -865,7 +869,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = { .slaves = omap2430_uart1_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* UART2 */ @@ -891,7 +894,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = { .slaves = omap2430_uart2_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* UART3 */ @@ -917,7 +919,6 @@ static struct omap_hwmod omap2430_uart3_hwmod = { .slaves = omap2430_uart3_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* dss */ @@ -965,7 +966,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), .masters = omap2430_dss_masters, .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .flags = HWMOD_NO_IDLEST, }; @@ -999,7 +999,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = { }, .slaves = omap2430_dss_dispc_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .flags = HWMOD_NO_IDLEST, }; @@ -1030,7 +1029,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = { }, .slaves = omap2430_dss_rfbi_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .flags = HWMOD_NO_IDLEST, }; @@ -1062,7 +1060,6 @@ static struct omap_hwmod omap2430_dss_venc_hwmod = { }, .slaves = omap2430_dss_venc_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .flags = HWMOD_NO_IDLEST, }; @@ -1123,7 +1120,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), .class = &i2c_class, .dev_attr = &i2c_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* I2C2 */ @@ -1151,7 +1147,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), .class = &i2c_class, .dev_attr = &i2c_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* l4_wkup -> gpio1 */ @@ -1273,7 +1268,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* gpio2 */ @@ -1299,7 +1293,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* gpio3 */ @@ -1325,7 +1318,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* gpio4 */ @@ -1351,7 +1343,6 @@ static struct omap_hwmod omap2430_gpio4_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* gpio5 */ @@ -1382,7 +1373,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), .class = &omap2xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* dma attributes */ @@ -1429,7 +1419,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { .masters = omap2430_dma_system_masters, .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), .dev_attr = &dma_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .flags = HWMOD_NO_IDLEST, }; @@ -1469,7 +1458,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { }, .slaves = omap2430_mailbox_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* mcspi1 */ @@ -1499,7 +1487,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), .class = &omap2xxx_mcspi_class, .dev_attr = &omap_mcspi1_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* mcspi2 */ @@ -1529,7 +1516,6 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), .class = &omap2xxx_mcspi_class, .dev_attr = &omap_mcspi2_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* mcspi3 */ @@ -1572,7 +1558,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), .class = &omap2xxx_mcspi_class, .dev_attr = &omap_mcspi3_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* @@ -1628,7 +1613,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { */ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; /* @@ -1689,7 +1673,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { }, .slaves = omap2430_mcbsp1_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* mcbsp2 */ @@ -1731,7 +1714,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { }, .slaves = omap2430_mcbsp2_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* mcbsp3 */ @@ -1783,7 +1765,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { }, .slaves = omap2430_mcbsp3_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* mcbsp4 */ @@ -1841,7 +1822,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { }, .slaves = omap2430_mcbsp4_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* mcbsp5 */ @@ -1899,7 +1879,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { }, .slaves = omap2430_mcbsp5_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* MMC/SD/SDIO common */ @@ -1966,7 +1945,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { .slaves = omap2430_mmc1_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), .class = &omap2430_mmc_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; /* MMC/SD/SDIO2 */ @@ -2010,7 +1988,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { .slaves = omap2430_mmc2_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), .class = &omap2430_mmc_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; static __initdata struct omap_hwmod *omap2430_hwmods[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 25bf43b..3008e16 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -156,7 +156,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = { .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), .slaves = omap3xxx_l3_main_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .flags = HWMOD_NO_IDLEST, }; @@ -459,7 +458,6 @@ static struct omap_hwmod omap3xxx_l4_core_hwmod = { .class = &l4_hwmod_class, .slaves = omap3xxx_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .flags = HWMOD_NO_IDLEST, }; @@ -474,7 +472,6 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = { .class = &l4_hwmod_class, .slaves = omap3xxx_l4_per_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .flags = HWMOD_NO_IDLEST, }; @@ -489,7 +486,6 @@ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { .class = &l4_hwmod_class, .slaves = omap3xxx_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .flags = HWMOD_NO_IDLEST, }; @@ -505,7 +501,6 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { .main_clk = "arm_fck", .masters = omap3xxx_mpu_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* @@ -533,7 +528,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .class = &iva_hwmod_class, .masters = omap3xxx_iva_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer class */ @@ -570,6 +564,21 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { .rev = OMAP_TIMER_IP_VERSION_1, }; +/* secure timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { + .timer_capability = OMAP_TIMER_SECURE, +}; + +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, +}; + +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, +}; + /* timer1 */ static struct omap_hwmod omap3xxx_timer1_hwmod; @@ -610,10 +619,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap3xxx_timer1_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer2 */ @@ -656,10 +665,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap3xxx_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer3 */ @@ -702,10 +711,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap3xxx_timer3_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer4 */ @@ -748,10 +757,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap3xxx_timer4_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer5 */ @@ -794,10 +803,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap3xxx_timer5_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer6 */ @@ -840,10 +849,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap3xxx_timer6_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer7 */ @@ -886,10 +895,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap3xxx_timer7_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer8 */ @@ -932,10 +941,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap3xxx_timer8_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer9 */ @@ -978,10 +987,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap3xxx_timer9_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer10 */ @@ -1015,10 +1024,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap3xxx_timer10_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer11 */ @@ -1052,10 +1061,10 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap3xxx_timer11_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* timer12*/ @@ -1102,10 +1111,10 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, }, }, + .dev_attr = &capability_secure_dev_attr, .slaves = omap3xxx_timer12_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), .class = &omap3xxx_timer_hwmod_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* l4_wkup -> wd_timer2 */ @@ -1182,7 +1191,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { }, .slaves = omap3xxx_wd_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), /* * XXX: Use software supervised mode, HW supervised smartidle seems to * block CORE power domain idle transitions. Maybe a HW bug in wdt2? @@ -1213,7 +1221,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { .slaves = omap3xxx_uart1_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* UART2 */ @@ -1239,7 +1246,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { .slaves = omap3xxx_uart2_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* UART3 */ @@ -1265,7 +1271,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { .slaves = omap3xxx_uart3_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* UART4 */ @@ -1302,7 +1307,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { .slaves = omap3xxx_uart4_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), .class = &omap2_uart_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; static struct omap_hwmod_class i2c_class = { @@ -1390,7 +1394,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), .masters = omap3xxx_dss_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), .flags = HWMOD_NO_IDLEST, }; @@ -1415,8 +1418,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), .masters = omap3xxx_dss_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 | - CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), }; /* l4_core -> dss_dispc */ @@ -1454,9 +1455,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { }, .slaves = omap3xxx_dss_dispc_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | - CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | - CHIP_GE_OMAP3630ES1_1), .flags = HWMOD_NO_IDLEST, }; @@ -1518,9 +1516,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { }, .slaves = omap3xxx_dss_dsi1_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | - CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | - CHIP_GE_OMAP3630ES1_1), .flags = HWMOD_NO_IDLEST, }; @@ -1558,9 +1553,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { }, .slaves = omap3xxx_dss_rfbi_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | - CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | - CHIP_GE_OMAP3630ES1_1), .flags = HWMOD_NO_IDLEST, }; @@ -1599,9 +1591,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = { }, .slaves = omap3xxx_dss_venc_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | - CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | - CHIP_GE_OMAP3630ES1_1), .flags = HWMOD_NO_IDLEST, }; @@ -1637,7 +1626,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), .class = &i2c_class, .dev_attr = &i2c1_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* I2C2 */ @@ -1672,7 +1660,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), .class = &i2c_class, .dev_attr = &i2c2_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* I2C3 */ @@ -1718,7 +1705,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), .class = &i2c_class, .dev_attr = &i2c3_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* l4_wkup -> gpio1 */ @@ -1880,7 +1866,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* gpio2 */ @@ -1912,7 +1897,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* gpio3 */ @@ -1944,7 +1928,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* gpio4 */ @@ -1976,7 +1959,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* gpio5 */ @@ -2013,7 +1995,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* gpio6 */ @@ -2050,7 +2031,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = { .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* dma_system -> L3 */ @@ -2134,7 +2114,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = { .masters = omap3xxx_dma_system_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), .dev_attr = &dma_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .flags = HWMOD_NO_IDLEST, }; @@ -2207,7 +2186,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { }, .slaves = omap3xxx_mcbsp1_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* mcbsp2 */ @@ -2264,7 +2242,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { .slaves = omap3xxx_mcbsp2_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), .dev_attr = &omap34xx_mcbsp2_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* mcbsp3 */ @@ -2321,7 +2298,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { .slaves = omap3xxx_mcbsp3_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), .dev_attr = &omap34xx_mcbsp3_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* mcbsp4 */ @@ -2379,7 +2355,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { }, .slaves = omap3xxx_mcbsp4_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* mcbsp5 */ @@ -2437,7 +2412,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { }, .slaves = omap3xxx_mcbsp5_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* 'mcbsp sidetone' class */ @@ -2498,7 +2472,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { }, .slaves = omap3xxx_mcbsp2_sidetone_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* mcbsp3_sidetone */ @@ -2547,7 +2520,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { }, .slaves = omap3xxx_mcbsp3_sidetone_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -2597,7 +2569,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = { .name = "sr1_hwmod", .class = &omap34xx_smartreflex_hwmod_class, .main_clk = "sr1_fck", - .vdd_name = "mpu", + .vdd_name = "mpu_iva", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -2609,9 +2581,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = { }, .slaves = omap3_sr1_slaves, .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | - CHIP_IS_OMAP3430ES3_0 | - CHIP_IS_OMAP3430ES3_1), .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; @@ -2619,7 +2588,7 @@ static struct omap_hwmod omap36xx_sr1_hwmod = { .name = "sr1_hwmod", .class = &omap36xx_smartreflex_hwmod_class, .main_clk = "sr1_fck", - .vdd_name = "mpu", + .vdd_name = "mpu_iva", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -2631,7 +2600,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = { }, .slaves = omap3_sr1_slaves, .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; /* SR2 */ @@ -2655,9 +2623,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = { }, .slaves = omap3_sr2_slaves, .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | - CHIP_IS_OMAP3430ES3_0 | - CHIP_IS_OMAP3430ES3_1), .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; @@ -2677,7 +2642,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { }, .slaves = omap3_sr2_slaves, .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; /* @@ -2745,7 +2709,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = { }, .slaves = omap3xxx_mailbox_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* l4 core -> mcspi1 interface */ @@ -2843,7 +2806,6 @@ static struct omap_hwmod omap34xx_mcspi1 = { .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi1_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* mcspi2 */ @@ -2873,7 +2835,6 @@ static struct omap_hwmod omap34xx_mcspi2 = { .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi2_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* mcspi3 */ @@ -2916,7 +2877,6 @@ static struct omap_hwmod omap34xx_mcspi3 = { .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi3_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* SPI4 */ @@ -2957,7 +2917,6 @@ static struct omap_hwmod omap34xx_mcspi4 = { .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi4_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* @@ -3014,7 +2973,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { */ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; /* usb_otg_hs */ @@ -3042,7 +3000,6 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = { .slaves = am35xx_usbhsotg_slaves, .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), .class = &am35xx_usbotg_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) }; /* MMC/SD/SDIO common */ @@ -3108,7 +3065,6 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = { .slaves = omap3xxx_mmc1_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), .class = &omap34xx_mmc_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* MMC/SD/SDIO2 */ @@ -3151,7 +3107,6 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = { .slaves = omap3xxx_mmc2_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), .class = &omap34xx_mmc_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; /* MMC/SD/SDIO3 */ @@ -3193,7 +3148,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { .slaves = omap3xxx_mmc3_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), .class = &omap34xx_mmc_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { @@ -3224,10 +3178,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_uart1_hwmod, &omap3xxx_uart2_hwmod, &omap3xxx_uart3_hwmod, - &omap3xxx_uart4_hwmod, /* dss class */ - &omap3430es1_dss_core_hwmod, - &omap3xxx_dss_core_hwmod, &omap3xxx_dss_dispc_hwmod, &omap3xxx_dss_dsi1_hwmod, &omap3xxx_dss_rfbi_hwmod, @@ -3239,9 +3190,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_i2c3_hwmod, &omap34xx_sr1_hwmod, &omap34xx_sr2_hwmod, - &omap36xx_sr1_hwmod, - &omap36xx_sr2_hwmod, - /* gpio class */ &omap3xxx_gpio1_hwmod, @@ -3272,16 +3220,96 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap34xx_mcspi3, &omap34xx_mcspi4, - /* usbotg class */ + NULL, +}; + +/* 3430ES1-only hwmods */ +static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { + &omap3430es1_dss_core_hwmod, + NULL +}; + +/* 3430ES2+-only hwmods */ +static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { + &omap3xxx_dss_core_hwmod, &omap3xxx_usbhsotg_hwmod, + NULL +}; - /* usbotg for am35x */ - &am35xx_usbhsotg_hwmod, +/* 34xx-only hwmods (all ES revisions) */ +static __initdata struct omap_hwmod *omap34xx_hwmods[] = { + &omap34xx_sr1_hwmod, + &omap34xx_sr2_hwmod, + NULL +}; - NULL, +/* 36xx-only hwmods (all ES revisions) */ +static __initdata struct omap_hwmod *omap36xx_hwmods[] = { + &omap3xxx_uart4_hwmod, + &omap3xxx_dss_core_hwmod, + &omap36xx_sr1_hwmod, + &omap36xx_sr2_hwmod, + &omap3xxx_usbhsotg_hwmod, + NULL +}; + +static __initdata struct omap_hwmod *am35xx_hwmods[] = { + &omap3xxx_dss_core_hwmod, /* XXX ??? */ + &am35xx_usbhsotg_hwmod, + NULL }; int __init omap3xxx_hwmod_init(void) { - return omap_hwmod_register(omap3xxx_hwmods); + int r; + struct omap_hwmod **h = NULL; + unsigned int rev; + + /* Register hwmods common to all OMAP3 */ + r = omap_hwmod_register(omap3xxx_hwmods); + if (!r) + return r; + + rev = omap_rev(); + + /* + * Register hwmods common to individual OMAP3 families, all + * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) + * All possible revisions should be included in this conditional. + */ + if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || + rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || + rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { + h = omap34xx_hwmods; + } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { + h = am35xx_hwmods; + } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || + rev == OMAP3630_REV_ES1_2) { + h = omap36xx_hwmods; + } else { + WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); + return -EINVAL; + }; + + r = omap_hwmod_register(h); + if (!r) + return r; + + /* + * Register hwmods specific to certain ES levels of a + * particular family of silicon (e.g., 34xx ES1.0) + */ + h = NULL; + if (rev == OMAP3430_REV_ES1_0) { + h = omap3430es1_hwmods; + } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || + rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || + rev == OMAP3430_REV_ES3_1_2) { + h = omap3430es2plus_hwmods; + }; + + if (h) + r = omap_hwmod_register(h); + + return r; } diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 6201422..7695e5d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -29,6 +29,7 @@ #include <plat/mcbsp.h> #include <plat/mmc.h> #include <plat/i2c.h> +#include <plat/dmtimer.h> #include "omap_hwmod_common_data.h" @@ -133,7 +134,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { .slaves = omap44xx_dmm_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), .mpu_irqs = omap44xx_dmm_irqs, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -189,7 +189,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = { }, .slaves = omap44xx_emif_fw_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -236,7 +235,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { }, .slaves = omap44xx_l3_instr_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* l3_main_1 */ @@ -336,7 +334,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { }, .slaves = omap44xx_l3_main_1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* l3_main_2 */ @@ -438,7 +435,6 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { }, .slaves = omap44xx_l3_main_2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* l3_main_3 */ @@ -496,7 +492,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = { }, .slaves = omap44xx_l3_main_3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -559,7 +554,6 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { }, .slaves = omap44xx_l4_abe_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* l4_cfg */ @@ -588,7 +582,6 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { }, .slaves = omap44xx_l4_cfg_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* l4_per */ @@ -617,7 +610,6 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { }, .slaves = omap44xx_l4_per_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* l4_wkup */ @@ -646,7 +638,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { }, .slaves = omap44xx_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -677,7 +668,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { .clkdm_name = "mpuss_clkdm", .slaves = omap44xx_mpu_private_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -828,7 +818,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), .masters = omap44xx_aess_masters, .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -856,7 +845,6 @@ static struct omap_hwmod omap44xx_bandgap_hwmod = { }, .opt_clks = bandgap_opt_clks, .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -917,7 +905,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { }, .slaves = omap44xx_counter_32k_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1005,7 +992,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), .masters = omap44xx_dma_system_masters, .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1098,7 +1084,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { }, .slaves = omap44xx_dmic_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1164,7 +1149,6 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = { .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, }, }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct omap_hwmod omap44xx_dsp_hwmod = { @@ -1187,7 +1171,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), .masters = omap44xx_dsp_masters, .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1278,7 +1261,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), .masters = omap44xx_dss_masters, .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1381,7 +1363,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks), .slaves = omap44xx_dss_dispc_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1480,7 +1461,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), .slaves = omap44xx_dss_dsi1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* dss_dsi2 */ @@ -1558,7 +1538,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), .slaves = omap44xx_dss_dsi2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1656,7 +1635,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), .slaves = omap44xx_dss_hdmi_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1748,7 +1726,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), .slaves = omap44xx_dss_rfbi_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1817,7 +1794,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { }, .slaves = omap44xx_dss_venc_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -1901,7 +1877,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .dev_attr = &gpio_dev_attr, .slaves = omap44xx_gpio1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* gpio2 */ @@ -1957,7 +1932,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { .dev_attr = &gpio_dev_attr, .slaves = omap44xx_gpio2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* gpio3 */ @@ -2013,7 +1987,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { .dev_attr = &gpio_dev_attr, .slaves = omap44xx_gpio3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* gpio4 */ @@ -2069,7 +2042,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { .dev_attr = &gpio_dev_attr, .slaves = omap44xx_gpio4_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* gpio5 */ @@ -2125,7 +2097,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { .dev_attr = &gpio_dev_attr, .slaves = omap44xx_gpio5_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* gpio6 */ @@ -2181,7 +2152,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .dev_attr = &gpio_dev_attr, .slaves = omap44xx_gpio6_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -2261,7 +2231,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), .masters = omap44xx_hsi_masters, .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -2345,7 +2314,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .slaves = omap44xx_i2c1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), .dev_attr = &i2c_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* i2c2 */ @@ -2402,7 +2370,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { .slaves = omap44xx_i2c2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), .dev_attr = &i2c_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* i2c3 */ @@ -2459,7 +2426,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .slaves = omap44xx_i2c3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), .dev_attr = &i2c_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* i2c4 */ @@ -2516,7 +2482,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .slaves = omap44xx_i2c4_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), .dev_attr = &i2c_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -2577,7 +2542,6 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = { .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, }, }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* Pseudo hwmod for reset control purpose only */ @@ -2593,7 +2557,6 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = { .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, }, }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct omap_hwmod omap44xx_ipu_hwmod = { @@ -2616,7 +2579,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), .masters = omap44xx_ipu_masters, .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -2706,7 +2668,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), .masters = omap44xx_iss_masters, .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -2781,7 +2742,6 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = { .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, }, }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* Pseudo hwmod for reset control purpose only */ @@ -2797,7 +2757,6 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = { .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, }, }, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static struct omap_hwmod omap44xx_iva_hwmod = { @@ -2820,7 +2779,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), .masters = omap44xx_iva_masters, .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -2890,7 +2848,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { }, .slaves = omap44xx_kbd_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -2956,7 +2913,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { }, .slaves = omap44xx_mailbox_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -3051,7 +3007,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { }, .slaves = omap44xx_mcbsp1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mcbsp2 */ @@ -3127,7 +3082,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { }, .slaves = omap44xx_mcbsp2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mcbsp3 */ @@ -3203,7 +3157,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { }, .slaves = omap44xx_mcbsp3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mcbsp4 */ @@ -3258,7 +3211,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { }, .slaves = omap44xx_mcbsp4_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -3353,7 +3305,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { }, .slaves = omap44xx_mcpdm_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -3442,7 +3393,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .dev_attr = &mcspi1_dev_attr, .slaves = omap44xx_mcspi1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mcspi2 */ @@ -3505,7 +3455,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .dev_attr = &mcspi2_dev_attr, .slaves = omap44xx_mcspi2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mcspi3 */ @@ -3568,7 +3517,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .dev_attr = &mcspi3_dev_attr, .slaves = omap44xx_mcspi3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mcspi4 */ @@ -3629,7 +3577,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .dev_attr = &mcspi4_dev_attr, .slaves = omap44xx_mcspi4_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -3718,7 +3665,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), .masters = omap44xx_mmc1_masters, .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mmc2 */ @@ -3779,7 +3725,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), .masters = omap44xx_mmc2_masters, .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mmc3 */ @@ -3834,7 +3779,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { }, .slaves = omap44xx_mmc3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mmc4 */ @@ -3890,7 +3834,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { }, .slaves = omap44xx_mmc4_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* mmc5 */ @@ -3945,7 +3888,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { }, .slaves = omap44xx_mmc5_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -3987,7 +3929,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { }, .masters = omap44xx_mpu_masters, .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -4063,7 +4004,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { }, .slaves = omap44xx_smartreflex_core_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* smartreflex_iva */ @@ -4112,7 +4052,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { }, .slaves = omap44xx_smartreflex_iva_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* smartreflex_mpu */ @@ -4161,7 +4100,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { }, .slaves = omap44xx_smartreflex_mpu_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -4224,7 +4162,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = { }, .slaves = omap44xx_spinlock_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -4265,6 +4202,16 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = { .sysc = &omap44xx_timer_sysc, }; +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, +}; + +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, +}; + /* timer1 */ static struct omap_hwmod omap44xx_timer1_hwmod; static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { @@ -4308,9 +4255,9 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap44xx_timer1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer2 */ @@ -4356,9 +4303,9 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap44xx_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer3 */ @@ -4404,9 +4351,9 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap44xx_timer3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer4 */ @@ -4452,9 +4399,9 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap44xx_timer4_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer5 */ @@ -4519,9 +4466,9 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap44xx_timer5_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer6 */ @@ -4587,9 +4534,9 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap44xx_timer6_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer7 */ @@ -4654,9 +4601,9 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_alwon_dev_attr, .slaves = omap44xx_timer7_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer8 */ @@ -4721,9 +4668,9 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap44xx_timer8_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer9 */ @@ -4769,9 +4716,9 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap44xx_timer9_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer10 */ @@ -4817,9 +4764,9 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap44xx_timer10_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* timer11 */ @@ -4865,9 +4812,9 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_pwm_dev_attr, .slaves = omap44xx_timer11_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -4944,7 +4891,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { }, .slaves = omap44xx_uart1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* uart2 */ @@ -4999,7 +4945,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { }, .slaves = omap44xx_uart2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* uart3 */ @@ -5055,7 +5000,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { }, .slaves = omap44xx_uart3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* uart4 */ @@ -5110,7 +5054,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { }, .slaves = omap44xx_uart4_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -5195,7 +5138,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), .masters = omap44xx_usb_otg_hs_masters, .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* @@ -5266,7 +5208,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { }, .slaves = omap44xx_wd_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; /* wd_timer3 */ @@ -5333,7 +5274,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { }, .slaves = omap44xx_wd_timer3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; static __initdata struct omap_hwmod *omap44xx_hwmods[] = { @@ -5430,7 +5370,7 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_mcbsp4_hwmod, /* mcpdm class */ -/* &omap44xx_mcpdm_hwmod, */ + &omap44xx_mcpdm_hwmod, /* mcspi class */ &omap44xx_mcspi1_hwmod, diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 07d6140..f515a1a 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -42,8 +42,11 @@ #define OMAP4_SRI2C_SLAVE_ADDR 0x12 #define OMAP4_VDD_MPU_SR_VOLT_REG 0x55 +#define OMAP4_VDD_MPU_SR_CMD_REG 0x56 #define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B +#define OMAP4_VDD_IVA_SR_CMD_REG 0x5C #define OMAP4_VDD_CORE_SR_VOLT_REG 0x61 +#define OMAP4_VDD_CORE_SR_CMD_REG 0x62 #define OMAP4_VP_CONFIG_ERROROFFSET 0x00 #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01 @@ -95,6 +98,8 @@ static unsigned long twl6030_vsel_to_uv(const u8 vsel) is_offset_valid = true; } + if (!vsel) + return 0; /* * There is no specific formula for voltage to vsel * conversion above 1.3V. There are special hardcoded @@ -106,9 +111,9 @@ static unsigned long twl6030_vsel_to_uv(const u8 vsel) return 1350000; if (smps_offset & 0x8) - return ((((vsel - 1) * 125) + 7000)) * 100; + return ((((vsel - 1) * 1266) + 70900)) * 10; else - return ((((vsel - 1) * 125) + 6000)) * 100; + return ((((vsel - 1) * 1266) + 60770)) * 10; } static u8 twl6030_uv_to_vsel(unsigned long uv) @@ -127,6 +132,8 @@ static u8 twl6030_uv_to_vsel(unsigned long uv) is_offset_valid = true; } + if (!uv) + return 0x00; /* * There is no specific formula for voltage to vsel * conversion above 1.3V. There are special hardcoded @@ -134,16 +141,21 @@ static u8 twl6030_uv_to_vsel(unsigned long uv) * hardcoding only for 1.35 V which is used for 1GH OPP for * OMAP4430. */ - if (uv == 1350000) + if (uv > twl6030_vsel_to_uv(0x39)) { + if (uv == 1350000) + return 0x3A; + pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n", + __func__, uv, twl6030_vsel_to_uv(0x39)); return 0x3A; + } if (smps_offset & 0x8) - return DIV_ROUND_UP(uv - 700000, 12500) + 1; + return DIV_ROUND_UP(uv - 709000, 12660) + 1; else - return DIV_ROUND_UP(uv - 600000, 12500) + 1; + return DIV_ROUND_UP(uv - 607700, 12660) + 1; } -static struct omap_volt_pmic_info omap3_mpu_volt_info = { +static struct omap_voltdm_pmic omap3_mpu_pmic = { .slew_rate = 4000, .step_size = 12500, .on_volt = 1200000, @@ -158,12 +170,13 @@ static struct omap_volt_pmic_info omap3_mpu_volt_info = { .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX, .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, - .pmic_reg = OMAP3_VDD_MPU_SR_CONTROL_REG, + .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG, + .i2c_high_speed = true, .vsel_to_uv = twl4030_vsel_to_uv, .uv_to_vsel = twl4030_uv_to_vsel, }; -static struct omap_volt_pmic_info omap3_core_volt_info = { +static struct omap_voltdm_pmic omap3_core_pmic = { .slew_rate = 4000, .step_size = 12500, .on_volt = 1200000, @@ -178,18 +191,19 @@ static struct omap_volt_pmic_info omap3_core_volt_info = { .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX, .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, - .pmic_reg = OMAP3_VDD_CORE_SR_CONTROL_REG, + .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG, + .i2c_high_speed = true, .vsel_to_uv = twl4030_vsel_to_uv, .uv_to_vsel = twl4030_uv_to_vsel, }; -static struct omap_volt_pmic_info omap4_mpu_volt_info = { +static struct omap_voltdm_pmic omap4_mpu_pmic = { .slew_rate = 4000, - .step_size = 12500, - .on_volt = 1350000, - .onlp_volt = 1350000, - .ret_volt = 837500, - .off_volt = 600000, + .step_size = 12660, + .on_volt = 1375000, + .onlp_volt = 1375000, + .ret_volt = 830000, + .off_volt = 0, .volt_setup_time = 0, .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, @@ -198,18 +212,20 @@ static struct omap_volt_pmic_info omap4_mpu_volt_info = { .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX, .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, - .pmic_reg = OMAP4_VDD_MPU_SR_VOLT_REG, + .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG, + .cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG, + .i2c_high_speed = true, .vsel_to_uv = twl6030_vsel_to_uv, .uv_to_vsel = twl6030_uv_to_vsel, }; -static struct omap_volt_pmic_info omap4_iva_volt_info = { +static struct omap_voltdm_pmic omap4_iva_pmic = { .slew_rate = 4000, - .step_size = 12500, - .on_volt = 1100000, - .onlp_volt = 1100000, - .ret_volt = 837500, - .off_volt = 600000, + .step_size = 12660, + .on_volt = 1188000, + .onlp_volt = 1188000, + .ret_volt = 830000, + .off_volt = 0, .volt_setup_time = 0, .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, @@ -218,18 +234,20 @@ static struct omap_volt_pmic_info omap4_iva_volt_info = { .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX, .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, - .pmic_reg = OMAP4_VDD_IVA_SR_VOLT_REG, + .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG, + .cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG, + .i2c_high_speed = true, .vsel_to_uv = twl6030_vsel_to_uv, .uv_to_vsel = twl6030_uv_to_vsel, }; -static struct omap_volt_pmic_info omap4_core_volt_info = { +static struct omap_voltdm_pmic omap4_core_pmic = { .slew_rate = 4000, - .step_size = 12500, - .on_volt = 1100000, - .onlp_volt = 1100000, - .ret_volt = 837500, - .off_volt = 600000, + .step_size = 12660, + .on_volt = 1200000, + .onlp_volt = 1200000, + .ret_volt = 830000, + .off_volt = 0, .volt_setup_time = 0, .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, @@ -238,7 +256,8 @@ static struct omap_volt_pmic_info omap4_core_volt_info = { .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX, .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, - .pmic_reg = OMAP4_VDD_CORE_SR_VOLT_REG, + .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG, + .cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG, .vsel_to_uv = twl6030_vsel_to_uv, .uv_to_vsel = twl6030_uv_to_vsel, }; @@ -250,14 +269,14 @@ int __init omap4_twl_init(void) if (!cpu_is_omap44xx()) return -ENODEV; - voltdm = omap_voltage_domain_lookup("mpu"); - omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info); + voltdm = voltdm_lookup("mpu"); + omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic); - voltdm = omap_voltage_domain_lookup("iva"); - omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info); + voltdm = voltdm_lookup("iva"); + omap_voltage_register_pmic(voltdm, &omap4_iva_pmic); - voltdm = omap_voltage_domain_lookup("core"); - omap_voltage_register_pmic(voltdm, &omap4_core_volt_info); + voltdm = voltdm_lookup("core"); + omap_voltage_register_pmic(voltdm, &omap4_core_pmic); return 0; } @@ -270,10 +289,10 @@ int __init omap3_twl_init(void) return -ENODEV; if (cpu_is_omap3630()) { - omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN; - omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX; - omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN; - omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; + omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN; + omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX; + omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN; + omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; } /* @@ -288,11 +307,11 @@ int __init omap3_twl_init(void) if (!twl_sr_enable_autoinit) omap3_twl_set_sr_bit(true); - voltdm = omap_voltage_domain_lookup("mpu"); - omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info); + voltdm = voltdm_lookup("mpu_iva"); + omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic); - voltdm = omap_voltage_domain_lookup("core"); - omap_voltage_register_pmic(voltdm, &omap3_core_volt_info); + voltdm = voltdm_lookup("core"); + omap_voltage_register_pmic(voltdm, &omap3_core_pmic); return 0; } diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index ab8b35b..9262a6b 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c @@ -69,7 +69,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, opp_def->hwmod_name, i); return -EINVAL; } - dev = &oh->od->pdev.dev; + dev = &oh->od->pdev->dev; r = opp_add(dev, opp_def->freq, opp_def->u_volt); if (r) { diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 472bf22..0844e2e 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -60,19 +60,19 @@ EXPORT_SYMBOL(omap4_get_dsp_device); static int _init_omap_device(char *name, struct device **new_dev) { struct omap_hwmod *oh; - struct omap_device *od; + struct platform_device *pdev; oh = omap_hwmod_lookup(name); if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", __func__, name)) return -ENODEV; - od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); - if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n", + pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); + if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", __func__, name)) return -ENODEV; - *new_dev = &od->pdev.dev; + *new_dev = &pdev->dev; return 0; } @@ -136,8 +136,8 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) ret = pwrdm_set_next_pwrst(pwrdm, state); if (ret) { - printk(KERN_ERR "Unable to set state of powerdomain: %s\n", - pwrdm->name); + pr_err("%s: unable to set state of powerdomain: %s\n", + __func__, pwrdm->name); goto err; } @@ -161,11 +161,11 @@ err: } /* - * This API is to be called during init to put the various voltage + * This API is to be called during init to set the various voltage * domains to the voltage as per the opp table. Typically we boot up * at the nominal voltage. So this function finds out the rate of * the clock associated with the voltage domain, finds out the correct - * opp entry and puts the voltage domain to the voltage specifies + * opp entry and sets the voltage domain to the voltage specified * in the opp entry */ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, @@ -177,21 +177,20 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, unsigned long freq, bootup_volt; if (!vdd_name || !clk_name || !dev) { - printk(KERN_ERR "%s: Invalid parameters!\n", __func__); + pr_err("%s: invalid parameters\n", __func__); goto exit; } - voltdm = omap_voltage_domain_lookup(vdd_name); + voltdm = voltdm_lookup(vdd_name); if (IS_ERR(voltdm)) { - printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n", + pr_err("%s: unable to get vdd pointer for vdd_%s\n", __func__, vdd_name); goto exit; } clk = clk_get(NULL, clk_name); if (IS_ERR(clk)) { - printk(KERN_ERR "%s: unable to get clk %s\n", - __func__, clk_name); + pr_err("%s: unable to get clk %s\n", __func__, clk_name); goto exit; } @@ -200,24 +199,23 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, opp = opp_find_freq_ceil(dev, &freq); if (IS_ERR(opp)) { - printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n", + pr_err("%s: unable to find boot up OPP for vdd_%s\n", __func__, vdd_name); goto exit; } bootup_volt = opp_get_voltage(opp); if (!bootup_volt) { - printk(KERN_ERR "%s: unable to find voltage corresponding" + pr_err("%s: unable to find voltage corresponding " "to the bootup OPP for vdd_%s\n", __func__, vdd_name); goto exit; } - omap_voltage_scale_vdd(voltdm, bootup_volt); + voltdm_scale(voltdm, bootup_volt); return 0; exit: - printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n", - __func__, vdd_name); + pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name); return -EINVAL; } @@ -226,7 +224,7 @@ static void __init omap3_init_voltages(void) if (!cpu_is_omap34xx()) return; - omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev); + omap2_set_init_voltage("mpu_iva", "dpll1_ck", mpu_dev); omap2_set_init_voltage("core", "l3_ick", l3_dev); } diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index bf089e7..cf0c216 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -53,8 +53,6 @@ #include "powerdomain.h" #include "clockdomain.h" -static int omap2_pm_debug; - #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state = PM_SUSPEND_ON; static inline bool is_suspending(void) @@ -96,7 +94,6 @@ static int omap2_fclks_active(void) static void omap2_enter_full_retention(void) { u32 l; - struct timespec ts_preidle, ts_postidle, ts_idle; /* There is 1 reference hold for all children of the oscillator * clock, the following will remove it. If no one else uses the @@ -124,10 +121,6 @@ static void omap2_enter_full_retention(void) omap2_gpio_prepare_for_idle(0); - if (omap2_pm_debug) { - getnstimeofday(&ts_preidle); - } - /* One last check for pending IRQs to avoid extra latency due * to sleeping unnecessarily. */ if (omap_irq_pending()) @@ -155,13 +148,6 @@ static void omap2_enter_full_retention(void) console_unlock(); no_sleep: - if (omap2_pm_debug) { - unsigned long long tmp; - - getnstimeofday(&ts_postidle); - ts_idle = timespec_sub(ts_postidle, ts_preidle); - tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; - } omap2_gpio_resume_after_idle(); clk_enable(osc_ck); @@ -219,7 +205,6 @@ static int omap2_allow_mpu_retention(void) static void omap2_enter_mpu_retention(void) { int only_idle = 0; - struct timespec ts_preidle, ts_postidle, ts_idle; /* Putting MPU into the WFI state while a transfer is active * seems to cause the I2C block to timeout. Why? Good question. */ @@ -246,19 +231,7 @@ static void omap2_enter_mpu_retention(void) only_idle = 1; } - if (omap2_pm_debug) { - getnstimeofday(&ts_preidle); - } - omap2_sram_idle(); - - if (omap2_pm_debug) { - unsigned long long tmp; - - getnstimeofday(&ts_postidle); - ts_idle = timespec_sub(ts_postidle, ts_preidle); - tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; - } } static int omap2_can_sleep(void) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 7255d9b..c8cbd00 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -55,7 +55,7 @@ static suspend_state_t suspend_state = PM_SUSPEND_ON; static inline bool is_suspending(void) { - return (suspend_state != PM_SUSPEND_ON); + return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled; } #else static inline bool is_suspending(void) diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c index 171fccd..f97afff 100644 --- a/arch/arm/mach-omap2/powerdomain-common.c +++ b/arch/arm/mach-omap2/powerdomain-common.c @@ -1,9 +1,8 @@ /* - * linux/arch/arm/mach-omap2/powerdomain-common.c - * Contains common powerdomain framework functions + * Common powerdomain framework functions * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation + * Copyright (C) 2010-2011 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation * * Derived from mach-omap2/powerdomain.c written by Paul Walmsley * diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index ef71fdd..5164d58 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -1,7 +1,7 @@ /* * OMAP powerdomain control * - * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc. * Copyright (C) 2007-2011 Nokia Corporation * * Written by Paul Walmsley @@ -77,13 +77,11 @@ static struct powerdomain *_pwrdm_lookup(const char *name) static int _pwrdm_register(struct powerdomain *pwrdm) { int i; + struct voltagedomain *voltdm; if (!pwrdm || !pwrdm->name) return -EINVAL; - if (!omap_chip_is(pwrdm->omap_chip)) - return -EINVAL; - if (cpu_is_omap44xx() && pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) { pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n", @@ -94,6 +92,16 @@ static int _pwrdm_register(struct powerdomain *pwrdm) if (_pwrdm_lookup(pwrdm->name)) return -EEXIST; + voltdm = voltdm_lookup(pwrdm->voltdm.name); + if (!voltdm) { + pr_err("powerdomain: %s: voltagedomain %s does not exist\n", + pwrdm->name, pwrdm->voltdm.name); + return -EINVAL; + } + pwrdm->voltdm.ptr = voltdm; + INIT_LIST_HEAD(&pwrdm->voltdm_node); + voltdm_add_pwrdm(voltdm, pwrdm); + list_add(&pwrdm->node, &pwrdm_list); /* Initialize the powerdomain's state counter */ @@ -194,36 +202,76 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) /* Public functions */ /** - * pwrdm_init - set up the powerdomain layer - * @pwrdms: array of struct powerdomain pointers to register - * @custom_funcs: func pointers for arch specific implementations + * pwrdm_register_platform_funcs - register powerdomain implementation fns + * @po: func pointers for arch specific implementations * - * Loop through the array of powerdomains @pwrdms, registering all - * that are available on the current CPU. Also, program all - * powerdomain target state as ON; this is to prevent domains from - * hitting low power states (if bootloader has target states set to - * something other than ON) and potentially even losing context while - * PM is not fully initialized. The PM late init code can then program - * the desired target state for all the power domains. No return - * value. + * Register the list of function pointers used to implement the + * powerdomain functions on different OMAP SoCs. Should be called + * before any other pwrdm_register*() function. Returns -EINVAL if + * @po is null, -EEXIST if platform functions have already been + * registered, or 0 upon success. */ -void pwrdm_init(struct powerdomain **pwrdms, struct pwrdm_ops *custom_funcs) +int pwrdm_register_platform_funcs(struct pwrdm_ops *po) +{ + if (!po) + return -EINVAL; + + if (arch_pwrdm) + return -EEXIST; + + arch_pwrdm = po; + + return 0; +} + +/** + * pwrdm_register_pwrdms - register SoC powerdomains + * @ps: pointer to an array of struct powerdomain to register + * + * Register the powerdomains available on a particular OMAP SoC. Must + * be called after pwrdm_register_platform_funcs(). May be called + * multiple times. Returns -EACCES if called before + * pwrdm_register_platform_funcs(); -EINVAL if the argument @ps is + * null; or 0 upon success. + */ +int pwrdm_register_pwrdms(struct powerdomain **ps) { struct powerdomain **p = NULL; - struct powerdomain *temp_p; - if (!custom_funcs) - WARN(1, "powerdomain: No custom pwrdm functions registered\n"); - else - arch_pwrdm = custom_funcs; + if (!arch_pwrdm) + return -EEXIST; - if (pwrdms) { - for (p = pwrdms; *p; p++) - _pwrdm_register(*p); - } + if (!ps) + return -EINVAL; + + for (p = ps; *p; p++) + _pwrdm_register(*p); + + return 0; +} + +/** + * pwrdm_complete_init - set up the powerdomain layer + * + * Do whatever is necessary to initialize registered powerdomains and + * powerdomain code. Currently, this programs the next power state + * for each powerdomain to ON. This prevents powerdomains from + * unexpectedly losing context or entering high wakeup latency modes + * with non-power-management-enabled kernels. Must be called after + * pwrdm_register_pwrdms(). Returns -EACCES if called before + * pwrdm_register_pwrdms(), or 0 upon success. + */ +int pwrdm_complete_init(void) +{ + struct powerdomain *temp_p; + + if (list_empty(&pwrdm_list)) + return -EACCES; list_for_each_entry(temp_p, &pwrdm_list, node) pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON); + + return 0; } /** @@ -390,6 +438,18 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, } /** + * pwrdm_get_voltdm - return a ptr to the voltdm that this pwrdm resides in + * @pwrdm: struct powerdomain * + * + * Return a pointer to the struct voltageomain that the specified powerdomain + * @pwrdm exists in. + */ +struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm) +{ + return pwrdm->voltdm.ptr; +} + +/** * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain * @pwrdm: struct powerdomain * * diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index d23d979..42e6dd8 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -24,6 +24,8 @@ #include <plat/cpu.h> +#include "voltage.h" + /* Powerdomain basic power states */ #define PWRDM_POWER_OFF 0x0 #define PWRDM_POWER_RET 0x1 @@ -78,7 +80,7 @@ struct powerdomain; /** * struct powerdomain - OMAP powerdomain * @name: Powerdomain name - * @omap_chip: represents the OMAP chip types containing this pwrdm + * @voltdm: voltagedomain containing this powerdomain * @prcm_offs: the address offset from CM_BASE/PRM_BASE * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs * @pwrsts: Possible powerdomain power states @@ -89,6 +91,7 @@ struct powerdomain; * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON * @pwrdm_clkdms: Clockdomains in this powerdomain * @node: list_head linking all powerdomains + * @voltdm_node: list_head linking all powerdomains in a voltagedomain * @state: * @state_counter: * @timer: @@ -98,7 +101,10 @@ struct powerdomain; */ struct powerdomain { const char *name; - const struct omap_chip_id omap_chip; + union { + const char *name; + struct voltagedomain *ptr; + } voltdm; const s16 prcm_offs; const u8 pwrsts; const u8 pwrsts_logic_ret; @@ -109,6 +115,7 @@ struct powerdomain { const u8 prcm_partition; struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; struct list_head node; + struct list_head voltdm_node; int state; unsigned state_counter[PWRDM_MAX_PWRSTS]; unsigned ret_logic_off_counter; @@ -162,7 +169,9 @@ struct pwrdm_ops { int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); }; -void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); +int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); +int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list); +int pwrdm_complete_init(void); struct powerdomain *pwrdm_lookup(const char *name); @@ -176,6 +185,7 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, int (*fn)(struct powerdomain *pwrdm, struct clockdomain *clkdm)); +struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm); int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); @@ -210,7 +220,8 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm); bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); -extern void omap2xxx_powerdomains_init(void); +extern void omap242x_powerdomains_init(void); +extern void omap243x_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index cf600e2..6a17e4c 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -1,7 +1,7 @@ /* * OMAP2 and OMAP3 powerdomain control * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2011 Texas Instruments, Inc. * Copyright (C) 2007-2009 Nokia Corporation * * Derived from mach-omap2/powerdomain.c written by Paul Walmsley diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c index 4210c33..d3a5399 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c @@ -1,7 +1,7 @@ /* * OMAP2/3 common powerdomain definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc. * Copyright (C) 2007-2011 Nokia Corporation * * Paul Walmsley, Jouni Högander @@ -12,20 +12,6 @@ */ /* - * To Do List - * -> Move the Sleep/Wakeup dependencies from Power Domain framework to - * Clock Domain Framework - */ - -/* - * This file contains all of the powerdomains that have some element - * of software control for the OMAP24xx and OMAP34xx chips. - * - * This is not an exhaustive listing of powerdomains on the chips; only - * powerdomains that can be controlled in software. - */ - -/* * The names for the DSP/IVA2 powerdomains are confusing. * * Most OMAP chips have an on-board DSP. @@ -59,8 +45,6 @@ struct powerdomain gfx_omap2_pwrdm = { .name = "gfx_pwrdm", .prcm_offs = GFX_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | - CHIP_IS_OMAP3430ES1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, @@ -70,11 +54,12 @@ struct powerdomain gfx_omap2_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, + .voltdm = { .name = "core" }, }; struct powerdomain wkup_omap2_pwrdm = { .name = "wkup_pwrdm", .prcm_offs = WKUP_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), .pwrsts = PWRSTS_ON, + .voltdm = { .name = "wakeup" }, }; diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c index cc389fb..2385c1f 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -1,7 +1,7 @@ /* * OMAP2XXX powerdomain definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc. * Copyright (C) 2007-2011 Nokia Corporation * * Paul Walmsley, Jouni Högander @@ -28,7 +28,6 @@ static struct powerdomain dsp_pwrdm = { .name = "dsp_pwrdm", .prcm_offs = OMAP24XX_DSP_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, @@ -38,12 +37,12 @@ static struct powerdomain dsp_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, }, + .voltdm = { .name = "core" }, }; static struct powerdomain mpu_24xx_pwrdm = { .name = "mpu_pwrdm", .prcm_offs = MPU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, @@ -53,12 +52,12 @@ static struct powerdomain mpu_24xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, }, + .voltdm = { .name = "core" }, }; static struct powerdomain core_24xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), .pwrsts = PWRSTS_OFF_RET_ON, .banks = 3, .pwrsts_mem_ret = { @@ -71,6 +70,7 @@ static struct powerdomain core_24xx_pwrdm = { [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */ }, + .voltdm = { .name = "core" }, }; @@ -78,14 +78,11 @@ static struct powerdomain core_24xx_pwrdm = { * 2430-specific powerdomains */ -#ifdef CONFIG_SOC_OMAP2430 - /* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ static struct powerdomain mdm_pwrdm = { .name = "mdm_pwrdm", .prcm_offs = OMAP2430_MDM_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, @@ -95,29 +92,44 @@ static struct powerdomain mdm_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, + .voltdm = { .name = "core" }, }; -#endif /* CONFIG_SOC_OMAP2430 */ - -/* As powerdomains are added or removed above, this list must also be changed */ -static struct powerdomain *powerdomains_omap2xxx[] __initdata = { +/* + * + */ +static struct powerdomain *powerdomains_omap24xx[] __initdata = { &wkup_omap2_pwrdm, &gfx_omap2_pwrdm, - -#ifdef CONFIG_ARCH_OMAP2 &dsp_pwrdm, &mpu_24xx_pwrdm, &core_24xx_pwrdm, -#endif + NULL +}; -#ifdef CONFIG_SOC_OMAP2430 +static struct powerdomain *powerdomains_omap2430[] __initdata = { &mdm_pwrdm, -#endif NULL }; -void __init omap2xxx_powerdomains_init(void) +void __init omap242x_powerdomains_init(void) +{ + if (!cpu_is_omap2420()) + return; + + pwrdm_register_platform_funcs(&omap2_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_omap24xx); + pwrdm_complete_init(); +} + +void __init omap243x_powerdomains_init(void) { - pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations); + if (!cpu_is_omap2430()) + return; + + pwrdm_register_platform_funcs(&omap2_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_omap24xx); + pwrdm_register_pwrdms(powerdomains_omap2430); + pwrdm_complete_init(); } diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 469a920..8ef26da 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -1,7 +1,7 @@ /* * OMAP3 powerdomain definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc. * Copyright (C) 2007-2011 Nokia Corporation * * Paul Walmsley, Jouni Högander @@ -14,6 +14,8 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <plat/cpu.h> + #include "powerdomain.h" #include "powerdomains2xxx_3xxx_data.h" @@ -27,8 +29,6 @@ * 34XX-specific powerdomains, dependencies */ -#ifdef CONFIG_ARCH_OMAP3 - /* * Powerdomains */ @@ -36,7 +36,6 @@ static struct powerdomain iva2_pwrdm = { .name = "iva2_pwrdm", .prcm_offs = OMAP3430_IVA2_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 4, @@ -52,12 +51,12 @@ static struct powerdomain iva2_pwrdm = { [2] = PWRSTS_OFF_ON, [3] = PWRSTS_ON, }, + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain mpu_3xxx_pwrdm = { .name = "mpu_pwrdm", .prcm_offs = MPU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .flags = PWRDM_HAS_MPU_QUIRK, @@ -68,6 +67,7 @@ static struct powerdomain mpu_3xxx_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_OFF_ON, }, + .voltdm = { .name = "mpu_iva" }, }; /* @@ -83,10 +83,6 @@ static struct powerdomain mpu_3xxx_pwrdm = { static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | - CHIP_IS_OMAP3430ES2 | - CHIP_IS_OMAP3430ES3_0 | - CHIP_IS_OMAP3630ES1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 2, @@ -98,13 +94,12 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ }, + .voltdm = { .name = "core" }, }; static struct powerdomain core_3xxx_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | - CHIP_GE_OMAP3630ES1_1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, /* @@ -121,11 +116,11 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = { [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ }, + .voltdm = { .name = "core" }, }; static struct powerdomain dss_pwrdm = { .name = "dss_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .prcm_offs = OMAP3430_DSS_MOD, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_RET, @@ -136,6 +131,7 @@ static struct powerdomain dss_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, + .voltdm = { .name = "core" }, }; /* @@ -146,7 +142,6 @@ static struct powerdomain dss_pwrdm = { static struct powerdomain sgx_pwrdm = { .name = "sgx_pwrdm", .prcm_offs = OMAP3430ES2_SGX_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), /* XXX This is accurate for 3430 SGX, but what about GFX? */ .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_RET, @@ -157,11 +152,11 @@ static struct powerdomain sgx_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, + .voltdm = { .name = "core" }, }; static struct powerdomain cam_pwrdm = { .name = "cam_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .prcm_offs = OMAP3430_CAM_MOD, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_RET, @@ -172,12 +167,12 @@ static struct powerdomain cam_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, + .voltdm = { .name = "core" }, }; static struct powerdomain per_pwrdm = { .name = "per_pwrdm", .prcm_offs = OMAP3430_PER_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, @@ -187,26 +182,26 @@ static struct powerdomain per_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, + .voltdm = { .name = "core" }, }; static struct powerdomain emu_pwrdm = { .name = "emu_pwrdm", .prcm_offs = OMAP3430_EMU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .voltdm = { .name = "core" }, }; static struct powerdomain neon_pwrdm = { .name = "neon_pwrdm", .prcm_offs = OMAP3430_NEON_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_RET, + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain usbhost_pwrdm = { .name = "usbhost_pwrdm", .prcm_offs = OMAP3430ES2_USBHOST_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_RET, /* @@ -223,65 +218,103 @@ static struct powerdomain usbhost_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, + .voltdm = { .name = "core" }, }; static struct powerdomain dpll1_pwrdm = { .name = "dpll1_pwrdm", .prcm_offs = MPU_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain dpll2_pwrdm = { .name = "dpll2_pwrdm", .prcm_offs = OMAP3430_IVA2_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain dpll3_pwrdm = { .name = "dpll3_pwrdm", .prcm_offs = PLL_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .voltdm = { .name = "core" }, }; static struct powerdomain dpll4_pwrdm = { .name = "dpll4_pwrdm", .prcm_offs = PLL_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .voltdm = { .name = "core" }, }; static struct powerdomain dpll5_pwrdm = { .name = "dpll5_pwrdm", .prcm_offs = PLL_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), + .voltdm = { .name = "core" }, }; /* As powerdomains are added or removed above, this list must also be changed */ -static struct powerdomain *powerdomains_omap3xxx[] __initdata = { - +static struct powerdomain *powerdomains_omap3430_common[] __initdata = { &wkup_omap2_pwrdm, - &gfx_omap2_pwrdm, &iva2_pwrdm, &mpu_3xxx_pwrdm, &neon_pwrdm, - &core_3xxx_pre_es3_1_pwrdm, - &core_3xxx_es3_1_pwrdm, &cam_pwrdm, &dss_pwrdm, &per_pwrdm, &emu_pwrdm, - &sgx_pwrdm, - &usbhost_pwrdm, &dpll1_pwrdm, &dpll2_pwrdm, &dpll3_pwrdm, &dpll4_pwrdm, + NULL +}; + +static struct powerdomain *powerdomains_omap3430es1[] __initdata = { + &gfx_omap2_pwrdm, + &core_3xxx_pre_es3_1_pwrdm, + NULL +}; + +/* also includes 3630ES1.0 */ +static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = { + &core_3xxx_pre_es3_1_pwrdm, + &sgx_pwrdm, + &usbhost_pwrdm, &dpll5_pwrdm, -#endif NULL }; +/* also includes 3630ES1.1+ */ +static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = { + &core_3xxx_es3_1_pwrdm, + &sgx_pwrdm, + &usbhost_pwrdm, + &dpll5_pwrdm, + NULL +}; void __init omap3xxx_powerdomains_init(void) { - pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations); + unsigned int rev; + + if (!cpu_is_omap34xx()) + return; + + pwrdm_register_platform_funcs(&omap3_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_omap3430_common); + + rev = omap_rev(); + + if (rev == OMAP3430_REV_ES1_0) + pwrdm_register_pwrdms(powerdomains_omap3430es1); + else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || + rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0) + pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); + else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 || + rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 || + rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) + pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); + else + WARN(1, "OMAP3 powerdomain init: unknown chip type\n"); + + pwrdm_complete_init(); } diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c index 247e794..704664c 100644 --- a/arch/arm/mach-omap2/powerdomains44xx_data.c +++ b/arch/arm/mach-omap2/powerdomains44xx_data.c @@ -33,9 +33,9 @@ /* core_44xx_pwrdm: CORE power domain */ static struct powerdomain core_44xx_pwrdm = { .name = "core_pwrdm", + .voltdm = { .name = "core" }, .prcm_offs = OMAP4430_PRM_CORE_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 5, @@ -59,9 +59,9 @@ static struct powerdomain core_44xx_pwrdm = { /* gfx_44xx_pwrdm: 3D accelerator power domain */ static struct powerdomain gfx_44xx_pwrdm = { .name = "gfx_pwrdm", + .voltdm = { .name = "core" }, .prcm_offs = OMAP4430_PRM_GFX_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_ON, .banks = 1, .pwrsts_mem_ret = { @@ -76,9 +76,9 @@ static struct powerdomain gfx_44xx_pwrdm = { /* abe_44xx_pwrdm: Audio back end power domain */ static struct powerdomain abe_44xx_pwrdm = { .name = "abe_pwrdm", + .voltdm = { .name = "iva" }, .prcm_offs = OMAP4430_PRM_ABE_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 2, @@ -96,9 +96,9 @@ static struct powerdomain abe_44xx_pwrdm = { /* dss_44xx_pwrdm: Display subsystem power domain */ static struct powerdomain dss_44xx_pwrdm = { .name = "dss_pwrdm", + .voltdm = { .name = "core" }, .prcm_offs = OMAP4430_PRM_DSS_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, @@ -114,9 +114,9 @@ static struct powerdomain dss_44xx_pwrdm = { /* tesla_44xx_pwrdm: Tesla processor power domain */ static struct powerdomain tesla_44xx_pwrdm = { .name = "tesla_pwrdm", + .voltdm = { .name = "iva" }, .prcm_offs = OMAP4430_PRM_TESLA_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 3, @@ -136,9 +136,9 @@ static struct powerdomain tesla_44xx_pwrdm = { /* wkup_44xx_pwrdm: Wake-up power domain */ static struct powerdomain wkup_44xx_pwrdm = { .name = "wkup_pwrdm", + .voltdm = { .name = "wakeup" }, .prcm_offs = OMAP4430_PRM_WKUP_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_ON, .banks = 1, .pwrsts_mem_ret = { @@ -152,9 +152,9 @@ static struct powerdomain wkup_44xx_pwrdm = { /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ static struct powerdomain cpu0_44xx_pwrdm = { .name = "cpu0_pwrdm", + .voltdm = { .name = "mpu" }, .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST, .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, @@ -169,9 +169,9 @@ static struct powerdomain cpu0_44xx_pwrdm = { /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ static struct powerdomain cpu1_44xx_pwrdm = { .name = "cpu1_pwrdm", + .voltdm = { .name = "mpu" }, .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST, .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, @@ -186,9 +186,9 @@ static struct powerdomain cpu1_44xx_pwrdm = { /* emu_44xx_pwrdm: Emulation power domain */ static struct powerdomain emu_44xx_pwrdm = { .name = "emu_pwrdm", + .voltdm = { .name = "wakeup" }, .prcm_offs = OMAP4430_PRM_EMU_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_ON, .banks = 1, .pwrsts_mem_ret = { @@ -202,9 +202,9 @@ static struct powerdomain emu_44xx_pwrdm = { /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ static struct powerdomain mpu_44xx_pwrdm = { .name = "mpu_pwrdm", + .voltdm = { .name = "mpu" }, .prcm_offs = OMAP4430_PRM_MPU_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 3, @@ -223,9 +223,9 @@ static struct powerdomain mpu_44xx_pwrdm = { /* ivahd_44xx_pwrdm: IVA-HD power domain */ static struct powerdomain ivahd_44xx_pwrdm = { .name = "ivahd_pwrdm", + .voltdm = { .name = "iva" }, .prcm_offs = OMAP4430_PRM_IVAHD_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 4, @@ -247,9 +247,9 @@ static struct powerdomain ivahd_44xx_pwrdm = { /* cam_44xx_pwrdm: Camera subsystem power domain */ static struct powerdomain cam_44xx_pwrdm = { .name = "cam_pwrdm", + .voltdm = { .name = "core" }, .prcm_offs = OMAP4430_PRM_CAM_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_ON, .banks = 1, .pwrsts_mem_ret = { @@ -264,9 +264,9 @@ static struct powerdomain cam_44xx_pwrdm = { /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ static struct powerdomain l3init_44xx_pwrdm = { .name = "l3init_pwrdm", + .voltdm = { .name = "core" }, .prcm_offs = OMAP4430_PRM_L3INIT_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, @@ -282,9 +282,9 @@ static struct powerdomain l3init_44xx_pwrdm = { /* l4per_44xx_pwrdm: Target peripherals power domain */ static struct powerdomain l4per_44xx_pwrdm = { .name = "l4per_pwrdm", + .voltdm = { .name = "core" }, .prcm_offs = OMAP4430_PRM_L4PER_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 2, @@ -305,18 +305,18 @@ static struct powerdomain l4per_44xx_pwrdm = { */ static struct powerdomain always_on_core_44xx_pwrdm = { .name = "always_on_core_pwrdm", + .voltdm = { .name = "core" }, .prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_ON, }; /* cefuse_44xx_pwrdm: Customer efuse controller power domain */ static struct powerdomain cefuse_44xx_pwrdm = { .name = "cefuse_pwrdm", + .voltdm = { .name = "core" }, .prcm_offs = OMAP4430_PRM_CEFUSE_INST, .prcm_partition = OMAP4430_PRM_PARTITION, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_ON, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -352,5 +352,7 @@ static struct powerdomain *powerdomains_omap44xx[] __initdata = { void __init omap44xx_powerdomains_init(void) { - pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations); + pwrdm_register_platform_funcs(&omap4_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_omap44xx); + pwrdm_complete_init(); } diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 051213f..f02d87f 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -20,6 +20,8 @@ #include <plat/cpu.h> #include <plat/prcm.h> +#include "vp.h" + #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" #include "prm-regbits-24xx.h" @@ -156,3 +158,57 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; } + +/* PRM VP */ + +/* + * struct omap3_vp - OMAP3 VP register access description. + * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg + */ +struct omap3_vp { + u32 tranxdone_status; +}; + +static struct omap3_vp omap3_vp[] = { + [OMAP3_VP_VDD_MPU_ID] = { + .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK, + }, + [OMAP3_VP_VDD_CORE_ID] = { + .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK, + }, +}; + +#define MAX_VP_ID ARRAY_SIZE(omap3_vp); + +u32 omap3_prm_vp_check_txdone(u8 vp_id) +{ + struct omap3_vp *vp = &omap3_vp[vp_id]; + u32 irqstatus; + + irqstatus = omap2_prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + return irqstatus & vp->tranxdone_status; +} + +void omap3_prm_vp_clear_txdone(u8 vp_id) +{ + struct omap3_vp *vp = &omap3_vp[vp_id]; + + omap2_prm_write_mod_reg(vp->tranxdone_status, + OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); +} + +u32 omap3_prm_vcvp_read(u8 offset) +{ + return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset); +} + +void omap3_prm_vcvp_write(u32 val, u8 offset) +{ + omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); +} + +u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) +{ + return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); +} diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index a1fc62a..cef533d 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -303,7 +303,19 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); +/* OMAP3-specific VP functions */ +u32 omap3_prm_vp_check_txdone(u8 vp_id); +void omap3_prm_vp_clear_txdone(u8 vp_id); + +/* + * OMAP3 access functions for voltage controller (VC) and + * voltage proccessor (VP) in the PRM. + */ +extern u32 omap3_prm_vcvp_read(u8 offset); +extern void omap3_prm_vcvp_write(u32 val, u8 offset); +extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); #endif /* CONFIG_ARCH_OMAP4 */ + #endif /* diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 0016555..495a31a 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -21,8 +21,11 @@ #include <plat/cpu.h> #include <plat/prcm.h> +#include "vp.h" #include "prm44xx.h" #include "prm-regbits-44xx.h" +#include "prcm44xx.h" +#include "prminst44xx.h" /* PRM low-level functions */ @@ -50,3 +53,71 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) return v; } + +/* PRM VP */ + +/* + * struct omap4_vp - OMAP4 VP register access description. + * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP + * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg + */ +struct omap4_vp { + u32 irqstatus_mpu; + u32 tranxdone_status; +}; + +static struct omap4_vp omap4_vp[] = { + [OMAP4_VP_VDD_MPU_ID] = { + .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET, + .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK, + }, + [OMAP4_VP_VDD_IVA_ID] = { + .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, + .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK, + }, + [OMAP4_VP_VDD_CORE_ID] = { + .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, + .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK, + }, +}; + +u32 omap4_prm_vp_check_txdone(u8 vp_id) +{ + struct omap4_vp *vp = &omap4_vp[vp_id]; + u32 irqstatus; + + irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, + OMAP4430_PRM_OCP_SOCKET_INST, + vp->irqstatus_mpu); + return irqstatus & vp->tranxdone_status; +} + +void omap4_prm_vp_clear_txdone(u8 vp_id) +{ + struct omap4_vp *vp = &omap4_vp[vp_id]; + + omap4_prminst_write_inst_reg(vp->tranxdone_status, + OMAP4430_PRM_PARTITION, + OMAP4430_PRM_OCP_SOCKET_INST, + vp->irqstatus_mpu); +}; + +u32 omap4_prm_vcvp_read(u8 offset) +{ + return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, + OMAP4430_PRM_DEVICE_INST, offset); +} + +void omap4_prm_vcvp_write(u32 val, u8 offset) +{ + omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, + OMAP4430_PRM_DEVICE_INST, offset); +} + +u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) +{ + return omap4_prminst_rmw_inst_reg_bits(mask, bits, + OMAP4430_PRM_PARTITION, + OMAP4430_PRM_DEVICE_INST, + offset); +} diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 7dfa379..3d66ccd 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -751,6 +751,18 @@ extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); +/* OMAP4-specific VP functions */ +u32 omap4_prm_vp_check_txdone(u8 vp_id); +void omap4_prm_vp_clear_txdone(u8 vp_id); + +/* + * OMAP4 access functions for voltage controller (VC) and + * voltage proccessor (VP) in the PRM. + */ +extern u32 omap4_prm_vcvp_read(u8 offset); +extern void omap4_prm_vcvp_write(u32 val, u8 offset); +extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); + # endif #endif diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 466fc722..3d1c1d3 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -711,7 +711,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) { struct omap_uart_state *uart; struct omap_hwmod *oh; - struct omap_device *od; + struct platform_device *pdev; void *pdata = NULL; u32 pdata_size = 0; char *name; @@ -799,20 +799,20 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) if (WARN_ON(!oh)) return; - od = omap_device_build(name, uart->num, oh, pdata, pdata_size, + pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, omap_uart_latency, ARRAY_SIZE(omap_uart_latency), false); - WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", + WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", name, oh->name); - omap_device_disable_idle_on_suspend(od); + omap_device_disable_idle_on_suspend(pdev); oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); uart->irq = oh->mpu_irqs[0].irq; uart->regshift = 2; uart->mapbase = oh->slaves[0]->addr->pa_start; uart->membase = omap_hwmod_get_mpu_rt_va(oh); - uart->pdev = &od->pdev; + uart->pdev = pdev; oh->dev_attr = uart; @@ -846,8 +846,8 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) if ((cpu_is_omap34xx() && uart->padconf) || (uart->wk_en && uart->wk_mask)) { - device_init_wakeup(&od->pdev.dev, true); - DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout); + device_init_wakeup(&pdev->dev, true); + DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout); } /* Enable the MDR1 errata for OMAP3 */ diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c index f438cf4..53d9d0a 100644 --- a/arch/arm/mach-omap2/smartreflex-class3.c +++ b/arch/arm/mach-omap2/smartreflex-class3.c @@ -15,7 +15,7 @@ static int sr_class3_enable(struct voltagedomain *voltdm) { - unsigned long volt = omap_voltage_get_nom_volt(voltdm); + unsigned long volt = voltdm_get_voltage(voltdm); if (!volt) { pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n", @@ -32,7 +32,7 @@ static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset) omap_vp_disable(voltdm); sr_disable(voltdm); if (is_volt_reset) - omap_voltage_reset(voltdm); + voltdm_reset(voltdm); return 0; } diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 34c01a7..0347b93 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -62,6 +62,7 @@ static LIST_HEAD(sr_list); static struct omap_sr_class_data *sr_class; static struct omap_sr_pmic_data *sr_pmic_data; +static struct dentry *sr_dbg_dir; static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value) { @@ -247,7 +248,7 @@ static void sr_stop_vddautocomp(struct omap_sr *sr) * driver register and sr device intializtion API's. Only one call * will ultimately succeed. * - * Currently this function registers interrrupt handler for a particular SR + * Currently this function registers interrupt handler for a particular SR * if smartreflex class driver is already registered and has * requested for interrupts and the SR interrupt line in present. */ @@ -826,9 +827,10 @@ static int __init omap_sr_probe(struct platform_device *pdev) struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL); struct omap_sr_data *pdata = pdev->dev.platform_data; struct resource *mem, *irq; - struct dentry *vdd_dbg_dir, *nvalue_dir; + struct dentry *nvalue_dir; struct omap_volt_data *volt_data; int i, ret = 0; + char *name; if (!sr_info) { dev_err(&pdev->dev, "%s: unable to allocate sr_info\n", @@ -899,18 +901,25 @@ static int __init omap_sr_probe(struct platform_device *pdev) } dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__); + if (!sr_dbg_dir) { + sr_dbg_dir = debugfs_create_dir("smartreflex", NULL); + if (!sr_dbg_dir) { + ret = PTR_ERR(sr_dbg_dir); + pr_err("%s:sr debugfs dir creation failed(%d)\n", + __func__, ret); + goto err_iounmap; + } + } - /* - * If the voltage domain debugfs directory is not created, do - * not try to create rest of the debugfs entries. - */ - vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm); - if (!vdd_dbg_dir) { - ret = -EINVAL; + name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name); + if (!name) { + dev_err(&pdev->dev, "%s: Unable to alloc debugfs name\n", + __func__); + ret = -ENOMEM; goto err_iounmap; } - - sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir); + sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir); + kfree(name); if (IS_ERR(sr_info->dbg_dir)) { dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n", __func__); diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 10d3c5e..eba9f9a 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -80,7 +80,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data, static int sr_dev_init(struct omap_hwmod *oh, void *user) { struct omap_sr_data *sr_data; - struct omap_device *od; + struct platform_device *pdev; struct omap_volt_data *volt_data; char *name = "smartreflex"; static int i; @@ -102,7 +102,7 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user) sr_data->senn_mod = 0x1; sr_data->senp_mod = 0x1; - sr_data->voltdm = omap_voltage_domain_lookup(oh->vdd_name); + sr_data->voltdm = voltdm_lookup(oh->vdd_name); if (IS_ERR(sr_data->voltdm)) { pr_err("%s: Unable to get voltage domain pointer for VDD %s\n", __func__, oh->vdd_name); @@ -120,10 +120,10 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user) sr_data->enable_on_init = sr_enable_on_init; - od = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), + pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), omap_sr_latency, ARRAY_SIZE(omap_sr_latency), 0); - if (IS_ERR(od)) + if (IS_ERR(pdev)) pr_warning("%s: Could not build omap_device for %s: %s.\n\n", __func__, name, oh->name); exit: diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index cf1de7d..1140e98 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -35,6 +35,7 @@ #include <linux/irq.h> #include <linux/clocksource.h> #include <linux/clockchips.h> +#include <linux/slab.h> #include <asm/mach/time.h> #include <plat/dmtimer.h> @@ -42,6 +43,10 @@ #include <asm/sched_clock.h> #include <plat/common.h> #include <plat/omap_hwmod.h> +#include <plat/omap_device.h> +#include <plat/omap-pm.h> + +#include "powerdomain.h" /* Parent clocks, eventually these will come from the clock framework */ @@ -67,7 +72,7 @@ /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12 -u32 sys_timer_reserved; +static u32 sys_timer_reserved; /* Clockevent code */ @@ -78,7 +83,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = &clockevent_gpt; - __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW); + __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); evt->event_handler(evt); return IRQ_HANDLED; @@ -93,7 +98,7 @@ static struct irqaction omap2_gp_timer_irq = { static int omap2_gp_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST, + __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 0xffffffff - cycles, 1); return 0; @@ -104,16 +109,16 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, { u32 period; - __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate); + __omap_dm_timer_stop(&clkev, 1, clkev.rate); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: period = clkev.rate / HZ; period -= 1; /* Looks like we need to first set the load value separately */ - __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG, + __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, 1); - __omap_dm_timer_load_start(clkev.io_base, + __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 0xffffffff - period, 1); break; @@ -189,7 +194,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, clk_put(src); } } - __omap_dm_timer_reset(timer->io_base, 1, 1); + __omap_dm_timer_init_regs(timer); + __omap_dm_timer_reset(timer, 1, 1); timer->posted = 1; timer->rate = clk_get_rate(timer->fclk); @@ -210,7 +216,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, omap2_gp_timer_irq.dev_id = (void *)&clkev; setup_irq(clkev.irq, &omap2_gp_timer_irq); - __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW); + __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, clockevent_gpt.shift); @@ -251,7 +257,7 @@ static struct omap_dm_timer clksrc; static DEFINE_CLOCK_DATA(cd); static cycle_t clocksource_read_cycles(struct clocksource *cs) { - return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1); + return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); } static struct clocksource clocksource_gpt = { @@ -266,7 +272,7 @@ static void notrace dmtimer_update_sched_clock(void) { u32 cyc; - cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1); + cyc = __omap_dm_timer_read_counter(&clksrc, 1); update_sched_clock(&cd, cyc, (u32)~0); } @@ -276,7 +282,7 @@ unsigned long long notrace sched_clock(void) u32 cyc = 0; if (clksrc.reserved) - cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1); + cyc = __omap_dm_timer_read_counter(&clksrc, 1); return cyc_to_sched_clock(&cd, cyc, (u32)~0); } @@ -293,7 +299,7 @@ static void __init omap2_gp_clocksource_init(int gptimer_id, pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", gptimer_id, clksrc.rate); - __omap_dm_timer_load_start(clksrc.io_base, + __omap_dm_timer_load_start(&clksrc, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate); @@ -341,3 +347,167 @@ static void __init omap4_timer_init(void) } OMAP_SYS_TIMER(4) #endif + +/** + * omap2_dm_timer_set_src - change the timer input clock source + * @pdev: timer platform device pointer + * @source: array index of parent clock source + */ +static int omap2_dm_timer_set_src(struct platform_device *pdev, int source) +{ + int ret; + struct dmtimer_platform_data *pdata = pdev->dev.platform_data; + struct clk *fclk, *parent; + char *parent_name = NULL; + + fclk = clk_get(&pdev->dev, "fck"); + if (IS_ERR_OR_NULL(fclk)) { + dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n", + __func__, __LINE__); + return -EINVAL; + } + + switch (source) { + case OMAP_TIMER_SRC_SYS_CLK: + parent_name = "sys_ck"; + break; + + case OMAP_TIMER_SRC_32_KHZ: + parent_name = "32k_ck"; + break; + + case OMAP_TIMER_SRC_EXT_CLK: + if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) { + parent_name = "alt_ck"; + break; + } + dev_err(&pdev->dev, "%s: %d: invalid clk src.\n", + __func__, __LINE__); + clk_put(fclk); + return -EINVAL; + } + + parent = clk_get(&pdev->dev, parent_name); + if (IS_ERR_OR_NULL(parent)) { + dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n", + __func__, __LINE__, parent_name); + clk_put(fclk); + return -EINVAL; + } + + ret = clk_set_parent(fclk, parent); + if (IS_ERR_VALUE(ret)) { + dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n", + __func__, parent_name); + ret = -EINVAL; + } + + clk_put(parent); + clk_put(fclk); + + return ret; +} + +struct omap_device_pm_latency omap2_dmtimer_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +/** + * omap_timer_init - build and register timer device with an + * associated timer hwmod + * @oh: timer hwmod pointer to be used to build timer device + * @user: parameter that can be passed from calling hwmod API + * + * Called by omap_hwmod_for_each_by_class to register each of the timer + * devices present in the system. The number of timer devices is known + * by parsing through the hwmod database for a given class name. At the + * end of function call memory is allocated for timer device and it is + * registered to the framework ready to be proved by the driver. + */ +static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) +{ + int id; + int ret = 0; + char *name = "omap_timer"; + struct dmtimer_platform_data *pdata; + struct omap_device *od; + struct omap_timer_capability_dev_attr *timer_dev_attr; + struct powerdomain *pwrdm; + + pr_debug("%s: %s\n", __func__, oh->name); + + /* on secure device, do not register secure timer */ + timer_dev_attr = oh->dev_attr; + if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) + if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) + return ret; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + pr_err("%s: No memory for [%s]\n", __func__, oh->name); + return -ENOMEM; + } + + /* + * Extract the IDs from name field in hwmod database + * and use the same for constructing ids' for the + * timer devices. In a way, we are avoiding usage of + * static variable witin the function to do the same. + * CAUTION: We have to be careful and make sure the + * name in hwmod database does not change in which case + * we might either make corresponding change here or + * switch back static variable mechanism. + */ + sscanf(oh->name, "timer%2d", &id); + + pdata->set_timer_src = omap2_dm_timer_set_src; + pdata->timer_ip_version = oh->class->rev; + + /* Mark clocksource and clockevent timers as reserved */ + if ((sys_timer_reserved >> (id - 1)) & 0x1) + pdata->reserved = 1; + + pwrdm = omap_hwmod_get_pwrdm(oh); + pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); +#ifdef CONFIG_PM + pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; +#endif + od = omap_device_build(name, id, oh, pdata, sizeof(*pdata), + omap2_dmtimer_latency, + ARRAY_SIZE(omap2_dmtimer_latency), + 0); + + if (IS_ERR(od)) { + pr_err("%s: Can't build omap_device for %s: %s.\n", + __func__, name, oh->name); + ret = -EINVAL; + } + + kfree(pdata); + + return ret; +} + +/** + * omap2_dm_timer_init - top level regular device initialization + * + * Uses dedicated hwmod api to parse through hwmod database for + * given class name and then build and register the timer device. + */ +static int __init omap2_dm_timer_init(void) +{ + int ret; + + ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); + if (unlikely(ret)) { + pr_err("%s: device registration failed.\n", __func__); + return -EINVAL; + } + + return 0; +} +arch_initcall(omap2_dm_timer_init); diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index daa056e..52243577 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -99,7 +99,7 @@ static struct regulator_init_data omap3_vdac_idata = { static struct regulator_consumer_supply omap3_vpll2_supplies[] = { REGULATOR_SUPPLY("vdds_dsi", "omapdss"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), }; static struct regulator_init_data omap3_vpll2_idata = { @@ -235,6 +235,12 @@ static struct regulator_init_data omap4_vana_idata = { }, }; +static struct regulator_consumer_supply omap4_vcxio_supply[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.1"), +}; + static struct regulator_init_data omap4_vcxio_idata = { .constraints = { .min_uV = 1800000, @@ -243,7 +249,10 @@ static struct regulator_init_data omap4_vcxio_idata = { | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, + .always_on = true, }, + .num_consumer_supplies = ARRAY_SIZE(omap4_vcxio_supply), + .consumer_supplies = omap4_vcxio_supply, }; static struct regulator_init_data omap4_vusb_idata = { diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index a65145b..19e4dac 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -137,9 +137,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) musb_plat.mode = board_data->mode; musb_plat.extvbus = board_data->extvbus; - if (cpu_is_omap44xx()) - omap4430_phy_init(dev); - if (cpu_is_omap3517() || cpu_is_omap3505()) { oh_name = "am35x_otg_hs"; name = "musb-am35x"; diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c new file mode 100644 index 0000000..031d116 --- /dev/null +++ b/arch/arm/mach-omap2/vc.c @@ -0,0 +1,367 @@ +/* + * OMAP Voltage Controller (VC) interface + * + * Copyright (C) 2011 Texas Instruments, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/init.h> + +#include <plat/cpu.h> + +#include "voltage.h" +#include "vc.h" +#include "prm-regbits-34xx.h" +#include "prm-regbits-44xx.h" +#include "prm44xx.h" + +/** + * struct omap_vc_channel_cfg - describe the cfg_channel bitfield + * @sa: bit for slave address + * @rav: bit for voltage configuration register + * @rac: bit for command configuration register + * @racen: enable bit for RAC + * @cmd: bit for command value set selection + * + * Channel configuration bits, common for OMAP3+ + * OMAP3 register: PRM_VC_CH_CONF + * OMAP4 register: PRM_VC_CFG_CHANNEL + * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG + */ +struct omap_vc_channel_cfg { + u8 sa; + u8 rav; + u8 rac; + u8 racen; + u8 cmd; +}; + +static struct omap_vc_channel_cfg vc_default_channel_cfg = { + .sa = BIT(0), + .rav = BIT(1), + .rac = BIT(2), + .racen = BIT(3), + .cmd = BIT(4), +}; + +/* + * On OMAP3+, all VC channels have the above default bitfield + * configuration, except the OMAP4 MPU channel. This appears + * to be a freak accident as every other VC channel has the + * default configuration, thus creating a mutant channel config. + */ +static struct omap_vc_channel_cfg vc_mutant_channel_cfg = { + .sa = BIT(0), + .rav = BIT(2), + .rac = BIT(3), + .racen = BIT(4), + .cmd = BIT(1), +}; + +static struct omap_vc_channel_cfg *vc_cfg_bits; +#define CFG_CHANNEL_MASK 0x1f + +/** + * omap_vc_config_channel - configure VC channel to PMIC mappings + * @voltdm: pointer to voltagdomain defining the desired VC channel + * + * Configures the VC channel to PMIC mappings for the following + * PMIC settings + * - i2c slave address (SA) + * - voltage configuration address (RAV) + * - command configuration address (RAC) and enable bit (RACEN) + * - command values for ON, ONLP, RET and OFF (CMD) + * + * This function currently only allows flexible configuration of the + * non-default channel. Starting with OMAP4, there are more than 2 + * channels, with one defined as the default (on OMAP4, it's MPU.) + * Only the non-default channel can be configured. + */ +static int omap_vc_config_channel(struct voltagedomain *voltdm) +{ + struct omap_vc_channel *vc = voltdm->vc; + + /* + * For default channel, the only configurable bit is RACEN. + * All others must stay at zero (see function comment above.) + */ + if (vc->flags & OMAP_VC_CHANNEL_DEFAULT) + vc->cfg_channel &= vc_cfg_bits->racen; + + voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift, + vc->cfg_channel << vc->cfg_channel_sa_shift, + vc->cfg_channel_reg); + + return 0; +} + +/* Voltage scale and accessory APIs */ +int omap_vc_pre_scale(struct voltagedomain *voltdm, + unsigned long target_volt, + u8 *target_vsel, u8 *current_vsel) +{ + struct omap_vc_channel *vc = voltdm->vc; + u32 vc_cmdval; + + /* Check if sufficient pmic info is available for this vdd */ + if (!voltdm->pmic) { + pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", + __func__, voltdm->name); + return -EINVAL; + } + + if (!voltdm->pmic->uv_to_vsel) { + pr_err("%s: PMIC function to convert voltage in uV to" + "vsel not registered. Hence unable to scale voltage" + "for vdd_%s\n", __func__, voltdm->name); + return -ENODATA; + } + + if (!voltdm->read || !voltdm->write) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, voltdm->name); + return -EINVAL; + } + + *target_vsel = voltdm->pmic->uv_to_vsel(target_volt); + *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt); + + /* Setting the ON voltage to the new target voltage */ + vc_cmdval = voltdm->read(vc->cmdval_reg); + vc_cmdval &= ~vc->common->cmd_on_mask; + vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift); + voltdm->write(vc_cmdval, vc->cmdval_reg); + + omap_vp_update_errorgain(voltdm, target_volt); + + return 0; +} + +void omap_vc_post_scale(struct voltagedomain *voltdm, + unsigned long target_volt, + u8 target_vsel, u8 current_vsel) +{ + u32 smps_steps = 0, smps_delay = 0; + + smps_steps = abs(target_vsel - current_vsel); + /* SMPS slew rate / step size. 2us added as buffer. */ + smps_delay = ((smps_steps * voltdm->pmic->step_size) / + voltdm->pmic->slew_rate) + 2; + udelay(smps_delay); +} + +/* vc_bypass_scale - VC bypass method of voltage scaling */ +int omap_vc_bypass_scale(struct voltagedomain *voltdm, + unsigned long target_volt) +{ + struct omap_vc_channel *vc = voltdm->vc; + u32 loop_cnt = 0, retries_cnt = 0; + u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; + u8 target_vsel, current_vsel; + int ret; + + ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel); + if (ret) + return ret; + + vc_valid = vc->common->valid; + vc_bypass_val_reg = vc->common->bypass_val_reg; + vc_bypass_value = (target_vsel << vc->common->data_shift) | + (vc->volt_reg_addr << vc->common->regaddr_shift) | + (vc->i2c_slave_addr << vc->common->slaveaddr_shift); + + voltdm->write(vc_bypass_value, vc_bypass_val_reg); + voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg); + + vc_bypass_value = voltdm->read(vc_bypass_val_reg); + /* + * Loop till the bypass command is acknowledged from the SMPS. + * NOTE: This is legacy code. The loop count and retry count needs + * to be revisited. + */ + while (!(vc_bypass_value & vc_valid)) { + loop_cnt++; + + if (retries_cnt > 10) { + pr_warning("%s: Retry count exceeded\n", __func__); + return -ETIMEDOUT; + } + + if (loop_cnt > 50) { + retries_cnt++; + loop_cnt = 0; + udelay(10); + } + vc_bypass_value = voltdm->read(vc_bypass_val_reg); + } + + omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); + return 0; +} + +static void __init omap3_vfsm_init(struct voltagedomain *voltdm) +{ + /* + * Voltage Manager FSM parameters init + * XXX This data should be passed in from the board file + */ + voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET); + voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET); + voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET); +} + +static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) +{ + static bool is_initialized; + + if (is_initialized) + return; + + omap3_vfsm_init(voltdm); + + is_initialized = true; +} + + +/* OMAP4 specific voltage init functions */ +static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) +{ + static bool is_initialized; + u32 vc_val; + + if (is_initialized) + return; + + /* XXX These are magic numbers and do not belong! */ + vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); + voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); + + is_initialized = true; +} + +/** + * omap_vc_i2c_init - initialize I2C interface to PMIC + * @voltdm: voltage domain containing VC data + * + * Use PMIC supplied seetings for I2C high-speed mode and + * master code (if set) and program the VC I2C configuration + * register. + * + * The VC I2C configuration is common to all VC channels, + * so this function only configures I2C for the first VC + * channel registers. All other VC channels will use the + * same configuration. + */ +static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) +{ + struct omap_vc_channel *vc = voltdm->vc; + static bool initialized; + static bool i2c_high_speed; + u8 mcode; + + if (initialized) { + if (voltdm->pmic->i2c_high_speed != i2c_high_speed) + pr_warn("%s: I2C config for all channels must match.", + __func__); + return; + } + + i2c_high_speed = voltdm->pmic->i2c_high_speed; + if (i2c_high_speed) + voltdm->rmw(vc->common->i2c_cfg_hsen_mask, + vc->common->i2c_cfg_hsen_mask, + vc->common->i2c_cfg_reg); + + mcode = voltdm->pmic->i2c_mcode; + if (mcode) + voltdm->rmw(vc->common->i2c_mcode_mask, + mcode << __ffs(vc->common->i2c_mcode_mask), + vc->common->i2c_cfg_reg); + + initialized = true; +} + +void __init omap_vc_init_channel(struct voltagedomain *voltdm) +{ + struct omap_vc_channel *vc = voltdm->vc; + u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; + u32 val; + + if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { + pr_err("%s: PMIC info requried to configure vc for" + "vdd_%s not populated.Hence cannot initialize vc\n", + __func__, voltdm->name); + return; + } + + if (!voltdm->read || !voltdm->write) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, voltdm->name); + return; + } + + vc->cfg_channel = 0; + if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT) + vc_cfg_bits = &vc_mutant_channel_cfg; + else + vc_cfg_bits = &vc_default_channel_cfg; + + /* get PMIC/board specific settings */ + vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr; + vc->volt_reg_addr = voltdm->pmic->volt_reg_addr; + vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; + vc->setup_time = voltdm->pmic->volt_setup_time; + + /* Configure the i2c slave address for this VC */ + voltdm->rmw(vc->smps_sa_mask, + vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), + vc->smps_sa_reg); + vc->cfg_channel |= vc_cfg_bits->sa; + + /* + * Configure the PMIC register addresses. + */ + voltdm->rmw(vc->smps_volra_mask, + vc->volt_reg_addr << __ffs(vc->smps_volra_mask), + vc->smps_volra_reg); + vc->cfg_channel |= vc_cfg_bits->rav; + + if (vc->cmd_reg_addr) { + voltdm->rmw(vc->smps_cmdra_mask, + vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), + vc->smps_cmdra_reg); + vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen; + } + + /* Set up the on, inactive, retention and off voltage */ + on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt); + onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt); + ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt); + off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt); + val = ((on_vsel << vc->common->cmd_on_shift) | + (onlp_vsel << vc->common->cmd_onlp_shift) | + (ret_vsel << vc->common->cmd_ret_shift) | + (off_vsel << vc->common->cmd_off_shift)); + voltdm->write(val, vc->cmdval_reg); + vc->cfg_channel |= vc_cfg_bits->cmd; + + /* Channel configuration */ + omap_vc_config_channel(voltdm); + + /* Configure the setup times */ + voltdm->rmw(voltdm->vfsm->voltsetup_mask, + vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask), + voltdm->vfsm->voltsetup_reg); + + omap_vc_i2c_init(voltdm); + + if (cpu_is_omap34xx()) + omap3_vc_init_channel(voltdm); + else if (cpu_is_omap44xx()) + omap4_vc_init_channel(voltdm); +} + diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h index e776777..478bf6b 100644 --- a/arch/arm/mach-omap2/vc.h +++ b/arch/arm/mach-omap2/vc.h @@ -19,12 +19,12 @@ #include <linux/kernel.h> +struct voltagedomain; + /** - * struct omap_vc_common_data - per-VC register/bitfield data + * struct omap_vc_common - per-VC register/bitfield data * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register - * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start - * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register @@ -33,15 +33,16 @@ * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register + * @i2c_cfg_reg: I2C configuration register offset + * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register + * @i2c_mcode_mask: MCODE field mask for I2C config register * * XXX One of cmd_on_mask and cmd_on_shift are not needed * XXX VALID should probably be a shift, not a mask */ -struct omap_vc_common_data { +struct omap_vc_common { u32 cmd_on_mask; u32 valid; - u8 smps_sa_reg; - u8 smps_volra_reg; u8 bypass_val_reg; u8 data_shift; u8 slaveaddr_shift; @@ -50,34 +51,75 @@ struct omap_vc_common_data { u8 cmd_onlp_shift; u8 cmd_ret_shift; u8 cmd_off_shift; + u8 i2c_cfg_reg; + u8 i2c_cfg_hsen_mask; + u8 i2c_mcode_mask; }; +/* omap_vc_channel.flags values */ +#define OMAP_VC_CHANNEL_DEFAULT BIT(0) +#define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1) + /** - * struct omap_vc_instance_data - VC per-instance data - * @vc_common: pointer to VC common data for this platform - * @smps_sa_mask: SA* bitmask in the PRM_VC_SMPS_SA register - * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register - * @smps_sa_shift: SA* field shift in the PRM_VC_SMPS_SA register - * @smps_volra_shift: VOLRA* field shift in the PRM_VC_VOL_RA register + * struct omap_vc_channel - VC per-instance data + * @i2c_slave_addr: I2C slave address of PMIC for this VC channel + * @volt_reg_addr: voltage configuration register address + * @cmd_reg_addr: command configuration register address + * @setup_time: setup time (in sys_clk cycles) of regulator for this channel + * @cfg_channel: current value of VC channel configuration register + * @i2c_high_speed: whether or not to use I2C high-speed mode * - * XXX It is not necessary to have both a *_mask and a *_shift - - * remove one + * @common: pointer to VC common data for this platform + * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register + * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register + * @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register + * @cmdval_reg: register for on/ret/off voltage level values for this channel + * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start + * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start + * @smps_cmdra_reg: Offset of PRM_VC_SMPS_CMD_RA reg from PRM start + * @cfg_channel_reg: VC channel configuration register + * @cfg_channel_sa_shift: bit shift for slave address cfg_channel register + * @flags: VC channel-specific flags (optional) */ -struct omap_vc_instance_data { - const struct omap_vc_common_data *vc_common; +struct omap_vc_channel { + /* channel state */ + u16 i2c_slave_addr; + u16 volt_reg_addr; + u16 cmd_reg_addr; + u16 setup_time; + u8 cfg_channel; + bool i2c_high_speed; + + /* register access data */ + const struct omap_vc_common *common; u32 smps_sa_mask; u32 smps_volra_mask; + u32 smps_cmdra_mask; u8 cmdval_reg; - u8 smps_sa_shift; - u8 smps_volra_shift; + u8 smps_sa_reg; + u8 smps_volra_reg; + u8 smps_cmdra_reg; + u8 cfg_channel_reg; + u8 cfg_channel_sa_shift; + u8 flags; }; -extern struct omap_vc_instance_data omap3_vc1_data; -extern struct omap_vc_instance_data omap3_vc2_data; +extern struct omap_vc_channel omap3_vc_mpu; +extern struct omap_vc_channel omap3_vc_core; + +extern struct omap_vc_channel omap4_vc_mpu; +extern struct omap_vc_channel omap4_vc_iva; +extern struct omap_vc_channel omap4_vc_core; -extern struct omap_vc_instance_data omap4_vc_mpu_data; -extern struct omap_vc_instance_data omap4_vc_iva_data; -extern struct omap_vc_instance_data omap4_vc_core_data; +void omap_vc_init_channel(struct voltagedomain *voltdm); +int omap_vc_pre_scale(struct voltagedomain *voltdm, + unsigned long target_volt, + u8 *target_vsel, u8 *current_vsel); +void omap_vc_post_scale(struct voltagedomain *voltdm, + unsigned long target_volt, + u8 target_vsel, u8 current_vsel); +int omap_vc_bypass_scale(struct voltagedomain *voltdm, + unsigned long target_volt); #endif diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c index f37dc4b..cfe348e 100644 --- a/arch/arm/mach-omap2/vc3xxx_data.c +++ b/arch/arm/mach-omap2/vc3xxx_data.c @@ -29,9 +29,7 @@ * VC data common to 34xx/36xx chips * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file. */ -static struct omap_vc_common_data omap3_vc_common = { - .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET, - .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET, +static struct omap_vc_common omap3_vc_common = { .bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET, .data_shift = OMAP3430_DATA_SHIFT, .slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT, @@ -42,22 +40,33 @@ static struct omap_vc_common_data omap3_vc_common = { .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, + .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK, + .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET, + .i2c_mcode_mask = OMAP3430_MCODE_MASK, }; -struct omap_vc_instance_data omap3_vc1_data = { - .vc_common = &omap3_vc_common, +struct omap_vc_channel omap3_vc_mpu = { + .common = &omap3_vc_common, + .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET, + .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET, + .smps_cmdra_reg = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET, + .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET, .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET, - .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT, .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK, - .smps_volra_shift = OMAP3430_VOLRA0_SHIFT, .smps_volra_mask = OMAP3430_VOLRA0_MASK, + .smps_cmdra_mask = OMAP3430_CMDRA0_MASK, + .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT, }; -struct omap_vc_instance_data omap3_vc2_data = { - .vc_common = &omap3_vc_common, +struct omap_vc_channel omap3_vc_core = { + .common = &omap3_vc_common, + .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET, + .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET, + .smps_cmdra_reg = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET, + .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET, .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET, - .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT, .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK, - .smps_volra_shift = OMAP3430_VOLRA1_SHIFT, .smps_volra_mask = OMAP3430_VOLRA1_MASK, + .smps_cmdra_mask = OMAP3430_CMDRA1_MASK, + .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT, }; diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c index a98da8d..2740a96 100644 --- a/arch/arm/mach-omap2/vc44xx_data.c +++ b/arch/arm/mach-omap2/vc44xx_data.c @@ -30,9 +30,7 @@ * VC data common to 44xx chips * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file. */ -static const struct omap_vc_common_data omap4_vc_common = { - .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET, - .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET, +static const struct omap_vc_common omap4_vc_common = { .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET, .data_shift = OMAP4430_DATA_SHIFT, .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT, @@ -43,33 +41,49 @@ static const struct omap_vc_common_data omap4_vc_common = { .cmd_onlp_shift = OMAP4430_ONLP_SHIFT, .cmd_ret_shift = OMAP4430_RET_SHIFT, .cmd_off_shift = OMAP4430_OFF_SHIFT, + .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET, + .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK, + .i2c_mcode_mask = OMAP4430_HSMCODE_MASK, }; /* VC instance data for each controllable voltage line */ -struct omap_vc_instance_data omap4_vc_mpu_data = { - .vc_common = &omap4_vc_common, +struct omap_vc_channel omap4_vc_mpu = { + .flags = OMAP_VC_CHANNEL_DEFAULT | OMAP_VC_CHANNEL_CFG_MUTANT, + .common = &omap4_vc_common, + .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET, + .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET, + .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET, + .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET, .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET, - .smps_sa_shift = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT, .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK, - .smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT, .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK, + .smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK, + .cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT, }; -struct omap_vc_instance_data omap4_vc_iva_data = { - .vc_common = &omap4_vc_common, +struct omap_vc_channel omap4_vc_iva = { + .common = &omap4_vc_common, + .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET, + .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET, + .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET, + .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET, .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET, - .smps_sa_shift = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT, .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK, - .smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT, .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK, + .smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK, + .cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT, }; -struct omap_vc_instance_data omap4_vc_core_data = { - .vc_common = &omap4_vc_common, +struct omap_vc_channel omap4_vc_core = { + .common = &omap4_vc_common, + .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET, + .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET, + .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET, + .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET, .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET, - .smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT, .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK, - .smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT, .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK, + .smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK, + .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT, }; diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 9ef3789..64070ac 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -21,10 +21,10 @@ #include <linux/delay.h> #include <linux/io.h> -#include <linux/clk.h> #include <linux/err.h> #include <linux/debugfs.h> #include <linux/slab.h> +#include <linux/clk.h> #include <plat/common.h> @@ -36,839 +36,88 @@ #include "control.h" #include "voltage.h" +#include "powerdomain.h" #include "vc.h" #include "vp.h" -#define VOLTAGE_DIR_SIZE 16 - - -static struct omap_vdd_info **vdd_info; - -/* - * Number of scalable voltage domains. - */ -static int nr_scalable_vdd; - -/* XXX document */ -static s16 prm_mod_offs; -static s16 prm_irqst_ocp_mod_offs; - -static struct dentry *voltage_dir; - -/* Init function pointers */ -static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd, - unsigned long target_volt); - -static u32 omap3_voltage_read_reg(u16 mod, u8 offset) -{ - return omap2_prm_read_mod_reg(mod, offset); -} - -static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset) -{ - omap2_prm_write_mod_reg(val, mod, offset); -} - -static u32 omap4_voltage_read_reg(u16 mod, u8 offset) -{ - return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, - mod, offset); -} - -static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset) -{ - omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset); -} - -static int __init _config_common_vdd_data(struct omap_vdd_info *vdd) -{ - char *sys_ck_name; - struct clk *sys_ck; - u32 sys_clk_speed, timeout_val, waittime; - - /* - * XXX Clockfw should handle this, or this should be in a - * struct record - */ - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - sys_ck_name = "sys_ck"; - else if (cpu_is_omap44xx()) - sys_ck_name = "sys_clkin_ck"; - else - return -EINVAL; - - /* - * Sys clk rate is require to calculate vp timeout value and - * smpswaittimemin and smpswaittimemax. - */ - sys_ck = clk_get(NULL, sys_ck_name); - if (IS_ERR(sys_ck)) { - pr_warning("%s: Could not get the sys clk to calculate" - "various vdd_%s params\n", __func__, vdd->voltdm.name); - return -EINVAL; - } - sys_clk_speed = clk_get_rate(sys_ck); - clk_put(sys_ck); - /* Divide to avoid overflow */ - sys_clk_speed /= 1000; - - /* Generic voltage parameters */ - vdd->volt_scale = vp_forceupdate_scale_voltage; - vdd->vp_enabled = false; - - vdd->vp_rt_data.vpconfig_erroroffset = - (vdd->pmic_info->vp_erroroffset << - vdd->vp_data->vp_common->vpconfig_erroroffset_shift); - - timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000; - vdd->vp_rt_data.vlimitto_timeout = timeout_val; - vdd->vp_rt_data.vlimitto_vddmin = vdd->pmic_info->vp_vddmin; - vdd->vp_rt_data.vlimitto_vddmax = vdd->pmic_info->vp_vddmax; - - waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) * - sys_clk_speed) / 1000; - vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime; - vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime; - vdd->vp_rt_data.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin; - vdd->vp_rt_data.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax; - - return 0; -} - -/* Voltage debugfs support */ -static int vp_volt_debug_get(void *data, u64 *val) -{ - struct omap_vdd_info *vdd = (struct omap_vdd_info *) data; - u8 vsel; - - if (!vdd) { - pr_warning("Wrong paramater passed\n"); - return -EINVAL; - } - - vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage); - - if (!vdd->pmic_info->vsel_to_uv) { - pr_warning("PMIC function to convert vsel to voltage" - "in uV not registerd\n"); - return -EINVAL; - } - - *val = vdd->pmic_info->vsel_to_uv(vsel); - return 0; -} - -static int nom_volt_debug_get(void *data, u64 *val) -{ - struct omap_vdd_info *vdd = (struct omap_vdd_info *) data; - - if (!vdd) { - pr_warning("Wrong paramater passed\n"); - return -EINVAL; - } - - *val = omap_voltage_get_nom_volt(&vdd->voltdm); - - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n"); -DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL, - "%llu\n"); -static void vp_latch_vsel(struct omap_vdd_info *vdd) -{ - u32 vpconfig; - unsigned long uvdc; - char vsel; - - uvdc = omap_voltage_get_nom_volt(&vdd->voltdm); - if (!uvdc) { - pr_warning("%s: unable to find current voltage for vdd_%s\n", - __func__, vdd->voltdm.name); - return; - } - - if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { - pr_warning("%s: PMIC function to convert voltage in uV to" - " vsel not registered\n", __func__); - return; - } - - vsel = vdd->pmic_info->uv_to_vsel(uvdc); - - vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig); - vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvoltage_mask | - vdd->vp_data->vp_common->vpconfig_initvdd); - vpconfig |= vsel << vdd->vp_data->vp_common->vpconfig_initvoltage_shift; - - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); - - /* Trigger initVDD value copy to voltage processor */ - vdd->write_reg((vpconfig | vdd->vp_data->vp_common->vpconfig_initvdd), - prm_mod_offs, vdd->vp_data->vpconfig); - - /* Clear initVDD copy trigger bit */ - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); -} - -/* Generic voltage init functions */ -static void __init vp_init(struct omap_vdd_info *vdd) -{ - u32 vp_val; - - if (!vdd->read_reg || !vdd->write_reg) { - pr_err("%s: No read/write API for accessing vdd_%s regs\n", - __func__, vdd->voltdm.name); - return; - } - - vp_val = vdd->vp_rt_data.vpconfig_erroroffset | - (vdd->vp_rt_data.vpconfig_errorgain << - vdd->vp_data->vp_common->vpconfig_errorgain_shift) | - vdd->vp_data->vp_common->vpconfig_timeouten; - vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vpconfig); - - vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin << - vdd->vp_data->vp_common->vstepmin_smpswaittimemin_shift) | - (vdd->vp_rt_data.vstepmin_stepmin << - vdd->vp_data->vp_common->vstepmin_stepmin_shift)); - vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmin); - - vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax << - vdd->vp_data->vp_common->vstepmax_smpswaittimemax_shift) | - (vdd->vp_rt_data.vstepmax_stepmax << - vdd->vp_data->vp_common->vstepmax_stepmax_shift)); - vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmax); - - vp_val = ((vdd->vp_rt_data.vlimitto_vddmax << - vdd->vp_data->vp_common->vlimitto_vddmax_shift) | - (vdd->vp_rt_data.vlimitto_vddmin << - vdd->vp_data->vp_common->vlimitto_vddmin_shift) | - (vdd->vp_rt_data.vlimitto_timeout << - vdd->vp_data->vp_common->vlimitto_timeout_shift)); - vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vlimitto); -} - -static void __init vdd_debugfs_init(struct omap_vdd_info *vdd) -{ - char *name; - - name = kzalloc(VOLTAGE_DIR_SIZE, GFP_KERNEL); - if (!name) { - pr_warning("%s: Unable to allocate memory for debugfs" - " directory name for vdd_%s", - __func__, vdd->voltdm.name); - return; - } - strcpy(name, "vdd_"); - strcat(name, vdd->voltdm.name); - - vdd->debug_dir = debugfs_create_dir(name, voltage_dir); - kfree(name); - if (IS_ERR(vdd->debug_dir)) { - pr_warning("%s: Unable to create debugfs directory for" - " vdd_%s\n", __func__, vdd->voltdm.name); - vdd->debug_dir = NULL; - return; - } - - (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir, - &(vdd->vp_rt_data.vpconfig_errorgain)); - (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO, - vdd->debug_dir, - &(vdd->vp_rt_data.vstepmin_smpswaittimemin)); - (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir, - &(vdd->vp_rt_data.vstepmin_stepmin)); - (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO, - vdd->debug_dir, - &(vdd->vp_rt_data.vstepmax_smpswaittimemax)); - (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir, - &(vdd->vp_rt_data.vstepmax_stepmax)); - (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir, - &(vdd->vp_rt_data.vlimitto_vddmax)); - (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir, - &(vdd->vp_rt_data.vlimitto_vddmin)); - (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir, - &(vdd->vp_rt_data.vlimitto_timeout)); - (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir, - (void *) vdd, &vp_volt_debug_fops); - (void) debugfs_create_file("curr_nominal_volt", S_IRUGO, - vdd->debug_dir, (void *) vdd, - &nom_volt_debug_fops); -} - -/* Voltage scale and accessory APIs */ -static int _pre_volt_scale(struct omap_vdd_info *vdd, - unsigned long target_volt, u8 *target_vsel, u8 *current_vsel) -{ - struct omap_volt_data *volt_data; - const struct omap_vc_common_data *vc_common; - const struct omap_vp_common_data *vp_common; - u32 vc_cmdval, vp_errgain_val; - - vc_common = vdd->vc_data->vc_common; - vp_common = vdd->vp_data->vp_common; - - /* Check if suffiecient pmic info is available for this vdd */ - if (!vdd->pmic_info) { - pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", - __func__, vdd->voltdm.name); - return -EINVAL; - } - - if (!vdd->pmic_info->uv_to_vsel) { - pr_err("%s: PMIC function to convert voltage in uV to" - "vsel not registered. Hence unable to scale voltage" - "for vdd_%s\n", __func__, vdd->voltdm.name); - return -ENODATA; - } - - if (!vdd->read_reg || !vdd->write_reg) { - pr_err("%s: No read/write API for accessing vdd_%s regs\n", - __func__, vdd->voltdm.name); - return -EINVAL; - } - - /* Get volt_data corresponding to target_volt */ - volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt); - if (IS_ERR(volt_data)) - volt_data = NULL; - - *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt); - *current_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage); - - /* Setting the ON voltage to the new target voltage */ - vc_cmdval = vdd->read_reg(prm_mod_offs, vdd->vc_data->cmdval_reg); - vc_cmdval &= ~vc_common->cmd_on_mask; - vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift); - vdd->write_reg(vc_cmdval, prm_mod_offs, vdd->vc_data->cmdval_reg); - - /* Setting vp errorgain based on the voltage */ - if (volt_data) { - vp_errgain_val = vdd->read_reg(prm_mod_offs, - vdd->vp_data->vpconfig); - vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain; - vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask; - vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain << - vp_common->vpconfig_errorgain_shift; - vdd->write_reg(vp_errgain_val, prm_mod_offs, - vdd->vp_data->vpconfig); - } - - return 0; -} - -static void _post_volt_scale(struct omap_vdd_info *vdd, - unsigned long target_volt, u8 target_vsel, u8 current_vsel) -{ - u32 smps_steps = 0, smps_delay = 0; - - smps_steps = abs(target_vsel - current_vsel); - /* SMPS slew rate / step size. 2us added as buffer. */ - smps_delay = ((smps_steps * vdd->pmic_info->step_size) / - vdd->pmic_info->slew_rate) + 2; - udelay(smps_delay); - - vdd->curr_volt = target_volt; -} - -/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */ -static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd, - unsigned long target_volt) -{ - u32 loop_cnt = 0, retries_cnt = 0; - u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; - u8 target_vsel, current_vsel; - int ret; - - ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel); - if (ret) - return ret; - - vc_valid = vdd->vc_data->vc_common->valid; - vc_bypass_val_reg = vdd->vc_data->vc_common->bypass_val_reg; - vc_bypass_value = (target_vsel << vdd->vc_data->vc_common->data_shift) | - (vdd->pmic_info->pmic_reg << - vdd->vc_data->vc_common->regaddr_shift) | - (vdd->pmic_info->i2c_slave_addr << - vdd->vc_data->vc_common->slaveaddr_shift); - - vdd->write_reg(vc_bypass_value, prm_mod_offs, vc_bypass_val_reg); - vdd->write_reg(vc_bypass_value | vc_valid, prm_mod_offs, - vc_bypass_val_reg); - - vc_bypass_value = vdd->read_reg(prm_mod_offs, vc_bypass_val_reg); - /* - * Loop till the bypass command is acknowledged from the SMPS. - * NOTE: This is legacy code. The loop count and retry count needs - * to be revisited. - */ - while (!(vc_bypass_value & vc_valid)) { - loop_cnt++; - - if (retries_cnt > 10) { - pr_warning("%s: Retry count exceeded\n", __func__); - return -ETIMEDOUT; - } - - if (loop_cnt > 50) { - retries_cnt++; - loop_cnt = 0; - udelay(10); - } - vc_bypass_value = vdd->read_reg(prm_mod_offs, - vc_bypass_val_reg); - } - - _post_volt_scale(vdd, target_volt, target_vsel, current_vsel); - return 0; -} - -/* VP force update method of voltage scaling */ -static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd, - unsigned long target_volt) -{ - u32 vpconfig; - u8 target_vsel, current_vsel, prm_irqst_reg; - int ret, timeout = 0; - - ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel); - if (ret) - return ret; - - prm_irqst_reg = vdd->vp_data->prm_irqst_data->prm_irqst_reg; - - /* - * Clear all pending TransactionDone interrupt/status. Typical latency - * is <3us - */ - while (timeout++ < VP_TRANXDONE_TIMEOUT) { - vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status, - prm_irqst_ocp_mod_offs, prm_irqst_reg); - if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) & - vdd->vp_data->prm_irqst_data->tranxdone_status)) - break; - udelay(1); - } - if (timeout >= VP_TRANXDONE_TIMEOUT) { - pr_warning("%s: vdd_%s TRANXDONE timeout exceeded." - "Voltage change aborted", __func__, vdd->voltdm.name); - return -ETIMEDOUT; - } - - /* Configure for VP-Force Update */ - vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig); - vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvdd | - vdd->vp_data->vp_common->vpconfig_forceupdate | - vdd->vp_data->vp_common->vpconfig_initvoltage_mask); - vpconfig |= ((target_vsel << - vdd->vp_data->vp_common->vpconfig_initvoltage_shift)); - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); - - /* Trigger initVDD value copy to voltage processor */ - vpconfig |= vdd->vp_data->vp_common->vpconfig_initvdd; - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); - - /* Force update of voltage */ - vpconfig |= vdd->vp_data->vp_common->vpconfig_forceupdate; - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); - - /* - * Wait for TransactionDone. Typical latency is <200us. - * Depends on SMPSWAITTIMEMIN/MAX and voltage change - */ - timeout = 0; - omap_test_timeout((vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) & - vdd->vp_data->prm_irqst_data->tranxdone_status), - VP_TRANXDONE_TIMEOUT, timeout); - if (timeout >= VP_TRANXDONE_TIMEOUT) - pr_err("%s: vdd_%s TRANXDONE timeout exceeded." - "TRANXDONE never got set after the voltage update\n", - __func__, vdd->voltdm.name); - - _post_volt_scale(vdd, target_volt, target_vsel, current_vsel); - - /* - * Disable TransactionDone interrupt , clear all status, clear - * control registers - */ - timeout = 0; - while (timeout++ < VP_TRANXDONE_TIMEOUT) { - vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status, - prm_irqst_ocp_mod_offs, prm_irqst_reg); - if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) & - vdd->vp_data->prm_irqst_data->tranxdone_status)) - break; - udelay(1); - } - - if (timeout >= VP_TRANXDONE_TIMEOUT) - pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying" - "to clear the TRANXDONE status\n", - __func__, vdd->voltdm.name); - - vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig); - /* Clear initVDD copy trigger bit */ - vpconfig &= ~vdd->vp_data->vp_common->vpconfig_initvdd; - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); - /* Clear force bit */ - vpconfig &= ~vdd->vp_data->vp_common->vpconfig_forceupdate; - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); - - return 0; -} - -static void __init omap3_vfsm_init(struct omap_vdd_info *vdd) -{ - /* - * Voltage Manager FSM parameters init - * XXX This data should be passed in from the board file - */ - vdd->write_reg(OMAP3_CLKSETUP, prm_mod_offs, OMAP3_PRM_CLKSETUP_OFFSET); - vdd->write_reg(OMAP3_VOLTOFFSET, prm_mod_offs, - OMAP3_PRM_VOLTOFFSET_OFFSET); - vdd->write_reg(OMAP3_VOLTSETUP2, prm_mod_offs, - OMAP3_PRM_VOLTSETUP2_OFFSET); -} - -static void __init omap3_vc_init(struct omap_vdd_info *vdd) -{ - static bool is_initialized; - u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; - u32 vc_val; - - if (is_initialized) - return; - - /* Set up the on, inactive, retention and off voltage */ - on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt); - onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt); - ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt); - off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt); - vc_val = ((on_vsel << vdd->vc_data->vc_common->cmd_on_shift) | - (onlp_vsel << vdd->vc_data->vc_common->cmd_onlp_shift) | - (ret_vsel << vdd->vc_data->vc_common->cmd_ret_shift) | - (off_vsel << vdd->vc_data->vc_common->cmd_off_shift)); - vdd->write_reg(vc_val, prm_mod_offs, vdd->vc_data->cmdval_reg); - - /* - * Generic VC parameters init - * XXX This data should be abstracted out - */ - vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, prm_mod_offs, - OMAP3_PRM_VC_CH_CONF_OFFSET); - vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, prm_mod_offs, - OMAP3_PRM_VC_I2C_CFG_OFFSET); - - omap3_vfsm_init(vdd); - - is_initialized = true; -} - - -/* OMAP4 specific voltage init functions */ -static void __init omap4_vc_init(struct omap_vdd_info *vdd) -{ - static bool is_initialized; - u32 vc_val; - - if (is_initialized) - return; - - /* TODO: Configure setup times and CMD_VAL values*/ - - /* - * Generic VC parameters init - * XXX This data should be abstracted out - */ - vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK | - OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK | - OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK); - vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET); - - /* XXX These are magic numbers and do not belong! */ - vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); - vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); - - is_initialized = true; -} - -static void __init omap_vc_init(struct omap_vdd_info *vdd) -{ - u32 vc_val; - - if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { - pr_err("%s: PMIC info requried to configure vc for" - "vdd_%s not populated.Hence cannot initialize vc\n", - __func__, vdd->voltdm.name); - return; - } - - if (!vdd->read_reg || !vdd->write_reg) { - pr_err("%s: No read/write API for accessing vdd_%s regs\n", - __func__, vdd->voltdm.name); - return; - } - - /* Set up the SMPS_SA(i2c slave address in VC */ - vc_val = vdd->read_reg(prm_mod_offs, - vdd->vc_data->vc_common->smps_sa_reg); - vc_val &= ~vdd->vc_data->smps_sa_mask; - vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_data->smps_sa_shift; - vdd->write_reg(vc_val, prm_mod_offs, - vdd->vc_data->vc_common->smps_sa_reg); - - /* Setup the VOLRA(pmic reg addr) in VC */ - vc_val = vdd->read_reg(prm_mod_offs, - vdd->vc_data->vc_common->smps_volra_reg); - vc_val &= ~vdd->vc_data->smps_volra_mask; - vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_data->smps_volra_shift; - vdd->write_reg(vc_val, prm_mod_offs, - vdd->vc_data->vc_common->smps_volra_reg); - - /* Configure the setup times */ - vc_val = vdd->read_reg(prm_mod_offs, vdd->vfsm->voltsetup_reg); - vc_val &= ~vdd->vfsm->voltsetup_mask; - vc_val |= vdd->pmic_info->volt_setup_time << - vdd->vfsm->voltsetup_shift; - vdd->write_reg(vc_val, prm_mod_offs, vdd->vfsm->voltsetup_reg); - - if (cpu_is_omap34xx()) - omap3_vc_init(vdd); - else if (cpu_is_omap44xx()) - omap4_vc_init(vdd); -} - -static int __init omap_vdd_data_configure(struct omap_vdd_info *vdd) -{ - int ret = -EINVAL; - - if (!vdd->pmic_info) { - pr_err("%s: PMIC info requried to configure vdd_%s not" - "populated.Hence cannot initialize vdd_%s\n", - __func__, vdd->voltdm.name, vdd->voltdm.name); - goto ovdc_out; - } - - if (IS_ERR_VALUE(_config_common_vdd_data(vdd))) - goto ovdc_out; - - if (cpu_is_omap34xx()) { - vdd->read_reg = omap3_voltage_read_reg; - vdd->write_reg = omap3_voltage_write_reg; - ret = 0; - } else if (cpu_is_omap44xx()) { - vdd->read_reg = omap4_voltage_read_reg; - vdd->write_reg = omap4_voltage_write_reg; - ret = 0; - } - -ovdc_out: - return ret; -} +static LIST_HEAD(voltdm_list); /* Public functions */ /** - * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage - * @voltdm: pointer to the VDD for which current voltage info is needed + * voltdm_get_voltage() - Gets the current non-auto-compensated voltage + * @voltdm: pointer to the voltdm for which current voltage info is needed * - * API to get the current non-auto-compensated voltage for a VDD. - * Returns 0 in case of error else returns the current voltage for the VDD. + * API to get the current non-auto-compensated voltage for a voltage domain. + * Returns 0 in case of error else returns the current voltage. */ -unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm) +unsigned long voltdm_get_voltage(struct voltagedomain *voltdm) { - struct omap_vdd_info *vdd; - if (!voltdm || IS_ERR(voltdm)) { pr_warning("%s: VDD specified does not exist!\n", __func__); return 0; } - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - - return vdd->curr_volt; + return voltdm->nominal_volt; } /** - * omap_vp_get_curr_volt() - API to get the current vp voltage. - * @voltdm: pointer to the VDD. - * - * This API returns the current voltage for the specified voltage processor - */ -unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm) -{ - struct omap_vdd_info *vdd; - u8 curr_vsel; - - if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); - return 0; - } - - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - if (!vdd->read_reg) { - pr_err("%s: No read API for reading vdd_%s regs\n", - __func__, voltdm->name); - return 0; - } - - curr_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage); - - if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) { - pr_warning("%s: PMIC function to convert vsel to voltage" - "in uV not registerd\n", __func__); - return 0; - } - - return vdd->pmic_info->vsel_to_uv(curr_vsel); -} - -/** - * omap_vp_enable() - API to enable a particular VP - * @voltdm: pointer to the VDD whose VP is to be enabled. - * - * This API enables a particular voltage processor. Needed by the smartreflex - * class drivers. - */ -void omap_vp_enable(struct voltagedomain *voltdm) -{ - struct omap_vdd_info *vdd; - u32 vpconfig; - - if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); - return; - } - - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - if (!vdd->read_reg || !vdd->write_reg) { - pr_err("%s: No read/write API for accessing vdd_%s regs\n", - __func__, voltdm->name); - return; - } - - /* If VP is already enabled, do nothing. Return */ - if (vdd->vp_enabled) - return; - - vp_latch_vsel(vdd); - - /* Enable VP */ - vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig); - vpconfig |= vdd->vp_data->vp_common->vpconfig_vpenable; - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); - vdd->vp_enabled = true; -} - -/** - * omap_vp_disable() - API to disable a particular VP - * @voltdm: pointer to the VDD whose VP is to be disabled. - * - * This API disables a particular voltage processor. Needed by the smartreflex - * class drivers. - */ -void omap_vp_disable(struct voltagedomain *voltdm) -{ - struct omap_vdd_info *vdd; - u32 vpconfig; - int timeout; - - if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); - return; - } - - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - if (!vdd->read_reg || !vdd->write_reg) { - pr_err("%s: No read/write API for accessing vdd_%s regs\n", - __func__, voltdm->name); - return; - } - - /* If VP is already disabled, do nothing. Return */ - if (!vdd->vp_enabled) { - pr_warning("%s: Trying to disable VP for vdd_%s when" - "it is already disabled\n", __func__, voltdm->name); - return; - } - - /* Disable VP */ - vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig); - vpconfig &= ~vdd->vp_data->vp_common->vpconfig_vpenable; - vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig); - - /* - * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us - */ - omap_test_timeout((vdd->read_reg(prm_mod_offs, vdd->vp_data->vstatus)), - VP_IDLE_TIMEOUT, timeout); - - if (timeout >= VP_IDLE_TIMEOUT) - pr_warning("%s: vdd_%s idle timedout\n", - __func__, voltdm->name); - - vdd->vp_enabled = false; - - return; -} - -/** - * omap_voltage_scale_vdd() - API to scale voltage of a particular - * voltage domain. - * @voltdm: pointer to the VDD which is to be scaled. - * @target_volt: The target voltage of the voltage domain + * voltdm_scale() - API to scale voltage of a particular voltage domain. + * @voltdm: pointer to the voltage domain which is to be scaled. + * @target_volt: The target voltage of the voltage domain * * This API should be called by the kernel to do the voltage scaling - * for a particular voltage domain during dvfs or any other situation. + * for a particular voltage domain during DVFS. */ -int omap_voltage_scale_vdd(struct voltagedomain *voltdm, - unsigned long target_volt) +int voltdm_scale(struct voltagedomain *voltdm, + unsigned long target_volt) { - struct omap_vdd_info *vdd; + int ret; if (!voltdm || IS_ERR(voltdm)) { pr_warning("%s: VDD specified does not exist!\n", __func__); return -EINVAL; } - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - - if (!vdd->volt_scale) { + if (!voltdm->scale) { pr_err("%s: No voltage scale API registered for vdd_%s\n", __func__, voltdm->name); return -ENODATA; } - return vdd->volt_scale(vdd, target_volt); + ret = voltdm->scale(voltdm, target_volt); + if (!ret) + voltdm->nominal_volt = target_volt; + + return ret; } /** - * omap_voltage_reset() - Resets the voltage of a particular voltage domain - * to that of the current OPP. - * @voltdm: pointer to the VDD whose voltage is to be reset. + * voltdm_reset() - Resets the voltage of a particular voltage domain + * to that of the current OPP. + * @voltdm: pointer to the voltage domain whose voltage is to be reset. * * This API finds out the correct voltage the voltage domain is supposed * to be at and resets the voltage to that level. Should be used especially * while disabling any voltage compensation modules. */ -void omap_voltage_reset(struct voltagedomain *voltdm) +void voltdm_reset(struct voltagedomain *voltdm) { - unsigned long target_uvdc; + unsigned long target_volt; if (!voltdm || IS_ERR(voltdm)) { pr_warning("%s: VDD specified does not exist!\n", __func__); return; } - target_uvdc = omap_voltage_get_nom_volt(voltdm); - if (!target_uvdc) { + target_volt = voltdm_get_voltage(voltdm); + if (!target_volt) { pr_err("%s: unable to find current voltage for vdd_%s\n", __func__, voltdm->name); return; } - omap_voltage_scale_vdd(voltdm, target_uvdc); + voltdm_scale(voltdm, target_volt); } /** @@ -884,18 +133,14 @@ void omap_voltage_reset(struct voltagedomain *voltdm) * */ void omap_voltage_get_volttable(struct voltagedomain *voltdm, - struct omap_volt_data **volt_data) + struct omap_volt_data **volt_data) { - struct omap_vdd_info *vdd; - if (!voltdm || IS_ERR(voltdm)) { pr_warning("%s: VDD specified does not exist!\n", __func__); return; } - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - - *volt_data = vdd->volt_data; + *volt_data = voltdm->volt_data; } /** @@ -914,9 +159,8 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm, * domain or if there is no matching entry. */ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, - unsigned long volt) + unsigned long volt) { - struct omap_vdd_info *vdd; int i; if (!voltdm || IS_ERR(voltdm)) { @@ -924,17 +168,15 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, return ERR_PTR(-EINVAL); } - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - - if (!vdd->volt_data) { + if (!voltdm->volt_data) { pr_warning("%s: voltage table does not exist for vdd_%s\n", __func__, voltdm->name); return ERR_PTR(-ENODATA); } - for (i = 0; vdd->volt_data[i].volt_nominal != 0; i++) { - if (vdd->volt_data[i].volt_nominal == volt) - return &vdd->volt_data[i]; + for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) { + if (voltdm->volt_data[i].volt_nominal == volt) + return &voltdm->volt_data[i]; } pr_notice("%s: Unable to match the current voltage with the voltage" @@ -947,54 +189,25 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, * omap_voltage_register_pmic() - API to register PMIC specific data * @voltdm: pointer to the VDD for which the PMIC specific data is * to be registered - * @pmic_info: the structure containing pmic info + * @pmic: the structure containing pmic info * * This API is to be called by the SOC/PMIC file to specify the - * pmic specific info as present in omap_volt_pmic_info structure. + * pmic specific info as present in omap_voltdm_pmic structure. */ int omap_voltage_register_pmic(struct voltagedomain *voltdm, - struct omap_volt_pmic_info *pmic_info) + struct omap_voltdm_pmic *pmic) { - struct omap_vdd_info *vdd; - if (!voltdm || IS_ERR(voltdm)) { pr_warning("%s: VDD specified does not exist!\n", __func__); return -EINVAL; } - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - - vdd->pmic_info = pmic_info; + voltdm->pmic = pmic; return 0; } /** - * omap_voltage_get_dbgdir() - API to get pointer to the debugfs directory - * corresponding to a voltage domain. - * - * @voltdm: pointer to the VDD whose debug directory is required. - * - * This API returns pointer to the debugfs directory corresponding - * to the voltage domain. Should be used by drivers requiring to - * add any debug entry for a particular voltage domain. Returns NULL - * in case of error. - */ -struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm) -{ - struct omap_vdd_info *vdd; - - if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); - return NULL; - } - - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - - return vdd->debug_dir; -} - -/** * omap_change_voltscale_method() - API to change the voltage scaling method. * @voltdm: pointer to the VDD whose voltage scaling method * has to be changed. @@ -1005,23 +218,19 @@ struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm) * defined in voltage.h */ void omap_change_voltscale_method(struct voltagedomain *voltdm, - int voltscale_method) + int voltscale_method) { - struct omap_vdd_info *vdd; - if (!voltdm || IS_ERR(voltdm)) { pr_warning("%s: VDD specified does not exist!\n", __func__); return; } - vdd = container_of(voltdm, struct omap_vdd_info, voltdm); - switch (voltscale_method) { case VOLTSCALE_VPFORCEUPDATE: - vdd->volt_scale = vp_forceupdate_scale_voltage; + voltdm->scale = omap_vp_forceupdate_scale; return; case VOLTSCALE_VCBYPASS: - vdd->volt_scale = vc_bypass_scale_voltage; + voltdm->scale = omap_vc_bypass_scale; return; default: pr_warning("%s: Trying to change the method of voltage scaling" @@ -1030,77 +239,192 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm, } /** - * omap_voltage_domain_lookup() - API to get the voltage domain pointer - * @name: Name of the voltage domain + * omap_voltage_late_init() - Init the various voltage parameters * - * This API looks up in the global vdd_info struct for the - * existence of voltage domain <name>. If it exists, the API returns - * a pointer to the voltage domain structure corresponding to the - * VDD<name>. Else retuns error pointer. + * This API is to be called in the later stages of the + * system boot to init the voltage controller and + * voltage processors. */ -struct voltagedomain *omap_voltage_domain_lookup(char *name) +int __init omap_voltage_late_init(void) { - int i; + struct voltagedomain *voltdm; - if (!vdd_info) { - pr_err("%s: Voltage driver init not yet happened.Faulting!\n", + if (list_empty(&voltdm_list)) { + pr_err("%s: Voltage driver support not added\n", __func__); - return ERR_PTR(-EINVAL); + return -EINVAL; } - if (!name) { - pr_err("%s: No name to get the votage domain!\n", __func__); - return ERR_PTR(-EINVAL); + list_for_each_entry(voltdm, &voltdm_list, node) { + struct clk *sys_ck; + + if (!voltdm->scalable) + continue; + + sys_ck = clk_get(NULL, voltdm->sys_clk.name); + if (IS_ERR(sys_ck)) { + pr_warning("%s: Could not get sys clk.\n", __func__); + return -EINVAL; + } + voltdm->sys_clk.rate = clk_get_rate(sys_ck); + WARN_ON(!voltdm->sys_clk.rate); + clk_put(sys_ck); + + if (voltdm->vc) { + voltdm->scale = omap_vc_bypass_scale; + omap_vc_init_channel(voltdm); + } + + if (voltdm->vp) { + voltdm->scale = omap_vp_forceupdate_scale; + omap_vp_init(voltdm); + } } - for (i = 0; i < nr_scalable_vdd; i++) { - if (!(strcmp(name, vdd_info[i]->voltdm.name))) - return &vdd_info[i]->voltdm; + return 0; +} + +static struct voltagedomain *_voltdm_lookup(const char *name) +{ + struct voltagedomain *voltdm, *temp_voltdm; + + voltdm = NULL; + + list_for_each_entry(temp_voltdm, &voltdm_list, node) { + if (!strcmp(name, temp_voltdm->name)) { + voltdm = temp_voltdm; + break; + } } - return ERR_PTR(-EINVAL); + return voltdm; } /** - * omap_voltage_late_init() - Init the various voltage parameters + * voltdm_add_pwrdm - add a powerdomain to a voltagedomain + * @voltdm: struct voltagedomain * to add the powerdomain to + * @pwrdm: struct powerdomain * to associate with a voltagedomain * - * This API is to be called in the later stages of the - * system boot to init the voltage controller and - * voltage processors. + * Associate the powerdomain @pwrdm with a voltagedomain @voltdm. This + * enables the use of voltdm_for_each_pwrdm(). Returns -EINVAL if + * presented with invalid pointers; -ENOMEM if memory could not be allocated; + * or 0 upon success. */ -int __init omap_voltage_late_init(void) +int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm) { - int i; + if (!voltdm || !pwrdm) + return -EINVAL; - if (!vdd_info) { - pr_err("%s: Voltage driver support not added\n", - __func__); + pr_debug("voltagedomain: associating powerdomain %s with voltagedomain " + "%s\n", pwrdm->name, voltdm->name); + + list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list); + + return 0; +} + +/** + * voltdm_for_each_pwrdm - call function for each pwrdm in a voltdm + * @voltdm: struct voltagedomain * to iterate over + * @fn: callback function * + * + * Call the supplied function @fn for each powerdomain in the + * voltagedomain @voltdm. Returns -EINVAL if presented with invalid + * pointers; or passes along the last return value of the callback + * function, which should be 0 for success or anything else to + * indicate failure. + */ +int voltdm_for_each_pwrdm(struct voltagedomain *voltdm, + int (*fn)(struct voltagedomain *voltdm, + struct powerdomain *pwrdm)) +{ + struct powerdomain *pwrdm; + int ret = 0; + + if (!fn) return -EINVAL; - } - voltage_dir = debugfs_create_dir("voltage", NULL); - if (IS_ERR(voltage_dir)) - pr_err("%s: Unable to create voltage debugfs main dir\n", - __func__); - for (i = 0; i < nr_scalable_vdd; i++) { - if (omap_vdd_data_configure(vdd_info[i])) - continue; - omap_vc_init(vdd_info[i]); - vp_init(vdd_info[i]); - vdd_debugfs_init(vdd_info[i]); + list_for_each_entry(pwrdm, &voltdm->pwrdm_list, voltdm_node) + ret = (*fn)(voltdm, pwrdm); + + return ret; +} + +/** + * voltdm_for_each - call function on each registered voltagedomain + * @fn: callback function * + * + * Call the supplied function @fn for each registered voltagedomain. + * The callback function @fn can return anything but 0 to bail out + * early from the iterator. Returns the last return value of the + * callback function, which should be 0 for success or anything else + * to indicate failure; or -EINVAL if the function pointer is null. + */ +int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user), + void *user) +{ + struct voltagedomain *temp_voltdm; + int ret = 0; + + if (!fn) + return -EINVAL; + + list_for_each_entry(temp_voltdm, &voltdm_list, node) { + ret = (*fn)(temp_voltdm, user); + if (ret) + break; } - return 0; + return ret; } -/* XXX document */ -int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_ocp_mod, - struct omap_vdd_info *omap_vdd_array[], - u8 omap_vdd_count) +static int _voltdm_register(struct voltagedomain *voltdm) { - prm_mod_offs = prm_mod; - prm_irqst_ocp_mod_offs = prm_irqst_ocp_mod; - vdd_info = omap_vdd_array; - nr_scalable_vdd = omap_vdd_count; + if (!voltdm || !voltdm->name) + return -EINVAL; + + INIT_LIST_HEAD(&voltdm->pwrdm_list); + list_add(&voltdm->node, &voltdm_list); + + pr_debug("voltagedomain: registered %s\n", voltdm->name); + return 0; } + +/** + * voltdm_lookup - look up a voltagedomain by name, return a pointer + * @name: name of voltagedomain + * + * Find a registered voltagedomain by its name @name. Returns a pointer + * to the struct voltagedomain if found, or NULL otherwise. + */ +struct voltagedomain *voltdm_lookup(const char *name) +{ + struct voltagedomain *voltdm ; + + if (!name) + return NULL; + + voltdm = _voltdm_lookup(name); + + return voltdm; +} + +/** + * voltdm_init - set up the voltagedomain layer + * @voltdm_list: array of struct voltagedomain pointers to register + * + * Loop through the array of voltagedomains @voltdm_list, registering all + * that are available on the current CPU. If voltdm_list is supplied + * and not null, all of the referenced voltagedomains will be + * registered. No return value. + */ +void voltdm_init(struct voltagedomain **voltdms) +{ + struct voltagedomain **v; + + if (voltdms) { + for (v = voltdms; *v; v++) + _voltdm_register(*v); + } +} diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index e9f5408..16a1b09 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -19,6 +19,8 @@ #include "vc.h" #include "vp.h" +struct powerdomain; + /* XXX document */ #define VOLTSCALE_VPFORCEUPDATE 1 #define VOLTSCALE_VCBYPASS 2 @@ -32,29 +34,60 @@ #define OMAP3_VOLTSETUP2 0xff /** - * struct omap_vfsm_instance_data - per-voltage manager FSM register/bitfield + * struct omap_vfsm_instance - per-voltage manager FSM register/bitfield * data * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base - * @voltsetup_shift: SETUP_TIME* field shift in the PRM_VOLTSETUP* register * * XXX What about VOLTOFFSET/VOLTCTRL? - * XXX It is not necessary to have both a _mask and a _shift for the same - * bitfield - remove one! */ -struct omap_vfsm_instance_data { +struct omap_vfsm_instance { u32 voltsetup_mask; u8 voltsetup_reg; - u8 voltsetup_shift; }; /** * struct voltagedomain - omap voltage domain global structure. - * @name: Name of the voltage domain which can be used as a unique - * identifier. + * @name: Name of the voltage domain which can be used as a unique identifier. + * @scalable: Whether or not this voltage domain is scalable + * @node: list_head linking all voltage domains + * @pwrdm_list: list_head linking all powerdomains in this voltagedomain + * @vc: pointer to VC channel associated with this voltagedomain + * @vp: pointer to VP associated with this voltagedomain + * @read: read a VC/VP register + * @write: write a VC/VP register + * @read: read-modify-write a VC/VP register + * @sys_clk: system clock name/frequency, used for various timing calculations + * @scale: function used to scale the voltage of the voltagedomain + * @nominal_volt: current nominal voltage for this voltage domain + * @volt_data: voltage table having the distinct voltages supported + * by the domain and other associated per voltage data. */ struct voltagedomain { char *name; + bool scalable; + struct list_head node; + struct list_head pwrdm_list; + struct omap_vc_channel *vc; + const struct omap_vfsm_instance *vfsm; + struct omap_vp_instance *vp; + struct omap_voltdm_pmic *pmic; + + /* VC/VP register access functions: SoC specific */ + u32 (*read) (u8 offset); + void (*write) (u32 val, u8 offset); + u32 (*rmw)(u32 mask, u32 bits, u8 offset); + + union { + const char *name; + u32 rate; + } sys_clk; + + int (*scale) (struct voltagedomain *voltdm, + unsigned long target_volt); + + u32 nominal_volt; + struct omap_volt_data *volt_data; }; /** @@ -77,13 +110,18 @@ struct omap_volt_data { }; /** - * struct omap_volt_pmic_info - PMIC specific data required by voltage driver. + * struct omap_voltdm_pmic - PMIC specific data required by voltage driver. * @slew_rate: PMIC slew rate (in uv/us) * @step_size: PMIC voltage step size (in uv) + * @i2c_slave_addr: I2C slave address of PMIC + * @volt_reg_addr: voltage configuration register address + * @cmd_reg_addr: command (on, on-LP, ret, off) configuration register address + * @i2c_high_speed: whether VC uses I2C high-speed mode to PMIC + * @i2c_mcode: master code value for I2C high-speed preamble transmission * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV. * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value. */ -struct omap_volt_pmic_info { +struct omap_voltdm_pmic { int slew_rate; int step_size; u32 on_volt; @@ -91,94 +129,44 @@ struct omap_volt_pmic_info { u32 ret_volt; u32 off_volt; u16 volt_setup_time; + u16 i2c_slave_addr; + u16 volt_reg_addr; + u16 cmd_reg_addr; u8 vp_erroroffset; u8 vp_vstepmin; u8 vp_vstepmax; u8 vp_vddmin; u8 vp_vddmax; u8 vp_timeout_us; - u8 i2c_slave_addr; - u8 pmic_reg; + bool i2c_high_speed; + u8 i2c_mcode; unsigned long (*vsel_to_uv) (const u8 vsel); u8 (*uv_to_vsel) (unsigned long uV); }; -/** - * omap_vdd_info - Per Voltage Domain info - * - * @volt_data : voltage table having the distinct voltages supported - * by the domain and other associated per voltage data. - * @pmic_info : pmic specific parameters which should be populted by - * the pmic drivers. - * @vp_data : the register values, shifts, masks for various - * vp registers - * @vp_rt_data : VP data derived at runtime, not predefined - * @vc_data : structure containing various various vc registers, - * shifts, masks etc. - * @vfsm : voltage manager FSM data - * @voltdm : pointer to the voltage domain structure - * @debug_dir : debug directory for this voltage domain. - * @curr_volt : current voltage for this vdd. - * @vp_enabled : flag to keep track of whether vp is enabled or not - * @volt_scale : API to scale the voltage of the vdd. - */ -struct omap_vdd_info { - struct omap_volt_data *volt_data; - struct omap_volt_pmic_info *pmic_info; - struct omap_vp_instance_data *vp_data; - struct omap_vp_runtime_data vp_rt_data; - struct omap_vc_instance_data *vc_data; - const struct omap_vfsm_instance_data *vfsm; - struct voltagedomain voltdm; - struct dentry *debug_dir; - u32 curr_volt; - bool vp_enabled; - u32 (*read_reg) (u16 mod, u8 offset); - void (*write_reg) (u32 val, u16 mod, u8 offset); - int (*volt_scale) (struct omap_vdd_info *vdd, - unsigned long target_volt); -}; - -unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm); -void omap_vp_enable(struct voltagedomain *voltdm); -void omap_vp_disable(struct voltagedomain *voltdm); -int omap_voltage_scale_vdd(struct voltagedomain *voltdm, - unsigned long target_volt); -void omap_voltage_reset(struct voltagedomain *voltdm); void omap_voltage_get_volttable(struct voltagedomain *voltdm, struct omap_volt_data **volt_data); struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, unsigned long volt); -unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm); -struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm); -int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_mod, - struct omap_vdd_info *omap_vdd_array[], - u8 omap_vdd_count); -#ifdef CONFIG_PM int omap_voltage_register_pmic(struct voltagedomain *voltdm, - struct omap_volt_pmic_info *pmic_info); + struct omap_voltdm_pmic *pmic); void omap_change_voltscale_method(struct voltagedomain *voltdm, int voltscale_method); -/* API to get the voltagedomain pointer */ -struct voltagedomain *omap_voltage_domain_lookup(char *name); - int omap_voltage_late_init(void); -#else -static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm, - struct omap_volt_pmic_info *pmic_info) -{ - return -EINVAL; -} -static inline void omap_change_voltscale_method(struct voltagedomain *voltdm, - int voltscale_method) {} -static inline int omap_voltage_late_init(void) -{ - return -EINVAL; -} -static inline struct voltagedomain *omap_voltage_domain_lookup(char *name) -{ - return ERR_PTR(-EINVAL); -} -#endif +extern void omap2xxx_voltagedomains_init(void); +extern void omap3xxx_voltagedomains_init(void); +extern void omap44xx_voltagedomains_init(void); + +struct voltagedomain *voltdm_lookup(const char *name); +void voltdm_init(struct voltagedomain **voltdm_list); +int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm); +int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user), + void *user); +int voltdm_for_each_pwrdm(struct voltagedomain *voltdm, + int (*fn)(struct voltagedomain *voltdm, + struct powerdomain *pwrdm)); +int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt); +void voltdm_reset(struct voltagedomain *voltdm); +unsigned long voltdm_get_voltage(struct voltagedomain *voltdm); #endif diff --git a/arch/arm/mach-omap2/voltagedomains2xxx_data.c b/arch/arm/mach-omap2/voltagedomains2xxx_data.c new file mode 100644 index 0000000..7a41349 --- /dev/null +++ b/arch/arm/mach-omap2/voltagedomains2xxx_data.c @@ -0,0 +1,32 @@ +/* + * OMAP3 voltage domain data + * + * Copyright (C) 2011 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/init.h> + +#include "voltage.h" + +static struct voltagedomain omap2_voltdm_core = { + .name = "core", +}; + +static struct voltagedomain omap2_voltdm_wkup = { + .name = "wakeup", +}; + +static struct voltagedomain *voltagedomains_omap2[] __initdata = { + &omap2_voltdm_core, + &omap2_voltdm_wkup, + NULL, +}; + +void __init omap2xxx_voltagedomains_init(void) +{ + voltdm_init(voltagedomains_omap2); +} diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index def230f..071101d 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -31,65 +31,70 @@ * VDD data */ -static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = { +static const struct omap_vfsm_instance omap3_vdd1_vfsm = { .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET, - .voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT, .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK, }; -static struct omap_vdd_info omap3_vdd1_info = { - .vp_data = &omap3_vp1_data, - .vc_data = &omap3_vc1_data, - .vfsm = &omap3_vdd1_vfsm_data, - .voltdm = { - .name = "mpu", - }, -}; - -static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = { +static const struct omap_vfsm_instance omap3_vdd2_vfsm = { .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET, - .voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT, .voltsetup_mask = OMAP3430_SETUP_TIME2_MASK, }; -static struct omap_vdd_info omap3_vdd2_info = { - .vp_data = &omap3_vp2_data, - .vc_data = &omap3_vc2_data, - .vfsm = &omap3_vdd2_vfsm_data, - .voltdm = { - .name = "core", - }, +static struct voltagedomain omap3_voltdm_mpu = { + .name = "mpu_iva", + .scalable = true, + .read = omap3_prm_vcvp_read, + .write = omap3_prm_vcvp_write, + .rmw = omap3_prm_vcvp_rmw, + .vc = &omap3_vc_mpu, + .vfsm = &omap3_vdd1_vfsm, + .vp = &omap3_vp_mpu, }; -/* OMAP3 VDD structures */ -static struct omap_vdd_info *omap3_vdd_info[] = { - &omap3_vdd1_info, - &omap3_vdd2_info, +static struct voltagedomain omap3_voltdm_core = { + .name = "core", + .scalable = true, + .read = omap3_prm_vcvp_read, + .write = omap3_prm_vcvp_write, + .rmw = omap3_prm_vcvp_rmw, + .vc = &omap3_vc_core, + .vfsm = &omap3_vdd2_vfsm, + .vp = &omap3_vp_core, }; -/* OMAP3 specific voltage init functions */ -static int __init omap3xxx_voltage_early_init(void) -{ - s16 prm_mod = OMAP3430_GR_MOD; - s16 prm_irqst_ocp_mod = OCP_MOD; +static struct voltagedomain omap3_voltdm_wkup = { + .name = "wakeup", +}; - if (!cpu_is_omap34xx()) - return 0; +static struct voltagedomain *voltagedomains_omap3[] __initdata = { + &omap3_voltdm_mpu, + &omap3_voltdm_core, + &omap3_voltdm_wkup, + NULL, +}; + +static const char *sys_clk_name __initdata = "sys_ck"; + +void __init omap3xxx_voltagedomains_init(void) +{ + struct voltagedomain *voltdm; + int i; /* * XXX Will depend on the process, validation, and binning * for the currently-running IC */ if (cpu_is_omap3630()) { - omap3_vdd1_info.volt_data = omap36xx_vddmpu_volt_data; - omap3_vdd2_info.volt_data = omap36xx_vddcore_volt_data; + omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data; + omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data; } else { - omap3_vdd1_info.volt_data = omap34xx_vddmpu_volt_data; - omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data; + omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data; + omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; } - return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod, - omap3_vdd_info, - ARRAY_SIZE(omap3_vdd_info)); + for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++) + voltdm->sys_clk.name = sys_clk_name; + + voltdm_init(voltagedomains_omap3); }; -core_initcall(omap3xxx_voltage_early_init); diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c index cb64996..c4584e9 100644 --- a/arch/arm/mach-omap2/voltagedomains44xx_data.c +++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c @@ -32,71 +32,80 @@ #include "vc.h" #include "vp.h" -static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = { +static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = { .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET, }; -static struct omap_vdd_info omap4_vdd_mpu_info = { - .vp_data = &omap4_vp_mpu_data, - .vc_data = &omap4_vc_mpu_data, - .vfsm = &omap4_vdd_mpu_vfsm_data, - .voltdm = { - .name = "mpu", - }, +static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = { + .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET, }; -static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = { - .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET, +static const struct omap_vfsm_instance omap4_vdd_core_vfsm = { + .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET, }; -static struct omap_vdd_info omap4_vdd_iva_info = { - .vp_data = &omap4_vp_iva_data, - .vc_data = &omap4_vc_iva_data, - .vfsm = &omap4_vdd_iva_vfsm_data, - .voltdm = { - .name = "iva", - }, +static struct voltagedomain omap4_voltdm_mpu = { + .name = "mpu", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_mpu, + .vfsm = &omap4_vdd_mpu_vfsm, + .vp = &omap4_vp_mpu, }; -static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = { - .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET, +static struct voltagedomain omap4_voltdm_iva = { + .name = "iva", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_iva, + .vfsm = &omap4_vdd_iva_vfsm, + .vp = &omap4_vp_iva, }; -static struct omap_vdd_info omap4_vdd_core_info = { - .vp_data = &omap4_vp_core_data, - .vc_data = &omap4_vc_core_data, - .vfsm = &omap4_vdd_core_vfsm_data, - .voltdm = { - .name = "core", - }, +static struct voltagedomain omap4_voltdm_core = { + .name = "core", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_core, + .vfsm = &omap4_vdd_core_vfsm, + .vp = &omap4_vp_core, }; -/* OMAP4 VDD structures */ -static struct omap_vdd_info *omap4_vdd_info[] = { - &omap4_vdd_mpu_info, - &omap4_vdd_iva_info, - &omap4_vdd_core_info, +static struct voltagedomain omap4_voltdm_wkup = { + .name = "wakeup", }; -/* OMAP4 specific voltage init functions */ -static int __init omap44xx_voltage_early_init(void) -{ - s16 prm_mod = OMAP4430_PRM_DEVICE_INST; - s16 prm_irqst_ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST; +static struct voltagedomain *voltagedomains_omap4[] __initdata = { + &omap4_voltdm_mpu, + &omap4_voltdm_iva, + &omap4_voltdm_core, + &omap4_voltdm_wkup, + NULL, +}; + +static const char *sys_clk_name __initdata = "sys_clkin_ck"; - if (!cpu_is_omap44xx()) - return 0; +void __init omap44xx_voltagedomains_init(void) +{ + struct voltagedomain *voltdm; + int i; /* * XXX Will depend on the process, validation, and binning * for the currently-running IC */ - omap4_vdd_mpu_info.volt_data = omap44xx_vdd_mpu_volt_data; - omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data; - omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data; + omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; + omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; + omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; + + for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) + voltdm->sys_clk.name = sys_clk_name; - return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod, - omap4_vdd_info, - ARRAY_SIZE(omap4_vdd_info)); + voltdm_init(voltagedomains_omap4); }; -core_initcall(omap44xx_voltage_early_init); diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c new file mode 100644 index 0000000..66bd700 --- /dev/null +++ b/arch/arm/mach-omap2/vp.c @@ -0,0 +1,278 @@ +#include <linux/kernel.h> +#include <linux/init.h> + +#include <plat/common.h> + +#include "voltage.h" +#include "vp.h" +#include "prm-regbits-34xx.h" +#include "prm-regbits-44xx.h" +#include "prm44xx.h" + +static u32 _vp_set_init_voltage(struct voltagedomain *voltdm, u32 volt) +{ + struct omap_vp_instance *vp = voltdm->vp; + u32 vpconfig; + char vsel; + + vsel = voltdm->pmic->uv_to_vsel(volt); + + vpconfig = voltdm->read(vp->vpconfig); + vpconfig &= ~(vp->common->vpconfig_initvoltage_mask | + vp->common->vpconfig_forceupdate | + vp->common->vpconfig_initvdd); + vpconfig |= vsel << __ffs(vp->common->vpconfig_initvoltage_mask); + voltdm->write(vpconfig, vp->vpconfig); + + /* Trigger initVDD value copy to voltage processor */ + voltdm->write((vpconfig | vp->common->vpconfig_initvdd), + vp->vpconfig); + + /* Clear initVDD copy trigger bit */ + voltdm->write(vpconfig, vp->vpconfig); + + return vpconfig; +} + +/* Generic voltage init functions */ +void __init omap_vp_init(struct voltagedomain *voltdm) +{ + struct omap_vp_instance *vp = voltdm->vp; + u32 val, sys_clk_rate, timeout, waittime; + u32 vddmin, vddmax, vstepmin, vstepmax; + + if (!voltdm->read || !voltdm->write) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, voltdm->name); + return; + } + + vp->enabled = false; + + /* Divide to avoid overflow */ + sys_clk_rate = voltdm->sys_clk.rate / 1000; + + timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000; + vddmin = voltdm->pmic->vp_vddmin; + vddmax = voltdm->pmic->vp_vddmax; + + waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) * + sys_clk_rate) / 1000; + vstepmin = voltdm->pmic->vp_vstepmin; + vstepmax = voltdm->pmic->vp_vstepmax; + + /* + * VP_CONFIG: error gain is not set here, it will be updated + * on each scale, based on OPP. + */ + val = (voltdm->pmic->vp_erroroffset << + __ffs(voltdm->vp->common->vpconfig_erroroffset_mask)) | + vp->common->vpconfig_timeouten; + voltdm->write(val, vp->vpconfig); + + /* VSTEPMIN */ + val = (waittime << vp->common->vstepmin_smpswaittimemin_shift) | + (vstepmin << vp->common->vstepmin_stepmin_shift); + voltdm->write(val, vp->vstepmin); + + /* VSTEPMAX */ + val = (vstepmax << vp->common->vstepmax_stepmax_shift) | + (waittime << vp->common->vstepmax_smpswaittimemax_shift); + voltdm->write(val, vp->vstepmax); + + /* VLIMITTO */ + val = (vddmax << vp->common->vlimitto_vddmax_shift) | + (vddmin << vp->common->vlimitto_vddmin_shift) | + (timeout << vp->common->vlimitto_timeout_shift); + voltdm->write(val, vp->vlimitto); +} + +int omap_vp_update_errorgain(struct voltagedomain *voltdm, + unsigned long target_volt) +{ + struct omap_volt_data *volt_data; + + if (!voltdm->vp) + return -EINVAL; + + /* Get volt_data corresponding to target_volt */ + volt_data = omap_voltage_get_voltdata(voltdm, target_volt); + if (IS_ERR(volt_data)) + return -EINVAL; + + /* Setting vp errorgain based on the voltage */ + voltdm->rmw(voltdm->vp->common->vpconfig_errorgain_mask, + volt_data->vp_errgain << + __ffs(voltdm->vp->common->vpconfig_errorgain_mask), + voltdm->vp->vpconfig); + + return 0; +} + +/* VP force update method of voltage scaling */ +int omap_vp_forceupdate_scale(struct voltagedomain *voltdm, + unsigned long target_volt) +{ + struct omap_vp_instance *vp = voltdm->vp; + u32 vpconfig; + u8 target_vsel, current_vsel; + int ret, timeout = 0; + + ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel); + if (ret) + return ret; + + /* + * Clear all pending TransactionDone interrupt/status. Typical latency + * is <3us + */ + while (timeout++ < VP_TRANXDONE_TIMEOUT) { + vp->common->ops->clear_txdone(vp->id); + if (!vp->common->ops->check_txdone(vp->id)) + break; + udelay(1); + } + if (timeout >= VP_TRANXDONE_TIMEOUT) { + pr_warning("%s: vdd_%s TRANXDONE timeout exceeded." + "Voltage change aborted", __func__, voltdm->name); + return -ETIMEDOUT; + } + + vpconfig = _vp_set_init_voltage(voltdm, target_volt); + + /* Force update of voltage */ + voltdm->write(vpconfig | vp->common->vpconfig_forceupdate, + voltdm->vp->vpconfig); + + /* + * Wait for TransactionDone. Typical latency is <200us. + * Depends on SMPSWAITTIMEMIN/MAX and voltage change + */ + timeout = 0; + omap_test_timeout(vp->common->ops->check_txdone(vp->id), + VP_TRANXDONE_TIMEOUT, timeout); + if (timeout >= VP_TRANXDONE_TIMEOUT) + pr_err("%s: vdd_%s TRANXDONE timeout exceeded." + "TRANXDONE never got set after the voltage update\n", + __func__, voltdm->name); + + omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); + + /* + * Disable TransactionDone interrupt , clear all status, clear + * control registers + */ + timeout = 0; + while (timeout++ < VP_TRANXDONE_TIMEOUT) { + vp->common->ops->clear_txdone(vp->id); + if (!vp->common->ops->check_txdone(vp->id)) + break; + udelay(1); + } + + if (timeout >= VP_TRANXDONE_TIMEOUT) + pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying" + "to clear the TRANXDONE status\n", + __func__, voltdm->name); + + /* Clear force bit */ + voltdm->write(vpconfig, vp->vpconfig); + + return 0; +} + +/** + * omap_vp_enable() - API to enable a particular VP + * @voltdm: pointer to the VDD whose VP is to be enabled. + * + * This API enables a particular voltage processor. Needed by the smartreflex + * class drivers. + */ +void omap_vp_enable(struct voltagedomain *voltdm) +{ + struct omap_vp_instance *vp; + u32 vpconfig, volt; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return; + } + + vp = voltdm->vp; + if (!voltdm->read || !voltdm->write) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, voltdm->name); + return; + } + + /* If VP is already enabled, do nothing. Return */ + if (vp->enabled) + return; + + volt = voltdm_get_voltage(voltdm); + if (!volt) { + pr_warning("%s: unable to find current voltage for %s\n", + __func__, voltdm->name); + return; + } + + vpconfig = _vp_set_init_voltage(voltdm, volt); + + /* Enable VP */ + vpconfig |= vp->common->vpconfig_vpenable; + voltdm->write(vpconfig, vp->vpconfig); + + vp->enabled = true; +} + +/** + * omap_vp_disable() - API to disable a particular VP + * @voltdm: pointer to the VDD whose VP is to be disabled. + * + * This API disables a particular voltage processor. Needed by the smartreflex + * class drivers. + */ +void omap_vp_disable(struct voltagedomain *voltdm) +{ + struct omap_vp_instance *vp; + u32 vpconfig; + int timeout; + + if (!voltdm || IS_ERR(voltdm)) { + pr_warning("%s: VDD specified does not exist!\n", __func__); + return; + } + + vp = voltdm->vp; + if (!voltdm->read || !voltdm->write) { + pr_err("%s: No read/write API for accessing vdd_%s regs\n", + __func__, voltdm->name); + return; + } + + /* If VP is already disabled, do nothing. Return */ + if (!vp->enabled) { + pr_warning("%s: Trying to disable VP for vdd_%s when" + "it is already disabled\n", __func__, voltdm->name); + return; + } + + /* Disable VP */ + vpconfig = voltdm->read(vp->vpconfig); + vpconfig &= ~vp->common->vpconfig_vpenable; + voltdm->write(vpconfig, vp->vpconfig); + + /* + * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us + */ + omap_test_timeout((voltdm->read(vp->vstatus)), + VP_IDLE_TIMEOUT, timeout); + + if (timeout >= VP_IDLE_TIMEOUT) + pr_warning("%s: vdd_%s idle timedout\n", + __func__, voltdm->name); + + vp->enabled = false; + + return; +} diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h index 7ce134f..7c155d2 100644 --- a/arch/arm/mach-omap2/vp.h +++ b/arch/arm/mach-omap2/vp.h @@ -19,44 +19,60 @@ #include <linux/kernel.h> +struct voltagedomain; + +/* + * Voltage Processor (VP) identifiers + */ +#define OMAP3_VP_VDD_MPU_ID 0 +#define OMAP3_VP_VDD_CORE_ID 1 +#define OMAP4_VP_VDD_CORE_ID 0 +#define OMAP4_VP_VDD_IVA_ID 1 +#define OMAP4_VP_VDD_MPU_ID 2 + /* XXX document */ #define VP_IDLE_TIMEOUT 200 #define VP_TRANXDONE_TIMEOUT 300 +/** + * struct omap_vp_ops - per-VP operations + * @check_txdone: check for VP transaction done + * @clear_txdone: clear VP transaction done status + */ +struct omap_vp_ops { + u32 (*check_txdone)(u8 vp_id); + void (*clear_txdone)(u8 vp_id); +}; /** - * struct omap_vp_common_data - register data common to all VDDs + * struct omap_vp_common - register data common to all VDDs + * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg - * @vpconfig_timeouten_mask: TIMEOUT bitmask in the PRM_VP*_CONFIG reg + * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg - * @vpconfig_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg - * @vpconfig_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg - * @vpconfig_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg - * @vpconfig_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg - * @vpconfig_vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg - * @vpconfig_vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg - * @vpconfig_vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg - * - * XXX It it not necessary to have both a mask and a shift for the same - * bitfield - remove one - * XXX Many of these fields are wrongly named -- e.g., vpconfig_smps* -- fix! + * @vstepmin_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg + * @vstepmin_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg + * @vstepmax_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg + * @vstepmax_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg + * @vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg + * @vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg + * @vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg + * @vpvoltage_mask: VPVOLTAGE field mask in PRM_VP*_VOLTAGE reg */ -struct omap_vp_common_data { +struct omap_vp_common { + u32 vpconfig_erroroffset_mask; u32 vpconfig_errorgain_mask; u32 vpconfig_initvoltage_mask; - u32 vpconfig_timeouten; - u32 vpconfig_initvdd; - u32 vpconfig_forceupdate; - u32 vpconfig_vpenable; - u8 vpconfig_erroroffset_shift; - u8 vpconfig_errorgain_shift; - u8 vpconfig_initvoltage_shift; + u8 vpconfig_timeouten; + u8 vpconfig_initvdd; + u8 vpconfig_forceupdate; + u8 vpconfig_vpenable; u8 vstepmin_stepmin_shift; u8 vstepmin_smpswaittimemin_shift; u8 vstepmax_stepmax_shift; @@ -64,80 +80,49 @@ struct omap_vp_common_data { u8 vlimitto_vddmin_shift; u8 vlimitto_vddmax_shift; u8 vlimitto_timeout_shift; -}; + u8 vpvoltage_mask; -/** - * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data - * @prm_irqst_reg: reg offset for PRM_IRQSTATUS_MPU from top of PRM - * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg - * - * XXX prm_irqst_reg does not belong here - * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a - * hardware bug - * XXX This structure is probably not needed - */ -struct omap_vp_prm_irqst_data { - u8 prm_irqst_reg; - u32 tranxdone_status; + const struct omap_vp_ops *ops; }; /** - * struct omap_vp_instance_data - VP register offsets (per-VDD) - * @vp_common: pointer to struct omap_vp_common_data * for this SoC - * @prm_irqst_data: pointer to struct omap_vp_prm_irqst_data for this VDD + * struct omap_vp_instance - VP register offsets (per-VDD) + * @common: pointer to struct omap_vp_common * for this SoC * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start + * @id: Unique identifier for VP instance. + * @enabled: flag to keep track of whether vp is enabled or not * * XXX vp_common is probably not needed since it is per-SoC */ -struct omap_vp_instance_data { - const struct omap_vp_common_data *vp_common; - const struct omap_vp_prm_irqst_data *prm_irqst_data; +struct omap_vp_instance { + const struct omap_vp_common *common; u8 vpconfig; u8 vstepmin; u8 vstepmax; u8 vlimitto; u8 vstatus; u8 voltage; + u8 id; + bool enabled; }; -/** - * struct omap_vp_runtime_data - VP data populated at runtime by code - * @vpconfig_erroroffset: value of ERROROFFSET bitfield in PRM_VP*_CONFIG - * @vpconfig_errorgain: value of ERRORGAIN bitfield in PRM_VP*_CONFIG - * @vstepmin_smpswaittimemin: value of SMPSWAITTIMEMIN bitfield in PRM_VP*_VSTEPMIN - * @vstepmax_smpswaittimemax: value of SMPSWAITTIMEMAX bitfield in PRM_VP*_VSTEPMAX - * @vlimitto_timeout: value of TIMEOUT bitfield in PRM_VP*_VLIMITTO - * @vstepmin_stepmin: value of VSTEPMIN bitfield in PRM_VP*_VSTEPMIN - * @vstepmax_stepmax: value of VSTEPMAX bitfield in PRM_VP*_VSTEPMAX - * @vlimitto_vddmin: value of VDDMIN bitfield in PRM_VP*_VLIMITTO - * @vlimitto_vddmax: value of VDDMAX bitfield in PRM_VP*_VLIMITTO - * - * XXX Is this structure really needed? Why not just program the - * device directly? They are in PRM space, therefore in the WKUP - * powerdomain, so register contents should not be lost in off-mode. - * XXX Some of these fields are incorrectly named, e.g., vstep* - */ -struct omap_vp_runtime_data { - u32 vpconfig_erroroffset; - u16 vpconfig_errorgain; - u16 vstepmin_smpswaittimemin; - u16 vstepmax_smpswaittimemax; - u16 vlimitto_timeout; - u8 vstepmin_stepmin; - u8 vstepmax_stepmax; - u8 vlimitto_vddmin; - u8 vlimitto_vddmax; -}; +extern struct omap_vp_instance omap3_vp_mpu; +extern struct omap_vp_instance omap3_vp_core; -extern struct omap_vp_instance_data omap3_vp1_data; -extern struct omap_vp_instance_data omap3_vp2_data; +extern struct omap_vp_instance omap4_vp_mpu; +extern struct omap_vp_instance omap4_vp_iva; +extern struct omap_vp_instance omap4_vp_core; -extern struct omap_vp_instance_data omap4_vp_mpu_data; -extern struct omap_vp_instance_data omap4_vp_iva_data; -extern struct omap_vp_instance_data omap4_vp_core_data; +void omap_vp_init(struct voltagedomain *voltdm); +void omap_vp_enable(struct voltagedomain *voltdm); +void omap_vp_disable(struct voltagedomain *voltdm); +int omap_vp_forceupdate_scale(struct voltagedomain *voltdm, + unsigned long target_volt); +int omap_vp_update_errorgain(struct voltagedomain *voltdm, + unsigned long target_volt); #endif diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c index 6452170..260c554 100644 --- a/arch/arm/mach-omap2/vp3xxx_data.c +++ b/arch/arm/mach-omap2/vp3xxx_data.c @@ -25,16 +25,20 @@ #include "voltage.h" #include "vp.h" +#include "prm2xxx_3xxx.h" + +static const struct omap_vp_ops omap3_vp_ops = { + .check_txdone = omap3_prm_vp_check_txdone, + .clear_txdone = omap3_prm_vp_clear_txdone, +}; /* * VP data common to 34xx/36xx chips * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file. */ -static const struct omap_vp_common_data omap3_vp_common = { - .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT, +static const struct omap_vp_common omap3_vp_common = { + .vpconfig_erroroffset_mask = OMAP3430_ERROROFFSET_MASK, .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK, - .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT, - .vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT, .vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK, .vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK, .vpconfig_initvdd = OMAP3430_INITVDD_MASK, @@ -47,36 +51,29 @@ static const struct omap_vp_common_data omap3_vp_common = { .vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT, .vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT, .vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT, -}; + .vpvoltage_mask = OMAP3430_VPVOLTAGE_MASK, -static const struct omap_vp_prm_irqst_data omap3_vp1_prm_irqst_data = { - .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET, - .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK, + .ops = &omap3_vp_ops, }; -struct omap_vp_instance_data omap3_vp1_data = { - .vp_common = &omap3_vp_common, +struct omap_vp_instance omap3_vp_mpu = { + .id = OMAP3_VP_VDD_MPU_ID, + .common = &omap3_vp_common, .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET, .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET, .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET, .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET, .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET, .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET, - .prm_irqst_data = &omap3_vp1_prm_irqst_data, -}; - -static const struct omap_vp_prm_irqst_data omap3_vp2_prm_irqst_data = { - .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET, - .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK, }; -struct omap_vp_instance_data omap3_vp2_data = { - .vp_common = &omap3_vp_common, +struct omap_vp_instance omap3_vp_core = { + .id = OMAP3_VP_VDD_CORE_ID, + .common = &omap3_vp_common, .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET, .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET, .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET, .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET, .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET, .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET, - .prm_irqst_data = &omap3_vp2_prm_irqst_data, }; diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c index 65d1ad6..b4e7704 100644 --- a/arch/arm/mach-omap2/vp44xx_data.c +++ b/arch/arm/mach-omap2/vp44xx_data.c @@ -27,15 +27,18 @@ #include "vp.h" +static const struct omap_vp_ops omap4_vp_ops = { + .check_txdone = omap4_prm_vp_check_txdone, + .clear_txdone = omap4_prm_vp_clear_txdone, +}; + /* * VP data common to 44xx chips * XXX This stuff presumably belongs in the vp44xx.c or vp.c file. */ -static const struct omap_vp_common_data omap4_vp_common = { - .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT, +static const struct omap_vp_common omap4_vp_common = { + .vpconfig_erroroffset_mask = OMAP4430_ERROROFFSET_MASK, .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK, - .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT, - .vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT, .vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK, .vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK, .vpconfig_initvdd = OMAP4430_INITVDD_MASK, @@ -48,53 +51,39 @@ static const struct omap_vp_common_data omap4_vp_common = { .vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT, .vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT, .vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT, + .vpvoltage_mask = OMAP4430_VPVOLTAGE_MASK, + .ops = &omap4_vp_ops, }; -static const struct omap_vp_prm_irqst_data omap4_vp_mpu_prm_irqst_data = { - .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET, - .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK, -}; - -struct omap_vp_instance_data omap4_vp_mpu_data = { - .vp_common = &omap4_vp_common, +struct omap_vp_instance omap4_vp_mpu = { + .id = OMAP4_VP_VDD_MPU_ID, + .common = &omap4_vp_common, .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET, .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET, .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET, .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET, .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET, .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET, - .prm_irqst_data = &omap4_vp_mpu_prm_irqst_data, }; -static const struct omap_vp_prm_irqst_data omap4_vp_iva_prm_irqst_data = { - .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, - .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK, -}; - -struct omap_vp_instance_data omap4_vp_iva_data = { - .vp_common = &omap4_vp_common, +struct omap_vp_instance omap4_vp_iva = { + .id = OMAP4_VP_VDD_IVA_ID, + .common = &omap4_vp_common, .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET, .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET, .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET, .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET, .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET, .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET, - .prm_irqst_data = &omap4_vp_iva_prm_irqst_data, -}; - -static const struct omap_vp_prm_irqst_data omap4_vp_core_prm_irqst_data = { - .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, - .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK, }; -struct omap_vp_instance_data omap4_vp_core_data = { - .vp_common = &omap4_vp_common, +struct omap_vp_instance omap4_vp_core = { + .id = OMAP4_VP_VDD_CORE_ID, + .common = &omap4_vp_common, .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET, .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET, .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET, .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET, .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET, .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET, - .prm_irqst_data = &omap4_vp_core_prm_irqst_data, }; - diff --git a/arch/arm/mach-orion5x/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot index 67039c3..760a0ef 100644 --- a/arch/arm/mach-orion5x/Makefile.boot +++ b/arch/arm/mach-orion5x/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 0ab531d..22ace0b 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -308,8 +308,8 @@ void __init orion5x_init(void) * Many orion-based systems have buggy bootloader implementations. * This is a common fixup for bogus memory tags. */ -void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t, - char **from, struct meminfo *meminfo) +void __init tag_fixup_mem32(struct tag *t, char **from, + struct meminfo *meminfo) { for (; t->hdr.size; t = tag_next(t)) if (t->hdr.tag == ATAG_MEM && diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 3e5499d..909489f 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -53,11 +53,9 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -struct machine_desc; struct meminfo; struct tag; -extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, - char **, struct meminfo *); +extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *); #endif diff --git a/arch/arm/mach-pnx4008/Makefile.boot b/arch/arm/mach-pnx4008/Makefile.boot index 44c7117..9fa19ba 100644 --- a/arch/arm/mach-pnx4008/Makefile.boot +++ b/arch/arm/mach-pnx4008/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x80008000 + zreladdr-y += 0x80008000 params_phys-y := 0x80000100 initrd_phys-y := 0x80800000 diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 7af7fc0..13dd160 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -3,5 +3,7 @@ obj-y += irq.o obj-y += clock.o obj-y += rstc.o obj-y += prima2.o +obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o +obj-$(CONFIG_SUSPEND) += pm.o sleep.o diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot index d023db3..c77a488 100644 --- a/arch/arm/mach-prima2/Makefile.boot +++ b/arch/arm/mach-prima2/Makefile.boot @@ -1,3 +1,3 @@ -zreladdr-y := 0x00008000 +zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c index 615a4e7..aebad7e 100644 --- a/arch/arm/mach-prima2/clock.c +++ b/arch/arm/mach-prima2/clock.c @@ -350,10 +350,10 @@ static struct clk_lookup onchip_clks[] = { .clk = &clk_mem, }, { .dev_id = "sys", - .clk = &clk_sys, + .clk = &clk_sys, }, { .dev_id = "io", - .clk = &clk_io, + .clk = &clk_io, }, }; diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c index 7af254d..d93ceef 100644 --- a/arch/arm/mach-prima2/irq.c +++ b/arch/arm/mach-prima2/irq.c @@ -13,6 +13,8 @@ #include <asm/mach/irq.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/irqdomain.h> +#include <linux/syscore_ops.h> #define SIRFSOC_INT_RISC_MASK0 0x0018 #define SIRFSOC_INT_RISC_MASK1 0x001C @@ -66,7 +68,48 @@ void __init sirfsoc_of_irq_init(void) if (!sirfsoc_intc_base) panic("unable to map intc cpu registers\n"); + irq_domain_add_simple(np, 0); + of_node_put(np); sirfsoc_irq_init(); } + +struct sirfsoc_irq_status { + u32 mask0; + u32 mask1; + u32 level0; + u32 level1; +}; + +static struct sirfsoc_irq_status sirfsoc_irq_st; + +static int sirfsoc_irq_suspend(void) +{ + sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); + sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); + sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); + sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); + + return 0; +} + +static void sirfsoc_irq_resume(void) +{ + writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); + writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); + writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); + writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); +} + +static struct syscore_ops sirfsoc_irq_syscore_ops = { + .suspend = sirfsoc_irq_suspend, + .resume = sirfsoc_irq_resume, +}; + +static int __init sirfsoc_irq_pm_init(void) +{ + register_syscore_ops(&sirfsoc_irq_syscore_ops); + return 0; +} +device_initcall(sirfsoc_irq_pm_init); diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c index 66c6387e..c998377 100644 --- a/arch/arm/mach-prima2/l2x0.c +++ b/arch/arm/mach-prima2/l2x0.c @@ -8,51 +8,24 @@ #include <linux/init.h> #include <linux/kernel.h> -#include <linux/io.h> -#include <linux/errno.h> #include <linux/of.h> -#include <linux/of_address.h> #include <asm/hardware/cache-l2x0.h> -#define L2X0_ADDR_FILTERING_START 0xC00 -#define L2X0_ADDR_FILTERING_END 0xC04 - -static struct of_device_id l2x_ids[] = { - { .compatible = "arm,pl310-cache" }, +static struct of_device_id prima2_l2x0_ids[] = { + { .compatible = "sirf,prima2-pl310-cache" }, + {}, }; -static int __init sirfsoc_of_l2x_init(void) +static int __init sirfsoc_l2x0_init(void) { struct device_node *np; - void __iomem *sirfsoc_l2x_base; - - np = of_find_matching_node(NULL, l2x_ids); - if (!np) - panic("unable to find compatible l2x node in dtb\n"); - - sirfsoc_l2x_base = of_iomap(np, 0); - if (!sirfsoc_l2x_base) - panic("unable to map l2x cpu registers\n"); - - of_node_put(np); - - if (!(readl_relaxed(sirfsoc_l2x_base + L2X0_CTRL) & 1)) { - /* - * set the physical memory windows L2 cache will cover - */ - writel_relaxed(PHYS_OFFSET + 1024 * 1024 * 1024, - sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END); - writel_relaxed(PHYS_OFFSET | 0x1, - sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START); - writel_relaxed(0, - sirfsoc_l2x_base + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(0, - sirfsoc_l2x_base + L2X0_DATA_LATENCY_CTRL); + np = of_find_matching_node(NULL, prima2_l2x0_ids); + if (np) { + pr_info("Initializing prima2 L2 cache\n"); + return l2x0_of_init(0x40000, 0); } - l2x0_init((void __iomem *)sirfsoc_l2x_base, 0x00040000, - 0x00000000); return 0; } -early_initcall(sirfsoc_of_l2x_init); +early_initcall(sirfsoc_l2x0_init); diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c new file mode 100644 index 0000000..cb53160 --- /dev/null +++ b/arch/arm/mach-prima2/pm.c @@ -0,0 +1,150 @@ +/* + * power management entry for CSR SiRFprimaII + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/kernel.h> +#include <linux/suspend.h> +#include <linux/slab.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/io.h> +#include <linux/rtc/sirfsoc_rtciobrg.h> +#include <asm/suspend.h> +#include <asm/hardware/cache-l2x0.h> + +#include "pm.h" + +/* + * suspend asm codes will access these to make DRAM become self-refresh and + * system sleep + */ +u32 sirfsoc_pwrc_base; +void __iomem *sirfsoc_memc_base; + +static void sirfsoc_set_wakeup_source(void) +{ + u32 pwr_trigger_en_reg; + pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + + SIRFSOC_PWRC_TRIGGER_EN); +#define X_ON_KEY_B (1 << 0) + sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B, + sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN); +} + +static void sirfsoc_set_sleep_mode(u32 mode) +{ + u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + + SIRFSOC_PWRC_PDN_CTRL); + sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1); + sleep_mode |= mode << 1; + sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base + + SIRFSOC_PWRC_PDN_CTRL); +} + +static int sirfsoc_pre_suspend_power_off(void) +{ + u32 wakeup_entry = virt_to_phys(cpu_resume); + + sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base + + SIRFSOC_PWRC_SCRATCH_PAD1); + + sirfsoc_set_wakeup_source(); + + sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE); + + return 0; +} + +static int sirfsoc_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_MEM: + sirfsoc_pre_suspend_power_off(); + + outer_flush_all(); + outer_disable(); + /* go zzz */ + cpu_suspend(0, sirfsoc_finish_suspend); + outer_resume(); + break; + default: + return -EINVAL; + } + return 0; +} + +static const struct platform_suspend_ops sirfsoc_pm_ops = { + .enter = sirfsoc_pm_enter, + .valid = suspend_valid_only_mem, +}; + +static int __init sirfsoc_pm_init(void) +{ + suspend_set_ops(&sirfsoc_pm_ops); + return 0; +} +late_initcall(sirfsoc_pm_init); + +static const struct of_device_id pwrc_ids[] = { + { .compatible = "sirf,prima2-pwrc" }, + {} +}; + +static int __init sirfsoc_of_pwrc_init(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, pwrc_ids); + if (!np) + panic("unable to find compatible pwrc node in dtb\n"); + + /* + * pwrc behind rtciobrg is not located in memory space + * though the property is named reg. reg only means base + * offset for pwrc. then of_iomap is not suitable here. + */ + if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base)) + panic("unable to find base address of pwrc node in dtb\n"); + + of_node_put(np); + + return 0; +} +postcore_initcall(sirfsoc_of_pwrc_init); + +static const struct of_device_id memc_ids[] = { + { .compatible = "sirf,prima2-memc" }, + {} +}; + +static int __devinit sirfsoc_memc_probe(struct platform_device *op) +{ + struct device_node *np = op->dev.of_node; + + sirfsoc_memc_base = of_iomap(np, 0); + if (!sirfsoc_memc_base) + panic("unable to map memc registers\n"); + + return 0; +} + +static struct platform_driver sirfsoc_memc_driver = { + .probe = sirfsoc_memc_probe, + .driver = { + .name = "sirfsoc-memc", + .owner = THIS_MODULE, + .of_match_table = memc_ids, + }, +}; + +static int __init sirfsoc_memc_init(void) +{ + return platform_driver_register(&sirfsoc_memc_driver); +} +postcore_initcall(sirfsoc_memc_init); diff --git a/arch/arm/mach-prima2/pm.h b/arch/arm/mach-prima2/pm.h new file mode 100644 index 0000000..bae6d77 --- /dev/null +++ b/arch/arm/mach-prima2/pm.h @@ -0,0 +1,29 @@ +/* + * arch/arm/mach-prima2/pm.h + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#ifndef _MACH_PRIMA2_PM_H_ +#define _MACH_PRIMA2_PM_H_ + +#define SIRFSOC_PWR_SLEEPFORCE 0x01 + +#define SIRFSOC_SLEEP_MODE_MASK 0x3 +#define SIRFSOC_DEEP_SLEEP_MODE 0x1 + +#define SIRFSOC_PWRC_PDN_CTRL 0x0 +#define SIRFSOC_PWRC_PON_OFF 0x4 +#define SIRFSOC_PWRC_TRIGGER_EN 0x8 +#define SIRFSOC_PWRC_PIN_STATUS 0x14 +#define SIRFSOC_PWRC_SCRATCH_PAD1 0x18 +#define SIRFSOC_PWRC_SCRATCH_PAD2 0x1C + +#ifndef __ASSEMBLY__ +extern int sirfsoc_finish_suspend(unsigned long); +#endif + +#endif + diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c index ee33c3d..ef555c0 100644 --- a/arch/arm/mach-prima2/prima2.c +++ b/arch/arm/mach-prima2/prima2.c @@ -1,5 +1,5 @@ /* - * Defines machines for CSR SiRFprimaII + * Defines machines for CSR SiRFprimaII * * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. * diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c new file mode 100644 index 0000000..9d80f1e --- /dev/null +++ b/arch/arm/mach-prima2/rtciobrg.c @@ -0,0 +1,139 @@ +/* + * RTC I/O Bridge interfaces for CSR SiRFprimaII + * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> + +#define SIRFSOC_CPUIOBRG_CTRL 0x00 +#define SIRFSOC_CPUIOBRG_WRBE 0x04 +#define SIRFSOC_CPUIOBRG_ADDR 0x08 +#define SIRFSOC_CPUIOBRG_DATA 0x0c + +/* + * suspend asm codes will access this address to make system deepsleep + * after DRAM becomes self-refresh + */ +void __iomem *sirfsoc_rtciobrg_base; +static DEFINE_SPINLOCK(rtciobrg_lock); + +/* + * symbols without lock are only used by suspend asm codes + * and these symbols are not exported too + */ +void sirfsoc_rtc_iobrg_wait_sync(void) +{ + while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL)) + cpu_relax(); +} + +void sirfsoc_rtc_iobrg_besyncing(void) +{ + unsigned long flags; + + spin_lock_irqsave(&rtciobrg_lock, flags); + + sirfsoc_rtc_iobrg_wait_sync(); + + spin_unlock_irqrestore(&rtciobrg_lock, flags); +} +EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_besyncing); + +u32 __sirfsoc_rtc_iobrg_readl(u32 addr) +{ + sirfsoc_rtc_iobrg_wait_sync(); + + writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); + writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); + writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); + + sirfsoc_rtc_iobrg_wait_sync(); + + return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); +} + +u32 sirfsoc_rtc_iobrg_readl(u32 addr) +{ + unsigned long flags, val; + + spin_lock_irqsave(&rtciobrg_lock, flags); + + val = __sirfsoc_rtc_iobrg_readl(addr); + + spin_unlock_irqrestore(&rtciobrg_lock, flags); + + return val; +} +EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_readl); + +void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr) +{ + sirfsoc_rtc_iobrg_wait_sync(); + + writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); + writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); + + writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); +} + +void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr) +{ + unsigned long flags; + + spin_lock_irqsave(&rtciobrg_lock, flags); + + sirfsoc_rtc_iobrg_pre_writel(val, addr); + + writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); + + sirfsoc_rtc_iobrg_wait_sync(); + + spin_unlock_irqrestore(&rtciobrg_lock, flags); +} +EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel); + +static const struct of_device_id rtciobrg_ids[] = { + { .compatible = "sirf,prima2-rtciobg" }, + {} +}; + +static int __devinit sirfsoc_rtciobrg_probe(struct platform_device *op) +{ + struct device_node *np = op->dev.of_node; + + sirfsoc_rtciobrg_base = of_iomap(np, 0); + if (!sirfsoc_rtciobrg_base) + panic("unable to map rtc iobrg registers\n"); + + return 0; +} + +static struct platform_driver sirfsoc_rtciobrg_driver = { + .probe = sirfsoc_rtciobrg_probe, + .driver = { + .name = "sirfsoc-rtciobrg", + .owner = THIS_MODULE, + .of_match_table = rtciobrg_ids, + }, +}; + +static int __init sirfsoc_rtciobrg_init(void) +{ + return platform_driver_register(&sirfsoc_rtciobrg_driver); +} +postcore_initcall(sirfsoc_rtciobrg_init); + +MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, " + "Barry Song <baohua.song@csr.com>"); +MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-prima2/sleep.S b/arch/arm/mach-prima2/sleep.S new file mode 100644 index 0000000..0745abc --- /dev/null +++ b/arch/arm/mach-prima2/sleep.S @@ -0,0 +1,64 @@ +/* + * sleep mode for CSR SiRFprimaII + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/linkage.h> +#include <asm/ptrace.h> +#include <asm/assembler.h> + +#include "pm.h" + +#define DENALI_CTL_22_OFF 0x58 +#define DENALI_CTL_112_OFF 0x1c0 + + .text + +ENTRY(sirfsoc_finish_suspend) + @ r5: mem controller + ldr r0, =sirfsoc_memc_base + ldr r5, [r0] + @ r6: pwrc base offset + ldr r0, =sirfsoc_pwrc_base + ldr r6, [r0] + @ r7: rtc iobrg controller + ldr r0, =sirfsoc_rtciobrg_base + ldr r7, [r0] + + @ Read the power control register and set the + @ sleep force bit. + add r0, r6, #SIRFSOC_PWRC_PDN_CTRL + bl __sirfsoc_rtc_iobrg_readl + orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE + add r1, r6, #SIRFSOC_PWRC_PDN_CTRL + bl sirfsoc_rtc_iobrg_pre_writel + mov r1, #0x1 + + @ read the MEM ctl register and set the self + @ refresh bit + + ldr r2, [r5, #DENALI_CTL_22_OFF] + orr r2, r2, #0x1 + + @ Following code has to run from cache since + @ the RAM is going to self refresh mode + .align 5 + str r2, [r5, #DENALI_CTL_22_OFF] + +1: + ldr r4, [r5, #DENALI_CTL_112_OFF] + tst r4, #0x1 + bne 1b + + @ write SLEEPFORCE through rtc iobridge + + str r1, [r7] + @ wait rtc io bridge sync +1: + ldr r3, [r7] + tst r3, #0x01 + bne 1b + b . diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c index ed7ec48..b7a6091 100644 --- a/arch/arm/mach-prima2/timer.c +++ b/arch/arm/mach-prima2/timer.c @@ -40,6 +40,17 @@ #define SIRFSOC_TIMER_LATCH_BIT BIT(0) +#define SIRFSOC_TIMER_REG_CNT 11 + +static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { + SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2, + SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5, + SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV, + SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI, +}; + +static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; + static void __iomem *sirfsoc_timer_base; static void __init sirfsoc_of_timer_map(void); @@ -106,6 +117,27 @@ static void sirfsoc_timer_set_mode(enum clock_event_mode mode, } } +static void sirfsoc_clocksource_suspend(struct clocksource *cs) +{ + int i; + + writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); + + for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) + sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); +} + +static void sirfsoc_clocksource_resume(struct clocksource *cs) +{ + int i; + + for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) + writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); + + writel_relaxed(sirfsoc_timer_reg_val[i - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); + writel_relaxed(sirfsoc_timer_reg_val[i - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); +} + static struct clock_event_device sirfsoc_clockevent = { .name = "sirfsoc_clockevent", .rating = 200, @@ -120,6 +152,8 @@ static struct clocksource sirfsoc_clocksource = { .mask = CLOCKSOURCE_MASK(64), .flags = CLOCK_SOURCE_IS_CONTINUOUS, .read = sirfsoc_timer_read, + .suspend = sirfsoc_clocksource_suspend, + .resume = sirfsoc_clocksource_resume, }; static struct irqaction sirfsoc_timer_irq = { @@ -133,14 +167,14 @@ static struct irqaction sirfsoc_timer_irq = { /* Overwrite weak default sched_clock with more precise one */ unsigned long long notrace sched_clock(void) { - static int is_mapped = 0; + static int is_mapped; /* * sched_clock is called earlier than .init of sys_timer * if we map timer memory in .init of sys_timer, system * will panic due to illegal memory access */ - if(!is_mapped) { + if (!is_mapped) { sirfsoc_of_timer_map(); is_mapped = 1; } diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index cd19309..61d3c72 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -2,6 +2,27 @@ if ARCH_PXA menu "Intel PXA2xx/PXA3xx Implementations" +config ARCH_PXA_V7 + bool "ARMv7 (PXA95x) based systems" + +if ARCH_PXA_V7 +comment "Marvell Dev Platforms (sorted by hardware release time)" +config MACH_TAVOREVB3 + bool "PXA95x Development Platform (aka TavorEVB III)" + select CPU_PXA955 + +config MACH_SAARB + bool "PXA955 Handheld Platform (aka SAARB)" + select CPU_PXA955 +endif + +config PXA_V7_MACH_AUTO + def_bool y + depends on ARCH_PXA_V7 + depends on !MACH_SAARB + select MACH_TAVOREVB3 + +if !ARCH_PXA_V7 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" config ARCH_LUBBOCK @@ -41,19 +62,11 @@ config MACH_TAVOREVB select PXA3xx select CPU_PXA930 -config MACH_TAVOREVB3 - bool "PXA95x Development Platform (aka TavorEVB III)" - select CPU_PXA950 - config MACH_SAAR bool "PXA930 Handheld Platform (aka SAAR)" select PXA3xx select CPU_PXA930 -config MACH_SAARB - bool "PXA955 Handheld Platform (aka SAARB)" - select CPU_PXA955 - comment "Third Party Dev Platforms (sorted by vendor name)" config ARCH_PXA_IDP @@ -414,6 +427,7 @@ config MACH_CENTRO bool "Palm Centro 685 (GSM)" default y depends on ARCH_PXA_PALM + select MACH_PALM27X select PXA27x select IWMMXT select PALM_TREO @@ -425,6 +439,7 @@ config MACH_TREO680 bool "Palm Treo 680" default y depends on ARCH_PXA_PALM + select MACH_PALM27X select PXA27x select IWMMXT select PALM_TREO @@ -436,15 +451,18 @@ config MACH_RAUMFELD_RC bool "Raumfeld Controller" select PXA3xx select CPU_PXA300 + select POWER_SUPPLY select HAVE_PWM config MACH_RAUMFELD_CONNECTOR bool "Raumfeld Connector" + select POWER_SUPPLY select PXA3xx select CPU_PXA300 config MACH_RAUMFELD_SPEAKER bool "Raumfeld Speaker" + select POWER_SUPPLY select PXA3xx select CPU_PXA300 @@ -598,7 +616,7 @@ config MACH_ZIPIT2 bool "Zipit Z2 Handheld" select PXA27x select HAVE_PWM - +endif endmenu config PXA25x @@ -688,6 +706,8 @@ config SHARPSL_PM config SHARPSL_PM_MAX1111 bool select HWMON + select SPI + select SPI_MASTER select SENSORS_MAX1111 config PXA_HAVE_ISA_IRQS diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index cc39d17..be0f7df 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -19,7 +19,7 @@ endif obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o -obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o +obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o pxa95x.o smemc.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o obj-$(CONFIG_CPU_PXA930) += pxa930.o diff --git a/arch/arm/mach-pxa/Makefile.boot b/arch/arm/mach-pxa/Makefile.boot index 1ead671..2c1ae92 100644 --- a/arch/arm/mach-pxa/Makefile.boot +++ b/arch/arm/mach-pxa/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0xa0008000 + zreladdr-y += 0xa0008000 diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 7765d67..fc0b854 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -591,7 +591,7 @@ static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ct BALLOON3_NAND_CONTROL_REG); if (balloon3_ctl_set) __raw_writel(balloon3_ctl_set, - BALLOON3_NAND_CONTROL_REG | + BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR); } @@ -608,7 +608,7 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip) __raw_writew( BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3, - BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); + BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR); /* Deassert correct nCE line */ __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip, @@ -626,7 +626,7 @@ static int balloon3_nand_probe(struct platform_device *pdev) int ret; __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, - BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR); + BALLOON3_NAND_CONTROL2_REG + BALLOON3_FPGA_SETnCLR); ver = __raw_readw(BALLOON3_FPGA_VER); if (ver < 0x4f08) @@ -649,7 +649,7 @@ static int balloon3_nand_probe(struct platform_device *pdev) BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | BALLOON3_NAND_CONTROL_FLWP, - BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); + BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR); return 0; err2: @@ -807,7 +807,7 @@ static void __init balloon3_init(void) static struct map_desc balloon3_io_desc[] __initdata = { { /* CPLD/FPGA */ - .virtual = BALLOON3_FPGA_VIRT, + .virtual = (unsigned long)BALLOON3_FPGA_VIRT, .pfn = __phys_to_pfn(BALLOON3_FPGA_PHYS), .length = BALLOON3_FPGA_LENGTH, .type = MT_DEVICE, diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 6bf479d..ebd9259 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -26,7 +26,7 @@ #include <asm/hardware/it8152.h> -unsigned long it8152_base_address; +void __iomem *it8152_base_address; static int cmx2xx_it8152_irq_gpio; static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index 349896c..f2e4190 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -39,7 +39,7 @@ extern void cmx270_init(void); #define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40) /* virtual addresses for statically mapped regions */ -#define CMX2XX_VIRT_BASE (0xe8000000) +#define CMX2XX_VIRT_BASE (void __iomem *)(0xe8000000) #define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE) /* physical address if local-bus attached devices */ @@ -482,7 +482,7 @@ static void __init cmx2xx_init_irq(void) /* Map PCI companion statically */ static struct map_desc cmx2xx_io_desc[] __initdata = { [0] = { /* PCI bridge */ - .virtual = CMX2XX_IT8152_VIRT, + .virtual = (unsigned long)CMX2XX_IT8152_VIRT, .pfn = __phys_to_pfn(PXA_CS4_PHYS), .length = SZ_64M, .type = MT_DEVICE diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 9ac0225..3a7387f 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -775,7 +775,6 @@ static struct gpio cm_x300_wi2wi_gpios[] __initdata = { static void __init cm_x300_init_wi2wi(void) { - int bt_reset, wlan_en; int err; if (system_rev < 130) { @@ -791,12 +790,11 @@ static void __init cm_x300_init_wi2wi(void) } udelay(10); - gpio_set_value(bt_reset, 0); + gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 0); udelay(10); - gpio_set_value(bt_reset, 1); + gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 1); - gpio_free(wlan_en); - gpio_free(bt_reset); + gpio_free_array(ARRAY_AND_SIZE(cm_x300_wi2wi_gpios)); } /* MFP */ @@ -839,8 +837,8 @@ static void __init cm_x300_init(void) cm_x300_init_bl(); } -static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, - char **cmdline, struct meminfo *mi) +static void __init cm_x300_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { /* Make sure that mi->bank[0].start = PHYS_ADDR */ for (; tags->hdr.size; tags = tag_next(tags)) diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 185a37c..3e9483b 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -705,8 +705,8 @@ static void __init corgi_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); } -static void __init fixup_corgi(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) +static void __init fixup_corgi(struct tag *tags, char **cmdline, + struct meminfo *mi) { sharpsl_save_param(); mi->nr_banks=1; diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index e823c54..8e697dd 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -41,8 +41,7 @@ #include "clock.h" /* Only e800 has 128MB RAM */ -void __init eseries_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) +void __init eseries_fixup(struct tag *tags, char **cmdline, struct meminfo *mi) { mi->nr_banks=1; mi->bank[0].start = 0xa0000000; diff --git a/arch/arm/mach-pxa/eseries.h b/arch/arm/mach-pxa/eseries.h index 5930f5e..be92196 100644 --- a/arch/arm/mach-pxa/eseries.h +++ b/arch/arm/mach-pxa/eseries.h @@ -1,5 +1,4 @@ -void __init eseries_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi); +void __init eseries_fixup(struct tag *tags, char **cmdline, struct meminfo *mi); extern struct pxa2xx_udc_mach_info e7xx_udc_mach_info; extern struct pxaficp_platform_data e7xx_ficp_platform_data; diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h index f4c0365..bbf9df3 100644 --- a/arch/arm/mach-pxa/include/mach/addr-map.h +++ b/arch/arm/mach-pxa/include/mach/addr-map.h @@ -20,7 +20,7 @@ * Peripheral Bus */ #define PERIPH_PHYS 0x40000000 -#define PERIPH_VIRT 0xf2000000 +#define PERIPH_VIRT IOMEM(0xf2000000) #define PERIPH_SIZE 0x02000000 /* @@ -28,21 +28,21 @@ */ #define PXA2XX_SMEMC_PHYS 0x48000000 #define PXA3XX_SMEMC_PHYS 0x4a000000 -#define SMEMC_VIRT 0xf6000000 +#define SMEMC_VIRT IOMEM(0xf6000000) #define SMEMC_SIZE 0x00100000 /* * Dynamic Memory Controller (only on PXA3xx) */ #define DMEMC_PHYS 0x48100000 -#define DMEMC_VIRT 0xf6100000 +#define DMEMC_VIRT IOMEM(0xf6100000) #define DMEMC_SIZE 0x00100000 /* * Internal Memory Controller (PXA27x and later) */ #define IMEMC_PHYS 0x58000000 -#define IMEMC_VIRT 0xfe000000 +#define IMEMC_VIRT IOMEM(0xfe000000) #define IMEMC_SIZE 0x00100000 #endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index 7074e76..6d7eab3 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -23,7 +23,7 @@ enum balloon3_features { }; #define BALLOON3_FPGA_PHYS PXA_CS4_PHYS -#define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */ +#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */ #define BALLOON3_FPGA_LENGTH 0x01000000 #define BALLOON3_FPGA_SETnCLR (0x1000) diff --git a/arch/arm/mach-pxa/include/mach/gpio-pxa.h b/arch/arm/mach-pxa/include/mach/gpio-pxa.h index 41b4c93..576868f 100644 --- a/arch/arm/mach-pxa/include/mach/gpio-pxa.h +++ b/arch/arm/mach-pxa/include/mach/gpio-pxa.h @@ -25,7 +25,7 @@ #define GPIO_REGS_VIRT io_p2v(0x40E00000) #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) -#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) +#define GPIO_REG(x) (GPIO_REGS_VIRT + (x)) /* GPIO Pin Level Registers */ #define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index de63ca3..8184669 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -36,22 +36,23 @@ * Note that not all PXA2xx chips implement all those addresses, and the * kernel only maps the minimum needed range of this mapping. */ -#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) +#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) #ifndef __ASSEMBLY__ - -# define __REG(x) (*((volatile u32 *)io_p2v(x))) +# define IOMEM(x) ((void __iomem *)(x)) +# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) /* With indexed regs we don't want to feed the index through io_p2v() especially if it is a variable, otherwise horrible code will result. */ # define __REG2(x,y) \ - (*(volatile u32 *)((u32)&__REG(x) + (y))) + (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) # define __PREG(x) (io_v2p((u32)&(x))) #else +# define IOMEM(x) x # define __REG(x) io_p2v(x) # define __PREG(x) io_v2p(x) diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h index cd07009..4edc712 100644 --- a/arch/arm/mach-pxa/include/mach/lpd270.h +++ b/arch/arm/mach-pxa/include/mach/lpd270.h @@ -13,13 +13,13 @@ #define __ASM_ARCH_LPD270_H #define LPD270_CPLD_PHYS PXA_CS2_PHYS -#define LPD270_CPLD_VIRT 0xf0000000 +#define LPD270_CPLD_VIRT IOMEM(0xf0000000) #define LPD270_CPLD_SIZE 0x00100000 #define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) /* CPLD registers */ -#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x))) +#define LPD270_CPLD_REG(x) (LPD270_CPLD_VIRT + (x)) #define LPD270_CONTROL LPD270_CPLD_REG(0x00) #define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) #define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h index 297387e..990d2bf 100644 --- a/arch/arm/mach-pxa/include/mach/mtd-xip.h +++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h @@ -16,7 +16,6 @@ #define __ARCH_PXA_MTD_XIP_H__ #include <mach/regs-ost.h> -#include <mach/regs-intc.h> #define xip_irqpending() (ICIP & ICMR) diff --git a/arch/arm/mach-pxa/include/mach/palm27x.h b/arch/arm/mach-pxa/include/mach/palm27x.h index 0a5e5ea..f80bbe2 100644 --- a/arch/arm/mach-pxa/include/mach/palm27x.h +++ b/arch/arm/mach-pxa/include/mach/palm27x.h @@ -34,7 +34,7 @@ extern struct pxafb_mode_info palm_320x320_new_lcd_mode; extern void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode); #else -static inline void palm27x_lcd_init(int power, struct pxafb_mode_info *mode) {} +#define palm27x_lcd_init(power, mode) do {} while (0) #endif #if defined(CONFIG_USB_GADGET_PXA27X) || \ diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h index 10abc4f..7074a6e 100644 --- a/arch/arm/mach-pxa/include/mach/palmtx.h +++ b/arch/arm/mach-pxa/include/mach/palmtx.h @@ -71,7 +71,7 @@ /* Various addresses */ #define PALMTX_PCMCIA_PHYS 0x28000000 -#define PALMTX_PCMCIA_VIRT 0xf0000000 +#define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000) #define PALMTX_PCMCIA_SIZE 0x100000 #define PALMTX_PHYS_RAM_START 0xa0000000 @@ -84,8 +84,8 @@ #define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24)) #define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25)) -#define PALMTX_NAND_ALE_VIRT 0xff100000 -#define PALMTX_NAND_CLE_VIRT 0xff200000 +#define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000) +#define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000) /* TOUCHSCREEN */ #define AC97_LINK_FRAME 21 diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h index b9b1bdc..7cff640 100644 --- a/arch/arm/mach-pxa/include/mach/pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/pxa27x.h @@ -1,6 +1,7 @@ #ifndef __MACH_PXA27x_H #define __MACH_PXA27x_H +#include <linux/suspend.h> #include <mach/hardware.h> #include <mach/pxa2xx-regs.h> #include <mach/mfp-pxa27x.h> @@ -21,6 +22,7 @@ extern void __init pxa27x_map_io(void); extern void __init pxa27x_init_irq(void); extern int __init pxa27x_set_pwrmode(unsigned int mode); +extern void pxa27x_cpu_pm_enter(suspend_state_t state); #define pxa27x_handle_irq ichp_handle_irq diff --git a/arch/arm/mach-pxa/include/mach/pxa95x.h b/arch/arm/mach-pxa/include/mach/pxa95x.h new file mode 100644 index 0000000..cbb097c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa95x.h @@ -0,0 +1,7 @@ +#ifndef __MACH_PXA95X_H +#define __MACH_PXA95X_H + +#include <mach/pxa3xx.h> +#include <mach/mfp-pxa930.h> + +#endif /* __MACH_PXA95X_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index 01a45ac4..486b4c5 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h @@ -158,5 +158,18 @@ struct pxafb_mach_info { void pxa_set_fb_info(struct device *, struct pxafb_mach_info *); unsigned long pxafb_get_hsync_time(struct device *dev); +#ifdef CONFIG_FB_PXA_SMARTPANEL extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); extern int pxafb_smart_flush(struct fb_info *info); +#else +static inline int pxafb_smart_queue(struct fb_info *info, + uint16_t *cmds, int n) +{ + return 0; +} + +static inline int pxafb_smart_flush(struct fb_info *info) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h index 654adc9..b7de471 100644 --- a/arch/arm/mach-pxa/include/mach/smemc.h +++ b/arch/arm/mach-pxa/include/mach/smemc.h @@ -13,7 +13,7 @@ #define PXA2XX_SMEMC_BASE 0x48000000 #define PXA3XX_SMEMC_BASE 0x4a000000 -#define SMEMC_VIRT 0xf6000000 +#define SMEMC_VIRT IOMEM(0xf6000000) #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h index 0641f31..56024f8 100644 --- a/arch/arm/mach-pxa/include/mach/zeus.h +++ b/arch/arm/mach-pxa/include/mach/zeus.h @@ -68,7 +68,7 @@ * Be gentle, and remap that over 32kB... */ -#define ZEUS_CPLD (0xf0000000) +#define ZEUS_CPLD IOMEM(0xf0000000) #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) #define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) @@ -76,7 +76,7 @@ /* CPLD register bits */ #define ZEUS_CPLD_CONTROL_CF_RST 0x01 -#define ZEUS_PC104IO (0xf1000000) +#define ZEUS_PC104IO IOMEM(0xf1000000) #define ZEUS_SRAM_SIZE (256 * 1024) diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h index ea24998..ecca976 100644 --- a/arch/arm/mach-pxa/include/mach/zylonite.h +++ b/arch/arm/mach-pxa/include/mach/zylonite.h @@ -19,7 +19,7 @@ extern int wm9713_irq; extern int lcd_id; extern int lcd_orientation; -#ifdef CONFIG_CPU_PXA300 +#ifdef CONFIG_MACH_ZYLONITE300 extern void zylonite_pxa300_init(void); #else static inline void zylonite_pxa300_init(void) @@ -29,7 +29,7 @@ static inline void zylonite_pxa300_init(void) } #endif -#ifdef CONFIG_CPU_PXA320 +#ifdef CONFIG_MACH_ZYLONITE320 extern void zylonite_pxa320_init(void); #else static inline void zylonite_pxa320_init(void) diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 8d9200f..532c5d3 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -26,7 +26,7 @@ #include "generic.h" -#define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) +#define IRQ_BASE io_p2v(0x40d00000) #define ICIP (0x000) #define ICMR (0x004) @@ -64,7 +64,7 @@ static inline void __iomem *irq_base(int i) 0x40d00130, }; - return (void __iomem *)io_p2v(phys_base[i]); + return io_p2v(phys_base[i]); } void pxa_mask_irq(struct irq_data *d) diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 64540d9..1dd5302 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -479,7 +479,7 @@ static void __init lpd270_init(void) static struct map_desc lpd270_io_desc[] __initdata = { { - .virtual = LPD270_CPLD_VIRT, + .virtual = (unsigned long)LPD270_CPLD_VIRT, .pfn = __phys_to_pfn(LPD270_CPLD_PHYS), .length = LPD270_CPLD_SIZE, .type = MT_DEVICE, diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 7346fbf..94e9708 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -423,6 +423,7 @@ static void __init palmphone_common_init(void) palmtreo_leds_init(); } +#ifdef CONFIG_MACH_TREO680 static void __init treo680_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); @@ -430,7 +431,9 @@ static void __init treo680_init(void) palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY, GPIO_NR_TREO680_SD_POWER, 0); } +#endif +#ifdef CONFIG_MACH_CENTRO static void __init centro_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config)); @@ -438,7 +441,9 @@ static void __init centro_init(void) palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, -1, GPIO_NR_CENTRO_SD_POWER, 1); } +#endif +#ifdef CONFIG_MACH_TREO680 MACHINE_START(TREO680, "Palm Treo 680") .atag_offset = 0x100, .map_io = pxa27x_map_io, @@ -448,7 +453,9 @@ MACHINE_START(TREO680, "Palm Treo 680") .timer = &pxa_timer, .init_machine = treo680_init, MACHINE_END +#endif +#ifdef CONFIG_MACH_CENTRO MACHINE_START(CENTRO, "Palm Centro 685") .atag_offset = 0x100, .map_io = pxa27x_map_io, @@ -458,3 +465,4 @@ MACHINE_START(CENTRO, "Palm Centro 685") .timer = &pxa_timer, .init_machine = centro_init, MACHINE_END +#endif diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 2b9e76f..4e3e459 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -247,7 +247,7 @@ static void palmtx_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; - unsigned long nandaddr = (unsigned long)this->IO_ADDR_W; + char __iomem *nandaddr = this->IO_ADDR_W; if (cmd == NAND_CMD_NONE) return; @@ -315,17 +315,17 @@ static inline void palmtx_nand_init(void) {} ******************************************************************************/ static struct map_desc palmtx_io_desc[] __initdata = { { - .virtual = PALMTX_PCMCIA_VIRT, + .virtual = (unsigned long)PALMTX_PCMCIA_VIRT, .pfn = __phys_to_pfn(PALMTX_PCMCIA_PHYS), .length = PALMTX_PCMCIA_SIZE, .type = MT_DEVICE, }, { - .virtual = PALMTX_NAND_ALE_VIRT, + .virtual = (unsigned long)PALMTX_NAND_ALE_VIRT, .pfn = __phys_to_pfn(PALMTX_NAND_ALE_PHYS), .length = SZ_1M, .type = MT_DEVICE, }, { - .virtual = PALMTX_NAND_CLE_VIRT, + .virtual = (unsigned long)PALMTX_NAND_CLE_VIRT, .pfn = __phys_to_pfn(PALMTX_NAND_CLE_PHYS), .length = SZ_1M, .type = MT_DEVICE, diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index a113ea9..948ce3e 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -454,8 +454,8 @@ static void __init poodle_init(void) poodle_init_spi(); } -static void __init fixup_poodle(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) +static void __init fixup_poodle(struct tag *tags, char **cmdline, + struct meminfo *mi) { sharpsl_save_param(); mi->nr_banks=1; diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 8746e10..f05f948 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -325,7 +325,7 @@ void __init pxa26x_init_irq(void) static struct map_desc pxa25x_io_desc[] __initdata = { { /* Mem Ctl */ - .virtual = SMEMC_VIRT, + .virtual = (unsigned long)SMEMC_VIRT, .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), .length = 0x00200000, .type = MT_DEVICE diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 2bb5cf8..bc5a98e 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -391,7 +391,7 @@ void __init pxa27x_init_irq(void) static struct map_desc pxa27x_io_desc[] __initdata = { { /* Mem Ctl */ - .virtual = SMEMC_VIRT, + .virtual = (unsigned long)SMEMC_VIRT, .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), .length = 0x00200000, .type = MT_DEVICE diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c index ce7168b..e28dfb8 100644 --- a/arch/arm/mach-pxa/pxa3xx-ulpi.c +++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c @@ -265,6 +265,7 @@ int pxa3xx_u2d_start_hc(struct usb_bus *host) return err; } +EXPORT_SYMBOL_GPL(pxa3xx_u2d_start_hc); void pxa3xx_u2d_stop_hc(struct usb_bus *host) { @@ -277,6 +278,7 @@ void pxa3xx_u2d_stop_hc(struct usb_bus *host) clk_disable(u2d->clk); } +EXPORT_SYMBOL_GPL(pxa3xx_u2d_stop_hc); static int pxa3xx_u2d_probe(struct platform_device *pdev) { diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f940a13..0737c59 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -393,7 +393,7 @@ void __init pxa3xx_init_irq(void) static struct map_desc pxa3xx_io_desc[] __initdata = { { /* Mem Ctl */ - .virtual = SMEMC_VIRT, + .virtual = (unsigned long)SMEMC_VIRT, .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), .length = 0x00200000, .type = MT_DEVICE diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 602d70b..fc2c1e0 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -540,7 +540,7 @@ static struct mtd_partition saar_onenand_partitions[] = { }, { .name = "filesystem", .offset = MTDPART_OFS_APPEND, - .size = SZ_48M, + .size = SZ_32M + SZ_16M, .mask_flags = 0, } }; diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c index 3c988b6f..3e999e3 100644 --- a/arch/arm/mach-pxa/saarb.c +++ b/arch/arm/mach-pxa/saarb.c @@ -24,6 +24,7 @@ #include <mach/hardware.h> #include <mach/mfp.h> #include <mach/mfp-pxa930.h> +#include <mach/pxa95x.h> #include "generic.h" diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 438c7b5..d8dec91 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -970,8 +970,8 @@ static void __init spitz_init(void) spitz_i2c_init(); } -static void __init spitz_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) +static void __init spitz_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { sharpsl_save_param(); mi->nr_banks = 1; diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 9f69a26..402b0c9 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -960,8 +960,8 @@ static void __init tosa_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); } -static void __init fixup_tosa(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) +static void __init fixup_tosa(struct tag *tags, char **cmdline, + struct meminfo *mi) { sharpsl_save_param(); mi->nr_banks=1; diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index 54930cc..70e1730 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c @@ -142,8 +142,7 @@ static struct platform_device *devices[] __initdata = { /* We have to state that there are HWMON devices on the I2C bus on XCEP. * Drivers for HWMON verify capabilities of the adapter when loading and - * refuse to attach if the adapter doesn't support HWMON class of devices. - * See also Documentation/i2c/porting-clients. */ + * refuse to attach if the adapter doesn't support HWMON class of devices. */ static struct i2c_pxa_platform_data xcep_i2c_platform_data = { .class = I2C_CLASS_HWMON }; diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index 84ed72d..ead32c9 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -686,7 +686,8 @@ static void z2_power_off(void) */ PSPR = 0x0; local_irq_disable(); - pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PHYS_OFFSET - PAGE_OFFSET); + pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP); + pxa27x_cpu_pm_enter(PM_SUSPEND_MEM); } #else #define z2_power_off NULL diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index c424e7d..498b83b 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -860,25 +860,25 @@ static void __init zeus_init(void) static struct map_desc zeus_io_desc[] __initdata = { { - .virtual = ZEUS_CPLD_VERSION, + .virtual = (unsigned long)ZEUS_CPLD_VERSION, .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS), .length = 0x1000, .type = MT_DEVICE, }, { - .virtual = ZEUS_CPLD_ISA_IRQ, + .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ, .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS), .length = 0x1000, .type = MT_DEVICE, }, { - .virtual = ZEUS_CPLD_CONTROL, + .virtual = (unsigned long)ZEUS_CPLD_CONTROL, .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS), .length = 0x1000, .type = MT_DEVICE, }, { - .virtual = ZEUS_PC104IO, + .virtual = (unsigned long)ZEUS_PC104IO, .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS), .length = 0x00800000, .type = MT_DEVICE, diff --git a/arch/arm/mach-realview/Makefile.boot b/arch/arm/mach-realview/Makefile.boot index d97e003..d2c3d78 100644 --- a/arch/arm/mach-realview/Makefile.boot +++ b/arch/arm/mach-realview/Makefile.boot @@ -1,9 +1,9 @@ ifeq ($(CONFIG_REALVIEW_HIGH_PHYS_OFFSET),y) - zreladdr-y := 0x70008000 + zreladdr-y += 0x70008000 params_phys-y := 0x70000100 initrd_phys-y := 0x70800000 else - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 endif diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 5c23450..d5ed5d4 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -517,8 +517,7 @@ void __init realview_timer_init(unsigned int timer_irq) /* * Setup the memory banks. */ -void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from, - struct meminfo *meminfo) +void realview_fixup(struct tag *tags, char **from, struct meminfo *meminfo) { /* * Most RealView platforms have 512MB contiguous RAM at 0x70000000. diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 5c83d1e..47259c8 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -63,8 +63,8 @@ extern int realview_flash_register(struct resource *res, u32 num); extern int realview_eth_register(const char *name, struct resource *res); extern int realview_usb_register(struct resource *res); extern void realview_init_early(void); -extern void realview_fixup(struct machine_desc *mdesc, struct tag *tags, - char **from, struct meminfo *meminfo); +extern void realview_fixup(struct tag *tags, char **from, + struct meminfo *meminfo); extern void (*realview_reset)(char); #endif diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h index 002ab5d..2a15fef 100644 --- a/arch/arm/mach-realview/include/mach/board-pb1176.h +++ b/arch/arm/mach-realview/include/mach/board-pb1176.h @@ -70,6 +70,7 @@ #define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */ #define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */ +#define REALVIEW_DC1176_ROM_BASE 0x10200000 /* 16KiB NRAM preudo-ROM, on devchip */ #define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */ #define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */ #define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */ diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 7263dea..c057540 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -26,6 +26,8 @@ #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/partitions.h> #include <linux/io.h> #include <mach/hardware.h> @@ -204,22 +206,48 @@ static struct amba_device *amba_devs[] __initdata = { * RealView PB1176 platform devices */ static struct resource realview_pb1176_flash_resources[] = { - [0] = { + { .start = REALVIEW_PB1176_FLASH_BASE, .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1, .flags = IORESOURCE_MEM, }, - [1] = { +#ifdef CONFIG_REALVIEW_PB1176_SECURE_FLASH + { .start = REALVIEW_PB1176_SEC_FLASH_BASE, .end = REALVIEW_PB1176_SEC_FLASH_BASE + REALVIEW_PB1176_SEC_FLASH_SIZE - 1, .flags = IORESOURCE_MEM, }, -}; -#ifdef CONFIG_REALVIEW_PB1176_SECURE_FLASH -#define PB1176_FLASH_BLOCKS 2 -#else -#define PB1176_FLASH_BLOCKS 1 #endif +}; + +static struct physmap_flash_data pb1176_rom_pdata = { + .probe_type = "map_rom", + .width = 4, + .nr_parts = 0, +}; + +static struct resource pb1176_rom_resources[] = { + /* + * This exposes the PB1176 DevChip ROM as an MTD ROM mapping. + * The reference manual states that this is actually a pseudo-ROM + * programmed in NVRAM. + */ + { + .start = REALVIEW_DC1176_ROM_BASE, + .end = REALVIEW_DC1176_ROM_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device pb1176_rom_device = { + .name = "physmap-flash", + .id = -1, + .num_resources = ARRAY_SIZE(pb1176_rom_resources), + .resource = pb1176_rom_resources, + .dev = { + .platform_data = &pb1176_rom_pdata, + }, +}; static struct resource realview_pb1176_smsc911x_resources[] = { [0] = { @@ -316,8 +344,7 @@ static void realview_pb1176_reset(char mode) __raw_writel(REALVIEW_PB1176_SYS_SOFT_RESET, reset_ctrl); } -static void realview_pb1176_fixup(struct machine_desc *mdesc, - struct tag *tags, char **from, +static void realview_pb1176_fixup(struct tag *tags, char **from, struct meminfo *meminfo) { /* @@ -338,7 +365,8 @@ static void __init realview_pb1176_init(void) #endif realview_flash_register(realview_pb1176_flash_resources, - PB1176_FLASH_BLOCKS); + ARRAY_SIZE(realview_pb1176_flash_resources)); + platform_device_register(&pb1176_rom_device); realview_eth_register(NULL, realview_pb1176_smsc911x_resources); platform_device_register(&realview_i2c_device); realview_usb_register(realview_pb1176_isp1761_resources); diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 8ec7e52..63c4114 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -319,8 +319,8 @@ static struct sys_timer realview_pbx_timer = { .init = realview_pbx_timer_init, }; -static void realview_pbx_fixup(struct machine_desc *mdesc, struct tag *tags, - char **from, struct meminfo *meminfo) +static void realview_pbx_fixup(struct tag *tags, char **from, + struct meminfo *meminfo) { #ifdef CONFIG_SPARSEMEM /* @@ -335,7 +335,7 @@ static void realview_pbx_fixup(struct machine_desc *mdesc, struct tag *tags, meminfo->bank[2].size = SZ_256M; meminfo->nr_banks = 3; #else - realview_fixup(mdesc, tags, from, meminfo); + realview_fixup(tags, from, meminfo); #endif } diff --git a/arch/arm/mach-rpc/Makefile.boot b/arch/arm/mach-rpc/Makefile.boot index 9c9e7685..ae2df0d 100644 --- a/arch/arm/mach-rpc/Makefile.boot +++ b/arch/arm/mach-rpc/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x10008000 + zreladdr-y += 0x10008000 params_phys-y := 0x10000100 initrd_phys-y := 0x18000000 diff --git a/arch/arm/mach-rpc/include/mach/hardware.h b/arch/arm/mach-rpc/include/mach/hardware.h index dde6b3c..050d63c 100644 --- a/arch/arm/mach-rpc/include/mach/hardware.h +++ b/arch/arm/mach-rpc/include/mach/hardware.h @@ -36,7 +36,7 @@ #define EASI_SIZE 0x08000000 /* EASI I/O */ #define EASI_START 0x08000000 -#define EASI_BASE 0xe5000000 +#define EASI_BASE IOMEM(0xe5000000) #define IO_START 0x03000000 /* I/O */ #define IO_SIZE 0x01000000 @@ -51,21 +51,20 @@ /* * IO Addresses */ -#define VIDC_BASE IOMEM(0xe0400000) -#define EXPMASK_BASE 0xe0360000 -#define IOMD_BASE IOMEM(0xe0200000) -#define IOC_BASE IOMEM(0xe0200000) -#define PCIO_BASE IOMEM(0xe0010000) -#define FLOPPYDMA_BASE IOMEM(0xe002a000) +#define ECARD_EASI_BASE (EASI_BASE) +#define VIDC_BASE (IO_BASE + 0x00400000) +#define EXPMASK_BASE (IO_BASE + 0x00360000) +#define ECARD_IOC4_BASE (IO_BASE + 0x00270000) +#define ECARD_IOC_BASE (IO_BASE + 0x00240000) +#define IOMD_BASE (IO_BASE + 0x00200000) +#define IOC_BASE (IO_BASE + 0x00200000) +#define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000) +#define FLOPPYDMA_BASE (IO_BASE + 0x0002a000) +#define PCIO_BASE (IO_BASE + 0x00010000) +#define ECARD_MEMC_BASE (IO_BASE + 0x00000000) #define vidc_writel(val) __raw_writel(val, VIDC_BASE) -#define IO_EC_EASI_BASE 0x81400000 -#define IO_EC_IOC4_BASE 0x8009c000 -#define IO_EC_IOC_BASE 0x80090000 -#define IO_EC_MEMC8_BASE 0x8000ac00 -#define IO_EC_MEMC_BASE 0x80000000 - #define NETSLOT_BASE 0x0302b000 #define NETSLOT_SIZE 0x00001000 diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h index 20da7f4..695f4ed 100644 --- a/arch/arm/mach-rpc/include/mach/io.h +++ b/arch/arm/mach-rpc/include/mach/io.h @@ -15,195 +15,18 @@ #include <mach/hardware.h> -#define IO_SPACE_LIMIT 0xffffffff +#define IO_SPACE_LIMIT 0xffff /* - * We use two different types of addressing - PC style addresses, and ARM - * addresses. PC style accesses the PC hardware with the normal PC IO - * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ - * and are translated to the start of IO. Note that all addresses are - * shifted left! - */ -#define __PORT_PCIO(x) (!((x) & 0x80000000)) - -/* - * Dynamic IO functions. - */ -static inline void __outb (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "strb %1, [%0, %2, lsl #2] @ outb" - : "=&r" (temp) - : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -static inline void __outw (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "str %1, [%0, %2, lsl #2] @ outw" - : "=&r" (temp) - : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -static inline void __outl (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "str %1, [%0, %2, lsl #2] @ outl" - : "=&r" (temp) - : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -#define DECLARE_DYN_IN(sz,fnsuffix,instr) \ -static inline unsigned sz __in##fnsuffix (unsigned int port) \ -{ \ - unsigned long temp, value; \ - __asm__ __volatile__( \ - "tst %2, #0x80000000\n\t" \ - "mov %0, %4\n\t" \ - "addeq %0, %0, %3\n\t" \ - "ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \ - : "=&r" (temp), "=r" (value) \ - : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ - : "cc"); \ - return (unsigned sz)value; \ -} - -static inline void __iomem *__deprecated __ioaddr(unsigned int port) -{ - void __iomem *ret; - if (__PORT_PCIO(port)) - ret = PCIO_BASE; - else - ret = IO_BASE; - return ret + (port << 2); -} - -#define DECLARE_IO(sz,fnsuffix,instr) \ - DECLARE_DYN_IN(sz,fnsuffix,instr) - -DECLARE_IO(char,b,"b") -DECLARE_IO(short,w,"") -DECLARE_IO(int,l,"") - -#undef DECLARE_IO -#undef DECLARE_DYN_IN - -/* - * Constant address IO functions + * We need PC style IO addressing for: + * - floppy (at 0x3f2,0x3f4,0x3f5,0x3f7) + * - parport (at 0x278-0x27a, 0x27b-0x27f, 0x778-0x77a) + * - 8250 serial (only for compile) * - * These have to be macros for the 'J' constraint to work - - * +/-4096 immediate operand. + * These peripherals are found in an area of MMIO which looks very much + * like an ISA bus, but with registers at the low byte of each word. */ -#define __outbc(value,port) \ -({ \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inbc(port) \ -({ \ - unsigned char result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result; \ -}) - -#define __outwc(value,port) \ -({ \ - unsigned long __v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outwc" \ - : : "r" (__v|__v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outwc" \ - : : "r" (__v|__v<<16), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inwc(port) \ -({ \ - unsigned short result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inwc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inwc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result & 0xffff; \ -}) - -#define __outlc(value,port) \ -({ \ - unsigned long __v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (__v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (__v), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inlc(port) \ -({ \ - unsigned long result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result; \ -}) - -#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) -#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) -#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) -#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) -#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) -#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) - -/* the following macro is deprecated */ -#define ioaddr(port) ((unsigned long)__ioaddr((port))) - -#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) -#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) - -#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) -#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) +#define __io(a) (PCIO_BASE + ((a) << 2)) /* * 1:1 mapping for ioremapped regions. diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c index a9241eb..8559598 100644 --- a/arch/arm/mach-rpc/riscpc.c +++ b/arch/arm/mach-rpc/riscpc.c @@ -74,7 +74,7 @@ static struct map_desc rpc_io_desc[] __initdata = { .length = IO_SIZE , .type = MT_DEVICE }, { /* EASI space */ - .virtual = EASI_BASE, + .virtual = (unsigned long)EASI_BASE, .pfn = __phys_to_pfn(EASI_START), .length = EASI_SIZE, .type = MT_DEVICE diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 7245a55..3700cf3 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -8,7 +8,6 @@ config CPU_S3C2410 select CPU_ARM920T select S3C_GPIO_PULL_UP select S3C2410_CLOCK - select S3C2410_GPIO select CPU_LLSERIAL_S3C2410 select S3C2410_PM if PM select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX @@ -28,11 +27,6 @@ config S3C2410_PM help Power Management code common to S3C2410 and better -config S3C2410_GPIO - bool - help - GPIO code for S3C2410 and similar processors - config SIMTEC_NOR bool help diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 8169535..782fd81 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_CPU_S3C2410) += s3c2410.o obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o -obj-$(CONFIG_S3C2410_GPIO) += gpio.o obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c2410/Makefile.boot index 58c1dd7..4457605 100644 --- a/arch/arm/mach-s3c2410/Makefile.boot +++ b/arch/arm/mach-s3c2410/Makefile.boot @@ -1,7 +1,7 @@ ifeq ($(CONFIG_PM_H1940),y) - zreladdr-y := 0x30108000 + zreladdr-y += 0x30108000 params_phys-y := 0x30100100 else - zreladdr-y := 0x30008000 + zreladdr-y += 0x30008000 params_phys-y := 0x30000100 endif diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 0d8e043..dbe43df 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_SPI0] = { .name = "spi0", .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, }, [DMACH_SPI1] = { .name = "spi1", .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, }, [DMACH_UART0] = { .name = "uart0", .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, }, [DMACH_UART1] = { .name = "uart1", .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, }, [DMACH_UART2] = { .name = "uart2", .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, }, [DMACH_TIMER] = { .name = "timer", @@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { .name = "i2s-sdi", .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_I2S_OUT] = { .name = "i2s-sdo", .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_USB_EP1] = { .name = "usb-ep1", diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c deleted file mode 100644 index 9664e01..0000000 --- a/arch/arm/mach-s3c2410/gpio.c +++ /dev/null @@ -1,72 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/gpio.c - * - * Copyright (c) 2004-2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 GPIO support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/gpio-fns.h> -#include <asm/irq.h> - -#include <mach/regs-gpio.h> - -int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, - unsigned int config) -{ - void __iomem *reg = S3C24XX_EINFLT0; - unsigned long flags; - unsigned long val; - - if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15)) - return -EINVAL; - - config &= 0xff; - - pin -= S3C2410_GPG(8); - reg += pin & ~3; - - local_irq_save(flags); - - /* update filter width and clock source */ - - val = __raw_readl(reg); - val &= ~(0xff << ((pin & 3) * 8)); - val |= config << ((pin & 3) * 8); - __raw_writel(val, reg); - - /* update filter enable */ - - val = __raw_readl(S3C24XX_EXTINT2); - val &= ~(1 << ((pin * 4) + 3)); - val |= on << ((pin * 4) + 3); - __raw_writel(val, S3C24XX_EXTINT2); - - local_irq_restore(flags); - - return 0; -} - -EXPORT_SYMBOL(s3c2410_gpio_irqfilter); diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h index 9813dbf..118749f 100644 --- a/arch/arm/mach-s3c2410/include/mach/io.h +++ b/arch/arm/mach-s3c2410/include/mach/io.h @@ -199,8 +199,6 @@ DECLARE_IO(int,l,"") #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) #define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) -/* the following macro is deprecated */ -#define ioaddr(port) __ioaddr((port)) #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 425552d..4cf495f 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -14,9 +14,53 @@ #define __ASM_ARCH_MAP_H #include <plat/map-base.h> -#include <plat/map.h> -#define S3C2410_ADDR(x) S3C_ADDR(x) +/* + * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400. + * So need to define it, and here is to avoid redefinition warning. + */ +#define S3C_UART_OFFSET (0x4000) + +#include <plat/map-s3c.h> + +/* + * interrupt controller is the first thing we put in, to make + * the assembly code for the irq detection easier + */ +#define S3C2410_PA_IRQ (0x4A000000) +#define S3C24XX_SZ_IRQ SZ_1M + +/* memory controller registers */ +#define S3C2410_PA_MEMCTRL (0x48000000) +#define S3C24XX_SZ_MEMCTRL SZ_1M + +/* UARTs */ +#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) + +/* Timers */ +#define S3C2410_PA_TIMER (0x51000000) +#define S3C24XX_SZ_TIMER SZ_1M + +/* Clock and Power management */ +#define S3C24XX_SZ_CLKPWR SZ_1M + +/* USB Device port */ +#define S3C2410_PA_USBDEV (0x52000000) +#define S3C24XX_SZ_USBDEV SZ_1M + +/* Watchdog */ +#define S3C2410_PA_WATCHDOG (0x53000000) +#define S3C24XX_SZ_WATCHDOG SZ_1M + +/* Standard size definitions for peripheral blocks. */ + +#define S3C24XX_SZ_UART SZ_1M +#define S3C24XX_SZ_IIS SZ_1M +#define S3C24XX_SZ_ADC SZ_1M +#define S3C24XX_SZ_SPI SZ_1M +#define S3C24XX_SZ_SDI SZ_1M +#define S3C24XX_SZ_NAND SZ_1M +#define S3C24XX_SZ_GPIO SZ_1M /* USB host controller */ #define S3C2410_PA_USBHOST (0x49000000) @@ -75,10 +119,8 @@ /* S3C2412 memory and IO controls */ #define S3C2412_PA_SSMC (0x4F000000) -#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) #define S3C2412_PA_EBI (0x48800000) -#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000) /* physical addresses of all the chip-select areas */ @@ -100,12 +142,10 @@ #define S3C24XX_PA_DMA S3C2410_PA_DMA #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR #define S3C24XX_PA_LCD S3C2410_PA_LCD -#define S3C24XX_PA_UART S3C2410_PA_UART #define S3C24XX_PA_TIMER S3C2410_PA_TIMER #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG #define S3C24XX_PA_IIS S3C2410_PA_IIS -#define S3C24XX_PA_GPIO S3C2410_PA_GPIO #define S3C24XX_PA_RTC S3C2410_PA_RTC #define S3C24XX_PA_ADC S3C2410_PA_ADC #define S3C24XX_PA_SPI S3C2410_PA_SPI diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index f1d3bd8..343a540 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -170,7 +170,9 @@ int __init s3c2410_init(void) { printk("S3C2410: Initialising architecture\n"); +#ifdef CONFIG_PM register_syscore_ops(&s3c2410_pm_syscore_ops); +#endif register_syscore_ops(&s3c24xx_irq_syscore_ops); return sysdev_register(&s3c2410_sysdev); diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index c2cf4e5..b8b9029 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig @@ -9,7 +9,6 @@ config CPU_S3C2412 select CPU_LLSERIAL_S3C2440 select S3C2412_PM if PM select S3C2412_DMA if S3C2410_DMA - select S3C2410_GPIO help Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile index 6c48a91..7e4d95f 100644 --- a/arch/arm/mach-s3c2412/Makefile +++ b/arch/arm/mach-s3c2412/Makefile @@ -12,7 +12,6 @@ obj- := obj-$(CONFIG_CPU_S3C2412) += s3c2412.o obj-$(CONFIG_CPU_S3C2412) += irq.o obj-$(CONFIG_CPU_S3C2412) += clock.o -obj-$(CONFIG_CPU_S3C2412) += gpio.o obj-$(CONFIG_S3C2412_DMA) += dma.o obj-$(CONFIG_S3C2412_PM) += pm.o obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index 7abecfc..c61e326 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { .name = "sdi", .channels = MAP(S3C2412_DMAREQSEL_SDI), .channels_rx = MAP(S3C2412_DMAREQSEL_SDI), - .hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA, - .hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA, }, [DMACH_SPI0] = { .name = "spi0", .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX), - .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, }, [DMACH_SPI1] = { .name = "spi1", .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX), - .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT, }, [DMACH_UART0] = { .name = "uart0", .channels = MAP(S3C2412_DMAREQSEL_UART0_0), .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0), - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, }, [DMACH_UART1] = { .name = "uart1", .channels = MAP(S3C2412_DMAREQSEL_UART1_0), .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0), - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, }, [DMACH_UART2] = { .name = "uart2", .channels = MAP(S3C2412_DMAREQSEL_UART2_0), .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0), - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, }, [DMACH_UART0_SRC2] = { .name = "uart0", .channels = MAP(S3C2412_DMAREQSEL_UART0_1), .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1), - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, }, [DMACH_UART1_SRC2] = { .name = "uart1", .channels = MAP(S3C2412_DMAREQSEL_UART1_1), .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1), - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, }, [DMACH_UART2_SRC2] = { .name = "uart2", .channels = MAP(S3C2412_DMAREQSEL_UART2_1), .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1), - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, }, [DMACH_TIMER] = { .name = "timer", diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c deleted file mode 100644 index 3404a87..0000000 --- a/arch/arm/mach-s3c2412/gpio.c +++ /dev/null @@ -1,62 +0,0 @@ -/* linux/arch/arm/mach-s3c2412/gpio.c - * - * Copyright (c) 2007 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://armlinux.simtec.co.uk/. - * - * S3C2412/S3C2413 specific GPIO support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/gpio.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/regs-gpio.h> -#include <mach/hardware.h> - -#include <plat/gpio-core.h> - -int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned long offs = pin - chip->chip.base; - unsigned long flags; - unsigned long slpcon; - - offs *= 2; - - if (pin < S3C2410_GPB(0)) - return -EINVAL; - - if (pin >= S3C2410_GPF(0) && - pin <= S3C2410_GPG(16)) - return -EINVAL; - - if (pin > S3C2410_GPH(16)) - return -EINVAL; - - local_irq_save(flags); - - slpcon = __raw_readl(chip->base + 0x0C); - - slpcon &= ~(3 << offs); - slpcon |= state << offs; - - __raw_writel(slpcon, chip->base + 0x0C); - - local_irq_restore(flags); - - return 0; -} - -EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg); diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index d6325ede..f1eec1b 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -92,8 +92,7 @@ static struct platform_device *smdk2413_devices[] __initdata = { &s3c_device_usbgadget, }; -static void __init smdk2413_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, +static void __init smdk2413_fixup(struct tag *tags, char **cmdline, struct meminfo *mi) { if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) { diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index 5955c15..1bbb1ef 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c @@ -129,9 +129,8 @@ static struct platform_device *vstms_devices[] __initdata = { &s3c_device_nand, }; -static void __init vstms_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, - struct meminfo *mi) +static void __init vstms_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) { mi->nr_banks=1; diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index ef0958d..57a1e01 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -245,7 +245,9 @@ int __init s3c2412_init(void) { printk("S3C2412: Initialising architecture\n"); +#ifdef CONFIG_PM register_syscore_ops(&s3c2412_pm_syscore_ops); +#endif register_syscore_ops(&s3c24xx_irq_syscore_ops); return sysdev_register(&s3c2412_sysdev); diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index 494ce91..20b3fdf 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -97,7 +97,9 @@ int __init s3c2416_init(void) s3c_fb_setname("s3c2443-fb"); +#ifdef CONFIG_PM register_syscore_ops(&s3c2416_pm_syscore_ops); +#endif register_syscore_ops(&s3c24xx_irq_syscore_ops); return sysdev_register(&s3c2416_sysdev); diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 50825a3..c461fb8 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -8,7 +8,6 @@ config CPU_S3C2440 select S3C_GPIO_PULL_UP select S3C2410_CLOCK select S3C2410_PM if PM - select S3C2410_GPIO select S3C2440_DMA if S3C2410_DMA select CPU_S3C244X select CPU_LLSERIAL_S3C2440 @@ -20,7 +19,6 @@ config CPU_S3C2442 select CPU_ARM920T select S3C_GPIO_PULL_DOWN select S3C2410_CLOCK - select S3C2410_GPIO select S3C2410_PM if PM select CPU_S3C244X select CPU_LLSERIAL_S3C2440 diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index 3b0529f..0e73f8f 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c @@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_SPI0] = { .name = "spi0", .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, }, [DMACH_SPI1] = { .name = "spi1", .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, }, [DMACH_UART0] = { .name = "uart0", .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, }, [DMACH_UART1] = { .name = "uart1", .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, }, [DMACH_UART2] = { .name = "uart2", .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, }, [DMACH_TIMER] = { .name = "timer", @@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { .name = "i2s-sdi", .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_I2S_OUT] = { .name = "i2s-sdo", .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID, .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_PCM_IN] = { .name = "pcm-in", .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID, .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID, - .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, }, [DMACH_PCM_OUT] = { .name = "pcm-out", .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID, .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID, - .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, }, [DMACH_MIC_IN] = { .name = "mic-in", .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID, .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID, - .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA, }, [DMACH_USB_EP1] = { .name = "usb-ep1", diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c index ce99ff7..2270d33 100644 --- a/arch/arm/mach-s3c2440/s3c2440.c +++ b/arch/arm/mach-s3c2440/s3c2440.c @@ -55,7 +55,9 @@ int __init s3c2440_init(void) /* register suspend/resume handlers */ +#ifdef CONFIG_PM register_syscore_ops(&s3c2410_pm_syscore_ops); +#endif register_syscore_ops(&s3c244x_pm_syscore_ops); register_syscore_ops(&s3c24xx_irq_syscore_ops); diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c index 9ad99f8..6f2b65e 100644 --- a/arch/arm/mach-s3c2440/s3c2442.c +++ b/arch/arm/mach-s3c2440/s3c2442.c @@ -169,7 +169,9 @@ int __init s3c2442_init(void) { printk("S3C2442: Initialising architecture\n"); +#ifdef CONFIG_PM register_syscore_ops(&s3c2410_pm_syscore_ops); +#endif register_syscore_ops(&s3c244x_pm_syscore_ops); register_syscore_ops(&s3c24xx_irq_syscore_ops); diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index 3f65868..fe52151 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c @@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = { [DMACH_SDI] = { .name = "sdi", .channels = MAP(S3C2443_DMAREQSEL_SDI), - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_SPI0] = { .name = "spi0", .channels = MAP(S3C2443_DMAREQSEL_SPI0TX), - .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, }, [DMACH_SPI1] = { .name = "spi1", .channels = MAP(S3C2443_DMAREQSEL_SPI1TX), - .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, }, [DMACH_UART0] = { .name = "uart0", .channels = MAP(S3C2443_DMAREQSEL_UART0_0), - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, }, [DMACH_UART1] = { .name = "uart1", .channels = MAP(S3C2443_DMAREQSEL_UART1_0), - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, }, [DMACH_UART2] = { .name = "uart2", .channels = MAP(S3C2443_DMAREQSEL_UART2_0), - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, }, [DMACH_UART3] = { .name = "uart3", .channels = MAP(S3C2443_DMAREQSEL_UART3_0), - .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH, - .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH, }, [DMACH_UART0_SRC2] = { .name = "uart0", .channels = MAP(S3C2443_DMAREQSEL_UART0_1), - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, }, [DMACH_UART1_SRC2] = { .name = "uart1", .channels = MAP(S3C2443_DMAREQSEL_UART1_1), - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, }, [DMACH_UART2_SRC2] = { .name = "uart2", .channels = MAP(S3C2443_DMAREQSEL_UART2_1), - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, }, [DMACH_UART3_SRC2] = { .name = "uart3", .channels = MAP(S3C2443_DMAREQSEL_UART3_1), - .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH, - .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH, }, [DMACH_TIMER] = { .name = "timer", @@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = { [DMACH_I2S_IN] = { .name = "i2s-sdi", .channels = MAP(S3C2443_DMAREQSEL_I2SRX), - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_I2S_OUT] = { .name = "i2s-sdo", .channels = MAP(S3C2443_DMAREQSEL_I2STX), - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, }, [DMACH_PCM_IN] = { .name = "pcm-in", .channels = MAP(S3C2443_DMAREQSEL_PCMIN), - .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, }, [DMACH_PCM_OUT] = { .name = "pcm-out", .channels = MAP(S3C2443_DMAREQSEL_PCMOUT), - .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, }, [DMACH_MIC_IN] = { .name = "mic-in", .channels = MAP(S3C2443_DMAREQSEL_MICIN), - .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA, }, }; diff --git a/arch/arm/mach-s3c64xx/Makefile.boot b/arch/arm/mach-s3c64xx/Makefile.boot index ba41fdc..c642333 100644 --- a/arch/arm/mach-s3c64xx/Makefile.boot +++ b/arch/arm/mach-s3c64xx/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x50008000 + zreladdr-y += 0x50008000 params_phys-y := 0x50000100 diff --git a/arch/arm/mach-s3c64xx/dev-uart.c b/arch/arm/mach-s3c64xx/dev-uart.c index f797f74..c681b99 100644 --- a/arch/arm/mach-s3c64xx/dev-uart.c +++ b/arch/arm/mach-s3c64xx/dev-uart.c @@ -37,21 +37,10 @@ static struct resource s3c64xx_uart0_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S3CUART_RX0, - .end = IRQ_S3CUART_RX0, + .start = IRQ_UART0, + .end = IRQ_UART0, .flags = IORESOURCE_IRQ, }, - [2] = { - .start = IRQ_S3CUART_TX0, - .end = IRQ_S3CUART_TX0, - .flags = IORESOURCE_IRQ, - - }, - [3] = { - .start = IRQ_S3CUART_ERR0, - .end = IRQ_S3CUART_ERR0, - .flags = IORESOURCE_IRQ, - } }; static struct resource s3c64xx_uart1_resource[] = { @@ -61,19 +50,8 @@ static struct resource s3c64xx_uart1_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S3CUART_RX1, - .end = IRQ_S3CUART_RX1, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S3CUART_TX1, - .end = IRQ_S3CUART_TX1, - .flags = IORESOURCE_IRQ, - - }, - [3] = { - .start = IRQ_S3CUART_ERR1, - .end = IRQ_S3CUART_ERR1, + .start = IRQ_UART1, + .end = IRQ_UART1, .flags = IORESOURCE_IRQ, }, }; @@ -85,19 +63,8 @@ static struct resource s3c6xx_uart2_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S3CUART_RX2, - .end = IRQ_S3CUART_RX2, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S3CUART_TX2, - .end = IRQ_S3CUART_TX2, - .flags = IORESOURCE_IRQ, - - }, - [3] = { - .start = IRQ_S3CUART_ERR2, - .end = IRQ_S3CUART_ERR2, + .start = IRQ_UART2, + .end = IRQ_UART2, .flags = IORESOURCE_IRQ, }, }; @@ -109,19 +76,8 @@ static struct resource s3c64xx_uart3_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S3CUART_RX3, - .end = IRQ_S3CUART_RX3, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S3CUART_TX3, - .end = IRQ_S3CUART_TX3, - .flags = IORESOURCE_IRQ, - - }, - [3] = { - .start = IRQ_S3CUART_ERR3, - .end = IRQ_S3CUART_ERR3, + .start = IRQ_UART3, + .end = IRQ_UART3, .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index c026f67..443f85b 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -27,36 +27,6 @@ #define IRQ_VIC0_BASE S3C_IRQ(0) #define IRQ_VIC1_BASE S3C_IRQ(32) -/* UART interrupts, each UART has 4 intterupts per channel so - * use the space between the ISA and S3C main interrupts. Note, these - * are not in the same order as the S3C24XX series! */ - -#define IRQ_S3CUART_BASE0 (16) -#define IRQ_S3CUART_BASE1 (20) -#define IRQ_S3CUART_BASE2 (24) -#define IRQ_S3CUART_BASE3 (28) - -#define UART_IRQ_RXD (0) -#define UART_IRQ_ERR (1) -#define UART_IRQ_TXD (2) -#define UART_IRQ_MODEM (3) - -#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) - -#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) -#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) -#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) - /* VIC based IRQs */ #define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index a1f13f0..23a1d71 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h @@ -16,6 +16,7 @@ #define __ASM_ARCH_MAP_H __FILE__ #include <plat/map-base.h> +#include <plat/map-s3c.h> /* * Post-mux Chip Select Regions Xm0CSn_ @@ -83,7 +84,6 @@ #define S3C64XX_PA_IIC1 (0x7F00F000) #define S3C64XX_PA_GPIO (0x7F008000) -#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000) #define S3C64XX_SZ_GPIO SZ_4K #define S3C64XX_PA_SDRAM (0x50000000) @@ -94,16 +94,10 @@ #define S3C64XX_PA_VIC1 (0x71300000) #define S3C64XX_PA_MODEM (0x74108000) -#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000) #define S3C64XX_PA_USBHOST (0x74300000) #define S3C64XX_PA_USB_HSPHY (0x7C100000) -#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) - -/* place VICs close together */ -#define VA_VIC0 (S3C_VA_IRQ + 0x00) -#define VA_VIC1 (S3C_VA_IRQ + 0x10000) /* compatibiltiy defines. */ #define S3C_PA_TIMER S3C64XX_PA_TIMER @@ -119,7 +113,6 @@ #define S3C_PA_FB S3C64XX_PA_FB #define S3C_PA_USBHOST S3C64XX_PA_USBHOST #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG -#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY #define S3C_PA_RTC S3C64XX_PA_RTC #define S3C_PA_WDT S3C64XX_PA_WATCHDOG diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c index 75d9a0e..b07357e 100644 --- a/arch/arm/mach-s3c64xx/irq.c +++ b/arch/arm/mach-s3c64xx/irq.c @@ -25,29 +25,6 @@ #include <plat/irq-uart.h> #include <plat/cpu.h> -static struct s3c_uart_irq uart_irqs[] = { - [0] = { - .regs = S3C_VA_UART0, - .base_irq = IRQ_S3CUART_BASE0, - .parent_irq = IRQ_UART0, - }, - [1] = { - .regs = S3C_VA_UART1, - .base_irq = IRQ_S3CUART_BASE1, - .parent_irq = IRQ_UART1, - }, - [2] = { - .regs = S3C_VA_UART2, - .base_irq = IRQ_S3CUART_BASE2, - .parent_irq = IRQ_UART2, - }, - [3] = { - .regs = S3C_VA_UART3, - .base_irq = IRQ_S3CUART_BASE3, - .parent_irq = IRQ_UART3, - }, -}; - /* setup the sources the vic should advertise resume for, even though it * is not doing the wake (set_irq_wake needs to be valid) */ #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) @@ -67,6 +44,4 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) /* add the timer sub-irqs */ s3c_init_vic_timer_irq(5, IRQ_TIMER0); - - s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index 4c76e084..8065803 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -329,9 +329,6 @@ static struct platform_device *crag6410_devices[] __initdata = { &s3c_device_fb, &s3c_device_ohci, &s3c_device_usb_hsotg, - &s3c_device_adc, - &s3c_device_rtc, - &s3c_device_ts, &s3c_device_timer[0], &s3c64xx_device_iis0, &s3c64xx_device_iis1, diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index e91f63f..fb8969a 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -205,12 +205,6 @@ static struct platform_device mini6410_lcd_powerdev = { .dev.platform_data = &mini6410_lcd_power_data, }; -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, -}; - static struct platform_device *mini6410_devices[] __initdata = { &mini6410_device_eth, &s3c_device_hsmmc0, @@ -319,7 +313,7 @@ static void __init mini6410_machine_init(void) s3c_nand_set_platdata(&mini6410_nand_info); s3c_fb_set_platdata(&mini6410_lcd_pdata); - s3c24xx_ts_set_platdata(&s3c_ts_platform); + s3c24xx_ts_set_platdata(NULL); /* configure nCS1 width to 16 bits */ diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c index 10870cb..93170d4 100644 --- a/arch/arm/mach-s3c64xx/mach-real6410.c +++ b/arch/arm/mach-s3c64xx/mach-real6410.c @@ -198,12 +198,6 @@ static struct platform_device *real6410_devices[] __initdata = { &s3c_device_ohci, }; -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, -}; - static void __init real6410_map_io(void) { u32 tmp; @@ -300,7 +294,7 @@ static void __init real6410_machine_init(void) s3c_fb_set_platdata(&real6410_lcd_pdata); s3c_nand_set_platdata(&real6410_nand_info); - s3c24xx_ts_set_platdata(&s3c_ts_platform); + s3c24xx_ts_set_platdata(NULL); /* configure nCS1 width to 16 bits */ diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 7b66ede..5f147c3 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -619,12 +619,6 @@ static struct i2c_board_info i2c_devs1[] __initdata = { { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ }; -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, -}; - /* LCD Backlight data */ static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = { .no = S3C64XX_GPF(15), @@ -666,7 +660,7 @@ static void __init smdk6410_machine_init(void) samsung_keypad_set_platdata(&smdk6410_keypad_data); - s3c24xx_ts_set_platdata(&s3c_ts_platform); + s3c24xx_ts_set_platdata(NULL); /* configure nCS1 width to 16 bits */ diff --git a/arch/arm/mach-s5p64x0/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot index ff90aa1..79ece40 100644 --- a/arch/arm/mach-s5p64x0/Makefile.boot +++ b/arch/arm/mach-s5p64x0/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x20008000 + zreladdr-y += 0x20008000 params_phys-y := 0x20000100 diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 3b84e9b..88857f5 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -129,12 +129,6 @@ static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = { /* To be populated */ }; -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, -}; - /* LCD Backlight data */ static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = { .no = S5P6440_GPF(15), @@ -155,7 +149,7 @@ static void __init smdk6440_map_io(void) static void __init smdk6440_machine_init(void) { - s3c24xx_ts_set_platdata(&s3c_ts_platform); + s3c24xx_ts_set_platdata(NULL); s3c_i2c0_set_platdata(&s5p6440_i2c0_data); s3c_i2c1_set_platdata(&s5p6440_i2c1_data); diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index d99d29b..e1b277b 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -148,12 +148,6 @@ static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = { { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */ }; -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, -}; - /* LCD Backlight data */ static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = { .no = S5P6450_GPF(15), @@ -174,7 +168,7 @@ static void __init smdk6450_map_io(void) static void __init smdk6450_machine_init(void) { - s3c24xx_ts_set_platdata(&s3c_ts_platform); + s3c24xx_ts_set_platdata(NULL); s3c_i2c0_set_platdata(&s5p6450_i2c0_data); s3c_i2c1_set_platdata(&s5p6450_i2c1_data); diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot index ff90aa1..79ece40 100644 --- a/arch/arm/mach-s5pc100/Makefile.boot +++ b/arch/arm/mach-s5pc100/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x20008000 + zreladdr-y += 0x20008000 params_phys-y := 0x20000100 diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 688f45b..26f5c91 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -203,12 +203,6 @@ static struct platform_device *smdkc100_devices[] __initdata = { &s5pc100_device_spdif, }; -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, -}; - /* LCD Backlight data */ static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = { .no = S5PC100_GPD(0), @@ -228,7 +222,7 @@ static void __init smdkc100_map_io(void) static void __init smdkc100_machine_init(void) { - s3c24xx_ts_set_platdata(&s3c_ts_platform); + s3c24xx_ts_set_platdata(NULL); /* I2C */ s3c_i2c0_set_platdata(NULL); diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 69dd87c..aaeb44a 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -14,7 +14,6 @@ config CPU_S5PV210 select S3C_PL330_DMA select S5P_EXT_INT select S5P_HRT - select S5PV210_PM if PM help Enable S5PV210 CPU support @@ -169,9 +168,4 @@ config MACH_TORBRECK endmenu -config S5PV210_PM - bool - help - Power Management code common to S5PV210 - endif diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 599a3c0..ef7e466 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -14,7 +14,7 @@ obj- := obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o -obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o +obj-$(CONFIG_PM) += pm.o sleep.o # machine support diff --git a/arch/arm/mach-s5pv210/Makefile.boot b/arch/arm/mach-s5pv210/Makefile.boot index ff90aa1..79ece40 100644 --- a/arch/arm/mach-s5pv210/Makefile.boot +++ b/arch/arm/mach-s5pv210/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x20008000 + zreladdr-y += 0x20008000 params_phys-y := 0x20000100 diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index e73e3b6d..a9106c3 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -265,12 +265,6 @@ static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = { /* To Be Updated */ }; -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, -}; - /* LCD Backlight data */ static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = { .no = S5PV210_GPD0(3), @@ -296,7 +290,7 @@ static void __init smdkv210_machine_init(void) smdkv210_dm9000_init(); samsung_keypad_set_platdata(&smdkv210_keypad_data); - s3c24xx_ts_set_platdata(&s3c_ts_platform); + s3c24xx_ts_set_platdata(NULL); s3c_i2c0_set_platdata(NULL); s3c_i2c1_set_platdata(NULL); diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index 73a5c64..ed7408d 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile @@ -45,7 +45,6 @@ obj-$(CONFIG_SA1100_PLEB) += pleb.o obj-$(CONFIG_SA1100_SHANNON) += shannon.o obj-$(CONFIG_SA1100_SIMPAD) += simpad.o -led-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o # LEDs support obj-$(CONFIG_LEDS) += $(led-y) diff --git a/arch/arm/mach-sa1100/Makefile.boot b/arch/arm/mach-sa1100/Makefile.boot index a56ad04..5a616f6 100644 --- a/arch/arm/mach-sa1100/Makefile.boot +++ b/arch/arm/mach-sa1100/Makefile.boot @@ -1,6 +1,7 @@ - zreladdr-y := 0xc0008000 ifeq ($(CONFIG_ARCH_SA1100),y) - zreladdr-$(CONFIG_SA1111) := 0xc0208000 + zreladdr-$(CONFIG_SA1111) += 0xc0208000 +else + zreladdr-y += 0xc0008000 endif params_phys-y := 0xc0000100 initrd_phys-y := 0xc0800000 diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index d40da5f..3dd133f 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -301,8 +301,7 @@ static void __init get_assabet_scr(void) } static void __init -fixup_assabet(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) +fixup_assabet(struct tag *tags, char **cmdline, struct meminfo *mi) { /* This must be done before any call to machine_has_neponset() */ map_sa1100_gpio_regs(); diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h index d8b43f3..dfc27ff 100644 --- a/arch/arm/mach-sa1100/include/mach/io.h +++ b/arch/arm/mach-sa1100/include/mach/io.h @@ -10,11 +10,9 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#define IO_SPACE_LIMIT 0xffffffff - /* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... + * __io() is required to be an equivalent mapping to __mem_pci() for + * SOC_COMMON to work. */ #define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h index 9296c45..db28118 100644 --- a/arch/arm/mach-sa1100/include/mach/simpad.h +++ b/arch/arm/mach-sa1100/include/mach/simpad.h @@ -48,32 +48,80 @@ #define GPIO_SMART_CARD GPIO_GPIO10 #define IRQ_GPIO_SMARD_CARD IRQ_GPIO10 -// CS3 Latch is write only, a shadow is necessary +/*--- ucb1x00 GPIO ---*/ +#define SIMPAD_UCB1X00_GPIO_BASE (GPIO_MAX + 1) +#define SIMPAD_UCB1X00_GPIO_PROG1 (SIMPAD_UCB1X00_GPIO_BASE) +#define SIMPAD_UCB1X00_GPIO_PROG2 (SIMPAD_UCB1X00_GPIO_BASE + 1) +#define SIMPAD_UCB1X00_GPIO_UP (SIMPAD_UCB1X00_GPIO_BASE + 2) +#define SIMPAD_UCB1X00_GPIO_DOWN (SIMPAD_UCB1X00_GPIO_BASE + 3) +#define SIMPAD_UCB1X00_GPIO_LEFT (SIMPAD_UCB1X00_GPIO_BASE + 4) +#define SIMPAD_UCB1X00_GPIO_RIGHT (SIMPAD_UCB1X00_GPIO_BASE + 5) +#define SIMPAD_UCB1X00_GPIO_6 (SIMPAD_UCB1X00_GPIO_BASE + 6) +#define SIMPAD_UCB1X00_GPIO_7 (SIMPAD_UCB1X00_GPIO_BASE + 7) +#define SIMPAD_UCB1X00_GPIO_HEADSET (SIMPAD_UCB1X00_GPIO_BASE + 8) +#define SIMPAD_UCB1X00_GPIO_SPEAKER (SIMPAD_UCB1X00_GPIO_BASE + 9) + +/*--- CS3 Latch ---*/ +#define SIMPAD_CS3_GPIO_BASE (GPIO_MAX + 11) +#define SIMPAD_CS3_VCC_5V_EN (SIMPAD_CS3_GPIO_BASE) +#define SIMPAD_CS3_VCC_3V_EN (SIMPAD_CS3_GPIO_BASE + 1) +#define SIMPAD_CS3_EN1 (SIMPAD_CS3_GPIO_BASE + 2) +#define SIMPAD_CS3_EN0 (SIMPAD_CS3_GPIO_BASE + 3) +#define SIMPAD_CS3_DISPLAY_ON (SIMPAD_CS3_GPIO_BASE + 4) +#define SIMPAD_CS3_PCMCIA_BUFF_DIS (SIMPAD_CS3_GPIO_BASE + 5) +#define SIMPAD_CS3_MQ_RESET (SIMPAD_CS3_GPIO_BASE + 6) +#define SIMPAD_CS3_PCMCIA_RESET (SIMPAD_CS3_GPIO_BASE + 7) +#define SIMPAD_CS3_DECT_POWER_ON (SIMPAD_CS3_GPIO_BASE + 8) +#define SIMPAD_CS3_IRDA_SD (SIMPAD_CS3_GPIO_BASE + 9) +#define SIMPAD_CS3_RS232_ON (SIMPAD_CS3_GPIO_BASE + 10) +#define SIMPAD_CS3_SD_MEDIAQ (SIMPAD_CS3_GPIO_BASE + 11) +#define SIMPAD_CS3_LED2_ON (SIMPAD_CS3_GPIO_BASE + 12) +#define SIMPAD_CS3_IRDA_MODE (SIMPAD_CS3_GPIO_BASE + 13) +#define SIMPAD_CS3_ENABLE_5V (SIMPAD_CS3_GPIO_BASE + 14) +#define SIMPAD_CS3_RESET_SIMCARD (SIMPAD_CS3_GPIO_BASE + 15) + +#define SIMPAD_CS3_PCMCIA_BVD1 (SIMPAD_CS3_GPIO_BASE + 16) +#define SIMPAD_CS3_PCMCIA_BVD2 (SIMPAD_CS3_GPIO_BASE + 17) +#define SIMPAD_CS3_PCMCIA_VS1 (SIMPAD_CS3_GPIO_BASE + 18) +#define SIMPAD_CS3_PCMCIA_VS2 (SIMPAD_CS3_GPIO_BASE + 19) +#define SIMPAD_CS3_LOCK_IND (SIMPAD_CS3_GPIO_BASE + 20) +#define SIMPAD_CS3_CHARGING_STATE (SIMPAD_CS3_GPIO_BASE + 21) +#define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22) +#define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23) -#define CS3BUSTYPE unsigned volatile long #define CS3_BASE 0xf1000000 -#define VCC_5V_EN 0x0001 // For 5V PCMCIA -#define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA -#define EN1 0x0004 // This is only for EPROM's -#define EN0 0x0008 // Both should be enable for 3.3V or 5V -#define DISPLAY_ON 0x0010 -#define PCMCIA_BUFF_DIS 0x0020 -#define MQ_RESET 0x0040 -#define PCMCIA_RESET 0x0080 -#define DECT_POWER_ON 0x0100 -#define IRDA_SD 0x0200 // Shutdown for powersave -#define RS232_ON 0x0400 -#define SD_MEDIAQ 0x0800 // Shutdown for powersave -#define LED2_ON 0x1000 -#define IRDA_MODE 0x2000 // Fast/Slow IrDA mode -#define ENABLE_5V 0x4000 // Enable 5V circuit -#define RESET_SIMCARD 0x8000 - -#define RS232_ENABLE 0x0440 -#define PCMCIAMASK 0x402f - - +long simpad_get_cs3_ro(void); +long simpad_get_cs3_shadow(void); +void simpad_set_cs3_bit(int value); +void simpad_clear_cs3_bit(int value); + +#define VCC_5V_EN 0x0001 /* For 5V PCMCIA */ +#define VCC_3V_EN 0x0002 /* FOR 3.3V PCMCIA */ +#define EN1 0x0004 /* This is only for EPROM's */ +#define EN0 0x0008 /* Both should be enable for 3.3V or 5V */ +#define DISPLAY_ON 0x0010 +#define PCMCIA_BUFF_DIS 0x0020 +#define MQ_RESET 0x0040 +#define PCMCIA_RESET 0x0080 +#define DECT_POWER_ON 0x0100 +#define IRDA_SD 0x0200 /* Shutdown for powersave */ +#define RS232_ON 0x0400 +#define SD_MEDIAQ 0x0800 /* Shutdown for powersave */ +#define LED2_ON 0x1000 +#define IRDA_MODE 0x2000 /* Fast/Slow IrDA mode */ +#define ENABLE_5V 0x4000 /* Enable 5V circuit */ +#define RESET_SIMCARD 0x8000 + +#define PCMCIA_BVD1 0x01 +#define PCMCIA_BVD2 0x02 +#define PCMCIA_VS1 0x04 +#define PCMCIA_VS2 0x08 +#define LOCK_IND 0x10 +#define CHARGING_STATE 0x20 +#define PCMCIA_SHORT 0x40 + +/*--- Battery ---*/ struct simpad_battery { unsigned char ac_status; /* line connected yes/no */ unsigned char status; /* battery loading yes/no */ diff --git a/arch/arm/mach-sa1100/leds-simpad.c b/arch/arm/mach-sa1100/leds-simpad.c deleted file mode 100644 index d50f4ee..0000000 --- a/arch/arm/mach-sa1100/leds-simpad.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/leds-simpad.c - * - * Author: Juergen Messerer <juergen.messerer@siemens.ch> - */ -#include <linux/init.h> - -#include <mach/hardware.h> -#include <asm/leds.h> -#include <asm/system.h> -#include <mach/simpad.h> - -#include "leds.h" - - -#define LED_STATE_ENABLED 1 -#define LED_STATE_CLAIMED 2 - -static unsigned int led_state; -static unsigned int hw_led_state; - -#define LED_GREEN (1) -#define LED_MASK (1) - -extern void set_cs3_bit(int value); -extern void clear_cs3_bit(int value); - -void simpad_leds_event(led_event_t evt) -{ - switch (evt) - { - case led_start: - hw_led_state = LED_GREEN; - led_state = LED_STATE_ENABLED; - break; - - case led_stop: - led_state &= ~LED_STATE_ENABLED; - break; - - case led_claim: - led_state |= LED_STATE_CLAIMED; - hw_led_state = LED_GREEN; - break; - - case led_release: - led_state &= ~LED_STATE_CLAIMED; - hw_led_state = LED_GREEN; - break; - -#ifdef CONFIG_LEDS_TIMER - case led_timer: - if (!(led_state & LED_STATE_CLAIMED)) - hw_led_state ^= LED_GREEN; - break; -#endif - -#ifdef CONFIG_LEDS_CPU - case led_idle_start: - break; - - case led_idle_end: - break; -#endif - - case led_halted: - break; - - case led_green_on: - if (led_state & LED_STATE_CLAIMED) - hw_led_state |= LED_GREEN; - break; - - case led_green_off: - if (led_state & LED_STATE_CLAIMED) - hw_led_state &= ~LED_GREEN; - break; - - case led_amber_on: - break; - - case led_amber_off: - break; - - case led_red_on: - break; - - case led_red_off: - break; - - default: - break; - } - - if (led_state & LED_STATE_ENABLED) - set_cs3_bit(LED2_ON); - else - clear_cs3_bit(LED2_ON); -} - diff --git a/arch/arm/mach-sa1100/leds.c b/arch/arm/mach-sa1100/leds.c index bbfe197..5fe71a0 100644 --- a/arch/arm/mach-sa1100/leds.c +++ b/arch/arm/mach-sa1100/leds.c @@ -42,8 +42,6 @@ sa1100_leds_init(void) leds_event = adsbitsy_leds_event; if (machine_is_pt_system3()) leds_event = system3_leds_event; - if (machine_is_simpad()) - leds_event = simpad_leds_event; /* what about machine registry? including led, apm... -zecke */ leds_event(led_start); return 0; diff --git a/arch/arm/mach-sa1100/leds.h b/arch/arm/mach-sa1100/leds.h index 68cc9f7..776b602 100644 --- a/arch/arm/mach-sa1100/leds.h +++ b/arch/arm/mach-sa1100/leds.h @@ -11,4 +11,3 @@ extern void pfs168_leds_event(led_event_t evt); extern void graphicsmaster_leds_event(led_event_t evt); extern void adsbitsy_leds_event(led_event_t evt); extern void system3_leds_event(led_event_t evt); -extern void simpad_leds_event(led_event_t evt); diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index a1c2427..4790f3f 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -13,6 +13,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/io.h> +#include <linux/gpio.h> #include <asm/irq.h> #include <mach/hardware.h> @@ -28,35 +29,92 @@ #include <linux/serial_core.h> #include <linux/ioport.h> +#include <linux/input.h> +#include <linux/gpio_keys.h> +#include <linux/leds.h> +#include <linux/i2c-gpio.h> #include "generic.h" -long cs3_shadow; +/* + * CS3 support + */ -long get_cs3_shadow(void) +static long cs3_shadow; +static spinlock_t cs3_lock; +static struct gpio_chip cs3_gpio; + +long simpad_get_cs3_ro(void) +{ + return readl(CS3_BASE); +} +EXPORT_SYMBOL(simpad_get_cs3_ro); + +long simpad_get_cs3_shadow(void) { return cs3_shadow; } +EXPORT_SYMBOL(simpad_get_cs3_shadow); -void set_cs3(long value) +static void __simpad_write_cs3(void) { - *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow = value; + writel(cs3_shadow, CS3_BASE); } -void set_cs3_bit(int value) +void simpad_set_cs3_bit(int value) { + unsigned long flags; + + spin_lock_irqsave(&cs3_lock, flags); cs3_shadow |= value; - *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow; + __simpad_write_cs3(); + spin_unlock_irqrestore(&cs3_lock, flags); } +EXPORT_SYMBOL(simpad_set_cs3_bit); -void clear_cs3_bit(int value) +void simpad_clear_cs3_bit(int value) { + unsigned long flags; + + spin_lock_irqsave(&cs3_lock, flags); cs3_shadow &= ~value; - *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow; + __simpad_write_cs3(); + spin_unlock_irqrestore(&cs3_lock, flags); } +EXPORT_SYMBOL(simpad_clear_cs3_bit); + +static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + if (offset > 15) + return; + if (value) + simpad_set_cs3_bit(1 << offset); + else + simpad_clear_cs3_bit(1 << offset); +}; + +static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + if (offset > 15) + return simpad_get_cs3_ro() & (1 << (offset - 16)); + return simpad_get_cs3_shadow() & (1 << offset); +}; -EXPORT_SYMBOL(set_cs3_bit); -EXPORT_SYMBOL(clear_cs3_bit); +static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + if (offset > 15) + return 0; + return -EINVAL; +}; + +static int cs3_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + if (offset > 15) + return -EINVAL; + cs3_gpio_set(chip, offset, value); + return 0; +}; static struct map_desc simpad_io_desc[] __initdata = { { /* MQ200 */ @@ -64,9 +122,9 @@ static struct map_desc simpad_io_desc[] __initdata = { .pfn = __phys_to_pfn(0x4b800000), .length = 0x00800000, .type = MT_DEVICE - }, { /* Paules CS3, write only */ - .virtual = 0xf1000000, - .pfn = __phys_to_pfn(0x18000000), + }, { /* Simpad CS3 */ + .virtual = CS3_BASE, + .pfn = __phys_to_pfn(SA1100_CS3_PHYS), .length = 0x00100000, .type = MT_DEVICE }, @@ -78,12 +136,12 @@ static void simpad_uart_pm(struct uart_port *port, u_int state, u_int oldstate) if (port->mapbase == (u_int)&Ser1UTCR0) { if (state) { - clear_cs3_bit(RS232_ON); - clear_cs3_bit(DECT_POWER_ON); + simpad_clear_cs3_bit(RS232_ON); + simpad_clear_cs3_bit(DECT_POWER_ON); }else { - set_cs3_bit(RS232_ON); - set_cs3_bit(DECT_POWER_ON); + simpad_set_cs3_bit(RS232_ON); + simpad_set_cs3_bit(DECT_POWER_ON); } } } @@ -132,6 +190,7 @@ static struct resource simpad_flash_resources [] = { static struct mcp_plat_data simpad_mcp_data = { .mccr0 = MCCR0_ADM, .sclk_rate = 11981000, + .gpio_base = SIMPAD_UCB1X00_GPIO_BASE, }; @@ -142,9 +201,10 @@ static void __init simpad_map_io(void) iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc)); - set_cs3_bit (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON | - ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON); - + /* Initialize CS3 */ + cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | + RS232_ON | ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON); + __simpad_write_cs3(); /* Spinlocks not yet initialized */ sa1100_register_uart_fns(&simpad_port_fns); sa1100_register_uart(0, 3); /* serial interface */ @@ -170,13 +230,14 @@ static void __init simpad_map_io(void) static void simpad_power_off(void) { - local_irq_disable(); // was cli - set_cs3(0x800); /* only SD_MEDIAQ */ + local_irq_disable(); + cs3_shadow = SD_MEDIAQ; + __simpad_write_cs3(); /* Bypass spinlock here */ /* disable internal oscillator, float CS lines */ PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); - /* enable wake-up on GPIO0 (Assabet...) */ - PWER = GFER = GRER = 1; + /* enable wake-up on GPIO0 */ + PWER = GFER = GRER = PWER_GPIO0; /* * set scratchpad to zero, just in case it is used as a * restart address by the bootloader. @@ -192,6 +253,91 @@ static void simpad_power_off(void) } +/* + * gpio_keys +*/ + +static struct gpio_keys_button simpad_button_table[] = { + { KEY_POWER, IRQ_GPIO_POWER_BUTTON, 1, "power button" }, +}; + +static struct gpio_keys_platform_data simpad_keys_data = { + .buttons = simpad_button_table, + .nbuttons = ARRAY_SIZE(simpad_button_table), +}; + +static struct platform_device simpad_keys = { + .name = "gpio-keys", + .dev = { + .platform_data = &simpad_keys_data, + }, +}; + +static struct gpio_keys_button simpad_polled_button_table[] = { + { KEY_PROG1, SIMPAD_UCB1X00_GPIO_PROG1, 1, "prog1 button" }, + { KEY_PROG2, SIMPAD_UCB1X00_GPIO_PROG2, 1, "prog2 button" }, + { KEY_UP, SIMPAD_UCB1X00_GPIO_UP, 1, "up button" }, + { KEY_DOWN, SIMPAD_UCB1X00_GPIO_DOWN, 1, "down button" }, + { KEY_LEFT, SIMPAD_UCB1X00_GPIO_LEFT, 1, "left button" }, + { KEY_RIGHT, SIMPAD_UCB1X00_GPIO_RIGHT, 1, "right button" }, +}; + +static struct gpio_keys_platform_data simpad_polled_keys_data = { + .buttons = simpad_polled_button_table, + .nbuttons = ARRAY_SIZE(simpad_polled_button_table), + .poll_interval = 50, +}; + +static struct platform_device simpad_polled_keys = { + .name = "gpio-keys-polled", + .dev = { + .platform_data = &simpad_polled_keys_data, + }, +}; + +/* + * GPIO LEDs + */ + +static struct gpio_led simpad_leds[] = { + { + .name = "simpad:power", + .gpio = SIMPAD_CS3_LED2_ON, + .active_low = 0, + .default_trigger = "default-on", + }, +}; + +static struct gpio_led_platform_data simpad_led_data = { + .num_leds = ARRAY_SIZE(simpad_leds), + .leds = simpad_leds, +}; + +static struct platform_device simpad_gpio_leds = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &simpad_led_data, + }, +}; + +/* + * i2c + */ +static struct i2c_gpio_platform_data simpad_i2c_data = { + .sda_pin = GPIO_GPIO21, + .scl_pin = GPIO_GPIO25, + .udelay = 10, + .timeout = HZ, +}; + +static struct platform_device simpad_i2c = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &simpad_i2c_data, + }, +}; /* * MediaQ Video Device @@ -202,7 +348,11 @@ static struct platform_device simpad_mq200fb = { }; static struct platform_device *devices[] __initdata = { - &simpad_mq200fb + &simpad_keys, + &simpad_polled_keys, + &simpad_mq200fb, + &simpad_gpio_leds, + &simpad_i2c, }; @@ -211,6 +361,19 @@ static int __init simpad_init(void) { int ret; + spin_lock_init(&cs3_lock); + + cs3_gpio.label = "simpad_cs3"; + cs3_gpio.base = SIMPAD_CS3_GPIO_BASE; + cs3_gpio.ngpio = 24; + cs3_gpio.set = cs3_gpio_set; + cs3_gpio.get = cs3_gpio_get; + cs3_gpio.direction_input = cs3_gpio_direction_input; + cs3_gpio.direction_output = cs3_gpio_direction_output; + ret = gpiochip_add(&cs3_gpio); + if (ret) + printk(KERN_WARNING "simpad: Unable to register cs3 GPIO device"); + pm_power_off = simpad_power_off; sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, diff --git a/arch/arm/mach-shark/Makefile.boot b/arch/arm/mach-shark/Makefile.boot index 4320f8b..e40e24e 100644 --- a/arch/arm/mach-shark/Makefile.boot +++ b/arch/arm/mach-shark/Makefile.boot @@ -1,2 +1,2 @@ - zreladdr-y := 0x08008000 + zreladdr-y += 0x08008000 diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c index c9e32de..ccd4918 100644 --- a/arch/arm/mach-shark/leds.c +++ b/arch/arm/mach-shark/leds.c @@ -36,7 +36,7 @@ static char led_state; static short hw_led_state; static short saved_state; -static DEFINE_SPINLOCK(leds_lock); +static DEFINE_RAW_SPINLOCK(leds_lock); short sequoia_read(int addr) { outw(addr,0x24); @@ -52,7 +52,7 @@ static void sequoia_leds_event(led_event_t evt) { unsigned long flags; - spin_lock_irqsave(&leds_lock, flags); + raw_spin_lock_irqsave(&leds_lock, flags); hw_led_state = sequoia_read(0x09); @@ -144,7 +144,7 @@ static void sequoia_leds_event(led_event_t evt) if (led_state & LED_STATE_ENABLED) sequoia_write(hw_led_state,0x09); - spin_unlock_irqrestore(&leds_lock, flags); + raw_spin_unlock_irqrestore(&leds_lock, flags); } static int __init leds_init(void) diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 1c08ee9..498efd9 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -1,7 +1,7 @@ __ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ $$[$(CONFIG_MEMORY_START) + 0x8000]') - zreladdr-y := $(__ZRELADDR) + zreladdr-y += $(__ZRELADDR) # Unsupported legacy stuff # diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index 5fde49d..475342b 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -355,14 +355,17 @@ static struct resource sdhi0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = gic_spi(83), .flags = IORESOURCE_IRQ, }, [2] = { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = gic_spi(84), .flags = IORESOURCE_IRQ, }, [3] = { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = gic_spi(85), .flags = IORESOURCE_IRQ, }, @@ -398,14 +401,17 @@ static struct resource sdhi1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = gic_spi(87), .flags = IORESOURCE_IRQ, }, [2] = { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = gic_spi(88), .flags = IORESOURCE_IRQ, }, [3] = { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = gic_spi(89), .flags = IORESOURCE_IRQ, }, diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index b622d8d..5b7edad 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -42,6 +42,7 @@ #include <linux/leds.h> #include <linux/input/sh_keysc.h> #include <linux/usb/r8a66597.h> +#include <linux/pm_clock.h> #include <linux/dma-mapping.h> #include <media/sh_mobile_ceu.h> @@ -1411,6 +1412,11 @@ static void __init ap4evb_init(void) sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); + sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); + hdmi_init_pm_clock(); fsi_init_pm_clock(); sh7372_pm_init(); diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index de2253d..3689ad2 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -39,7 +39,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> -#include <linux/pm_runtime.h> +#include <linux/pm_clock.h> #include <linux/smsc911x.h> #include <linux/sh_intc.h> #include <linux/tca6416_keypad.h> @@ -811,6 +811,7 @@ static struct usbhs_private usbhs1_private = { }, .driver_param = { .buswait_bwait = 4, + .has_otg = 1, .pipe_type = usbhs1_pipe_cfg, .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg), .d0_tx_id = SHDMA_SLAVE_USB1_TX, @@ -1071,14 +1072,17 @@ static struct resource sdhi1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */ .flags = IORESOURCE_IRQ, }, [2] = { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ .flags = IORESOURCE_IRQ, }, [3] = { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ .flags = IORESOURCE_IRQ, }, @@ -1122,14 +1126,17 @@ static struct resource sdhi2_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT, .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */ .flags = IORESOURCE_IRQ, }, [2] = { + .name = SH_MOBILE_SDHI_IRQ_SDCARD, .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ .flags = IORESOURCE_IRQ, }, [3] = { + .name = SH_MOBILE_SDHI_IRQ_SDIO, .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */ .flags = IORESOURCE_IRQ, }, @@ -1590,7 +1597,17 @@ static void __init mackerel_init(void) sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device); + sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device); sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); +#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); +#endif + sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device); + sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); hdmi_init_pm_clock(); sh7372_pm_init(); diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 06aecb3..c0cdbf9 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -35,8 +35,8 @@ extern void sh7372_add_standard_devices(void); extern void sh7372_clock_init(void); extern void sh7372_pinmux_init(void); extern void sh7372_pm_init(void); -extern void sh7372_cpu_suspend(void); -extern void sh7372_cpu_resume(void); +extern void sh7372_resume_core_standby_a3sm(void); +extern int sh7372_do_idle_a3sm(unsigned long unused); extern struct clk sh7372_extal1_clk; extern struct clk sh7372_extal2_clk; diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index 24e63a8..84532f9 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -479,7 +479,12 @@ struct platform_device; struct sh7372_pm_domain { struct generic_pm_domain genpd; + struct dev_power_governor *gov; + void (*suspend)(void); + void (*resume)(void); unsigned int bit_shift; + bool no_debug; + bool stay_on; }; static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d) @@ -491,16 +496,24 @@ static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d) extern struct sh7372_pm_domain sh7372_a4lc; extern struct sh7372_pm_domain sh7372_a4mp; extern struct sh7372_pm_domain sh7372_d4; +extern struct sh7372_pm_domain sh7372_a4r; extern struct sh7372_pm_domain sh7372_a3rv; extern struct sh7372_pm_domain sh7372_a3ri; +extern struct sh7372_pm_domain sh7372_a3sp; extern struct sh7372_pm_domain sh7372_a3sg; extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd); extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd, struct platform_device *pdev); +extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd, + struct sh7372_pm_domain *sh7372_sd); #else #define sh7372_init_pm_domain(pd) do { } while(0) #define sh7372_add_device_to_domain(pd, pdev) do { } while(0) +#define sh7372_pm_add_subdomain(pd, sd) do { } while(0) #endif /* CONFIG_PM */ +extern void sh7372_intcs_suspend(void); +extern void sh7372_intcs_resume(void); + #endif /* __ASM_SH7372_H__ */ diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index 739315e..29cdc05 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -606,9 +606,16 @@ static void intcs_demux(unsigned int irq, struct irq_desc *desc) generic_handle_irq(intcs_evt2irq(evtcodeas)); } +static void __iomem *intcs_ffd2; +static void __iomem *intcs_ffd5; + void __init sh7372_init_irq(void) { - void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + void __iomem *intevtsa; + + intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); + intevtsa = intcs_ffd2 + 0x100; + intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); register_intc_controller(&intca_desc); register_intc_controller(&intcs_desc); @@ -617,3 +624,46 @@ void __init sh7372_init_irq(void) irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } + +static unsigned short ffd2[0x200]; +static unsigned short ffd5[0x100]; + +void sh7372_intcs_suspend(void) +{ + int k; + + for (k = 0x00; k <= 0x30; k += 4) + ffd2[k] = __raw_readw(intcs_ffd2 + k); + + for (k = 0x80; k <= 0xb0; k += 4) + ffd2[k] = __raw_readb(intcs_ffd2 + k); + + for (k = 0x180; k <= 0x188; k += 4) + ffd2[k] = __raw_readb(intcs_ffd2 + k); + + for (k = 0x00; k <= 0x3c; k += 4) + ffd5[k] = __raw_readw(intcs_ffd5 + k); + + for (k = 0x80; k <= 0x9c; k += 4) + ffd5[k] = __raw_readb(intcs_ffd5 + k); +} + +void sh7372_intcs_resume(void) +{ + int k; + + for (k = 0x00; k <= 0x30; k += 4) + __raw_writew(ffd2[k], intcs_ffd2 + k); + + for (k = 0x80; k <= 0xb0; k += 4) + __raw_writeb(ffd2[k], intcs_ffd2 + k); + + for (k = 0x180; k <= 0x188; k += 4) + __raw_writeb(ffd2[k], intcs_ffd2 + k); + + for (k = 0x00; k <= 0x3c; k += 4) + __raw_writew(ffd5[k], intcs_ffd5 + k); + + for (k = 0x80; k <= 0x9c; k += 4) + __raw_writeb(ffd5[k], intcs_ffd5 + k); +} diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c index 933fb41..7961273 100644 --- a/arch/arm/mach-shmobile/pm-sh7372.c +++ b/arch/arm/mach-shmobile/pm-sh7372.c @@ -15,23 +15,61 @@ #include <linux/list.h> #include <linux/err.h> #include <linux/slab.h> -#include <linux/pm_runtime.h> +#include <linux/pm_clock.h> #include <linux/platform_device.h> #include <linux/delay.h> +#include <linux/irq.h> +#include <linux/bitrev.h> #include <asm/system.h> #include <asm/io.h> #include <asm/tlbflush.h> +#include <asm/suspend.h> #include <mach/common.h> #include <mach/sh7372.h> -#define SMFRAM 0xe6a70000 -#define SYSTBCR 0xe6150024 -#define SBAR 0xe6180020 -#define APARMBAREA 0xe6f10020 +/* DBG */ +#define DBGREG1 0xe6100020 +#define DBGREG9 0xe6100040 +/* CPGA */ +#define SYSTBCR 0xe6150024 +#define MSTPSR0 0xe6150030 +#define MSTPSR1 0xe6150038 +#define MSTPSR2 0xe6150040 +#define MSTPSR3 0xe6150048 +#define MSTPSR4 0xe615004c +#define PLLC01STPCR 0xe61500c8 + +/* SYSC */ #define SPDCR 0xe6180008 #define SWUCR 0xe6180014 +#define SBAR 0xe6180020 +#define WUPRMSK 0xe6180028 +#define WUPSMSK 0xe618002c +#define WUPSMSK2 0xe6180048 #define PSTR 0xe6180080 +#define WUPSFAC 0xe6180098 +#define IRQCR 0xe618022c +#define IRQCR2 0xe6180238 +#define IRQCR3 0xe6180244 +#define IRQCR4 0xe6180248 +#define PDNSEL 0xe6180254 + +/* INTC */ +#define ICR1A 0xe6900000 +#define ICR2A 0xe6900004 +#define ICR3A 0xe6900008 +#define ICR4A 0xe690000c +#define INTMSK00A 0xe6900040 +#define INTMSK10A 0xe6900044 +#define INTMSK20A 0xe6900048 +#define INTMSK30A 0xe690004c + +/* MFIS */ +#define SMFRAM 0xe6a70000 + +/* AP-System Core */ +#define APARMBAREA 0xe6f10020 #define PSTR_RETRIES 100 #define PSTR_DELAY_US 10 @@ -43,6 +81,12 @@ static int pd_power_down(struct generic_pm_domain *genpd) struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd); unsigned int mask = 1 << sh7372_pd->bit_shift; + if (sh7372_pd->suspend) + sh7372_pd->suspend(); + + if (sh7372_pd->stay_on) + return 0; + if (__raw_readl(PSTR) & mask) { unsigned int retry_count; @@ -55,8 +99,9 @@ static int pd_power_down(struct generic_pm_domain *genpd) } } - pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n", - mask, __raw_readl(PSTR)); + if (!sh7372_pd->no_debug) + pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n", + mask, __raw_readl(PSTR)); return 0; } @@ -68,6 +113,9 @@ static int pd_power_up(struct generic_pm_domain *genpd) unsigned int retry_count; int ret = 0; + if (sh7372_pd->stay_on) + goto out; + if (__raw_readl(PSTR) & mask) goto out; @@ -84,66 +132,48 @@ static int pd_power_up(struct generic_pm_domain *genpd) if (__raw_readl(SWUCR) & mask) ret = -EIO; + if (!sh7372_pd->no_debug) + pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n", + mask, __raw_readl(PSTR)); + out: - pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n", - mask, __raw_readl(PSTR)); + if (ret == 0 && sh7372_pd->resume) + sh7372_pd->resume(); return ret; } -static int pd_power_up_a3rv(struct generic_pm_domain *genpd) +static void sh7372_a4r_suspend(void) { - int ret = pd_power_up(genpd); - - /* force A4LC on after A3RV has been requested on */ - pm_genpd_poweron(&sh7372_a4lc.genpd); - - return ret; + sh7372_intcs_suspend(); + __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */ } -static int pd_power_down_a3rv(struct generic_pm_domain *genpd) +static bool pd_active_wakeup(struct device *dev) { - int ret = pd_power_down(genpd); - - /* try to power down A4LC after A3RV is requested off */ - genpd_queue_power_off_work(&sh7372_a4lc.genpd); - - return ret; + return true; } -static int pd_power_down_a4lc(struct generic_pm_domain *genpd) +static bool sh7372_power_down_forbidden(struct dev_pm_domain *domain) { - /* only power down A4LC if A3RV is off */ - if (!(__raw_readl(PSTR) & (1 << sh7372_a3rv.bit_shift))) - return pd_power_down(genpd); - - return -EBUSY; + return false; } -static bool pd_active_wakeup(struct device *dev) -{ - return true; -} +struct dev_power_governor sh7372_always_on_gov = { + .power_down_ok = sh7372_power_down_forbidden, +}; void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd) { struct generic_pm_domain *genpd = &sh7372_pd->genpd; - pm_genpd_init(genpd, NULL, false); + pm_genpd_init(genpd, sh7372_pd->gov, false); genpd->stop_device = pm_clk_suspend; genpd->start_device = pm_clk_resume; + genpd->dev_irq_safe = true; genpd->active_wakeup = pd_active_wakeup; - - if (sh7372_pd == &sh7372_a4lc) { - genpd->power_off = pd_power_down_a4lc; - genpd->power_on = pd_power_up; - } else if (sh7372_pd == &sh7372_a3rv) { - genpd->power_off = pd_power_down_a3rv; - genpd->power_on = pd_power_up_a3rv; - } else { - genpd->power_off = pd_power_down; - genpd->power_on = pd_power_up; - } + genpd->power_off = pd_power_down; + genpd->power_on = pd_power_up; genpd->power_on(&sh7372_pd->genpd); } @@ -152,11 +182,15 @@ void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd, { struct device *dev = &pdev->dev; - if (!dev->power.subsys_data) { - pm_clk_init(dev); - pm_clk_add(dev, NULL); - } pm_genpd_add_device(&sh7372_pd->genpd, dev); + if (pm_clk_no_clocks(dev)) + pm_clk_add(dev, NULL); +} + +void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd, + struct sh7372_pm_domain *sh7372_sd) +{ + pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd); } struct sh7372_pm_domain sh7372_a4lc = { @@ -171,6 +205,14 @@ struct sh7372_pm_domain sh7372_d4 = { .bit_shift = 3, }; +struct sh7372_pm_domain sh7372_a4r = { + .bit_shift = 5, + .gov = &sh7372_always_on_gov, + .suspend = sh7372_a4r_suspend, + .resume = sh7372_intcs_resume, + .stay_on = true, +}; + struct sh7372_pm_domain sh7372_a3rv = { .bit_shift = 6, }; @@ -179,39 +221,187 @@ struct sh7372_pm_domain sh7372_a3ri = { .bit_shift = 8, }; +struct sh7372_pm_domain sh7372_a3sp = { + .bit_shift = 11, + .gov = &sh7372_always_on_gov, + .no_debug = true, +}; + struct sh7372_pm_domain sh7372_a3sg = { .bit_shift = 13, }; #endif /* CONFIG_PM */ +#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) +static int sh7372_do_idle_core_standby(unsigned long unused) +{ + cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */ + return 0; +} + static void sh7372_enter_core_standby(void) { - void __iomem *smfram = (void __iomem *)SMFRAM; + /* set reset vector, translate 4k */ + __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR); + __raw_writel(0, APARMBAREA); - __raw_writel(0, APARMBAREA); /* translate 4k */ - __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */ - __raw_writel(0x10, SYSTBCR); /* enable core standby */ + /* enter sleep mode with SYSTBCR to 0x10 */ + __raw_writel(0x10, SYSTBCR); + cpu_suspend(0, sh7372_do_idle_core_standby); + __raw_writel(0, SYSTBCR); - __raw_writel(0, smfram + 0x3c); /* clear page table address */ + /* disable reset vector translation */ + __raw_writel(0, SBAR); +} +#endif + +#ifdef CONFIG_SUSPEND +static void sh7372_enter_a3sm_common(int pllc0_on) +{ + /* set reset vector, translate 4k */ + __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR); + __raw_writel(0, APARMBAREA); + + if (pllc0_on) + __raw_writel(0, PLLC01STPCR); + else + __raw_writel(1 << 28, PLLC01STPCR); + + __raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */ + __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */ + cpu_suspend(0, sh7372_do_idle_a3sm); + __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */ + + /* disable reset vector translation */ + __raw_writel(0, SBAR); +} + +static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p) +{ + unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4; + unsigned long msk, msk2; + + /* check active clocks to determine potential wakeup sources */ + + mstpsr0 = __raw_readl(MSTPSR0); + if ((mstpsr0 & 0x00000003) != 0x00000003) { + pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0); + return 0; + } + + mstpsr1 = __raw_readl(MSTPSR1); + if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) { + pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1); + return 0; + } - sh7372_cpu_suspend(); - cpu_init(); + mstpsr2 = __raw_readl(MSTPSR2); + if ((mstpsr2 & 0x000741ff) != 0x000741ff) { + pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2); + return 0; + } - /* if page table address is non-NULL then we have been powered down */ - if (__raw_readl(smfram + 0x3c)) { - __raw_writel(__raw_readl(smfram + 0x40), - __va(__raw_readl(smfram + 0x3c))); + mstpsr3 = __raw_readl(MSTPSR3); + if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) { + pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3); + return 0; + } - flush_tlb_all(); - set_cr(__raw_readl(smfram + 0x38)); + mstpsr4 = __raw_readl(MSTPSR4); + if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) { + pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4); + return 0; } - __raw_writel(0, SYSTBCR); /* disable core standby */ - __raw_writel(0, SBAR); /* disable reset vector translation */ + msk = 0; + msk2 = 0; + + /* make bitmaps of limited number of wakeup sources */ + + if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */ + msk |= 1 << 31; + + if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */ + msk |= 1 << 21; + + if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */ + msk |= 1 << 2; + + if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */ + msk |= 1 << 1; + + if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */ + msk |= 1 << 1; + + if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */ + msk |= 1 << 1; + + if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */ + msk2 |= 1 << 17; + + *mskp = msk; + *msk2p = msk2; + + return 1; +} + +static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p) +{ + u16 tmp, irqcr1, irqcr2; + int k; + + irqcr1 = 0; + irqcr2 = 0; + + /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */ + for (k = 0; k <= 7; k++) { + tmp = (icr >> ((7 - k) * 4)) & 0xf; + irqcr1 |= (tmp & 0x03) << (k * 2); + irqcr2 |= (tmp >> 2) << (k * 2); + } + + *irqcr1p = irqcr1; + *irqcr2p = irqcr2; +} + +static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2) +{ + u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high; + unsigned long tmp; + + /* read IRQ0A -> IRQ15A mask */ + tmp = bitrev8(__raw_readb(INTMSK00A)); + tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8; + + /* setup WUPSMSK from clocks and external IRQ mask */ + msk = (~msk & 0xc030000f) | (tmp << 4); + __raw_writel(msk, WUPSMSK); + + /* propage level/edge trigger for external IRQ 0->15 */ + sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low); + sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high); + __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR); + __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2); + + /* read IRQ16A -> IRQ31A mask */ + tmp = bitrev8(__raw_readb(INTMSK20A)); + tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8; + + /* setup WUPSMSK2 from clocks and external IRQ mask */ + msk2 = (~msk2 & 0x00030000) | tmp; + __raw_writel(msk2, WUPSMSK2); + + /* propage level/edge trigger for external IRQ 16->31 */ + sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low); + sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high); + __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3); + __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4); } +#endif #ifdef CONFIG_CPU_IDLE + static void sh7372_cpuidle_setup(struct cpuidle_device *dev) { struct cpuidle_state *state; @@ -239,9 +429,25 @@ static void sh7372_cpuidle_init(void) {} #endif #ifdef CONFIG_SUSPEND + static int sh7372_enter_suspend(suspend_state_t suspend_state) { - sh7372_enter_core_standby(); + unsigned long msk, msk2; + + /* check active clocks to determine potential wakeup sources */ + if (sh7372_a3sm_valid(&msk, &msk2)) { + + /* convert INTC mask and sense to SYSC mask and sense */ + sh7372_setup_a3sm(msk, msk2); + + /* enter A3SM sleep with PLLC0 off */ + pr_debug("entering A3SM\n"); + sh7372_enter_a3sm_common(0); + } else { + /* default to Core Standby that supports all wakeup sources */ + pr_debug("entering Core Standby\n"); + sh7372_enter_core_standby(); + } return 0; } @@ -253,9 +459,6 @@ static void sh7372_suspend_init(void) static void sh7372_suspend_init(void) {} #endif -#define DBGREG1 0xe6100020 -#define DBGREG9 0xe6100040 - void __init sh7372_pm_init(void) { /* enable DBG hardware block to kick SYSC */ @@ -263,6 +466,9 @@ void __init sh7372_pm_init(void) __raw_writel(0x0000a501, DBGREG9); __raw_writel(0x00000000, DBGREG1); + /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */ + __raw_writel(0, PDNSEL); + sh7372_suspend_init(); sh7372_cpuidle_init(); } diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c index 6ec454e..bd5c6a3 100644 --- a/arch/arm/mach-shmobile/pm_runtime.c +++ b/arch/arm/mach-shmobile/pm_runtime.c @@ -15,6 +15,7 @@ #include <linux/io.h> #include <linux/pm_runtime.h> #include <linux/pm_domain.h> +#include <linux/pm_clock.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/sh_clk.h> diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 2d9b1b1..2380389 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -30,6 +30,7 @@ #include <linux/sh_dma.h> #include <linux/sh_intc.h> #include <linux/sh_timer.h> +#include <linux/pm_domain.h> #include <mach/hardware.h> #include <mach/sh7372.h> #include <asm/mach-types.h> @@ -990,9 +991,14 @@ void __init sh7372_add_standard_devices(void) sh7372_init_pm_domain(&sh7372_a4lc); sh7372_init_pm_domain(&sh7372_a4mp); sh7372_init_pm_domain(&sh7372_d4); + sh7372_init_pm_domain(&sh7372_a4r); sh7372_init_pm_domain(&sh7372_a3rv); sh7372_init_pm_domain(&sh7372_a3ri); sh7372_init_pm_domain(&sh7372_a3sg); + sh7372_init_pm_domain(&sh7372_a3sp); + + sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv); + sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc); platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); @@ -1003,6 +1009,25 @@ void __init sh7372_add_standard_devices(void) sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device); sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device); sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device); + sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device); + sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device); + sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device); + sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device); + sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device); + sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device); + sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device); } void __init sh7372_add_early_devices(void) diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index d37d3ca..f3ab3c5 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -30,58 +30,20 @@ */ #include <linux/linkage.h> +#include <linux/init.h> +#include <asm/memory.h> #include <asm/assembler.h> -#define SMFRAM 0xe6a70000 - - .align -kernel_flush: - .word v7_flush_dcache_all - - .align 3 -ENTRY(sh7372_cpu_suspend) - stmfd sp!, {r0-r12, lr} @ save registers on stack - - ldr r8, =SMFRAM - - mov r4, sp @ Store sp - mrs r5, spsr @ Store spsr - mov r6, lr @ Store lr - stmia r8!, {r4-r6} - - mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register - mrc p15, 0, r5, c2, c0, 0 @ TTBR0 - mrc p15, 0, r6, c2, c0, 1 @ TTBR1 - mrc p15, 0, r7, c2, c0, 2 @ TTBCR - stmia r8!, {r4-r7} - - mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register - mrc p15, 0, r5, c10, c2, 0 @ PRRR - mrc p15, 0, r6, c10, c2, 1 @ NMRR - stmia r8!,{r4-r6} - - mrc p15, 0, r4, c13, c0, 1 @ Context ID - mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID - mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address - mrs r7, cpsr @ Store current cpsr - stmia r8!, {r4-r7} - - mrc p15, 0, r4, c1, c0, 0 @ save control register - stmia r8!, {r4} - - /* - * jump out to kernel flush routine - * - reuse that code is better - * - it executes in a cached space so is faster than refetch per-block - * - should be faster and will change with kernel - * - 'might' have to copy address, load and jump to it - * Flush all data from the L1 data cache before disabling - * SCTLR.C bit. - */ - ldr r1, kernel_flush - mov lr, pc - bx r1 +#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) + .align 12 + .text + .global sh7372_resume_core_standby_a3sm +sh7372_resume_core_standby_a3sm: + ldr pc, 1f +1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET + .global sh7372_do_idle_a3sm +sh7372_do_idle_a3sm: /* * Clear the SCTLR.C bit to prevent further data cache * allocation. Clearing SCTLR.C would make all the data accesses @@ -92,10 +54,13 @@ ENTRY(sh7372_cpu_suspend) mcr p15, 0, r0, c1, c0, 0 isb + /* disable L2 cache in the aux control register */ + mrc p15, 0, r10, c1, c0, 1 + bic r10, r10, #2 + mcr p15, 0, r10, c1, c0, 1 + /* - * Invalidate L1 data cache. Even though only invalidate is - * necessary exported flush API is used here. Doing clean - * on already clean cache would be almost NOP. + * Invalidate data cache again. */ ldr r1, kernel_flush blx r1 @@ -115,146 +80,16 @@ ENTRY(sh7372_cpu_suspend) dsb dmb -/* - * =================================== - * == WFI instruction => Enter idle == - * =================================== - */ - wfi @ wait for interrupt - -/* - * =================================== - * == Resume path for non-OFF modes == - * =================================== - */ - mrc p15, 0, r0, c1, c0, 0 - tst r0, #(1 << 2) @ Check C bit enabled? - orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared - mcreq p15, 0, r0, c1, c0, 0 - isb - -/* - * =================================== - * == Exit point from non-OFF modes == - * =================================== - */ - ldmfd sp!, {r0-r12, pc} @ restore regs and return +#define SPDCR 0xe6180008 +#define A3SM (1 << 12) - .pool + /* A3SM power down */ + ldr r0, =SPDCR + ldr r1, =A3SM + str r1, [r0] +1: + b 1b - .align 12 - .text - .global sh7372_cpu_resume -sh7372_cpu_resume: - - mov r1, #0 - /* - * Invalidate all instruction caches to PoU - * and flush branch target cache - */ - mcr p15, 0, r1, c7, c5, 0 - - ldr r3, =SMFRAM - - ldmia r3!, {r4-r6} - mov sp, r4 @ Restore sp - msr spsr_cxsf, r5 @ Restore spsr - mov lr, r6 @ Restore lr - - ldmia r3!, {r4-r7} - mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register - mcr p15, 0, r5, c2, c0, 0 @ TTBR0 - mcr p15, 0, r6, c2, c0, 1 @ TTBR1 - mcr p15, 0, r7, c2, c0, 2 @ TTBCR - - ldmia r3!,{r4-r6} - mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register - mcr p15, 0, r5, c10, c2, 0 @ PRRR - mcr p15, 0, r6, c10, c2, 1 @ NMRR - - ldmia r3!,{r4-r7} - mcr p15, 0, r4, c13, c0, 1 @ Context ID - mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID - mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address - msr cpsr, r7 @ store cpsr - - /* Starting to enable MMU here */ - mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl - /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */ - and r7, #0x7 - cmp r7, #0x0 - beq usettbr0 -ttbr_error: - /* - * More work needs to be done to support N[0:2] value other than 0 - * So looping here so that the error can be detected - */ - b ttbr_error - - .align -cache_pred_disable_mask: - .word 0xFFFFE7FB -ttbrbit_mask: - .word 0xFFFFC000 -table_index_mask: - .word 0xFFF00000 -table_entry: - .word 0x00000C02 -usettbr0: - - mrc p15, 0, r2, c2, c0, 0 - ldr r5, ttbrbit_mask - and r2, r5 - mov r4, pc - ldr r5, table_index_mask - and r4, r5 @ r4 = 31 to 20 bits of pc - /* Extract the value to be written to table entry */ - ldr r6, table_entry - /* r6 has the value to be written to table entry */ - add r6, r6, r4 - /* Getting the address of table entry to modify */ - lsr r4, #18 - /* r2 has the location which needs to be modified */ - add r2, r4 - ldr r4, [r2] - str r6, [r2] /* modify the table entry */ - - mov r7, r6 - mov r5, r2 - mov r6, r4 - /* r5 = original page table address */ - /* r6 = original page table data */ - - mov r0, #0 - mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer - mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array - mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB - mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB - - /* - * Restore control register. This enables the MMU. - * The caches and prediction are not enabled here, they - * will be enabled after restoring the MMU table entry. - */ - ldmia r3!, {r4} - stmia r3!, {r5} /* save original page table address */ - stmia r3!, {r6} /* save original page table data */ - stmia r3!, {r7} /* save modified page table data */ - - ldr r2, cache_pred_disable_mask - and r4, r2 - mcr p15, 0, r4, c1, c0, 0 - dsb - isb - - ldr r0, =restoremmu_on - bx r0 - -/* - * ============================== - * == Exit point from OFF mode == - * ============================== - */ -restoremmu_on: - - ldmfd sp!, {r0-r12, pc} @ restore regs and return +kernel_flush: + .word v7_flush_dcache_all +#endif diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot index 7a1f3c0..4674a4c 100644 --- a/arch/arm/mach-spear3xx/Makefile.boot +++ b/arch/arm/mach-spear3xx/Makefile.boot @@ -1,3 +1,3 @@ -zreladdr-y := 0x00008000 +zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot index 7a1f3c0..4674a4c 100644 --- a/arch/arm/mach-spear6xx/Makefile.boot +++ b/arch/arm/mach-spear6xx/Makefile.boot @@ -1,3 +1,3 @@ -zreladdr-y := 0x00008000 +zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-tcc8k/Makefile.boot b/arch/arm/mach-tcc8k/Makefile.boot index f135c9d..5e02d41 100644 --- a/arch/arm/mach-tcc8k/Makefile.boot +++ b/arch/arm/mach-tcc8k/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x20008000 + zreladdr-y += 0x20008000 params_phys-y := 0x20000100 initrd_phys-y := 0x20800000 diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 428ad12..5e870d2 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -1,4 +1,4 @@ -zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00008000 +zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) += 0x00008000 params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index 5835225..f0bdc5e 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -125,8 +125,8 @@ static struct platform_device *harmony_devices[] __initdata = { &harmony_audio_device, }; -static void __init tegra_harmony_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) +static void __init tegra_harmony_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { mi->nr_banks = 2; mi->bank[0].start = PHYS_OFFSET; diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 39363e5..55c55ba 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -135,8 +135,8 @@ static void paz00_usb_init(void) platform_device_register(&tegra_ehci3_device); } -static void __init tegra_paz00_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) +static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { mi->nr_banks = 1; mi->bank[0].start = PHYS_OFFSET; diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c index 9908894..1a6617b 100644 --- a/arch/arm/mach-tegra/board-trimslice.c +++ b/arch/arm/mach-tegra/board-trimslice.c @@ -126,8 +126,8 @@ static void trimslice_usb_init(void) platform_device_register(&tegra_ehci1_device); } -static void __init tegra_trimslice_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) +static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline, + struct meminfo *mi) { mi->nr_banks = 2; mi->bank[0].start = PHYS_OFFSET; diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index d5e3f89..690b888 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -61,7 +61,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { NULL, NULL, 0, 0}, }; -void __init tegra_init_cache(void) +static void __init tegra_init_cache(void) { #ifdef CONFIG_CACHE_L2X0 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c index 0e1016a..bb5ce39 100644 --- a/arch/arm/mach-tegra/cpu-tegra.c +++ b/arch/arm/mach-tegra/cpu-tegra.c @@ -32,7 +32,6 @@ #include <asm/system.h> -#include <mach/hardware.h> #include <mach/clk.h> /* Frequency table index must be sequential starting at 0 */ @@ -57,12 +56,12 @@ static unsigned long target_cpu_speed[NUM_CPUS]; static DEFINE_MUTEX(tegra_cpu_lock); static bool is_suspended; -int tegra_verify_speed(struct cpufreq_policy *policy) +static int tegra_verify_speed(struct cpufreq_policy *policy) { return cpufreq_frequency_table_verify(policy, freq_table); } -unsigned int tegra_getspeed(unsigned int cpu) +static unsigned int tegra_getspeed(unsigned int cpu) { unsigned long rate; @@ -130,7 +129,7 @@ static int tegra_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) { - int idx; + unsigned int idx; unsigned int freq; int ret = 0; diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index 57e35d2..489e82b 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -29,7 +29,9 @@ #include <mach/iomap.h> #include <mach/dma.h> #include <mach/usb_phy.h> + #include "gpio-names.h" +#include "devices.h" static struct resource i2c_resource1[] = { [0] = { diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c index f4ef5eb..c0cf967 100644 --- a/arch/arm/mach-tegra/dma.c +++ b/arch/arm/mach-tegra/dma.c @@ -105,13 +105,17 @@ #define NV_DMA_MAX_TRASFER_SIZE 0x10000 -const unsigned int ahb_addr_wrap_table[8] = { +static const unsigned int ahb_addr_wrap_table[8] = { 0, 32, 64, 128, 256, 512, 1024, 2048 }; -const unsigned int apb_addr_wrap_table[8] = {0, 1, 2, 4, 8, 16, 32, 64}; +static const unsigned int apb_addr_wrap_table[8] = { + 0, 1, 2, 4, 8, 16, 32, 64 +}; -const unsigned int bus_width_table[5] = {8, 16, 32, 64, 128}; +static const unsigned int bus_width_table[5] = { + 8, 16, 32, 64, 128 +}; #define TEGRA_DMA_NAME_SIZE 16 struct tegra_dma_channel { @@ -157,7 +161,7 @@ void tegra_dma_dequeue(struct tegra_dma_channel *ch) return; } -void tegra_dma_stop(struct tegra_dma_channel *ch) +static void tegra_dma_stop(struct tegra_dma_channel *ch) { u32 csr; u32 status; @@ -174,7 +178,7 @@ void tegra_dma_stop(struct tegra_dma_channel *ch) writel(status, ch->addr + APB_DMA_CHAN_STA); } -int tegra_dma_cancel(struct tegra_dma_channel *ch) +static int tegra_dma_cancel(struct tegra_dma_channel *ch) { u32 csr; unsigned long irq_flags; diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h index e69de29..40a8c17 100644 --- a/arch/arm/mach-tegra/include/mach/gpio.h +++ b/arch/arm/mach-tegra/include/mach/gpio.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h index 4cea223..35a011f 100644 --- a/arch/arm/mach-tegra/include/mach/io.h +++ b/arch/arm/mach-tegra/include/mach/io.h @@ -33,20 +33,26 @@ * */ +#ifdef __ASSEMBLY__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + #define IO_IRAM_PHYS 0x40000000 -#define IO_IRAM_VIRT 0xFE400000 +#define IO_IRAM_VIRT IOMEM(0xFE400000) #define IO_IRAM_SIZE SZ_256K #define IO_CPU_PHYS 0x50040000 -#define IO_CPU_VIRT 0xFE000000 +#define IO_CPU_VIRT IOMEM(0xFE000000) #define IO_CPU_SIZE SZ_16K #define IO_PPSB_PHYS 0x60000000 -#define IO_PPSB_VIRT 0xFE200000 +#define IO_PPSB_VIRT IOMEM(0xFE200000) #define IO_PPSB_SIZE SZ_1M #define IO_APB_PHYS 0x70000000 -#define IO_APB_VIRT 0xFE300000 +#define IO_APB_VIRT IOMEM(0xFE300000) #define IO_APB_SIZE SZ_1M #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) @@ -61,7 +67,7 @@ IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \ IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \ IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \ - 0) + NULL) #ifndef __ASSEMBLER__ @@ -71,7 +77,7 @@ void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type); void tegra_iounmap(volatile void __iomem *addr); -#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n)) +#define IO_ADDRESS(n) (IO_TO_VIRT(n)) #ifdef CONFIG_TEGRA_PCI extern void __iomem *tegra_pcie_io_base; diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h index 401d1b7..39c396d 100644 --- a/arch/arm/mach-tegra/include/mach/powergate.h +++ b/arch/arm/mach-tegra/include/mach/powergate.h @@ -31,7 +31,6 @@ int tegra_powergate_power_on(int id); int tegra_powergate_power_off(int id); -bool tegra_powergate_is_powered(int id); int tegra_powergate_remove_clamping(int id); /* Must be called with clk disabled, and returns with clk enabled */ diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c index ea50fe2..5489f8b 100644 --- a/arch/arm/mach-tegra/io.c +++ b/arch/arm/mach-tegra/io.c @@ -31,25 +31,25 @@ static struct map_desc tegra_io_desc[] __initdata = { { - .virtual = IO_PPSB_VIRT, + .virtual = (unsigned long)IO_PPSB_VIRT, .pfn = __phys_to_pfn(IO_PPSB_PHYS), .length = IO_PPSB_SIZE, .type = MT_DEVICE, }, { - .virtual = IO_APB_VIRT, + .virtual = (unsigned long)IO_APB_VIRT, .pfn = __phys_to_pfn(IO_APB_PHYS), .length = IO_APB_SIZE, .type = MT_DEVICE, }, { - .virtual = IO_CPU_VIRT, + .virtual = (unsigned long)IO_CPU_VIRT, .pfn = __phys_to_pfn(IO_CPU_PHYS), .length = IO_CPU_SIZE, .type = MT_DEVICE, }, { - .virtual = IO_IRAM_VIRT, + .virtual = (unsigned long)IO_IRAM_VIRT, .pfn = __phys_to_pfn(IO_IRAM_PHYS), .length = IO_IRAM_SIZE, .type = MT_DEVICE, diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index f1f699d..f5aa173 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -41,6 +41,8 @@ #include <mach/clk.h> #include <mach/powergate.h> +#include "board.h" + /* register definitions */ #define AFI_OFFSET 0x3800 #define PADS_OFFSET 0x3000 @@ -150,9 +152,9 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); #define pmc_writel(value, reg) \ - __raw_writel(value, (u32)reg_pmc_base + (reg)) + __raw_writel(value, reg_pmc_base + (reg)) #define pmc_readl(reg) \ - __raw_readl((u32)reg_pmc_base + (reg)) + __raw_readl(reg_pmc_base + (reg)) /* * Tegra2 defines 1GB in the AXI address map for PCIe. @@ -460,7 +462,7 @@ static struct pci_bus __init *tegra_pcie_scan_bus(int nr, struct tegra_pcie_port *pp; if (nr >= tegra_pcie.num_ports) - return 0; + return NULL; pp = tegra_pcie.port + nr; pp->root_bus_nr = sys->busnr; diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 3cee9aa..9483064 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -89,12 +89,11 @@ int tegra_powergate_power_off(int id) return tegra_powergate_set(id, false); } -bool tegra_powergate_is_powered(int id) +static bool tegra_powergate_is_powered(int id) { u32 status; - if (id < 0 || id >= TEGRA_NUM_POWERGATE) - return -EINVAL; + WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE); status = pmc_read(PWRGATE_STATUS) & (1 << id); return !!status; diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 0fe9b3e..371869d 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -166,13 +166,13 @@ static DEFINE_SPINLOCK(clock_register_lock); static int tegra_periph_clk_enable_refcount[3 * 32]; #define clk_writel(value, reg) \ - __raw_writel(value, (u32)reg_clk_base + (reg)) + __raw_writel(value, reg_clk_base + (reg)) #define clk_readl(reg) \ - __raw_readl((u32)reg_clk_base + (reg)) + __raw_readl(reg_clk_base + (reg)) #define pmc_writel(value, reg) \ - __raw_writel(value, (u32)reg_pmc_base + (reg)) + __raw_writel(value, reg_pmc_base + (reg)) #define pmc_readl(reg) \ - __raw_readl((u32)reg_pmc_base + (reg)) + __raw_readl(reg_pmc_base + (reg)) unsigned long clk_measure_input_freq(void) { @@ -918,7 +918,7 @@ static struct clk_ops tegra_pll_div_ops = { static void tegra2_periph_clk_init(struct clk *c) { u32 val = clk_readl(c->reg); - const struct clk_mux_sel *mux = 0; + const struct clk_mux_sel *mux = NULL; const struct clk_mux_sel *sel; if (c->flags & MUX) { for (sel = c->inputs; sel->input != NULL; sel++) { @@ -1459,7 +1459,7 @@ static struct clk tegra_pll_s = { static struct clk_mux_sel tegra_clk_m_sel[] = { { .input = &tegra_clk_32k, .value = 0}, { .input = &tegra_pll_s, .value = 1}, - { 0, 0}, + { NULL , 0}, }; static struct clk tegra_clk_m = { @@ -1861,7 +1861,7 @@ static const struct audio_sources { { .name = "ext_audio_clk1", .value = 6 }, { .name = "ext_vimclk", .value = 7 }, #endif - { 0, 0 } + { NULL, 0 } }; static struct clk tegra_clk_audio = { @@ -1885,7 +1885,7 @@ static struct clk tegra_clk_audio_2x = { }, }; -struct clk_lookup tegra_audio_clk_lookups[] = { +static struct clk_lookup tegra_audio_clk_lookups[] = { { .con_id = "audio", .clk = &tegra_clk_audio }, { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x } }; @@ -1926,7 +1926,7 @@ static struct clk_mux_sel mux_cclk[] = { { .input = &tegra_pll_p_out3, .value = 6}, { .input = &tegra_clk_d, .value = 7}, { .input = &tegra_pll_x, .value = 8}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_sclk[] = { @@ -1938,7 +1938,7 @@ static struct clk_mux_sel mux_sclk[] = { { .input = &tegra_clk_d, .value = 5}, { .input = &tegra_clk_32k, .value = 6}, { .input = &tegra_pll_m_out1, .value = 7}, - { 0, 0}, + { NULL, 0}, }; static struct clk tegra_clk_cclk = { @@ -2009,7 +2009,7 @@ static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { { .input = &tegra_pll_c, .value = 1}, { .input = &tegra_pll_p, .value = 2}, { .input = &tegra_pll_a_out0, .value = 3}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { @@ -2017,7 +2017,7 @@ static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { { .input = &tegra_pll_c, .value = 1}, { .input = &tegra_pll_p, .value = 2}, { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { @@ -2025,7 +2025,7 @@ static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { { .input = &tegra_pll_c, .value = 1}, { .input = &tegra_pll_m, .value = 2}, { .input = &tegra_clk_m, .value = 3}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = { @@ -2033,7 +2033,7 @@ static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = { {.input = &tegra_clk_audio_2x, .value = 1}, {.input = &tegra_pll_p, .value = 2}, {.input = &tegra_clk_m, .value = 3}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { @@ -2041,7 +2041,7 @@ static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { {.input = &tegra_pll_d_out0, .value = 1}, {.input = &tegra_pll_c, .value = 2}, {.input = &tegra_clk_m, .value = 3}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = { @@ -2050,39 +2050,39 @@ static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = { {.input = &tegra_clk_audio, .value = 2}, {.input = &tegra_clk_m, .value = 3}, {.input = &tegra_clk_32k, .value = 4}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_pllp_pllc_pllm[] = { {.input = &tegra_pll_p, .value = 0}, {.input = &tegra_pll_c, .value = 1}, {.input = &tegra_pll_m, .value = 2}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_clk_m[] = { { .input = &tegra_clk_m, .value = 0}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_pllp_out3[] = { { .input = &tegra_pll_p_out3, .value = 0}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_plld[] = { { .input = &tegra_pll_d, .value = 0}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_clk_32k[] = { { .input = &tegra_clk_32k, .value = 0}, - { 0, 0}, + { NULL, 0}, }; static struct clk_mux_sel mux_pclk[] = { { .input = &tegra_clk_pclk, .value = 0}, - { 0, 0}, + { NULL, 0}, }; static struct clk tegra_clk_emc = { @@ -2125,7 +2125,7 @@ static struct clk tegra_clk_emc = { .parent = _parent, \ } -struct clk tegra_list_clks[] = { +static struct clk tegra_list_clks[] = { PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0), PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), @@ -2221,7 +2221,7 @@ struct clk tegra_list_clks[] = { * configuration. List those here to register them twice in the clock lookup * table under two names. */ -struct clk_duplicate tegra_clk_duplicates[] = { +static struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("uarta", "tegra_uart.0", NULL), CLK_DUPLICATE("uartb", "tegra_uart.1", NULL), CLK_DUPLICATE("uartc", "tegra_uart.2", NULL), @@ -2252,7 +2252,7 @@ struct clk_duplicate tegra_clk_duplicates[] = { .clk = ck, \ } -struct clk *tegra_ptr_clks[] = { +static struct clk *tegra_ptr_clks[] = { &tegra_clk_32k, &tegra_pll_s, &tegra_clk_m, diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 9035042..e2272d2 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -62,9 +62,9 @@ static struct timespec persistent_ts; static u64 persistent_ms, last_persistent_ms; #define timer_writel(value, reg) \ - __raw_writel(value, (u32)timer_reg_base + (reg)) + __raw_writel(value, timer_reg_base + (reg)) #define timer_readl(reg) \ - __raw_readl((u32)timer_reg_base + (reg)) + __raw_readl(timer_reg_base + (reg)) static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) @@ -133,7 +133,7 @@ static void notrace tegra_update_sched_clock(void) * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ -u64 tegra_rtc_read_ms(void) +static u64 tegra_rtc_read_ms(void) { u32 ms = readl(rtc_base + RTC_MILLISECONDS); u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 7b5c229..1cbcd4f 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -6,6 +6,8 @@ comment "ST-Ericsson Mobile Platform Products" config MACH_U300 bool "U300" + select PINCTRL + select PINMUX_U300 select GPIO_U300 comment "ST-Ericsson U300/U330/U335/U365 Feature Selections" @@ -49,39 +51,12 @@ config MACH_U300_BS365 endchoice -choice - prompt "Memory configuration" - default MACH_U300_SINGLE_RAM - ---help--- - You have to config the kernel according to the physical memory - configuration. - -config MACH_U300_SINGLE_RAM - bool "Single RAM" - help - Select this if you want support for Single RAM phones. - -config MACH_U300_DUAL_RAM - bool "Dual RAM" - help - Select this if you want support for Dual RAM phones. - This is two RAM memories on different EMIFs. -endchoice - config U300_DEBUG bool "Debug support for U300" depends on PM help Debug support for U300 in sysfs, procfs etc. -config MACH_U300_SEMI_IS_SHARED - bool "The SEMI is used by both the access and application side" - depends on MACH_U300 - help - This makes it possible to use the SEMI (Shared External - Memory Interface) from both from access and application - side. - config MACH_U300_SPIDUMMY bool "SSP/SPI dummy chip" select SPI @@ -94,25 +69,6 @@ config MACH_U300_SPIDUMMY you don't need it. Selecting this will activate the SPI framework and ARM PL022 support. -comment "All the settings below must match the bootloader's settings" - -config MACH_U300_ACCESS_MEM_SIZE - int "Access CPU memory allocation" - range 7 25 - depends on MACH_U300_SINGLE_RAM - default 13 - help - How much memory in MiB that the Access side CPU has allocated - -config MACH_U300_2MB_ALIGNMENT_FIX - bool "2MiB alignment fix" - depends on MACH_U300_SINGLE_RAM - default y - help - If yes and the Access side CPU has allocated an odd size in - MiB, this fix gives you one MiB extra that would otherwise be - lost due to Linux 2 MiB alignment policy. - endmenu endif diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile index 8fd354a..2855381 100644 --- a/arch/arm/mach-u300/Makefile +++ b/arch/arm/mach-u300/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel, U300 machine. # -obj-y := core.o clock.o timer.o padmux.o +obj-y := core.o clock.o timer.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-u300/Makefile.boot b/arch/arm/mach-u300/Makefile.boot index 6fbfc6e..87811de 100644 --- a/arch/arm/mach-u300/Makefile.boot +++ b/arch/arm/mach-u300/Makefile.boot @@ -1,15 +1,4 @@ -# Note: the following conditions must always be true: -# ZRELADDR == virt_to_phys(TEXTADDR) -# PARAMS_PHYS must be within 4MB of ZRELADDR -# INITRD_PHYS must be in RAM - -ifdef CONFIG_MACH_U300_SINGLE_RAM - zreladdr-y := 0x28E08000 - params_phys-y := 0x28E00100 -else - zreladdr-y := 0x48008000 - params_phys-y := 0x48000100 -endif - + zreladdr-y += 0x48008000 +params_phys-y := 0x48000100 # This isn't used. -#initrd_phys-y := 0x29800000 +#initrd_phys-y := 0x48800000 diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 22c5ab7..ac0791e 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -25,6 +25,8 @@ #include <linux/err.h> #include <linux/mtd/nand.h> #include <linux/mtd/fsmc.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinmux.h> #include <linux/dma-mapping.h> #include <asm/types.h> @@ -70,25 +72,6 @@ static struct map_desc u300_io_desc[] __initdata = { .length = SZ_32K, .type = MT_DEVICE, }, - { - .virtual = 0xffff2000, /* TCM memory */ - .pfn = __phys_to_pfn(0xffff2000), - .length = SZ_16K, - .type = MT_DEVICE, - }, - - /* - * This overlaps with the IRQ vectors etc at 0xffff0000, so these - * may have to be moved to 0x00000000 in order to use the ROM. - */ - /* - { - .virtual = U300_BOOTROM_VIRT_BASE, - .pfn = __phys_to_pfn(U300_BOOTROM_PHYS_BASE), - .length = SZ_64K, - .type = MT_ROM, - }, - */ }; void __init u300_map_io(void) @@ -365,51 +348,6 @@ static struct resource wdog_resources[] = { } }; -/* TODO: These should be protected by suitable #ifdef's */ -static struct resource ave_resources[] = { - { - .name = "AVE3e I/O Area", - .start = U300_VIDEOENC_BASE, - .end = U300_VIDEOENC_BASE + SZ_512K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "AVE3e IRQ0", - .start = IRQ_U300_VIDEO_ENC_0, - .end = IRQ_U300_VIDEO_ENC_0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "AVE3e IRQ1", - .start = IRQ_U300_VIDEO_ENC_1, - .end = IRQ_U300_VIDEO_ENC_1, - .flags = IORESOURCE_IRQ, - }, - { - .name = "AVE3e Physmem Area", - .start = 0, /* 0 will be remapped to reserved memory */ - .end = SZ_1M - 1, - .flags = IORESOURCE_MEM, - }, - /* - * The AVE3e requires two regions of 256MB that it considers - * "invisible". The hardware will not be able to access these - * addresses, so they should never point to system RAM. - */ - { - .name = "AVE3e Reserved 0", - .start = 0xd0000000, - .end = 0xd0000000 + SZ_256M - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "AVE3e Reserved 1", - .start = 0xe0000000, - .end = 0xe0000000 + SZ_256M - 1, - .flags = IORESOURCE_MEM, - }, -}; - static struct resource dma_resource[] = { { .start = U300_DMAC_BASE, @@ -1539,6 +1477,14 @@ static struct coh901318_platform coh901318_platform = { .max_channels = U300_DMA_CHANNELS, }; +static struct resource pinmux_resources[] = { + { + .start = U300_SYSCON_BASE, + .end = U300_SYSCON_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + static struct platform_device wdog_device = { .name = "coh901327_wdog", .id = -1, @@ -1640,13 +1586,6 @@ static struct platform_device nand_device = { }, }; -static struct platform_device ave_device = { - .name = "video_enc", - .id = -1, - .num_resources = ARRAY_SIZE(ave_resources), - .resource = ave_resources, -}; - static struct platform_device dma_device = { .name = "coh901318", .id = -1, @@ -1658,6 +1597,72 @@ static struct platform_device dma_device = { }, }; +static struct platform_device pinmux_device = { + .name = "pinmux-u300", + .id = -1, + .num_resources = ARRAY_SIZE(pinmux_resources), + .resource = pinmux_resources, +}; + +/* Pinmux settings */ +static struct pinmux_map u300_pinmux_map[] = { + /* anonymous maps for chip power and EMIFs */ + PINMUX_MAP_PRIMARY_SYS_HOG("POWER", "power"), + PINMUX_MAP_PRIMARY_SYS_HOG("EMIF0", "emif0"), + PINMUX_MAP_PRIMARY_SYS_HOG("EMIF1", "emif1"), + /* per-device maps for MMC/SD, SPI and UART */ + PINMUX_MAP_PRIMARY("MMCSD", "mmc0", "mmci"), + PINMUX_MAP_PRIMARY("SPI", "spi0", "pl022"), + PINMUX_MAP_PRIMARY("UART0", "uart0", "uart0"), +}; + +struct u300_mux_hog { + const char *name; + struct device *dev; + struct pinmux *pmx; +}; + +static struct u300_mux_hog u300_mux_hogs[] = { + { + .name = "uart0", + .dev = &uart0_device.dev, + }, + { + .name = "spi0", + .dev = &pl022_device.dev, + }, + { + .name = "mmc0", + .dev = &mmcsd_device.dev, + }, +}; + +static int __init u300_pinmux_fetch(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) { + struct pinmux *pmx; + int ret; + + pmx = pinmux_get(u300_mux_hogs[i].dev, NULL); + if (IS_ERR(pmx)) { + pr_err("u300: could not get pinmux hog %s\n", + u300_mux_hogs[i].name); + continue; + } + ret = pinmux_enable(pmx); + if (ret) { + pr_err("u300: could enable pinmux hog %s\n", + u300_mux_hogs[i].name); + continue; + } + u300_mux_hogs[i].pmx = pmx; + } + return 0; +} +subsys_initcall(u300_pinmux_fetch); + /* * Notice that AMBA devices are initialized before platform devices. * @@ -1671,10 +1676,9 @@ static struct platform_device *platform_devs[] __initdata = { &gpio_device, &nand_device, &wdog_device, - &ave_device + &pinmux_device, }; - /* * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected * together so some interrupts are connected to the first one and some @@ -1856,6 +1860,10 @@ void __init u300_init_devices(void) u300_assign_physmem(); + /* Initialize pinmuxing */ + pinmux_register_mappings(u300_pinmux_map, + ARRAY_SIZE(u300_pinmux_map)); + /* Register subdevices on the I2C buses */ u300_i2c_register_board_devices(); @@ -1865,17 +1873,10 @@ void __init u300_init_devices(void) /* Register subdevices on the SPI bus */ u300_spi_register_board_devices(); -#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED - /* - * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when - * both subsystems are requesting this mode. - * If we not share the Acc SDRAM, this is never the case. Therefore - * enable it here from the App side. - */ + /* Enable SEMI self refresh */ val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) | U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR); -#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */ } static int core_module_init(void) diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h index e69de29..40a8c17 100644 --- a/arch/arm/mach-u300/include/mach/gpio.h +++ b/arch/arm/mach-u300/include/mach/gpio.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h index 7034bae..c808f34 100644 --- a/arch/arm/mach-u300/include/mach/memory.h +++ b/arch/arm/mach-u300/include/mach/memory.h @@ -13,25 +13,7 @@ #ifndef __MACH_MEMORY_H #define __MACH_MEMORY_H -#ifdef CONFIG_MACH_U300_DUAL_RAM - -#define PLAT_PHYS_OFFSET UL(0x48000000) -#define BOOT_PARAMS_OFFSET 0x100 - -#else - -#ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX -#define PLAT_PHYS_OFFSET (0x28000000 + \ - (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \ - (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) -#define BOOT_PARAMS_OFFSET (0x100 + \ - (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1)*1024*1024*2) -#else -#define PLAT_PHYS_OFFSET (0x28000000 + \ - (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \ - (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) -#define BOOT_PARAMS_OFFSET 0x100 -#endif -#endif +#define PLAT_PHYS_OFFSET UL(0x48000000) +#define BOOT_PARAMS_OFFSET 0x100 #endif diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h index 7444f5c..6e84f07 100644 --- a/arch/arm/mach-u300/include/mach/syscon.h +++ b/arch/arm/mach-u300/include/mach/syscon.h @@ -234,91 +234,6 @@ #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) -/* PAD MUX Control register 1 (LOW) 16bit (R/W) */ -#define U300_SYSCON_PMC1LR (0x007C) -#define U300_SYSCON_PMC1LR_MASK (0xFFFF) -#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000) -#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000) -#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000) -#ifdef CONFIG_MACH_U300_BS335 -#define U300_SYSCON_PMC1LR_CDI_CDI2 (0x8000) -#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO (0xC000) -#elif CONFIG_MACH_U300_BS365 -#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000) -#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000) -#endif -#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000) -#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000) -#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000) -#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000) -#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00) -#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000) -#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400) -#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800) -#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00) -#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300) -#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000) -#define U300_SYSCON_PMC1LR_ETM_APP (0x0100) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080) -#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020) -#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008) -#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C) -#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003) -#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000) -#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001) -#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002) -#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003) -/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ -#define U300_SYSCON_PMC1HR (0x007E) -#define U300_SYSCON_PMC1HR_MASK (0xFFFF) -#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000) -#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000) -#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000) -#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000) -#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800) -#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040) -#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0) -#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030) -#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010) -#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020) -#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030) -#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C) -#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004) -#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008) -#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C) -#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003) -#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000) -#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001) -#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003) /* Step one for killing the applications system 16bit (-/W) */ #define U300_SYSCON_KA1R (0x0080) #define U300_SYSCON_KA1R_MASK (0xFFFF) @@ -357,57 +272,6 @@ #define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080) #define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040) #define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F) -/* Padmux 2 control */ -#define U300_SYSCON_PMC2R (0x100) -#define U300_SYSCON_PMC2R_APP_MISC_0_MASK (0x00C0) -#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM (0x0040) -#define U300_SYSCON_PMC2R_APP_MISC_0_MMC (0x0080) -#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 (0x00C0) -#define U300_SYSCON_PMC2R_APP_MISC_1_MASK (0x0300) -#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM (0x0100) -#define U300_SYSCON_PMC2R_APP_MISC_1_MMC (0x0200) -#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 (0x0300) -#define U300_SYSCON_PMC2R_APP_MISC_2_MASK (0x0C00) -#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM (0x0400) -#define U300_SYSCON_PMC2R_APP_MISC_2_MMC (0x0800) -#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 (0x0C00) -#define U300_SYSCON_PMC2R_APP_MISC_3_MASK (0x3000) -#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM (0x1000) -#define U300_SYSCON_PMC2R_APP_MISC_3_MMC (0x2000) -#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 (0x3000) -#define U300_SYSCON_PMC2R_APP_MISC_4_MASK (0xC000) -#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO (0x0000) -#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM (0x4000) -#define U300_SYSCON_PMC2R_APP_MISC_4_MMC (0x8000) -#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO (0xC000) -/* TODO: More SYSCON registers missing */ -#define U300_SYSCON_PMC3R (0x10c) -#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000) -#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000) -#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000) -#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000) -/* TODO: Missing other configs */ -#define U300_SYSCON_PMC4R (0x168) -#define U300_SYSCON_PMC4R_APP_MISC_12_MASK (0x0003) -#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO (0x0000) -#define U300_SYSCON_PMC4R_APP_MISC_13_MASK (0x000C) -#define U300_SYSCON_PMC4R_APP_MISC_13_CDI (0x0000) -#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA (0x0004) -#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 (0x0008) -#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO (0x000C) -#define U300_SYSCON_PMC4R_APP_MISC_14_MASK (0x0030) -#define U300_SYSCON_PMC4R_APP_MISC_14_CDI (0x0000) -#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA (0x0010) -#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 (0x0020) -#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO (0x0030) -#define U300_SYSCON_PMC4R_APP_MISC_16_MASK (0x0300) -#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 (0x0000) -#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS (0x0100) -#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N (0x0200) /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ #define U300_SYSCON_S0CCR (0x120) #define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c index d9a5c92..4d482aa 100644 --- a/arch/arm/mach-u300/mmc.c +++ b/arch/arm/mach-u300/mmc.c @@ -21,7 +21,6 @@ #include <mach/gpio-u300.h> #include "mmc.h" -#include "padmux.h" static struct mmci_platform_data mmc0_plat_data = { /* @@ -45,24 +44,9 @@ static struct mmci_platform_data mmc0_plat_data = { int __devinit mmc_init(struct amba_device *adev) { struct device *mmcsd_device = &adev->dev; - struct pmx *pmx; int ret = 0; mmcsd_device->platform_data = &mmc0_plat_data; - /* - * Setup padmuxing for MMC. Since this must always be - * compiled into the kernel, pmx is never released. - */ - pmx = pmx_get(mmcsd_device, U300_APP_PMX_MMC_SETTING); - - if (IS_ERR(pmx)) - pr_warning("Could not get padmux handle\n"); - else { - ret = pmx_activate(mmcsd_device, pmx); - if (IS_ERR_VALUE(ret)) - pr_warning("Could not activate padmuxing\n"); - } - return ret; } diff --git a/arch/arm/mach-u300/padmux.c b/arch/arm/mach-u300/padmux.c deleted file mode 100644 index 4c93c6c..0000000 --- a/arch/arm/mach-u300/padmux.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * - * arch/arm/mach-u300/padmux.c - * - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * U300 PADMUX functions - * Author: Martin Persson <martin.persson@stericsson.com> - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/err.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/mutex.h> -#include <linux/string.h> -#include <linux/bug.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <mach/u300-regs.h> -#include <mach/syscon.h> -#include "padmux.h" - -static DEFINE_MUTEX(pmx_mutex); - -const u32 pmx_registers[] = { - (U300_SYSCON_VBASE + U300_SYSCON_PMC1LR), - (U300_SYSCON_VBASE + U300_SYSCON_PMC1HR), - (U300_SYSCON_VBASE + U300_SYSCON_PMC2R), - (U300_SYSCON_VBASE + U300_SYSCON_PMC3R), - (U300_SYSCON_VBASE + U300_SYSCON_PMC4R) -}; - -/* High level functionality */ - -/* Lazy dog: - * onmask = { - * {"PMC1LR" mask, "PMC1LR" value}, - * {"PMC1HR" mask, "PMC1HR" value}, - * {"PMC2R" mask, "PMC2R" value}, - * {"PMC3R" mask, "PMC3R" value}, - * {"PMC4R" mask, "PMC4R" value} - * } - */ -static struct pmx mmc_setting = { - .setting = U300_APP_PMX_MMC_SETTING, - .default_on = false, - .activated = false, - .name = "MMC", - .onmask = { - {U300_SYSCON_PMC1LR_MMCSD_MASK, - U300_SYSCON_PMC1LR_MMCSD_MMCSD}, - {0, 0}, - {0, 0}, - {0, 0}, - {U300_SYSCON_PMC4R_APP_MISC_12_MASK, - U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO} - }, -}; - -static struct pmx spi_setting = { - .setting = U300_APP_PMX_SPI_SETTING, - .default_on = false, - .activated = false, - .name = "SPI", - .onmask = {{0, 0}, - {U300_SYSCON_PMC1HR_APP_SPI_2_MASK | - U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK | - U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK, - U300_SYSCON_PMC1HR_APP_SPI_2_SPI | - U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI | - U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI}, - {0, 0}, - {0, 0}, - {0, 0} - }, -}; - -/* Available padmux settings */ -static struct pmx *pmx_settings[] = { - &mmc_setting, - &spi_setting, -}; - -static void update_registers(struct pmx *pmx, bool activate) -{ - u16 regval, val, mask; - int i; - - for (i = 0; i < ARRAY_SIZE(pmx_registers); i++) { - if (activate) - val = pmx->onmask[i].val; - else - val = 0; - - mask = pmx->onmask[i].mask; - if (mask != 0) { - regval = readw(pmx_registers[i]); - regval &= ~mask; - regval |= val; - writew(regval, pmx_registers[i]); - } - } -} - -struct pmx *pmx_get(struct device *dev, enum pmx_settings setting) -{ - int i; - struct pmx *pmx = ERR_PTR(-ENOENT); - - if (dev == NULL) - return ERR_PTR(-EINVAL); - - mutex_lock(&pmx_mutex); - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (setting == pmx_settings[i]->setting) { - - if (pmx_settings[i]->dev != NULL) { - WARN(1, "padmux: required setting " - "in use by another consumer\n"); - } else { - pmx = pmx_settings[i]; - pmx->dev = dev; - dev_dbg(dev, "padmux: setting nr %d is now " - "bound to %s and ready to use\n", - setting, dev_name(dev)); - break; - } - } - } - mutex_unlock(&pmx_mutex); - - return pmx; -} -EXPORT_SYMBOL(pmx_get); - -int pmx_put(struct device *dev, struct pmx *pmx) -{ - int i; - int ret = -ENOENT; - - if (pmx == NULL || dev == NULL) - return -EINVAL; - - mutex_lock(&pmx_mutex); - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (pmx->setting == pmx_settings[i]->setting) { - - if (dev != pmx->dev) { - WARN(1, "padmux: cannot release handle as " - "it is bound to another consumer\n"); - ret = -EINVAL; - break; - } else { - pmx_settings[i]->dev = NULL; - ret = 0; - break; - } - } - } - mutex_unlock(&pmx_mutex); - - return ret; -} -EXPORT_SYMBOL(pmx_put); - -int pmx_activate(struct device *dev, struct pmx *pmx) -{ - int i, j, ret; - ret = 0; - - if (pmx == NULL || dev == NULL) - return -EINVAL; - - mutex_lock(&pmx_mutex); - - /* Make sure the required bits are not used */ - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (pmx_settings[i]->dev == NULL || pmx_settings[i] == pmx) - continue; - - for (j = 0; j < ARRAY_SIZE(pmx_registers); j++) { - - if (pmx_settings[i]->onmask[j].mask & pmx-> - onmask[j].mask) { - /* More than one entry on the same bits */ - WARN(1, "padmux: cannot activate " - "setting. Bit conflict with " - "an active setting\n"); - - ret = -EUSERS; - goto exit; - } - } - } - update_registers(pmx, true); - pmx->activated = true; - dev_dbg(dev, "padmux: setting nr %d is activated\n", - pmx->setting); - -exit: - mutex_unlock(&pmx_mutex); - return ret; -} -EXPORT_SYMBOL(pmx_activate); - -int pmx_deactivate(struct device *dev, struct pmx *pmx) -{ - int i; - int ret = -ENOENT; - - if (pmx == NULL || dev == NULL) - return -EINVAL; - - mutex_lock(&pmx_mutex); - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (pmx_settings[i]->dev == NULL) - continue; - - if (pmx->setting == pmx_settings[i]->setting) { - - if (dev != pmx->dev) { - WARN(1, "padmux: cannot deactivate " - "pmx setting as it was activated " - "by another consumer\n"); - - ret = -EBUSY; - continue; - } else { - update_registers(pmx, false); - pmx_settings[i]->dev = NULL; - pmx->activated = false; - ret = 0; - dev_dbg(dev, "padmux: setting nr %d is deactivated", - pmx->setting); - break; - } - } - } - mutex_unlock(&pmx_mutex); - - return ret; -} -EXPORT_SYMBOL(pmx_deactivate); - -/* - * For internal use only. If it is to be exported, - * it should be reentrant. Notice that pmx_activate - * (i.e. runtime settings) always override default settings. - */ -static int pmx_set_default(void) -{ - /* Used to identify several entries on the same bits */ - u16 modbits[ARRAY_SIZE(pmx_registers)]; - - int i, j; - - memset(modbits, 0, ARRAY_SIZE(pmx_registers) * sizeof(u16)); - - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - - if (!pmx_settings[i]->default_on) - continue; - - for (j = 0; j < ARRAY_SIZE(pmx_registers); j++) { - - /* Make sure there is only one entry on the same bits */ - if (modbits[j] & pmx_settings[i]->onmask[j].mask) { - BUG(); - return -EUSERS; - } - modbits[j] |= pmx_settings[i]->onmask[j].mask; - } - update_registers(pmx_settings[i], true); - } - return 0; -} - -#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) -static int pmx_show(struct seq_file *s, void *data) -{ - int i; - seq_printf(s, "-------------------------------------------------\n"); - seq_printf(s, "SETTING BOUND TO DEVICE STATE\n"); - seq_printf(s, "-------------------------------------------------\n"); - mutex_lock(&pmx_mutex); - for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { - /* Format pmx and device name nicely */ - char cdp[33]; - int chars; - - chars = snprintf(&cdp[0], 17, "%s", pmx_settings[i]->name); - while (chars < 16) { - cdp[chars] = ' '; - chars++; - } - chars = snprintf(&cdp[16], 17, "%s", pmx_settings[i]->dev ? - dev_name(pmx_settings[i]->dev) : "N/A"); - while (chars < 16) { - cdp[chars+16] = ' '; - chars++; - } - cdp[32] = '\0'; - - seq_printf(s, - "%s\t%s\n", - &cdp[0], - pmx_settings[i]->activated ? - "ACTIVATED" : "DEACTIVATED" - ); - - } - mutex_unlock(&pmx_mutex); - return 0; -} - -static int pmx_open(struct inode *inode, struct file *file) -{ - return single_open(file, pmx_show, NULL); -} - -static const struct file_operations pmx_operations = { - .owner = THIS_MODULE, - .open = pmx_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init init_pmx_read_debugfs(void) -{ - /* Expose a simple debugfs interface to view pmx settings */ - (void) debugfs_create_file("padmux", S_IFREG | S_IRUGO, - NULL, NULL, - &pmx_operations); - return 0; -} - -/* - * This needs to come in after the core_initcall(), - * because debugfs is not available until - * the subsystems come up. - */ -module_init(init_pmx_read_debugfs); -#endif - -static int __init pmx_init(void) -{ - int ret; - - ret = pmx_set_default(); - - if (IS_ERR_VALUE(ret)) - pr_crit("padmux: default settings could not be set\n"); - - return 0; -} - -/* Should be initialized before consumers */ -core_initcall(pmx_init); diff --git a/arch/arm/mach-u300/padmux.h b/arch/arm/mach-u300/padmux.h deleted file mode 100644 index 6e8b860..0000000 --- a/arch/arm/mach-u300/padmux.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * - * arch/arm/mach-u300/padmux.h - * - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * U300 PADMUX API - * Author: Martin Persson <martin.persson@stericsson.com> - */ - -#ifndef __MACH_U300_PADMUX_H -#define __MACH_U300_PADMUX_H - -enum pmx_settings { - U300_APP_PMX_MMC_SETTING, - U300_APP_PMX_SPI_SETTING -}; - -struct pmx_onmask { - u16 mask; /* Mask bits */ - u16 val; /* Value when active */ -}; - -struct pmx { - struct device *dev; - enum pmx_settings setting; - char *name; - bool activated; - bool default_on; - struct pmx_onmask onmask[]; -}; - -struct pmx *pmx_get(struct device *dev, enum pmx_settings setting); -int pmx_put(struct device *dev, struct pmx *pmx); -int pmx_activate(struct device *dev, struct pmx *pmx); -int pmx_deactivate(struct device *dev, struct pmx *pmx); - -#endif diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c index 7b597e2..a1affac 100644 --- a/arch/arm/mach-u300/spi.c +++ b/arch/arm/mach-u300/spi.c @@ -14,8 +14,6 @@ #include <mach/coh901318.h> #include <mach/dma_channels.h> -#include "padmux.h" - /* * The following is for the actual devices on the SSP/SPI bus */ @@ -95,25 +93,7 @@ static struct pl022_ssp_controller ssp_platform_data = { void __init u300_spi_init(struct amba_device *adev) { - struct pmx *pmx; - adev->dev.platform_data = &ssp_platform_data; - /* - * Setup padmuxing for SPI. Since this must always be - * compiled into the kernel, pmx is never released. - */ - pmx = pmx_get(&adev->dev, U300_APP_PMX_SPI_SETTING); - - if (IS_ERR(pmx)) - dev_warn(&adev->dev, "Could not get padmux handle\n"); - else { - int ret; - - ret = pmx_activate(&adev->dev, pmx); - if (IS_ERR_VALUE(ret)) - dev_warn(&adev->dev, "Could not activate padmuxing\n"); - } - } void __init u300_spi_register_board_devices(void) diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c index 80e7305..89422ee 100644 --- a/arch/arm/mach-u300/u300.c +++ b/arch/arm/mach-u300/u300.c @@ -23,21 +23,6 @@ #include <asm/mach/arch.h> #include <asm/memory.h> -static void __init u300_reserve(void) -{ - /* - * U300 - This platform family can share physical memory - * between two ARM cpus, one running Linux and the other - * running another OS. - */ -#ifdef CONFIG_MACH_U300_SINGLE_RAM -#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \ - CONFIG_MACH_U300_2MB_ALIGNMENT_FIX - memblock_reserve(PHYS_OFFSET, 0x00100000); -#endif -#endif -} - static void __init u300_init_machine(void) { u300_init_devices(); @@ -63,7 +48,6 @@ MACHINE_START(U300, MACH_U300_STRING) /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ .atag_offset = BOOT_PARAMS_OFFSET, .map_io = u300_map_io, - .reserve = u300_reserve, .init_irq = u300_init_irq, .timer = &u300_timer, .init_machine = u300_init_machine, diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 4210cb4..a3e0c86 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -6,6 +6,7 @@ config UX500_SOC_COMMON select ARM_GIC select HAS_MTU select ARM_ERRATA_753970 + select ARM_ERRATA_754322 menu "Ux500 SoC" diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 1694916..6bd2f45 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -3,7 +3,8 @@ # obj-y := clock.o cpu.o devices.o devices-common.o \ - id.o usb.o + id.o usb.o timer.o +obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot index c7e75ac..ff0a4b5 100644 --- a/arch/arm/mach-ux500/Makefile.boot +++ b/arch/arm/mach-ux500/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 15b23e4..74bfcff 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -153,7 +153,7 @@ static pin_cfg_t mop500_pins_default[] = { GPIO7_U1_RTSn | PIN_OUTPUT_HIGH, }; -static pin_cfg_t mop500_pins_hrefv60[] = { +static pin_cfg_t hrefv60_pins[] = { /* WLAN */ GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */ @@ -279,14 +279,26 @@ static pin_cfg_t snowball_pins[] = { void __init mop500_pins_init(void) { nmk_config_pins(mop500_pins_common, - ARRAY_SIZE(mop500_pins_common)); - if (machine_is_hrefv60()) - nmk_config_pins(mop500_pins_hrefv60, - ARRAY_SIZE(mop500_pins_hrefv60)); - else if (machine_is_snowball()) - nmk_config_pins(snowball_pins, - ARRAY_SIZE(snowball_pins)); - else - nmk_config_pins(mop500_pins_default, - ARRAY_SIZE(mop500_pins_default)); + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(mop500_pins_default, + ARRAY_SIZE(mop500_pins_default)); +} + +void __init snowball_pins_init(void) +{ + nmk_config_pins(mop500_pins_common, + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(snowball_pins, + ARRAY_SIZE(snowball_pins)); +} + +void __init hrefv60_pins_init(void) +{ + nmk_config_pins(mop500_pins_common, + ARRAY_SIZE(mop500_pins_common)); + + nmk_config_pins(hrefv60_pins, + ARRAY_SIZE(hrefv60_pins)); } diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index d0cb9e5..6826fae 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -216,30 +216,48 @@ void __init mop500_sdi_init(void) /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */ if (!cpu_is_u8500v10()) mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; - /* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */ - if (!machine_is_snowball()) - db8500_add_sdi2(&mop500_sdi2_data, periphid); + + db8500_add_sdi2(&mop500_sdi2_data, periphid); /* On-board eMMC */ db8500_add_sdi4(&mop500_sdi4_data, periphid); - if (machine_is_hrefv60() || machine_is_snowball()) { - if (machine_is_hrefv60()) { - mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; - sdi0_en = HREFV60_SDMMC_EN_GPIO; - sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; - } else if (machine_is_snowball()) { - mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; - mop500_sdi0_data.cd_invert = true; - sdi0_en = SNOWBALL_SDMMC_EN_GPIO; - sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; - } - sdi0_configure(); - } - /* * On boards with the TC35892 GPIO expander, sdi0 will finally * be added when the TC35892 initializes and calls * mop500_sdi_tc35892_init() above. */ } + +void __init snowball_sdi_init(void) +{ + u32 periphid = 0x10480180; + + mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; + + /* On-board eMMC */ + db8500_add_sdi4(&mop500_sdi4_data, periphid); + + mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; + mop500_sdi0_data.cd_invert = true; + sdi0_en = SNOWBALL_SDMMC_EN_GPIO; + sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; + sdi0_configure(); +} + +void __init hrefv60_sdi_init(void) +{ + u32 periphid = 0x10480180; + + mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; + + db8500_add_sdi2(&mop500_sdi2_data, periphid); + + /* On-board eMMC */ + db8500_add_sdi4(&mop500_sdi4_data, periphid); + + mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; + sdi0_en = HREFV60_SDMMC_EN_GPIO; + sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; + sdi0_configure(); +} diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index f67b83d..bdd7b80 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -604,28 +604,72 @@ static void __init mop500_init_machine(void) { int i2c0_devs; + mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; + + u8500_init_devices(); + + mop500_pins_init(); + + platform_add_devices(mop500_platform_devs, + ARRAY_SIZE(mop500_platform_devs)); + + mop500_i2c_init(); + mop500_sdi_init(); + mop500_spi_init(); + mop500_uart_init(); + + i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); + + i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); + i2c_register_board_info(2, mop500_i2c2_devices, + ARRAY_SIZE(mop500_i2c2_devices)); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); +} + +static void __init snowball_init_machine(void) +{ + int i2c0_devs; + + u8500_init_devices(); + + snowball_pins_init(); + + platform_add_devices(snowball_platform_devs, + ARRAY_SIZE(snowball_platform_devs)); + + mop500_i2c_init(); + snowball_sdi_init(); + mop500_spi_init(); + mop500_uart_init(); + + i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); + i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); + i2c_register_board_info(2, mop500_i2c2_devices, + ARRAY_SIZE(mop500_i2c2_devices)); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); +} + +static void __init hrefv60_init_machine(void) +{ + int i2c0_devs; + /* * The HREFv60 board removed a GPIO expander and routed * all these GPIO pins to the internal GPIO controller * instead. */ - if (!machine_is_snowball()) { - if (machine_is_hrefv60()) - mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; - else - mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; - } + mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; u8500_init_devices(); - mop500_pins_init(); + hrefv60_pins_init(); - if (machine_is_snowball()) - platform_add_devices(snowball_platform_devs, - ARRAY_SIZE(snowball_platform_devs)); - else - platform_add_devices(mop500_platform_devs, - ARRAY_SIZE(mop500_platform_devs)); + platform_add_devices(mop500_platform_devs, + ARRAY_SIZE(mop500_platform_devs)); mop500_i2c_init(); mop500_sdi_init(); @@ -633,8 +677,8 @@ static void __init mop500_init_machine(void) mop500_uart_init(); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); - if (machine_is_hrefv60()) - i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; + + i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(2, mop500_i2c2_devices, @@ -659,7 +703,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") .map_io = u8500_map_io, .init_irq = ux500_init_irq, .timer = &ux500_timer, - .init_machine = mop500_init_machine, + .init_machine = hrefv60_init_machine, MACHINE_END MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") @@ -668,5 +712,5 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ .timer = &ux500_timer, - .init_machine = mop500_init_machine, + .init_machine = snowball_init_machine, MACHINE_END diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index ee77a89..de18a2a 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -40,10 +40,13 @@ struct i2c_board_info; extern void mop500_sdi_init(void); +extern void snowball_sdi_init(void); extern void mop500_sdi_tc35892_init(void); void __init mop500_u8500uib_init(void); void __init mop500_stuib_init(void); void __init mop500_pins_init(void); +void __init hrefv60_pins_init(void); +void __init snowball_pins_init(void); void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, unsigned n); diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c new file mode 100644 index 0000000..122ddde --- /dev/null +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/io.h> +#include <asm/cacheflush.h> +#include <asm/hardware/cache-l2x0.h> +#include <mach/hardware.h> +#include <mach/id.h> + +static void __iomem *l2x0_base; + +static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) +{ + /* wait for the operation to complete */ + while (readl_relaxed(reg) & mask) + cpu_relax(); +} + +static inline void ux500_cache_sync(void) +{ + writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC); + ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1); +} + +/* + * The L2 cache cannot be turned off in the non-secure world. + * Dummy until a secure service is in place. + */ +static void ux500_l2x0_disable(void) +{ +} + +/* + * This is only called when doing a kexec, just after turning off the L2 + * and L1 cache, and it is surrounded by a spinlock in the generic version. + * However, we're not really turning off the L2 cache right now and the + * PL310 does not support exclusive accesses (used to implement the spinlock). + * So, the invalidation needs to be done without the spinlock. + */ +static void ux500_l2x0_inv_all(void) +{ + uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ + + /* invalidate all ways */ + writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); + ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); + ux500_cache_sync(); +} + +static int __init ux500_l2x0_unlock(void) +{ + int i; + + /* + * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions + * apparently locks both caches before jumping to the kernel. The + * l2x0 core will not touch the unlock registers if the l2x0 is + * already enabled, so we do it right here instead. The PL310 has + * 8 sets of registers, one per possible CPU. + */ + for (i = 0; i < 8; i++) { + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + + i * L2X0_LOCKDOWN_STRIDE); + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + + i * L2X0_LOCKDOWN_STRIDE); + } + return 0; +} + +static int __init ux500_l2x0_init(void) +{ + if (cpu_is_u5500()) + l2x0_base = __io_address(U5500_L2CC_BASE); + else if (cpu_is_u8500()) + l2x0_base = __io_address(U8500_L2CC_BASE); + else + ux500_unknown_soc(); + + /* Unlock before init */ + ux500_l2x0_unlock(); + + /* 64KB way size, 8 way associativity, force WA */ + l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); + + /* Override invalidate function */ + outer_cache.disable = ux500_l2x0_disable; + outer_cache.inv_all = ux500_l2x0_inv_all; + + return 0; +} + +early_initcall(ux500_l2x0_init); diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 1da23bb..1405d0e 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -10,14 +10,12 @@ #include <linux/clk.h> #include <linux/mfd/db8500-prcmu.h> #include <linux/mfd/db5500-prcmu.h> +#include <linux/clksrc-dbx500-prcmu.h> -#include <asm/cacheflush.h> -#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/gic.h> #include <asm/mach/map.h> #include <asm/localtimer.h> -#include <plat/mtu.h> #include <mach/hardware.h> #include <mach/setup.h> #include <mach/devices.h> @@ -26,10 +24,6 @@ void __iomem *_PRCMU_BASE; -#ifdef CONFIG_CACHE_L2X0 -static void __iomem *l2x0_base; -#endif - void __init ux500_init_irq(void) { void __iomem *dist_base; @@ -56,93 +50,3 @@ void __init ux500_init_irq(void) prcmu_early_init(); clk_init(); } - -#ifdef CONFIG_CACHE_L2X0 -static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) -{ - /* wait for the operation to complete */ - while (readl_relaxed(reg) & mask) - ; -} - -static inline void ux500_cache_sync(void) -{ - void __iomem *base = l2x0_base; - - writel_relaxed(0, base + L2X0_CACHE_SYNC); - ux500_cache_wait(base + L2X0_CACHE_SYNC, 1); -} - -/* - * The L2 cache cannot be turned off in the non-secure world. - * Dummy until a secure service is in place. - */ -static void ux500_l2x0_disable(void) -{ -} - -/* - * This is only called when doing a kexec, just after turning off the L2 - * and L1 cache, and it is surrounded by a spinlock in the generic version. - * However, we're not really turning off the L2 cache right now and the - * PL310 does not support exclusive accesses (used to implement the spinlock). - * So, the invalidation needs to be done without the spinlock. - */ -static void ux500_l2x0_inv_all(void) -{ - void __iomem *base = l2x0_base; - uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ - - /* invalidate all ways */ - writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY); - ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask); - ux500_cache_sync(); -} - -static int ux500_l2x0_init(void) -{ - if (cpu_is_u5500()) - l2x0_base = __io_address(U5500_L2CC_BASE); - else if (cpu_is_u8500()) - l2x0_base = __io_address(U8500_L2CC_BASE); - else - ux500_unknown_soc(); - - /* 64KB way size, 8 way associativity, force WA */ - l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); - - /* Override invalidate function */ - outer_cache.disable = ux500_l2x0_disable; - outer_cache.inv_all = ux500_l2x0_inv_all; - - return 0; -} -early_initcall(ux500_l2x0_init); -#endif - -static void __init ux500_timer_init(void) -{ -#ifdef CONFIG_LOCAL_TIMERS - /* Setup the local timer base */ - if (cpu_is_u5500()) - twd_base = __io_address(U5500_TWD_BASE); - else if (cpu_is_u8500()) - twd_base = __io_address(U8500_TWD_BASE); - else - ux500_unknown_soc(); -#endif - if (cpu_is_u5500()) - mtu_base = __io_address(U5500_MTU0_BASE); - else if (cpu_is_u8500ed()) - mtu_base = __io_address(U8500_MTU0_BASE_ED); - else if (cpu_is_u8500()) - mtu_base = __io_address(U8500_MTU0_BASE); - else - ux500_unknown_soc(); - - nmdk_timer_init(); -} - -struct sys_timer ux500_timer = { - .init = ux500_timer_init, -}; diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 6ad9832..994b5fe 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -61,6 +61,8 @@ #define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) #define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) #define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) +#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338) +#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 0499971..751b0e6 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -102,10 +102,13 @@ #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) +#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) +#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) + /* per3 base addresses */ #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) #define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 7dd0807..6fb3c4b 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -51,15 +51,9 @@ static void flush(void) static inline void arch_decomp_setup(void) { /* Check in run time if we run on an U8500 or U5500 */ - if (machine_is_u8500() || - machine_is_svp8500v1() || - machine_is_svp8500v2() || - machine_is_hrefv60() || - machine_is_snowball()) - ux500_uart_base = U8500_UART2_BASE; - else if (machine_is_u5500()) + if (machine_is_u5500()) ux500_uart_base = U5500_UART0_BASE; - else /* not much can be done to help here */ + else ux500_uart_base = U8500_UART2_BASE; } diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h index f923764..8b1d1a7 100644 --- a/arch/arm/mach-ux500/pins-db8500.h +++ b/arch/arm/mach-ux500/pins-db8500.h @@ -35,40 +35,40 @@ #define GPIO4_GPIO PIN_CFG(4, GPIO) #define GPIO4_U1_RXD PIN_CFG(4, ALT_A) -#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) +#define GPIO4_I2C4_SCL PIN_CFG_INPUT(4, ALT_B, PULLUP) #define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) #define GPIO5_GPIO PIN_CFG(5, GPIO) #define GPIO5_U1_TXD PIN_CFG(5, ALT_A) -#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) +#define GPIO5_I2C4_SDA PIN_CFG_INPUT(5, ALT_B, PULLUP) #define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) #define GPIO6_GPIO PIN_CFG(6, GPIO) #define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) -#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) +#define GPIO6_I2C1_SCL PIN_CFG_INPUT(6, ALT_B, PULLUP) #define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) #define GPIO7_GPIO PIN_CFG(7, GPIO) #define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) -#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) +#define GPIO7_I2C1_SDA PIN_CFG_INPUT(7, ALT_B, PULLUP) #define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) #define GPIO8_GPIO PIN_CFG(8, GPIO) -#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) -#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) +#define GPIO8_IPI2C_SDA PIN_CFG_INPUT(8, ALT_A, PULLUP) +#define GPIO8_I2C2_SDA PIN_CFG_INPUT(8, ALT_B, PULLUP) #define GPIO9_GPIO PIN_CFG(9, GPIO) -#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) -#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) +#define GPIO9_IPI2C_SCL PIN_CFG_INPUT(9, ALT_A, PULLUP) +#define GPIO9_I2C2_SCL PIN_CFG_INPUT(9, ALT_B, PULLUP) #define GPIO10_GPIO PIN_CFG(10, GPIO) -#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) -#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) +#define GPIO10_IPI2C_SDA PIN_CFG_INPUT(10, ALT_A, PULLUP) +#define GPIO10_I2C2_SDA PIN_CFG_INPUT(10, ALT_B, PULLUP) #define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) #define GPIO11_GPIO PIN_CFG(11, GPIO) -#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) -#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) +#define GPIO11_IPI2C_SCL PIN_CFG_INPUT(11, ALT_A, PULLUP) +#define GPIO11_I2C2_SCL PIN_CFG_INPUT(11, ALT_B, PULLUP) #define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) #define GPIO12_GPIO PIN_CFG(12, GPIO) @@ -87,66 +87,66 @@ #define GPIO16_GPIO PIN_CFG(16, GPIO) #define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) -#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) +#define GPIO16_I2C1_SCL PIN_CFG_INPUT(16, ALT_B, PULLUP) #define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) #define GPIO17_GPIO PIN_CFG(17, GPIO) #define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) -#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) +#define GPIO17_I2C1_SDA PIN_CFG_INPUT(17, ALT_B, PULLUP) #define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) #define GPIO18_GPIO PIN_CFG(18, GPIO) -#define GPIO18_MC0_CMDDIR PIN_CFG_PULL(18, ALT_A, UP) +#define GPIO18_MC0_CMDDIR PIN_CFG_INPUT(18, ALT_A, PULLUP) #define GPIO18_U2_RXD PIN_CFG(18, ALT_B) #define GPIO18_MS_IEP PIN_CFG(18, ALT_C) #define GPIO19_GPIO PIN_CFG(19, GPIO) -#define GPIO19_MC0_DAT0DIR PIN_CFG_PULL(19, ALT_A, UP) +#define GPIO19_MC0_DAT0DIR PIN_CFG_INPUT(19, ALT_A, PULLUP) #define GPIO19_U2_TXD PIN_CFG(19, ALT_B) #define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) #define GPIO20_GPIO PIN_CFG(20, GPIO) -#define GPIO20_MC0_DAT2DIR PIN_CFG_PULL(20, ALT_A, UP) +#define GPIO20_MC0_DAT2DIR PIN_CFG_INPUT(20, ALT_A, PULLUP) #define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) #define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) #define GPIO21_GPIO PIN_CFG(21, GPIO) -#define GPIO21_MC0_DAT31DIR PIN_CFG_PULL(21, ALT_A, UP) +#define GPIO21_MC0_DAT31DIR PIN_CFG_INPUT(21, ALT_A, PULLUP) #define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) #define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) #define GPIO22_GPIO PIN_CFG(22, GPIO) -#define GPIO22_MC0_FBCLK PIN_CFG_PULL(22, ALT_A, UP) +#define GPIO22_MC0_FBCLK PIN_CFG_INPUT(22, ALT_A, PULLUP) #define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) #define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) #define GPIO23_GPIO PIN_CFG(23, GPIO) -#define GPIO23_MC0_CLK PIN_CFG_PULL(23, ALT_A, UP) +#define GPIO23_MC0_CLK PIN_CFG_INPUT(23, ALT_A, PULLUP) #define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) #define GPIO23_MS_CLK PIN_CFG(23, ALT_C) #define GPIO24_GPIO PIN_CFG(24, GPIO) -#define GPIO24_MC0_CMD PIN_CFG_PULL(24, ALT_A, UP) +#define GPIO24_MC0_CMD PIN_CFG_INPUT(24, ALT_A, PULLUP) #define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) #define GPIO24_MS_BS PIN_CFG(24, ALT_C) #define GPIO25_GPIO PIN_CFG(25, GPIO) -#define GPIO25_MC0_DAT0 PIN_CFG_PULL(25, ALT_A, UP) +#define GPIO25_MC0_DAT0 PIN_CFG_INPUT(25, ALT_A, PULLUP) #define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) #define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) #define GPIO26_GPIO PIN_CFG(26, GPIO) -#define GPIO26_MC0_DAT1 PIN_CFG_PULL(26, ALT_A, UP) +#define GPIO26_MC0_DAT1 PIN_CFG_INPUT(26, ALT_A, PULLUP) #define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) #define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) #define GPIO27_GPIO PIN_CFG(27, GPIO) -#define GPIO27_MC0_DAT2 PIN_CFG_PULL(27, ALT_A, UP) +#define GPIO27_MC0_DAT2 PIN_CFG_INPUT(27, ALT_A, PULLUP) #define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) #define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) #define GPIO28_GPIO PIN_CFG(28, GPIO) -#define GPIO28_MC0_DAT3 PIN_CFG_PULL(28, ALT_A, UP) +#define GPIO28_MC0_DAT3 PIN_CFG_INPUT(28, ALT_A, PULLUP) #define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) #define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) @@ -357,48 +357,48 @@ #define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) #define GPIO128_GPIO PIN_CFG(128, GPIO) -#define GPIO128_MC2_CLK PIN_CFG_PULL(128, ALT_A, UP) +#define GPIO128_MC2_CLK PIN_CFG_INPUT(128, ALT_A, PULLUP) #define GPIO128_SM_CKO PIN_CFG(128, ALT_B) #define GPIO129_GPIO PIN_CFG(129, GPIO) -#define GPIO129_MC2_CMD PIN_CFG_PULL(129, ALT_A, UP) +#define GPIO129_MC2_CMD PIN_CFG_INPUT(129, ALT_A, PULLUP) #define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) #define GPIO130_GPIO PIN_CFG(130, GPIO) -#define GPIO130_MC2_FBCLK PIN_CFG_PULL(130, ALT_A, UP) +#define GPIO130_MC2_FBCLK PIN_CFG_INPUT(130, ALT_A, PULLUP) #define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) #define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) #define GPIO131_GPIO PIN_CFG(131, GPIO) -#define GPIO131_MC2_DAT0 PIN_CFG_PULL(131, ALT_A, UP) +#define GPIO131_MC2_DAT0 PIN_CFG_INPUT(131, ALT_A, PULLUP) #define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) #define GPIO132_GPIO PIN_CFG(132, GPIO) -#define GPIO132_MC2_DAT1 PIN_CFG_PULL(132, ALT_A, UP) +#define GPIO132_MC2_DAT1 PIN_CFG_INPUT(132, ALT_A, PULLUP) #define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) #define GPIO133_GPIO PIN_CFG(133, GPIO) -#define GPIO133_MC2_DAT2 PIN_CFG_PULL(133, ALT_A, UP) +#define GPIO133_MC2_DAT2 PIN_CFG_INPUT(133, ALT_A, PULLUP) #define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) #define GPIO134_GPIO PIN_CFG(134, GPIO) -#define GPIO134_MC2_DAT3 PIN_CFG_PULL(134, ALT_A, UP) +#define GPIO134_MC2_DAT3 PIN_CFG_INPUT(134, ALT_A, PULLUP) #define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) #define GPIO135_GPIO PIN_CFG(135, GPIO) -#define GPIO135_MC2_DAT4 PIN_CFG_PULL(135, ALT_A, UP) +#define GPIO135_MC2_DAT4 PIN_CFG_INPUT(135, ALT_A, PULLUP) #define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) #define GPIO136_GPIO PIN_CFG(136, GPIO) -#define GPIO136_MC2_DAT5 PIN_CFG_PULL(136, ALT_A, UP) +#define GPIO136_MC2_DAT5 PIN_CFG_INPUT(136, ALT_A, PULLUP) #define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) #define GPIO137_GPIO PIN_CFG(137, GPIO) -#define GPIO137_MC2_DAT6 PIN_CFG_PULL(137, ALT_A, UP) +#define GPIO137_MC2_DAT6 PIN_CFG_INPUT(137, ALT_A, PULLUP) #define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) #define GPIO138_GPIO PIN_CFG(138, GPIO) -#define GPIO138_MC2_DAT7 PIN_CFG_PULL(138, ALT_A, UP) +#define GPIO138_MC2_DAT7 PIN_CFG_INPUT(138, ALT_A, PULLUP) #define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) #define GPIO139_GPIO PIN_CFG(139, GPIO) @@ -434,10 +434,10 @@ #define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) #define GPIO147_GPIO PIN_CFG(147, GPIO) -#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) +#define GPIO147_I2C0_SCL PIN_CFG_INPUT(147, ALT_A, PULLUP) #define GPIO148_GPIO PIN_CFG(148, GPIO) -#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) +#define GPIO148_I2C0_SDA PIN_CFG_INPUT(148, ALT_A, PULLUP) #define GPIO149_GPIO PIN_CFG(149, GPIO) #define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) @@ -459,82 +459,82 @@ #define GPIO152_KP_O9 PIN_CFG(152, ALT_C) #define GPIO153_GPIO PIN_CFG(153, GPIO) -#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) +#define GPIO153_KP_I7 PIN_CFG_INPUT(153, ALT_A, PULLDOWN) #define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) #define GPIO153_U2_RXD PIN_CFG(153, ALT_C) #define GPIO154_GPIO PIN_CFG(154, GPIO) -#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) +#define GPIO154_KP_I6 PIN_CFG_INPUT(154, ALT_A, PULLDOWN) #define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) #define GPIO154_U2_TXD PIN_CFG(154, ALT_C) #define GPIO155_GPIO PIN_CFG(155, GPIO) -#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) +#define GPIO155_KP_I5 PIN_CFG_INPUT(155, ALT_A, PULLDOWN) #define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) #define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) #define GPIO156_GPIO PIN_CFG(156, GPIO) -#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) +#define GPIO156_KP_I4 PIN_CFG_INPUT(156, ALT_A, PULLDOWN) #define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) #define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) #define GPIO157_GPIO PIN_CFG(157, GPIO) -#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) +#define GPIO157_KP_O7 PIN_CFG_INPUT(157, ALT_A, PULLUP) #define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) #define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) #define GPIO158_GPIO PIN_CFG(158, GPIO) -#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) +#define GPIO158_KP_O6 PIN_CFG_INPUT(158, ALT_A, PULLUP) #define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) #define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) #define GPIO159_GPIO PIN_CFG(159, GPIO) -#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) +#define GPIO159_KP_O5 PIN_CFG_INPUT(159, ALT_A, PULLUP) #define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) #define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) #define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) +#define GPIO160_KP_O4 PIN_CFG_INPUT(160, ALT_A, PULLUP) #define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) #define GPIO160_NONE PIN_CFG(160, ALT_C) #define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) +#define GPIO161_KP_I3 PIN_CFG_INPUT(161, ALT_A, PULLDOWN) #define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) #define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) #define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) +#define GPIO162_KP_I2 PIN_CFG_INPUT(162, ALT_A, PULLDOWN) #define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) #define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) #define GPIO163_GPIO PIN_CFG(163, GPIO) -#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) +#define GPIO163_KP_I1 PIN_CFG_INPUT(163, ALT_A, PULLDOWN) #define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) #define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) #define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) +#define GPIO164_KP_I0 PIN_CFG_INPUT(164, ALT_A, PULLUP) #define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) #define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) #define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) +#define GPIO165_KP_O3 PIN_CFG_INPUT(165, ALT_A, PULLUP) #define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) #define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) #define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) +#define GPIO166_KP_O2 PIN_CFG_INPUT(166, ALT_A, PULLUP) #define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) #define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) #define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) +#define GPIO167_KP_O1 PIN_CFG_INPUT(167, ALT_A, PULLUP) #define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) #define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) #define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) +#define GPIO168_KP_O0 PIN_CFG_INPUT(168, ALT_A, PULLUP) #define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) #define GPIO168_NONE PIN_CFG(168, ALT_C) @@ -569,39 +569,39 @@ #define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) #define GPIO197_GPIO PIN_CFG(197, GPIO) -#define GPIO197_MC4_DAT3 PIN_CFG_PULL(197, ALT_A, UP) +#define GPIO197_MC4_DAT3 PIN_CFG_INPUT(197, ALT_A, PULLUP) #define GPIO198_GPIO PIN_CFG(198, GPIO) -#define GPIO198_MC4_DAT2 PIN_CFG_PULL(198, ALT_A, UP) +#define GPIO198_MC4_DAT2 PIN_CFG_INPUT(198, ALT_A, PULLUP) #define GPIO199_GPIO PIN_CFG(199, GPIO) -#define GPIO199_MC4_DAT1 PIN_CFG_PULL(199, ALT_A, UP) +#define GPIO199_MC4_DAT1 PIN_CFG_INPUT(199, ALT_A, PULLUP) #define GPIO200_GPIO PIN_CFG(200, GPIO) -#define GPIO200_MC4_DAT0 PIN_CFG_PULL(200, ALT_A, UP) +#define GPIO200_MC4_DAT0 PIN_CFG_INPUT(200, ALT_A, PULLUP) #define GPIO201_GPIO PIN_CFG(201, GPIO) -#define GPIO201_MC4_CMD PIN_CFG_PULL(201, ALT_A, UP) +#define GPIO201_MC4_CMD PIN_CFG_INPUT(201, ALT_A, PULLUP) #define GPIO202_GPIO PIN_CFG(202, GPIO) -#define GPIO202_MC4_FBCLK PIN_CFG_PULL(202, ALT_A, UP) +#define GPIO202_MC4_FBCLK PIN_CFG_INPUT(202, ALT_A, PULLUP) #define GPIO202_PWL PIN_CFG(202, ALT_B) #define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) #define GPIO203_GPIO PIN_CFG(203, GPIO) -#define GPIO203_MC4_CLK PIN_CFG_PULL(203, ALT_A, UP) +#define GPIO203_MC4_CLK PIN_CFG_INPUT(203, ALT_A, PULLUP) #define GPIO204_GPIO PIN_CFG(204, GPIO) -#define GPIO204_MC4_DAT7 PIN_CFG_PULL(204, ALT_A, UP) +#define GPIO204_MC4_DAT7 PIN_CFG_INPUT(204, ALT_A, PULLUP) #define GPIO205_GPIO PIN_CFG(205, GPIO) -#define GPIO205_MC4_DAT6 PIN_CFG_PULL(205, ALT_A, UP) +#define GPIO205_MC4_DAT6 PIN_CFG_INPUT(205, ALT_A, PULLUP) #define GPIO206_GPIO PIN_CFG(206, GPIO) -#define GPIO206_MC4_DAT5 PIN_CFG_PULL(206, ALT_A, UP) +#define GPIO206_MC4_DAT5 PIN_CFG_INPUT(206, ALT_A, PULLUP) #define GPIO207_GPIO PIN_CFG(207, GPIO) -#define GPIO207_MC4_DAT4 PIN_CFG_PULL(207, ALT_A, UP) +#define GPIO207_MC4_DAT4 PIN_CFG_INPUT(207, ALT_A, PULLUP) #define GPIO208_GPIO PIN_CFG(208, GPIO) #define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) @@ -632,21 +632,25 @@ #define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) #define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) #define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) +#define GPIO215_SPI2_TXD PIN_CFG(215, ALT_C) #define GPIO216_GPIO PIN_CFG(216, GPIO) #define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) #define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) -#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) +#define GPIO216_I2C3_SDA PIN_CFG_INPUT(216, ALT_C, PULLUP) +#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C) #define GPIO217_GPIO PIN_CFG(217, GPIO) #define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) #define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) #define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) +#define GPIO217_SPI2_CLK PIN_CFG(217, ALT_C) #define GPIO218_GPIO PIN_CFG(218, GPIO) #define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) #define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) -#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) +#define GPIO218_I2C3_SCL PIN_CFG_INPUT(218, ALT_C, PULLUP) +#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C) #define GPIO219_GPIO PIN_CFG(219, GPIO) #define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) @@ -694,12 +698,12 @@ #define GPIO229_GPIO PIN_CFG(229, GPIO) #define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) #define GPIO229_PWL PIN_CFG(229, ALT_B) -#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) +#define GPIO229_I2C3_SDA PIN_CFG_INPUT(229, ALT_C, PULLUP) #define GPIO230_GPIO PIN_CFG(230, GPIO) #define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) #define GPIO230_PWL PIN_CFG(230, ALT_B) -#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) +#define GPIO230_I2C3_SCL PIN_CFG_INPUT(230, ALT_C, PULLUP) #define GPIO256_GPIO PIN_CFG(256, GPIO) #define GPIO256_USB_NXT PIN_CFG(256, ALT_A) diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c new file mode 100644 index 0000000..aea467d --- /dev/null +++ b/arch/arm/mach-ux500/timer.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson + */ +#include <linux/io.h> +#include <linux/errno.h> +#include <linux/clksrc-dbx500-prcmu.h> + +#include <asm/localtimer.h> + +#include <plat/mtu.h> + +#include <mach/setup.h> +#include <mach/hardware.h> + +static void __init ux500_timer_init(void) +{ + void __iomem *prcmu_timer_base; + + if (cpu_is_u5500()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base = __io_address(U5500_TWD_BASE); +#endif + mtu_base = __io_address(U5500_MTU0_BASE); + prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); + } else if (cpu_is_u8500()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base = __io_address(U8500_TWD_BASE); +#endif + mtu_base = __io_address(U8500_MTU0_BASE); + prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); + } else { + ux500_unknown_soc(); + } + + /* + * Here we register the timerblocks active in the system. + * Localtimers (twd) is started when both cpu is up and running. + * MTU register a clocksource, clockevent and sched_clock. + * Since the MTU is located in the VAPE power domain + * it will be cleared in sleep which makes it unsuitable. + * We however need it as a timer tick (clockevent) + * during boot to calibrate delay until twd is started. + * RTC-RTT have problems as timer tick during boot since it is + * depending on delay which is not yet calibrated. RTC-RTT is in the + * always-on powerdomain and is used as clockevent instead of twd when + * sleeping. + * The PRCMU timer 4(3 for DB5500) register a clocksource and + * sched_clock with higher rating then MTU since is always-on. + * + */ + + nmdk_timer_init(); + clksrc_dbx500_prcmu_init(prcmu_timer_base); +} + +static void ux500_timer_reset(void) +{ + nmdk_clkevt_reset(); + nmdk_clksrc_reset(); +} + +struct sys_timer ux500_timer = { + .init = ux500_timer_init, + .resume = ux500_timer_reset, +}; diff --git a/arch/arm/mach-versatile/Makefile.boot b/arch/arm/mach-versatile/Makefile.boot index c7e75ac..ff0a4b5 100644 --- a/arch/arm/mach-versatile/Makefile.boot +++ b/arch/arm/mach-versatile/Makefile.boot @@ -1,4 +1,4 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot index 07c2d9c..8630b3d 100644 --- a/arch/arm/mach-vexpress/Makefile.boot +++ b/arch/arm/mach-vexpress/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x60008000 + zreladdr-y += 0x60008000 params_phys-y := 0x60000100 initrd_phys-y := 0x60800000 diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c index ea4cbfb..3668cf9 100644 --- a/arch/arm/mach-vexpress/hotplug.c +++ b/arch/arm/mach-vexpress/hotplug.c @@ -13,6 +13,7 @@ #include <linux/smp.h> #include <asm/cacheflush.h> +#include <asm/system.h> extern volatile int pen_release; @@ -62,13 +63,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) * code will have already disabled interrupts */ for (;;) { - /* - * here's the WFI - */ - asm(".word 0xe320f003\n" - : - : - : "memory", "cc"); + wfi(); if (pen_release == cpu) { /* diff --git a/arch/arm/mach-vexpress/include/mach/gpio.h b/arch/arm/mach-vexpress/include/mach/gpio.h new file mode 100644 index 0000000..40a8c17 --- /dev/null +++ b/arch/arm/mach-vexpress/include/mach/gpio.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h index 748bb52..13522d8 100644 --- a/arch/arm/mach-vexpress/include/mach/io.h +++ b/arch/arm/mach-vexpress/include/mach/io.h @@ -20,8 +20,6 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#define IO_SPACE_LIMIT 0xffffffff - #define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) diff --git a/arch/arm/mach-vt8500/Makefile.boot b/arch/arm/mach-vt8500/Makefile.boot index a8acc4e..b79c41c 100644 --- a/arch/arm/mach-vt8500/Makefile.boot +++ b/arch/arm/mach-vt8500/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x01000000 diff --git a/arch/arm/mach-vt8500/include/mach/io.h b/arch/arm/mach-vt8500/include/mach/io.h index 9077239..46181ee 100644 --- a/arch/arm/mach-vt8500/include/mach/io.h +++ b/arch/arm/mach-vt8500/include/mach/io.h @@ -20,8 +20,6 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#define IO_SPACE_LIMIT 0xffff - #define __io(a) __typesafe_io((a) + 0xf0000000) #define __mem_pci(a) (a) diff --git a/arch/arm/mach-w90x900/Makefile.boot b/arch/arm/mach-w90x900/Makefile.boot index a057b54..6c3d421 100644 --- a/arch/arm/mach-w90x900/Makefile.boot +++ b/arch/arm/mach-w90x900/Makefile.boot @@ -1,3 +1,3 @@ -zreladdr-y := 0x00008000 +zreladdr-y += 0x00008000 params_phys-y := 0x00000100 diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c index 83c5632..0a235e5 100644 --- a/arch/arm/mach-w90x900/cpu.c +++ b/arch/arm/mach-w90x900/cpu.c @@ -60,7 +60,7 @@ static DEFINE_CLK(emc, 7); static DEFINE_SUBCLK(rmii, 2); static DEFINE_CLK(usbd, 8); static DEFINE_CLK(usbh, 9); -static DEFINE_CLK(g2d, 10);; +static DEFINE_CLK(g2d, 10); static DEFINE_CLK(pwm, 18); static DEFINE_CLK(ps2, 24); static DEFINE_CLK(kpi, 25); diff --git a/arch/arm/mach-zynq/Makefile.boot b/arch/arm/mach-zynq/Makefile.boot index 67039c3..760a0ef 100644 --- a/arch/arm/mach-zynq/Makefile.boot +++ b/arch/arm/mach-zynq/Makefile.boot @@ -1,3 +1,3 @@ - zreladdr-y := 0x00008000 + zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index cfbcf8b..c335c76 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -86,16 +86,6 @@ core_param(alignment, ai_usermode, int, 0600); #define UM_FIXUP (1 << 1) #define UM_SIGNAL (1 << 2) -#ifdef CONFIG_PROC_FS -static const char *usermode_action[] = { - "ignored", - "warn", - "fixup", - "fixup+warn", - "signal", - "signal+warn" -}; - /* Return true if and only if the ARMv6 unaligned access model is in use. */ static bool cpu_is_v6_unaligned(void) { @@ -123,6 +113,16 @@ static int safe_usermode(int new_usermode, bool warn) return new_usermode; } +#ifdef CONFIG_PROC_FS +static const char *usermode_action[] = { + "ignored", + "warn", + "fixup", + "fixup+warn", + "signal", + "signal+warn" +}; + static int alignment_proc_show(struct seq_file *m, void *v) { seq_printf(m, "User:\t\t%lu\n", ai_user); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 9ecfdb5..8ac9e9f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -16,9 +16,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include <linux/err.h> #include <linux/init.h> #include <linux/spinlock.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> @@ -26,15 +29,23 @@ #define CACHE_LINE_SIZE 32 static void __iomem *l2x0_base; -static DEFINE_SPINLOCK(l2x0_lock); +static DEFINE_RAW_SPINLOCK(l2x0_lock); static uint32_t l2x0_way_mask; /* Bitmask of active ways */ static uint32_t l2x0_size; +struct l2x0_regs l2x0_saved_regs; + +struct l2x0_of_data { + void (*setup)(const struct device_node *, __u32 *, __u32 *); + void (*save)(void); + void (*resume)(void); +}; + static inline void cache_wait_way(void __iomem *reg, unsigned long mask) { /* wait for cache operation by line or way to complete */ while (readl_relaxed(reg) & mask) - ; + cpu_relax(); } #ifdef CONFIG_CACHE_PL310 @@ -115,9 +126,9 @@ static void l2x0_cache_sync(void) { unsigned long flags; - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); } static void __l2x0_flush_all(void) @@ -134,9 +145,9 @@ static void l2x0_flush_all(void) unsigned long flags; /* clean all ways */ - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); __l2x0_flush_all(); - spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_clean_all(void) @@ -144,11 +155,11 @@ static void l2x0_clean_all(void) unsigned long flags; /* clean all ways */ - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_inv_all(void) @@ -156,13 +167,13 @@ static void l2x0_inv_all(void) unsigned long flags; /* invalidate all ways */ - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); /* Invalidating when L2 is enabled is a nono */ BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1); writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_inv_range(unsigned long start, unsigned long end) @@ -170,7 +181,7 @@ static void l2x0_inv_range(unsigned long start, unsigned long end) void __iomem *base = l2x0_base; unsigned long flags; - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); if (start & (CACHE_LINE_SIZE - 1)) { start &= ~(CACHE_LINE_SIZE - 1); debug_writel(0x03); @@ -195,13 +206,13 @@ static void l2x0_inv_range(unsigned long start, unsigned long end) } if (blk_end < end) { - spin_unlock_irqrestore(&l2x0_lock, flags); - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); } } cache_wait(base + L2X0_INV_LINE_PA, 1); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_clean_range(unsigned long start, unsigned long end) @@ -214,7 +225,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end) return; } - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); start &= ~(CACHE_LINE_SIZE - 1); while (start < end) { unsigned long blk_end = start + min(end - start, 4096UL); @@ -225,13 +236,13 @@ static void l2x0_clean_range(unsigned long start, unsigned long end) } if (blk_end < end) { - spin_unlock_irqrestore(&l2x0_lock, flags); - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); } } cache_wait(base + L2X0_CLEAN_LINE_PA, 1); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_flush_range(unsigned long start, unsigned long end) @@ -244,7 +255,7 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) return; } - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); start &= ~(CACHE_LINE_SIZE - 1); while (start < end) { unsigned long blk_end = start + min(end - start, 4096UL); @@ -257,27 +268,27 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) debug_writel(0x00); if (blk_end < end) { - spin_unlock_irqrestore(&l2x0_lock, flags); - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); } } cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_disable(void) { unsigned long flags; - spin_lock_irqsave(&l2x0_lock, flags); + raw_spin_lock_irqsave(&l2x0_lock, flags); __l2x0_flush_all(); writel_relaxed(0, l2x0_base + L2X0_CTRL); dsb(); - spin_unlock_irqrestore(&l2x0_lock, flags); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); } -static void __init l2x0_unlock(__u32 cache_id) +static void l2x0_unlock(__u32 cache_id) { int lockregs; int i; @@ -353,6 +364,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) /* l2x0 controller is disabled */ writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); + l2x0_saved_regs.aux_ctrl = aux; + l2x0_inv_all(); /* enable L2X0 */ @@ -372,3 +385,202 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", ways, cache_id, aux, l2x0_size); } + +#ifdef CONFIG_OF +static void __init l2x0_of_setup(const struct device_node *np, + __u32 *aux_val, __u32 *aux_mask) +{ + u32 data[2] = { 0, 0 }; + u32 tag = 0; + u32 dirty = 0; + u32 val = 0, mask = 0; + + of_property_read_u32(np, "arm,tag-latency", &tag); + if (tag) { + mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; + val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; + } + + of_property_read_u32_array(np, "arm,data-latency", + data, ARRAY_SIZE(data)); + if (data[0] && data[1]) { + mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | + L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; + val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | + ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); + } + + of_property_read_u32(np, "arm,dirty-latency", &dirty); + if (dirty) { + mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; + val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; + } + + *aux_val &= ~mask; + *aux_val |= val; + *aux_mask &= ~mask; +} + +static void __init pl310_of_setup(const struct device_node *np, + __u32 *aux_val, __u32 *aux_mask) +{ + u32 data[3] = { 0, 0, 0 }; + u32 tag[3] = { 0, 0, 0 }; + u32 filter[2] = { 0, 0 }; + + of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); + if (tag[0] && tag[1] && tag[2]) + writel_relaxed( + ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | + ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | + ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), + l2x0_base + L2X0_TAG_LATENCY_CTRL); + + of_property_read_u32_array(np, "arm,data-latency", + data, ARRAY_SIZE(data)); + if (data[0] && data[1] && data[2]) + writel_relaxed( + ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | + ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | + ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), + l2x0_base + L2X0_DATA_LATENCY_CTRL); + + of_property_read_u32_array(np, "arm,filter-ranges", + filter, ARRAY_SIZE(filter)); + if (filter[1]) { + writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), + l2x0_base + L2X0_ADDR_FILTER_END); + writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, + l2x0_base + L2X0_ADDR_FILTER_START); + } +} + +static void __init pl310_save(void) +{ + u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & + L2X0_CACHE_ID_RTL_MASK; + + l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base + + L2X0_TAG_LATENCY_CTRL); + l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base + + L2X0_DATA_LATENCY_CTRL); + l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base + + L2X0_ADDR_FILTER_END); + l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base + + L2X0_ADDR_FILTER_START); + + if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) { + /* + * From r2p0, there is Prefetch offset/control register + */ + l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base + + L2X0_PREFETCH_CTRL); + /* + * From r3p0, there is Power control register + */ + if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0) + l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base + + L2X0_POWER_CTRL); + } +} + +static void l2x0_resume(void) +{ + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { + /* restore aux ctrl and enable l2 */ + l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID)); + + writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base + + L2X0_AUX_CTRL); + + l2x0_inv_all(); + + writel_relaxed(1, l2x0_base + L2X0_CTRL); + } +} + +static void pl310_resume(void) +{ + u32 l2x0_revision; + + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { + /* restore pl310 setup */ + writel_relaxed(l2x0_saved_regs.tag_latency, + l2x0_base + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(l2x0_saved_regs.data_latency, + l2x0_base + L2X0_DATA_LATENCY_CTRL); + writel_relaxed(l2x0_saved_regs.filter_end, + l2x0_base + L2X0_ADDR_FILTER_END); + writel_relaxed(l2x0_saved_regs.filter_start, + l2x0_base + L2X0_ADDR_FILTER_START); + + l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & + L2X0_CACHE_ID_RTL_MASK; + + if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) { + writel_relaxed(l2x0_saved_regs.prefetch_ctrl, + l2x0_base + L2X0_PREFETCH_CTRL); + if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0) + writel_relaxed(l2x0_saved_regs.pwr_ctrl, + l2x0_base + L2X0_POWER_CTRL); + } + } + + l2x0_resume(); +} + +static const struct l2x0_of_data pl310_data = { + pl310_of_setup, + pl310_save, + pl310_resume, +}; + +static const struct l2x0_of_data l2x0_data = { + l2x0_of_setup, + NULL, + l2x0_resume, +}; + +static const struct of_device_id l2x0_ids[] __initconst = { + { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data }, + { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data }, + { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data }, + {} +}; + +int __init l2x0_of_init(__u32 aux_val, __u32 aux_mask) +{ + struct device_node *np; + struct l2x0_of_data *data; + struct resource res; + + np = of_find_matching_node(NULL, l2x0_ids); + if (!np) + return -ENODEV; + + if (of_address_to_resource(np, 0, &res)) + return -ENODEV; + + l2x0_base = ioremap(res.start, resource_size(&res)); + if (!l2x0_base) + return -ENOMEM; + + l2x0_saved_regs.phy_base = res.start; + + data = of_match_node(l2x0_ids, np)->data; + + /* L2 configuration can only be changed if the cache is disabled */ + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { + if (data->setup) + data->setup(np, &aux_val, &aux_mask); + } + + if (data->save) + data->save(); + + l2x0_init(l2x0_base, aux_val, aux_mask); + + outer_cache.resume = data->resume; + return 0; +} +#endif diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index b0ee9ba..93aac06 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -16,7 +16,7 @@ #include <asm/mmu_context.h> #include <asm/tlbflush.h> -static DEFINE_SPINLOCK(cpu_asid_lock); +static DEFINE_RAW_SPINLOCK(cpu_asid_lock); unsigned int cpu_last_asid = ASID_FIRST_VERSION; #ifdef CONFIG_SMP DEFINE_PER_CPU(struct mm_struct *, current_mm); @@ -31,7 +31,7 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm); void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) { mm->context.id = 0; - spin_lock_init(&mm->context.id_lock); + raw_spin_lock_init(&mm->context.id_lock); } static void flush_context(void) @@ -58,7 +58,7 @@ static void set_mm_context(struct mm_struct *mm, unsigned int asid) * the broadcast. This function is also called via IPI so the * mm->context.id_lock has to be IRQ-safe. */ - spin_lock_irqsave(&mm->context.id_lock, flags); + raw_spin_lock_irqsave(&mm->context.id_lock, flags); if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) { /* * Old version of ASID found. Set the new one and @@ -67,7 +67,7 @@ static void set_mm_context(struct mm_struct *mm, unsigned int asid) mm->context.id = asid; cpumask_clear(mm_cpumask(mm)); } - spin_unlock_irqrestore(&mm->context.id_lock, flags); + raw_spin_unlock_irqrestore(&mm->context.id_lock, flags); /* * Set the mm_cpumask(mm) bit for the current CPU. @@ -117,7 +117,7 @@ void __new_context(struct mm_struct *mm) { unsigned int asid; - spin_lock(&cpu_asid_lock); + raw_spin_lock(&cpu_asid_lock); #ifdef CONFIG_SMP /* * Check the ASID again, in case the change was broadcast from @@ -125,7 +125,7 @@ void __new_context(struct mm_struct *mm) */ if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) { cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm)); - spin_unlock(&cpu_asid_lock); + raw_spin_unlock(&cpu_asid_lock); return; } #endif @@ -153,5 +153,5 @@ void __new_context(struct mm_struct *mm) } set_mm_context(mm, asid); - spin_unlock(&cpu_asid_lock); + raw_spin_unlock(&cpu_asid_lock); } diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c index b806151..7d0a8c2 100644 --- a/arch/arm/mm/copypage-v4mc.c +++ b/arch/arm/mm/copypage-v4mc.c @@ -30,7 +30,7 @@ #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ L_PTE_MT_MINICACHE) -static DEFINE_SPINLOCK(minicache_lock); +static DEFINE_RAW_SPINLOCK(minicache_lock); /* * ARMv4 mini-dcache optimised copy_user_highpage @@ -76,14 +76,14 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from, if (!test_and_set_bit(PG_dcache_clean, &from->flags)) __flush_dcache_page(page_mapping(from), from); - spin_lock(&minicache_lock); + raw_spin_lock(&minicache_lock); set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(page_to_pfn(from), minicache_pgprot), 0); flush_tlb_kernel_page(0xffff8000); mc_copy_user_page((void *)0xffff8000, kto); - spin_unlock(&minicache_lock); + raw_spin_unlock(&minicache_lock); kunmap_atomic(kto, KM_USER1); } diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c index 63cca00..3d9a155 100644 --- a/arch/arm/mm/copypage-v6.c +++ b/arch/arm/mm/copypage-v6.c @@ -27,7 +27,7 @@ #define from_address (0xffff8000) #define to_address (0xffffc000) -static DEFINE_SPINLOCK(v6_lock); +static DEFINE_RAW_SPINLOCK(v6_lock); /* * Copy the user page. No aliasing to deal with so we can just @@ -88,7 +88,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to, * Now copy the page using the same cache colour as the * pages ultimate destination. */ - spin_lock(&v6_lock); + raw_spin_lock(&v6_lock); set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(page_to_pfn(from), PAGE_KERNEL), 0); set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(page_to_pfn(to), PAGE_KERNEL), 0); @@ -101,7 +101,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to, copy_page((void *)kto, (void *)kfrom); - spin_unlock(&v6_lock); + raw_spin_unlock(&v6_lock); } /* @@ -121,13 +121,13 @@ static void v6_clear_user_highpage_aliasing(struct page *page, unsigned long vad * Now clear the page using the same cache colour as * the pages ultimate destination. */ - spin_lock(&v6_lock); + raw_spin_lock(&v6_lock); set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(page_to_pfn(page), PAGE_KERNEL), 0); flush_tlb_kernel_page(to); clear_page((void *)to); - spin_unlock(&v6_lock); + raw_spin_unlock(&v6_lock); } struct cpu_user_fns v6_user_fns __initdata = { diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c index 649bbcd..610c24c 100644 --- a/arch/arm/mm/copypage-xscale.c +++ b/arch/arm/mm/copypage-xscale.c @@ -32,7 +32,7 @@ #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ L_PTE_MT_MINICACHE) -static DEFINE_SPINLOCK(minicache_lock); +static DEFINE_RAW_SPINLOCK(minicache_lock); /* * XScale mini-dcache optimised copy_user_highpage @@ -98,14 +98,14 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from, if (!test_and_set_bit(PG_dcache_clean, &from->flags)) __flush_dcache_page(page_mapping(from), from); - spin_lock(&minicache_lock); + raw_spin_lock(&minicache_lock); set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(page_to_pfn(from), minicache_pgprot), 0); flush_tlb_kernel_page(COPYPAGE_MINICACHE); mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); - spin_unlock(&minicache_lock); + raw_spin_unlock(&minicache_lock); kunmap_atomic(kto, KM_USER1); } diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 01f5987..e4e7f6c 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -120,9 +120,8 @@ static void __dma_free_buffer(struct page *page, size_t size) #ifdef CONFIG_MMU - #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT) -#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PGDIR_SHIFT) +#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT) /* * These are the page tables (2MB each) covering uncached, DMA consistent allocations @@ -206,7 +205,7 @@ static int __init consistent_init(void) } consistent_pte[i++] = pte; - base += (1 << PGDIR_SHIFT); + base += PMD_SIZE; } while (base < CONSISTENT_END); return ret; diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 34409a0..04e9a92 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -496,6 +496,13 @@ static void __init free_unused_memmap(struct meminfo *mi) */ bank_start = min(bank_start, ALIGN(prev_bank_end, PAGES_PER_SECTION)); +#else + /* + * Align down here since the VM subsystem insists that the + * memmap entries are valid from the bank start aligned to + * MAX_ORDER_NR_PAGES. + */ + bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES); #endif /* * If we had a previous bank, and there is a space diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index ab50627..bdb248c 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -289,6 +289,27 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) } EXPORT_SYMBOL(__arm_ioremap); +/* + * Remap an arbitrary physical address space into the kernel virtual + * address space as memory. Needed when the kernel wants to execute + * code in external memory. This is needed for reprogramming source + * clocks that would affect normal memory for example. Please see + * CONFIG_GENERIC_ALLOCATOR for allocating external memory. + */ +void __iomem * +__arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached) +{ + unsigned int mtype; + + if (cached) + mtype = MT_MEMORY; + else + mtype = MT_MEMORY_NONCACHED; + + return __arm_ioremap_caller(phys_addr, size, mtype, + __builtin_return_address(0)); +} + void __iounmap(volatile void __iomem *io_addr) { void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr); diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 0105667..ad7cce3 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -12,8 +12,8 @@ static inline pmd_t *pmd_off_k(unsigned long virt) struct mem_type { pteval_t prot_pte; - unsigned int prot_l1; - unsigned int prot_sect; + pmdval_t prot_l1; + pmdval_t prot_sect; unsigned int domain; }; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index ea9c9f3..dc8c550 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -60,7 +60,7 @@ EXPORT_SYMBOL(pgprot_kernel); struct cachepolicy { const char policy[16]; unsigned int cr_mask; - unsigned int pmd; + pmdval_t pmd; pteval_t pte; }; @@ -296,7 +296,7 @@ static void __init build_mem_type_table(void) { struct cachepolicy *cp; unsigned int cr = get_cr(); - unsigned int user_pgprot, kern_pgprot, vecs_pgprot; + pteval_t user_pgprot, kern_pgprot, vecs_pgprot; int cpu_arch = cpu_architecture(); int i; @@ -871,14 +871,14 @@ static inline void prepare_page_table(void) /* * Clear out all the mappings below the kernel image. */ - for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE) + for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); #ifdef CONFIG_XIP_KERNEL /* The XIP kernel is mapped in the module area -- skip over it */ - addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK; + addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; #endif - for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) + for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); /* @@ -893,10 +893,12 @@ static inline void prepare_page_table(void) * memory bank, up to the end of the vmalloc region. */ for (addr = __phys_to_virt(end); - addr < VMALLOC_END; addr += PGDIR_SIZE) + addr < VMALLOC_END; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); } +#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) + /* * Reserve the special regions of memory */ @@ -906,7 +908,7 @@ void __init arm_mm_memblock_reserve(void) * Reserve the page tables. These are already in use, * and can only be in node 0. */ - memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); + memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); #ifdef CONFIG_SA1111 /* @@ -934,7 +936,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc) */ vectors_page = early_alloc(PAGE_SIZE); - for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) + for (addr = VMALLOC_END; addr; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); /* diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 6af366c..2c559ac 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -218,7 +218,7 @@ ENDPROC(cpu_v7_set_pte_ext) /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ .globl cpu_v7_suspend_size .equ cpu_v7_suspend_size, 4 * 7 -#ifdef CONFIG_PM_SLEEP +#ifdef CONFIG_ARM_CPU_SUSPEND ENTRY(cpu_v7_do_suspend) stmfd sp!, {r4 - r10, lr} mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index a5353fc..4c8fdbc 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -39,7 +39,7 @@ config ARCH_MX503 select ARCH_MX50_SUPPORTED select ARCH_MX53_SUPPORTED help - This enables support for machines using Freescale's i.MX50 and i.MX51 + This enables support for machines using Freescale's i.MX50 and i.MX53 processors. config ARCH_MX51 diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 175e364..8cced35 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -187,18 +187,11 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port); static int mxc_audmux_v2_init(void) { int ret; -#if defined(CONFIG_ARCH_MX5) if (cpu_is_mx51()) { audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR); - ret = 0; - return ret; - } -#endif -#if defined(CONFIG_ARCH_MX3) - if (cpu_is_mx31()) + } else if (cpu_is_mx31()) { audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); - - else if (cpu_is_mx35()) { + } else if (cpu_is_mx35()) { audmux_clk = clk_get(NULL, "audmux"); if (IS_ERR(audmux_clk)) { ret = PTR_ERR(audmux_clk); @@ -207,10 +200,7 @@ static int mxc_audmux_v2_init(void) return ret; } audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); - } -#endif -#if defined(CONFIG_SOC_IMX25) - if (cpu_is_mx25()) { + } else if (cpu_is_mx25()) { audmux_clk = clk_get(NULL, "audmux"); if (IS_ERR(audmux_clk)) { ret = PTR_ERR(audmux_clk); @@ -220,7 +210,7 @@ static int mxc_audmux_v2_init(void) } audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); } -#endif /* if defined(CONFIG_SOC_IMX25) */ + audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 0d6ed31..4d55a7a 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -23,73 +23,6 @@ #include <linux/platform_device.h> #include <mach/common.h> -int __init mxc_register_device(struct platform_device *pdev, void *data) -{ - int ret; - - pdev->dev.platform_data = data; - - ret = platform_device_register(pdev); - if (ret) - pr_debug("Unable to register platform device '%s': %d\n", - pdev->name, ret); - - return ret; -} - -struct platform_device *__init imx_add_platform_device_dmamask( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data, u64 dmamask) -{ - int ret = -ENOMEM; - struct platform_device *pdev; - - pdev = platform_device_alloc(name, id); - if (!pdev) - goto err; - - if (dmamask) { - /* - * This memory isn't freed when the device is put, - * I don't have a nice idea for that though. Conceptually - * dma_mask in struct device should not be a pointer. - * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 - */ - pdev->dev.dma_mask = - kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); - if (!pdev->dev.dma_mask) - /* ret is still -ENOMEM; */ - goto err; - - *pdev->dev.dma_mask = dmamask; - pdev->dev.coherent_dma_mask = dmamask; - } - - if (res) { - ret = platform_device_add_resources(pdev, res, num_resources); - if (ret) - goto err; - } - - if (data) { - ret = platform_device_add_data(pdev, data, size_data); - if (ret) - goto err; - } - - ret = platform_device_add(pdev); - if (ret) { -err: - if (dmamask) - kfree(pdev->dev.dma_mask); - platform_device_put(pdev); - return ERR_PTR(ret); - } - - return pdev; -} - struct device mxc_aips_bus = { .init_name = "mxc_aips", .parent = &platform_bus, diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index bd294ad..cb3e3ee 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -1,6 +1,6 @@ config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53 config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN @@ -31,6 +31,9 @@ config IMX_HAVE_PLATFORM_IMX_I2C config IMX_HAVE_PLATFORM_IMX_KEYPAD bool +config IMX_HAVE_PLATFORM_PATA_IMX + bool + config IMX_HAVE_PLATFORM_IMX_SSI bool @@ -76,3 +79,7 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX config IMX_HAVE_PLATFORM_SPI_IMX bool + +config IMX_HAVE_PLATFORM_AHCI + bool + default y if ARCH_MX53 diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index b41bf97..c11ac84 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -10,6 +10,7 @@ obj-y += platform-imx-dma.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o @@ -25,3 +26,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c new file mode 100644 index 0000000..d8a56ae --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/device.h> +#include <linux/dma-mapping.h> +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_ahci_imx_data_entry_single(soc, _devid) \ + { \ + .devid = _devid, \ + .iobase = soc ## _SATA_BASE_ADDR, \ + .irq = soc ## _INT_SATA, \ + } + +#ifdef CONFIG_SOC_IMX53 +const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst = + imx_ahci_imx_data_entry_single(MX53, "imx53-ahci"); +#endif + +enum { + HOST_CAP = 0x00, + HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ + HOST_PORTS_IMPL = 0x0c, + HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ +}; + +static struct clk *sata_clk, *sata_ref_clk; + +/* AHCI module Initialization, if return 0, initialization is successful. */ +static int imx_sata_init(struct device *dev, void __iomem *addr) +{ + u32 tmpdata; + int ret = 0; + struct clk *clk; + + sata_clk = clk_get(dev, "ahci"); + if (IS_ERR(sata_clk)) { + dev_err(dev, "no sata clock.\n"); + return PTR_ERR(sata_clk); + } + ret = clk_enable(sata_clk); + if (ret) { + dev_err(dev, "can't enable sata clock.\n"); + goto put_sata_clk; + } + + /* Get the AHCI SATA PHY CLK */ + sata_ref_clk = clk_get(dev, "ahci_phy"); + if (IS_ERR(sata_ref_clk)) { + dev_err(dev, "no sata ref clock.\n"); + ret = PTR_ERR(sata_ref_clk); + goto release_sata_clk; + } + ret = clk_enable(sata_ref_clk); + if (ret) { + dev_err(dev, "can't enable sata ref clock.\n"); + goto put_sata_ref_clk; + } + + /* Get the AHB clock rate, and configure the TIMER1MS reg later */ + clk = clk_get(dev, "ahci_dma"); + if (IS_ERR(clk)) { + dev_err(dev, "no dma clock.\n"); + ret = PTR_ERR(clk); + goto release_sata_ref_clk; + } + tmpdata = clk_get_rate(clk) / 1000; + clk_put(clk); + + writel(tmpdata, addr + HOST_TIMER1MS); + + tmpdata = readl(addr + HOST_CAP); + if (!(tmpdata & HOST_CAP_SSS)) { + tmpdata |= HOST_CAP_SSS; + writel(tmpdata, addr + HOST_CAP); + } + + if (!(readl(addr + HOST_PORTS_IMPL) & 0x1)) + writel((readl(addr + HOST_PORTS_IMPL) | 0x1), + addr + HOST_PORTS_IMPL); + + return 0; + +release_sata_ref_clk: + clk_disable(sata_ref_clk); +put_sata_ref_clk: + clk_put(sata_ref_clk); +release_sata_clk: + clk_disable(sata_clk); +put_sata_clk: + clk_put(sata_clk); + + return ret; +} + +static void imx_sata_exit(struct device *dev) +{ + clk_disable(sata_ref_clk); + clk_put(sata_ref_clk); + + clk_disable(sata_clk); + clk_put(sata_clk); + +} +struct platform_device *__init imx_add_ahci_imx( + const struct imx_ahci_imx_data *data, + const struct ahci_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device_dmamask(data->devid, 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} + +struct platform_device *__init imx53_add_ahci_imx(void) +{ + struct ahci_platform_data pdata = { + .init = imx_sata_init, + .exit = imx_sata_exit, + }; + + return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata); +} diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c index 23ce08e..848038f 100644 --- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -36,6 +36,11 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = imx_fsl_usb2_udc_data_entry_single(MX35); #endif /* ifdef CONFIG_SOC_IMX35 */ +#ifdef CONFIG_SOC_IMX51 +const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX51); +#endif + struct platform_device *__init imx_add_fsl_usb2_udc( const struct imx_fsl_usb2_udc_data *data, const struct fsl_usb2_platform_data *pdata) diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index afe60f7..19ad580 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -85,6 +85,12 @@ const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) imx51_imx_i2c_data_entry(0, 1), imx51_imx_i2c_data_entry(1, 2), + { + .id = 2, + .iobase = MX51_HSI2C_DMA_BASE_ADDR, + .iosize = SZ_16K, + .irq = MX51_INT_HS_I2C, + }, }; #endif /* ifdef CONFIG_SOC_IMX51 */ diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c index e1763e0..35851d8 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -49,6 +49,15 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = imx_mxc_ehci_data_entry_single(MX35, 1, HS); #endif /* ifdef CONFIG_SOC_IMX35 */ +#ifdef CONFIG_SOC_IMX51 +const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX51, 0, OTG); +const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX51, 1, HS1), + imx_mxc_ehci_data_entry_single(MX51, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + struct platform_device *__init imx_add_mxc_ehci( const struct imx_mxc_ehci_data *data, const struct mxc_usbh_platform_data *pdata) diff --git a/arch/arm/plat-mxc/devices/platform-pata_imx.c b/arch/arm/plat-mxc/devices/platform-pata_imx.c new file mode 100644 index 0000000..70e2f2a --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-pata_imx.c @@ -0,0 +1,59 @@ +/* + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_pata_imx_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _ATA_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_ATA, \ + } + +#ifdef CONFIG_SOC_IMX27 +const struct imx_pata_imx_data imx27_pata_imx_data __initconst = + imx_pata_imx_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_pata_imx_data imx31_pata_imx_data __initconst = + imx_pata_imx_data_entry_single(MX31, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_pata_imx_data imx35_pata_imx_data __initconst = + imx_pata_imx_data_entry_single(MX35, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_pata_imx_data imx51_pata_imx_data __initconst = + imx_pata_imx_data_entry_single(MX51, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_pata_imx_data imx53_pata_imx_data __initconst = + imx_pata_imx_data_entry_single(MX53, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX53 */ + +struct platform_device *__init imx_add_pata_imx( + const struct imx_pata_imx_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device("pata_imx", -1, + res, ARRAY_SIZE(res), NULL, 0); +} + diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 4e3d978..d7149d1 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -66,10 +66,20 @@ extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); -extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); extern void mxc_arch_reset_init(void __iomem *); extern void mx51_efikamx_reset(void); extern int mx53_revision(void); extern int mx53_display_revision(void); + +enum mxc_cpu_pwr_mode { + WAIT_CLOCKED, /* wfi only */ + WAIT_UNCLOCKED, /* WAIT */ + WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ + STOP_POWER_ON, /* just STOP */ + STOP_POWER_OFF, /* STOP + SRPG */ +}; + +extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); +extern void (*imx_idle)(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 524538a..def9ba5 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -14,10 +14,22 @@ extern struct device mxc_aips_bus; extern struct device mxc_ahb_bus; -struct platform_device *imx_add_platform_device_dmamask( +static inline struct platform_device *imx_add_platform_device_dmamask( const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data, u64 dmamask); + const void *data, size_t size_data, u64 dmamask) +{ + struct platform_device_info pdevinfo = { + .name = name, + .id = id, + .res = res, + .num_res = num_resources, + .data = data, + .size_data = size_data, + .dma_mask = dmamask, + }; + return platform_device_register_full(&pdevinfo); +} static inline struct platform_device *imx_add_platform_device( const char *name, int id, @@ -251,6 +263,14 @@ struct platform_device *__init imx_add_mxc_nand( const struct imx_mxc_nand_data *data, const struct mxc_nand_platform_data *pdata); +struct imx_pata_imx_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_pata_imx( + const struct imx_pata_imx_data *data); + struct imx_mxc_pwm_data { int id; resource_size_t iobase; @@ -301,3 +321,13 @@ struct platform_device *__init imx_add_spi_imx( struct platform_device *imx_add_imx_dma(void); struct platform_device *imx_add_imx_sdma(char *name, resource_size_t iobase, int irq, struct sdma_platform_data *pdata); + +#include <linux/ahci_platform.h> +struct imx_ahci_imx_data { + const char *devid; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_ahci_imx( + const struct imx_ahci_imx_data *data, + const struct ahci_platform_data *pdata); diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 3e1ffc8..40a8c17 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -1,33 +1 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_GPIO_H__ -#define __ASM_ARCH_MXC_GPIO_H__ - -#include <linux/spinlock.h> -#include <mach/hardware.h> - - -/* There's a off-by-one betweem the gpio bank number and the gpiochip */ -/* range e.g. GPIO_1_5 is gpio 5 under linux */ -#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) - -#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio)) -#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) - -#endif +/* empty */ diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index a8bfd56..eba3118 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -81,11 +81,16 @@ * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 * mx51: + * TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 - * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + * mx53: + * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 */ #define IMX_IO_P2V(x) ( \ 0xf4000000 + \ @@ -116,4 +121,10 @@ .type = _type, \ } +/* There's a off-by-one betweem the gpio bank number and the gpiochip */ +/* range e.g. GPIO_1_5 is gpio 5 under linux */ +#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) + +#define IMX_GPIO_TO_IRQ(gpio) (MXC_GPIO_IRQ_START + (gpio)) + #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/i2c.h b/arch/arm/plat-mxc/include/mach/i2c.h index 4a5dc5c..375cdd0 100644 --- a/arch/arm/plat-mxc/include/mach/i2c.h +++ b/arch/arm/plat-mxc/include/mach/i2c.h @@ -11,14 +11,10 @@ /** * struct imxi2c_platform_data - structure of platform data for MXC I2C driver - * @init: Initialise gpio's and other board specific things - * @exit: Free everything initialised by @init * @bitrate: Bus speed measured in Hz * **/ struct imxi2c_platform_data { - int (*init)(struct device *dev); - void (*exit)(struct device *dev); int bitrate; }; diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index 4347a87..338300b 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -14,32 +14,22 @@ /* Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff -#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35) -#include <mach/hardware.h> - #define __arch_ioremap __imx_ioremap #define __arch_iounmap __iounmap #define addr_in_module(addr, mod) \ ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) +extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int); + static inline void __iomem * __imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) { - if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) { - /* - * Access all peripherals below 0x80000000 as nonshared device - * on mx3, but leave l2cc alone. Otherwise cache corruptions - * can occur. - */ - if (phys_addr < 0x80000000 && - !addr_in_module(phys_addr, MX3x_L2CC)) - mtype = MT_DEVICE_NONSHARED; - } - - return __arm_ioremap(phys_addr, size, mtype); + if (imx_ioremap != NULL) + return imx_ioremap(phys_addr, size, mtype); + else + return __arm_ioremap(phys_addr, size, mtype); } -#endif /* io address mapping macro */ #define __io(a) __typesafe_io(a) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index df6acc0..c7f5169a 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -14,6 +14,8 @@ #define __MACH_IOMUX_MX51_H__ #include <mach/iomux-v3.h> +#define __NA_ 0x000 + /* Pad control groupings */ #define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ @@ -47,1521 +49,765 @@ /* Raw pin modes without pad control */ /* PAD MUX ALT INPSE PATH PADCTRL */ -#define _MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0) -#define _MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0) -#define _MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0) -#define _MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0) -#define _MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0) -#define _MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0) -#define _MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0) -#define _MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0) -#define _MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0) -#define _MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0) -#define _MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0) -#define _MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0) -#define _MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0) -#define _MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0) -#define _MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0) -#define _MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0) -#define _MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0) -#define _MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0) -#define _MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0) -#define _MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0) -#define _MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0) -#define _MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0) -#define _MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0) -#define _MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0) -#define _MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0) -#define _MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0) -#define _MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0) -#define _MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0) -#define _MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0) -#define _MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0) -#define _MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0) -#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0) -#define _MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0) -#define _MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0) -#define _MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0) -#define _MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0) -#define _MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0) -#define _MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0) -#define _MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0) -#define _MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0) -#define _MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0) -#define _MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0) -#define _MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0) -#define _MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0) -#define _MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0) -#define _MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0) -#define _MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0) -#define _MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0) -#define _MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0) -#define _MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0) -#define _MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0) -#define _MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0) -#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0) -#define _MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0) -#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0) -#define _MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0) -#define _MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0) -#define _MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0) -#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0) -#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0) -#define _MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0) -#define _MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0) -#define _MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0) -#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0) -#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0) -#define _MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0) -#define _MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0) -#define _MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0) -#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0) -#define _MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0) -#define _MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0) -#define _MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0) -#define _MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0) -#define _MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0) -#define _MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0) -#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0) -#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0) -#define _MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0) -#define _MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0) -#define _MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0) -#define _MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0) -#define _MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0) -#define _MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0) -#define _MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0) -#define _MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0) -#define _MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0) -#define _MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0) -#define _MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0) -#define _MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0) -#define _MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0) -#define _MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0) -#define _MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0) -#define _MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0) -#define _MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0) -#define _MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0) -#define _MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0) -#define _MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0) -#define _MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0) -#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0) -#define _MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0) -#define _MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0) -#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0) -#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0) -#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0) -#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0) -#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0) -#define _MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0) -#define _MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0) -#define _MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0) -#define _MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0) -#define _MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0) -#define _MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0) -#define _MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) -#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) -#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0) -#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) -#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) -#define _MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0) -#define _MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0) -#define _MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0) -#define _MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0) -#define _MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0) -#define _MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0) -#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0) -#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0) -#define _MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0) -#define _MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0) -#define _MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0) -#define _MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0) -#define _MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0) -#define _MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0) -#define _MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0) -#define _MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0) -#define _MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0) -#define _MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0) -#define _MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0) -#define _MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0) -#define _MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) -#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) -#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0) -#define _MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0) -#define _MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0) -#define _MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0) -#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0) -#define _MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0) -#define _MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0) -#define _MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0) -#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0) -#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0) -#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0) -#define _MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0) -#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0) -#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0) -#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0) -#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0) -#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0) -#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0) -#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0) -#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0) -#define _MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0) -#define _MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0) -#define _MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0) -#define _MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0) -#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0) -#define _MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0) -#define _MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0) -#define _MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0) -#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0) -#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0) -#define _MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0) -#define _MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0) -#define _MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0) -#define _MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0) -#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0) -#define _MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0) -#define _MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0) -#define _MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0) -#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0) -#define _MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0) -#define _MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0) -#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0) -#define _MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0) -#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0) -#define _MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0) -#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0) -#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0) -#define _MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0) -#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0) -#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0) -#define _MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0) -#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0) -#define _MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0) -#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0) -#define _MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0) -#define _MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0) -#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0) -#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0) -#define _MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0) -#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0) -#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0) -#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0) -#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0) -#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0) -#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0) -#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0) -#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0) -#define _MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0) -#define _MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0) -#define _MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0) -#define _MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0) -#define _MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0) -#define _MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0) -#define _MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0) -#define _MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0) -#define _MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0) -#define _MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0) -#define _MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0) -#define _MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0) -#define _MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0) -#define _MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0) -#define _MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0) -#define _MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0) -#define _MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0) -#define _MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0) -#define _MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0) -#define _MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0) -#define _MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0) -#define _MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0) -#define _MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0) -#define _MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0) -#define _MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0) -#define _MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0) -#define _MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0) -#define _MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0) -#define _MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0) -#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0) -#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0) -#define _MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0) -#define _MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0) -#define _MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0) -#define _MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0) /* The same pins as above but with the default pad control values applied */ -#define MX51_PAD_EIM_D16__AUD4_RXFS (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D16__AUD5_TXD (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D16__EIM_D16 (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D16__GPIO2_0 (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D16__I2C1_SDA (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_EIM_D16__UART2_CTS (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D16__USBH2_DATA0 (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D17__AUD5_RXD (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D17__EIM_D17 (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D17__GPIO2_1 (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D17__UART2_RXD (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D17__UART3_CTS (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D17__USBH2_DATA1 (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D18__AUD5_TXC (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D18__EIM_D18 (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D18__GPIO2_2 (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D18__UART2_TXD (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D18__UART3_RTS (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D18__USBH2_DATA2 (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D19__AUD4_RXC (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D19__AUD5_TXFS (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D19__EIM_D19 (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D19__GPIO2_3 (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D19__I2C1_SCL (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_EIM_D19__UART2_RTS (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D24__EIM_D24 (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D24__GPIO2_8 (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D24__I2C2_SDA (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_EIM_D24__UART3_CTS (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D24__USBOTG_DATA0 (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D25__EIM_D25 (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D25__KEY_COL6 (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D25__UART2_CTS (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D25__UART3_RXD (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D25__USBOTG_DATA1 (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D26__EIM_D26 (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D26__KEY_COL7 (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D26__UART2_RTS (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D26__UART3_TXD (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D26__USBOTG_DATA2 (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D27__AUD6_RXC (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D27__EIM_D27 (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D27__GPIO2_9 (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_D27__I2C2_SCL (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_EIM_D27__UART3_RTS (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_EIM_D27__USBOTG_DATA3 (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D28__AUD6_TXD (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D28__EIM_D28 (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D28__KEY_ROW4 (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D28__USBOTG_DATA4 (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D29__AUD6_RXD (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D29__EIM_D29 (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D29__KEY_ROW5 (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D29__USBOTG_DATA5 (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D30__AUD6_TXC (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D30__EIM_D30 (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D30__KEY_ROW6 (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D30__USBOTG_DATA6 (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D31__AUD6_TXFS (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D31__EIM_D31 (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D31__KEY_ROW7 (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_D31__USBOTG_DATA7 (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A16__EIM_A16 (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A16__GPIO2_10 (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A17__EIM_A17 (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A17__GPIO2_11 (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A18__BOOT_LPB0 (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A18__EIM_A18 (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A18__GPIO2_12 (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A19__BOOT_LPB1 (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A19__EIM_A19 (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A19__GPIO2_13 (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A20__EIM_A20 (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A20__GPIO2_14 (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A21__EIM_A21 (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A21__GPIO2_15 (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A22__EIM_A22 (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A22__GPIO2_16 (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A23__BOOT_HPN_EN (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A23__EIM_A23 (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A23__GPIO2_17 (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A24__EIM_A24 (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A24__GPIO2_18 (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A24__USBH2_CLK (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A25__DISP1_PIN4 (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A25__EIM_A25 (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A25__GPIO2_19 (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A25__USBH2_DIR (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A26__CSI1_DATA_EN (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A26__DISP2_EXT_CLK (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A26__EIM_A26 (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A26__GPIO2_20 (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A26__USBH2_STP (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A27__CSI2_DATA_EN (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A27__DISP1_PIN1 (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A27__EIM_A27 (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_A27__GPIO2_21 (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_A27__USBH2_NXT (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB0__EIM_EB0 (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB1__EIM_EB1 (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB2__AUD5_RXFS (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB2__CSI1_D2 (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB2__EIM_EB2 (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB2__FEC_MDIO (_MX51_PAD_EIM_EB2__FEC_MDIO | \ +#define MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL) +#define MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__FEC_MDIO (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \ MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) -#define MX51_PAD_EIM_EB2__GPIO2_22 (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB3__AUD5_RXC (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB3__CSI1_D3 (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB3__EIM_EB3 (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB3__FEC_RDATA1 (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_EB3__GPIO2_23 (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_OE__EIM_OE (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_OE__GPIO2_24 (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_CS0__EIM_CS0 (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS0__GPIO2_25 (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_CS1__EIM_CS1 (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS1__GPIO2_26 (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_CS2__AUD5_TXD (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS2__CSI1_D4 (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS2__EIM_CS2 (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS2__FEC_RDATA2 (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS2__GPIO2_27 (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_CS2__USBOTG_STP (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS3__AUD5_RXD (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS3__CSI1_D5 (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS3__EIM_CS3 (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS3__FEC_RDATA3 (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS3__GPIO2_28 (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_CS3__USBOTG_NXT (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS4__AUD5_TXC (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS4__CSI1_D6 (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS4__EIM_CS4 (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS4__FEC_RX_ER (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) -#define MX51_PAD_EIM_CS4__GPIO2_29 (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_CS4__USBOTG_CLK (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS5__AUD5_TXFS (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS5__CSI1_D7 (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS5__EIM_CS5 (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CS5__FEC_CRS (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) -#define MX51_PAD_EIM_CS5__GPIO2_30 (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_CS5__USBOTG_DIR (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DTACK__EIM_DTACK (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DTACK__GPIO2_31 (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_LBA__EIM_LBA (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_LBA__GPIO3_1 (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_EIM_CRE__EIM_CRE (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) -#define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) -#define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_CS2__FEC_TX_ER (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) -#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) -#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D14__ECSPI2_SS3 (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_D14__GPIO3_26 (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D9__FEC_RDATA0 (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) -#define MX51_PAD_NANDF_D9__GPIO3_31 (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D9__NANDF_D9 (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D9__PATA_DATA9 (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D9__SD3_DATA1 (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D8__FEC_TDATA0 (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_NANDF_D8__GPIO4_0 (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D8__NANDF_D8 (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D8__CSI1_D8 (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D8__GPIO3_12 (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI1_D9__CSI1_D9 (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D9__GPIO3_13 (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI1_D10__CSI1_D10 (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D11__CSI1_D11 (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D12__CSI1_D12 (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D13__CSI1_D13 (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D14__CSI1_D14 (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D15__CSI1_D15 (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D16__CSI1_D16 (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D17__CSI1_D17 (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D18__CSI1_D18 (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_D19__CSI1_D19 (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_VSYNC__GPIO3_14 (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_HSYNC__GPIO3_15 (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D12__CSI2_D12 (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D12__GPIO4_9 (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI2_D13__CSI2_D13 (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D13__GPIO4_10 (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI2_D14__CSI2_D14 (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D15__CSI2_D15 (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D16__CSI2_D16 (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D17__CSI2_D17 (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D18__CSI2_D18 (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D18__GPIO4_11 (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI2_D19__CSI2_D19 (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_D19__GPIO4_12 (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_VSYNC__GPIO4_13 (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_HSYNC__GPIO4_14 (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_I2C1_CLK__GPIO4_16 (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_I2C1_CLK__I2C1_CLK (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_I2C1_DAT__GPIO4_17 (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_I2C1_DAT__I2C1_DAT (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_RXD__UART3_RXD (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_CK__AUD3_TXC (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_CK__GPIO4_20 (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_FS__GPIO4_21 (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_AUD3_BB_FS__UART3_TXD (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_CSPI1_MOSI__GPIO4_22 (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSPI1_MOSI__I2C1_SDA (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_CSPI1_MISO__AUD4_RXD (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_CSPI1_MISO__GPIO4_23 (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSPI1_SS0__AUD4_TXC (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_CSPI1_SS0__GPIO4_24 (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSPI1_SS1__AUD4_TXD (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_CSPI1_SS1__GPIO4_25 (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSPI1_RDY__AUD4_TXFS (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_CSPI1_RDY__GPIO4_26 (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_CSPI1_SCLK__GPIO4_27 (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_CSPI1_SCLK__I2C1_SCL (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_UART1_RXD__GPIO4_28 (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_UART1_RXD__UART1_RXD (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_UART1_TXD__GPIO4_29 (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_UART1_TXD__PWM2_PWMO (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_UART1_TXD__UART1_TXD (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_UART1_RTS__GPIO4_30 (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_UART1_RTS__UART1_RTS (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_UART1_CTS__GPIO4_31 (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_UART1_CTS__UART1_CTS (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_UART2_RXD__FIRI_TXD (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_UART2_RXD__GPIO1_20 (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_UART2_RXD__UART2_RXD (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_UART2_TXD__FIRI_RXD (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_UART2_TXD__GPIO1_21 (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_UART2_TXD__UART2_TXD (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_UART3_RXD__CSI1_D0 (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_UART3_RXD__GPIO1_22 (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_UART3_RXD__UART1_DTR (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_UART3_RXD__UART3_RXD (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_UART3_TXD__CSI1_D1 (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_UART3_TXD__GPIO1_23 (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_UART3_TXD__UART1_DSR (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_UART3_TXD__UART3_TXD (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_OWIRE_LINE__GPIO1_24 (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_OWIRE_LINE__OWIRE_LINE (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_OWIRE_LINE__SPDIF_OUT (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_ROW0__KEY_ROW0 (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_ROW1__KEY_ROW1 (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_ROW2__KEY_ROW2 (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_ROW3__KEY_ROW3 (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL0__KEY_COL0 (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL0__PLL1_BYP (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL1__KEY_COL1 (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL1__PLL2_BYP (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL2__KEY_COL2 (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL2__PLL3_BYP (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL3__KEY_COL3 (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL4__I2C2_SCL (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_KEY_COL4__KEY_COL4 (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL4__SPDIF_OUT1 (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL4__UART1_RI (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_KEY_COL4__UART3_RTS (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_KEY_COL5__I2C2_SDA (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_KEY_COL5__KEY_COL5 (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_KEY_COL5__UART1_DCD (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_KEY_COL5__UART3_CTS (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_USBH1_CLK__CSPI_SCLK (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_CLK__GPIO1_25 (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_CLK__I2C2_SCL (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_USBH1_CLK__USBH1_CLK (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DIR__CSPI_MOSI (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_DIR__GPIO1_26 (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DIR__I2C2_SDA (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_USBH1_DIR__USBH1_DIR (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_STP__CSPI_RDY (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_STP__GPIO1_27 (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_STP__UART3_RXD (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_USBH1_STP__USBH1_STP (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_NXT__CSPI_MISO (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_NXT__GPIO1_28 (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_NXT__UART3_TXD (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_USBH1_NXT__USBH1_NXT (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA0__GPIO1_11 (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA0__UART2_CTS (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA1__GPIO1_12 (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA1__UART2_RXD (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA2__GPIO1_13 (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA2__UART2_TXD (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA3__GPIO1_14 (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA3__UART2_RTS (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA4__CSPI_SS0 (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA4__GPIO1_15 (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA5__CSPI_SS1 (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA5__GPIO1_16 (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA6__CSPI_SS3 (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA6__GPIO1_17 (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA7__GPIO1_18 (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) -#define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN3__DI1_PIN3 (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI1_PIN2__DI1_PIN2 (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP2__DISP1_SER_CLK (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP2__DISP2_WAIT (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP3__CSI1_DATA_EN (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP3__DISP1_SER_DIO (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP3__FEC_TX_ER (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI2_PIN4__DI2_PIN4 (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI2_PIN4__FEC_CRS (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI2_PIN2__DI2_PIN2 (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI2_PIN2__FEC_MDC (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_DI2_PIN3__DI2_PIN3 (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI2_PIN3__FEC_MDIO (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP4__DI2_PIN15 (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP4__DISP1_SER_DIN (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP4__DISP2_PIN1 (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DI_GP4__FEC_RDATA2 (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT0__KEY_COL6 (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT0__UART3_RXD (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT0__USBH3_CLK (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT1__FEC_RX_ER (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT1__KEY_COL7 (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT1__UART3_TXD (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT1__USBH3_DIR (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_DISP2_DAT6__GPIO1_19 (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT6__KEY_ROW4 (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT6__USBH3_STP (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_DISP2_DAT7__GPIO1_29 (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT7__KEY_ROW5 (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT7__USBH3_NXT (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_DISP2_DAT8__GPIO1_30 (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT8__KEY_ROW6 (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT9__AUD6_RXC (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT9__FEC_TX_EN (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_DISP2_DAT9__GPIO1_31 (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT10__FEC_COL (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT10__KEY_ROW7 (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT11__AUD6_TXD (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT11__GPIO1_10 (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT12__AUD6_RXD (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT12__FEC_RX_DV (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT13__AUD6_TXC (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) -#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT14__AUD6_TXFS (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) -#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT15__AUD6_RXFS (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) -#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_CMD__AUD5_RXFS (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_CMD__CSPI_MOSI (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_CMD__SD1_CMD (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_SD1_CLK__AUD5_RXC (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_CLK__CSPI_SCLK (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) -#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) -#define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) -#define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA14__EIM_DA14 (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_EIM_DA15__EIM_DA15 (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_CMD__CSPI_MOSI (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_SD2_CMD__I2C1_SCL (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_SD2_CMD__SD2_CMD (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_SD2_CLK__CSPI_SCLK (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_SD2_CLK__I2C1_SDA (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) -#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) -#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) -#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) -#define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) -#define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) -#define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL) +#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL) +#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL) +#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4) +#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4) +#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index 5408fd1..527f8fe 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -23,2359 +23,1197 @@ /* These 2 defines are for pins that may not have a mux register, but could * have a pad setting register, and vice-versa. */ -#define NON_PAD_I 0x00 +#define __NA_ 0x00 #define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ PAD_CTL_SRE_FAST) -#define PAD_CTRL_I2C (PAD_CTL_SRE_FAST | PAD_CTL_ODE | PAD_CTL_PKE | \ - PAD_CTL_PUE | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP \ - | PAD_CTL_HYS) -#define _MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0) -#define _MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0) -#define _MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0) -#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0) -#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0) -#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0) -#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0) -#define _MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0) -#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x2C, 4, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0) -#define _MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0) -#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0) -#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0) -#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0) -#define _MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0) -#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0) -#define _MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0) -#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0) -#define _MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0) -#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0) -#define _MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0) -#define _MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0) -#define _MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0) -#define _MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0) -#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0) -#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0) -#define _MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0) -#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0) -#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0) -#define _MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x48, 4, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0) -#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0) -#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0) -#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0) -#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0) -#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0) -#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0) -#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0) -#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0) -#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0) -#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0) -#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0) -#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0) -#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0) -#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0) -#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0) -#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0) -#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0) -#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0) -#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0) -#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0) -#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0) -#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0) -#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0) -#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0) -#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0) -#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0) -#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0) -#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0) -#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0) -#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0) -#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0) -#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0) -#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0) -#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0) -#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0) -#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0) -#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0) -#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0) -#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0) -#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0) -#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0) -#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0) -#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0) -#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0) -#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0) -#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0) -#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0) -#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0) -#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0) -#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0) -#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0) -#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0) -#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0) -#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0) -#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0) -#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0) -#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0) -#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0) -#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0xF0, 2, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0) -#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0xF8, 2, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0) -#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0) -#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0) -#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0) -#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0) -#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0) -#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0) -#define _MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0) -#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0) -#define _MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, 0) -#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0) -#define _MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0) -#define _MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, 0) -#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0) -#define _MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0) -#define _MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, 0) -#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0) -#define _MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0) -#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0) -#define _MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0) -#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0) -#define _MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, 0) -#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0) -#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0) -#define _MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0) -#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0) -#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0) -#define _MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0) -#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0) -#define _MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0) -#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0) -#define _MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0) -#define _MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0) -#define _MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0) -#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0) -#define _MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0) -#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0) -#define _MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0) -#define _MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0) -#define _MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, 0) -#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0) -#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0) -#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0) -#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0) -#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0) -#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0) -#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0) -#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0) -#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0) -#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0) -#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0) -#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0) -#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0) -#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0) -#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0) -#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0) -#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0) -#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0) -#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0) -#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0) -#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0) -#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0) -#define _MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0) -#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0) -#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0) -#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0) -#define _MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0) -#define _MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0) -#define _MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0) -#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0) -#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0) -#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0) -#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0) -#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0) -#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0) -#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0) -#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0) -#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0) -#define _MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0) -#define _MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0) -#define _MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0) -#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0) -#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0) -#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0) -#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0) -#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0) -#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0) -#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0) -#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0) -#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0) -#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0) -#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0) -#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0) -#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0) -#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0) -#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0) -#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0) -#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0) -#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0) -#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0) -#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0) -#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0) -#define _MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0) -#define _MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0) -#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0) -#define _MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0) -#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0) -#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0) -#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0) -#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0) -#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0) -#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0) -#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0) -#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0) -#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0) -#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0) -#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0) -#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0) -#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0) -#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0) -#define _MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0) -#define _MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0) -#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0) -#define _MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0) -#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0) -#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0) -#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0) -#define _MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0) -#define _MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0) -#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0) -#define _MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0) -#define _MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0) -#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0) -#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0) -#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0) -#define _MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0) -#define _MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0) -#define _MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0) -#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0) -#define _MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0) -#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0) -#define _MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0) -#define _MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0) -#define _MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0) -#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0) -#define _MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0) -#define _MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0) -#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0) -#define _MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0) -#define _MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0) -#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0) -#define _MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0) -#define _MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0) -#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0) -#define _MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0) -#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0) -#define _MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0) -#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0) -#define _MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0) -#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0) -#define _MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0) -#define _MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0) -#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0) -#define _MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0) -#define _MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0) -#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0) -#define _MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0) -#define _MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0) -#define _MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0) -#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0) -#define _MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0) -#define _MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0) -#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0) -#define _MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0) -#define _MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0) -#define _MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0) -#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0) -#define _MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0) -#define _MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0) -#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0) -#define _MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0) -#define _MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0) -#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0) -#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0) -#define _MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0) -#define _MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, 0) -#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0) -#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0) -#define _MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0) -#define _MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0) -#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0) -#define _MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0) -#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0) -#define _MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0) -#define _MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0) -#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0) -#define _MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0) -#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0) -#define _MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0) -#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0) -#define _MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0) -#define _MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0) -#define _MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0) -#define _MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0) -#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0) -#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0) -#define _MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0) -#define _MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0) -#define _MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0) -#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0) -#define _MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0) -#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0) -#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0) -#define _MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0) -#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0) -#define MX53_PAD_GPIO_19__KPP_COL_5 (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_19__GPIO4_5 (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_19__CCM_CLKO (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_19__SPDIF_OUT1 (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_19__ECSPI1_RDY (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_19__FEC_TDATA_3 (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_19__SRC_INT_BOOT (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL0__KPP_COL_0 (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL0__GPIO4_6 (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL0__UART4_TXD_MUX (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_KEY_COL0__ECSPI1_SCLK (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL0__FEC_RDATA_3 (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW0__KPP_ROW_0 (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW0__GPIO4_7 (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW0__FEC_TX_ER (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL1__KPP_COL_1 (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL1__GPIO4_8 (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL1__UART5_TXD_MUX (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_KEY_COL1__ECSPI1_MISO (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL1__FEC_RX_CLK (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW1__KPP_ROW_1 (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW1__GPIO4_9 (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW1__FEC_COL (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL2__KPP_COL_2 (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL2__GPIO4_10 (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL2__CAN1_TXCAN (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL2__FEC_MDIO (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL2__ECSPI1_SS1 (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL2__FEC_RDATA_2 (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW2__KPP_ROW_2 (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW2__GPIO4_11 (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW2__CAN1_RXCAN (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW2__FEC_MDC (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL3__KPP_COL_3 (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL3__GPIO4_12 (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL3__USBOH3_H2_DP (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL3__SPDIF_IN1 (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL3__I2C2_SCL (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_KEY_COL3__ECSPI1_SS3 (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL3__FEC_CRS (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW3__KPP_ROW_3 (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW3__GPIO4_13 (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW3__I2C2_SDA (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL4__KPP_COL_4 (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL4__GPIO4_14 (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL4__CAN2_TXCAN (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL4__IPU_SISG_4 (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL4__UART5_RTS (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW4__KPP_ROW_4 (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW4__GPIO4_15 (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW4__CAN2_RXCAN (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW4__IPU_SISG_5 (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW4__UART5_CTS (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN15__GPIO4_17 (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN2__GPIO4_18 (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN3__GPIO4_19 (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN4__GPIO4_20 (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN4__ESDHC1_WP (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT0__GPIO4_21 (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT0__CSPI_SCLK (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT1__GPIO4_22 (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT1__CSPI_MOSI (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT2__GPIO4_23 (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT2__CSPI_MISO (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT3__GPIO4_24 (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT3__CSPI_SS0 (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT4__GPIO4_25 (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT4__CSPI_SS1 (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT5__GPIO4_26 (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT5__CSPI_SS2 (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT6__GPIO4_27 (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT6__CSPI_SS3 (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT7__GPIO4_28 (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT7__CSPI_RDY (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT8__GPIO4_29 (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT8__PWM1_PWMO (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT9__GPIO4_30 (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT9__PWM2_PWMO (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT10__GPIO4_31 (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT11__GPIO5_5 (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT12__GPIO5_6 (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT13__GPIO5_7 (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT14__GPIO5_8 (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT15__GPIO5_9 (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT16__GPIO5_10 (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT17__GPIO5_11 (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT18__GPIO5_12 (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT19__GPIO5_13 (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT20__GPIO5_14 (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT21__GPIO5_15 (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT22__GPIO5_16 (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT23__GPIO5_17 (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_MCLK__GPIO5_19 (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_VSYNC__GPIO5_21 (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT4__GPIO5_22 (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT4__KPP_COL_5 (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT5__GPIO5_23 (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT6__GPIO5_24 (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT6__KPP_COL_6 (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT7__GPIO5_25 (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT8__GPIO5_26 (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT8__KPP_COL_7 (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT8__I2C1_SDA (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT9__GPIO5_27 (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT9__I2C1_SCL (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT10__GPIO5_28 (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT11__GPIO5_29 (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT12__GPIO5_30 (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT13__GPIO5_31 (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT14__GPIO6_0 (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT15__GPIO6_1 (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT16__GPIO6_2 (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT16__UART4_RTS (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT17__GPIO6_3 (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT17__UART4_CTS (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT18__GPIO6_4 (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT18__UART5_RTS (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT19__GPIO6_5 (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT19__UART5_CTS (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A25__GPIO5_2 (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A25__ECSPI2_RDY (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A25__CSPI_SS1 (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A25__USBPHY1_BISTOK (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB2__GPIO2_30 (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB2__ECSPI1_SS0 (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB2__I2C2_SCL (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D16__GPIO3_16 (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D16__ECSPI1_SCLK (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D16__I2C2_SDA (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D17__GPIO3_17 (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D17__ECSPI1_MISO (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D17__I2C3_SCL (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D18__GPIO3_18 (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D18__ECSPI1_MOSI (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D18__I2C3_SDA (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D19__GPIO3_19 (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D19__ECSPI1_SS1 (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D19__EPIT1_EPITO (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D19__UART1_CTS (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D20__GPIO3_20 (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D20__CSPI_SS0 (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D20__EPIT2_EPITO (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D20__UART1_RTS (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D21__GPIO3_21 (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D21__CSPI_SCLK (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D21__I2C1_SCL (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D22__GPIO3_22 (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D22__CSPI_MISO (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D23__GPIO3_23 (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D23__UART3_CTS (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D23__UART1_DCD (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB3__GPIO2_31 (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB3__UART3_RTS (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_EB3__UART1_RI (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D24__GPIO3_24 (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D24__UART3_TXD_MUX (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D24__ECSPI1_SS2 (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D24__CSPI_SS2 (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D24__ECSPI2_SS2 (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D24__UART1_DTR (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D25__GPIO3_25 (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D25__UART3_RXD_MUX (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D25__ECSPI1_SS3 (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D25__CSPI_SS3 (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D25__ECSPI2_SS3 (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D25__UART1_DSR (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D26__GPIO3_26 (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D26__UART2_TXD_MUX (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D26__FIRI_RXD (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D26__IPU_SISG_2 (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D27__GPIO3_27 (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D27__UART2_RXD_MUX (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D27__FIRI_TXD (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D27__IPU_SISG_3 (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D28__GPIO3_28 (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D28__CSPI_MOSI (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_EIM_D28__IPU_EXT_TRIG (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D29__GPIO3_29 (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D29__UART2_RTS (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D29__CSPI_SS0 (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D30__GPIO3_30 (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D30__UART3_CTS (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D31__GPIO3_31 (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D31__UART3_RTS (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A24__GPIO5_4 (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A24__IPU_SISG_2 (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A24__USBPHY2_BVALID (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A23__GPIO6_6 (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A23__IPU_SISG_3 (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A22__GPIO2_16 (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A21__GPIO2_17 (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A20__GPIO2_18 (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A19__GPIO2_19 (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A18__GPIO2_20 (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A17__GPIO2_21 (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A16__GPIO2_22 (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_CS0__GPIO2_23 (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_CS0__ECSPI2_SCLK (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_CS1__GPIO2_24 (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_CS1__ECSPI2_MOSI (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_OE__EMI_WEIM_OE (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_OE__GPIO2_25 (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_OE__ECSPI2_MISO (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_OE__USBPHY2_IDDIG (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_RW__EMI_WEIM_RW (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_RW__GPIO2_26 (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_RW__ECSPI2_SS0 (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_LBA__GPIO2_27 (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_LBA__ECSPI2_SS1 (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB0__GPIO2_28 (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB1__GPIO2_29 (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA0__GPIO3_0 (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA1__GPIO3_1 (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA2__GPIO3_2 (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA3__GPIO3_3 (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA4__GPIO3_4 (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA5__GPIO3_5 (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA6__GPIO3_6 (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA7__GPIO3_7 (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA8__GPIO3_8 (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA9__GPIO3_9 (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA10__GPIO3_10 (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA11__GPIO3_11 (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA12__GPIO3_12 (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA13__GPIO3_13 (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA14__GPIO3_14 (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA15__GPIO3_15 (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_WE_B__GPIO6_12 (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_RE_B__GPIO6_13 (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_WAIT__GPIO5_0 (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_10__GPIO4_0 (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_10__OSC32k_32K_OUT (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_11__GPIO4_1 (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_12__GPIO4_2 (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_13__GPIO4_3 (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_14__GPIO4_4 (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CLE__GPIO6_7 (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_ALE__GPIO6_8 (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_WP_B__GPIO6_9 (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_RB0__GPIO6_10 (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS0__GPIO6_11 (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS1__GPIO6_14 (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS1__MLB_MLBCLK (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS2__GPIO6_15 (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS2__IPU_SISG_0 (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS2__ESAI1_TX0 (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS2__MLB_MLBSIG (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS3__GPIO6_16 (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS3__IPU_SISG_1 (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS3__ESAI1_TX1 (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS3__MLB_MLBDAT (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDIO__FEC_MDIO (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDIO__GPIO1_22 (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDIO__ESAI1_SCKR (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDIO__FEC_COL (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_REF_CLK__GPIO1_23 (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RX_ER__FEC_RX_ER (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RX_ER__GPIO1_24 (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_CRS_DV__GPIO1_25 (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD1__GPIO1_26 (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD1__ESAI1_FST (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD1__MLB_MLBSIG (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD0__GPIO1_27 (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD0__ESAI1_HCKT (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TX_EN__FEC_TX_EN (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TX_EN__GPIO1_28 (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD1__GPIO1_29 (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD1__MLB_MLBCLK (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD0__GPIO1_30 (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDC__FEC_MDC (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDC__GPIO1_31 (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDC__MLB_MLBDAT (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DIOW__PATA_DIOW (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DIOW__GPIO6_17 (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DMACK__PATA_DMACK (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DMACK__GPIO6_18 (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DMARQ__PATA_DMARQ (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DMARQ__GPIO7_0 (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_INTRQ__PATA_INTRQ (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_INTRQ__GPIO7_2 (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_INTRQ__UART2_CTS (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DIOR__PATA_DIOR (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DIOR__GPIO7_3 (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DIOR__UART2_RTS (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_DIOR__CAN1_RXCAN (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_RESET_B__GPIO7_4 (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_IORDY__PATA_IORDY (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_IORDY__GPIO7_5 (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_IORDY__CAN2_RXCAN (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_0__PATA_DA_0 (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_0__GPIO7_6 (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_0__ESDHC3_RST (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_0__OWIRE_LINE (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_1__PATA_DA_1 (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_1__GPIO7_7 (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_1__ESDHC4_CMD (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DA_1__UART3_CTS (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_2__PATA_DA_2 (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_2__GPIO7_8 (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DA_2__ESDHC4_CLK (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DA_2__UART3_RTS (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_CS_0__PATA_CS_0 (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_CS_0__GPIO7_9 (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_CS_1__PATA_CS_1 (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_CS_1__GPIO7_10 (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA0__PATA_DATA_0 (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA0__GPIO2_0 (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA1__PATA_DATA_1 (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA1__GPIO2_1 (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA2__PATA_DATA_2 (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA2__GPIO2_2 (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA3__PATA_DATA_3 (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA3__GPIO2_3 (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA4__PATA_DATA_4 (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA4__GPIO2_4 (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA5__PATA_DATA_5 (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA5__GPIO2_5 (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA6__PATA_DATA_6 (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA6__GPIO2_6 (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA7__PATA_DATA_7 (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA7__GPIO2_7 (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__PATA_DATA_8 (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__GPIO2_8 (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__PATA_DATA_9 (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__GPIO2_9 (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__PATA_DATA_10 (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__GPIO2_10 (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__PATA_DATA_11 (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__GPIO2_11 (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__PATA_DATA_12 (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__GPIO2_12 (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__PATA_DATA_13 (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__GPIO2_13 (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__PATA_DATA_14 (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__GPIO2_14 (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__PATA_DATA_15 (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__GPIO2_15 (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD1_DATA0__GPIO1_16 (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA0__CSPI_MISO (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD1_DATA1__GPIO1_17 (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA1__CSPI_SS0 (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CMD__ESDHC1_CMD (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD1_CMD__GPIO1_18 (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CMD__CSPI_MOSI (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__GPIO1_19 (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__PWM2_PWMO (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__CSPI_SS1 (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CLK__ESDHC1_CLK (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD1_CLK__GPIO1_20 (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CLK__GPT_CLKIN (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CLK__CSPI_SCLK (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__GPIO1_21 (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__PWM1_PWMO (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__CSPI_SS2 (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CLK__ESDHC2_CLK (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD2_CLK__GPIO1_10 (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CLK__KPP_COL_5 (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CLK__CSPI_SCLK (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CLK__SCC_RANDOM_V (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CMD__ESDHC2_CMD (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD2_CMD__GPIO1_11 (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CMD__KPP_ROW_5 (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CMD__CSPI_MOSI (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_CMD__SCC_RANDOM (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD2_DATA3__GPIO1_12 (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA3__KPP_COL_6 (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA3__CSPI_SS2 (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA3__SJC_DONE (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD2_DATA2__GPIO1_13 (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA2__KPP_ROW_6 (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA2__CSPI_SS1 (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA2__SJC_FAIL (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD2_DATA1__GPIO1_14 (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA1__KPP_COL_7 (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA1__CSPI_SS0 (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) -#define MX53_PAD_SD2_DATA0__GPIO1_15 (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA0__KPP_ROW_7 (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA0__CSPI_MISO (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_0__CCM_CLKO (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_0__GPIO1_0 (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_0__KPP_COL_5 (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_0__EPIT1_EPITO (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_0__CSU_TD (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_1__ESAI1_SCKR (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_1__GPIO1_1 (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_1__KPP_ROW_5 (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_1__PWM2_PWMO (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_1__WDOG2_WDOG_B (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_1__ESDHC1_CD (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_1__SRC_TESTER_ACK (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_9__ESAI1_FSR (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_9__GPIO1_9 (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_9__KPP_COL_6 (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_9__CCM_REF_EN_B (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_9__PWM1_PWMO (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_9__WDOG1_WDOG_B (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_9__ESDHC1_WP (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_9__SCC_FAIL_STATE (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_3__ESAI1_HCKR (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_3__GPIO1_3 (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_3__I2C3_SCL (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_3__CCM_CLKO2 (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_3__MLB_MLBCLK (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_6__ESAI1_SCKT (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_6__GPIO1_6 (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_6__I2C3_SDA (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_6__ESDHC2_LCTL (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_6__MLB_MLBSIG (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_2__ESAI1_FST (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_2__GPIO1_2 (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_2__KPP_ROW_6 (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_2__ESDHC2_WP (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_2__MLB_MLBDAT (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_4__ESAI1_HCKT (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_4__GPIO1_4 (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_4__KPP_COL_7 (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_4__ESDHC2_CD (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_4__SCC_SEC_STATE (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_5__GPIO1_5 (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_5__KPP_ROW_7 (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_5__CCM_CLKO (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_5__I2C3_SCL (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_GPIO_5__CCM_PLL1_BYP (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_7__GPIO1_7 (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_7__EPIT1_EPITO (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_7__CAN1_TXCAN (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_7__UART2_TXD_MUX (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_GPIO_7__FIRI_RXD (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_7__SPDIF_PLOCK (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_7__CCM_PLL2_BYP (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_8__GPIO1_8 (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_8__EPIT2_EPITO (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_8__CAN1_RXCAN (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_8__UART2_RXD_MUX (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) -#define MX53_PAD_GPIO_8__FIRI_TXD (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_8__SPDIF_SRCLK (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_8__CCM_PLL3_BYP (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_16__GPIO7_11 (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_16__SPDIF_IN1 (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_16__I2C3_SDA (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) -#define MX53_PAD_GPIO_16__SJC_DE_B (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_17__ESAI1_TX0 (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_17__GPIO7_12 (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_17__GPC_PMIC_RDY (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_17__SPDIF_OUT1 (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_17__IPU_SNOOP2 (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_17__SJC_JTAG_ACT (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_18__ESAI1_TX1 (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_18__GPIO7_13 (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_18__OWIRE_LINE (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_18__ESDHC1_LCTL (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ + IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ + IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ + IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ + IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ + IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ + IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ + IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \ + IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \ + IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \ + IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \ + IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ + IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C) +#define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL) +#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL) +#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) +#define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index ebbce33..2fa3b54 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -80,6 +80,7 @@ typedef u64 iomux_v3_cfg_t; ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) +#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad)) /* * Use to set PAD control */ @@ -89,11 +90,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_HYS (1 << 8) #define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6) -#define PAD_CTL_PUS_100K_DOWN (0 << 4) -#define PAD_CTL_PUS_47K_UP (1 << 4) -#define PAD_CTL_PUS_100K_UP (2 << 4) -#define PAD_CTL_PUS_22K_UP (3 << 4) +#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) +#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) #define PAD_CTL_ODE (1 << 3) diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 1dc1c52..6265357 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -24,10 +24,6 @@ #ifndef __MACH_MX27_H__ #define __MACH_MX27_H__ -#ifndef __ASSEMBLER__ -#include <linux/io.h> -#endif - #define MX27_AIPI_BASE_ADDR 0x10000000 #define MX27_AIPI_SIZE SZ_1M #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) @@ -131,16 +127,6 @@ #define MX27_IO_P2V(x) IMX_IO_P2V(x) #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) -#ifndef __ASSEMBLER__ -static inline void mx27_setup_weimcs(size_t cs, - unsigned upper, unsigned lower, unsigned addional) -{ - __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs))); - __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs))); - __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs))); -} -#endif - /* fixed interrupt numbers */ #define MX27_INT_I2C2 1 #define MX27_INT_GPT6 2 diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 79e7fc0..e27619e 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -1,10 +1,6 @@ #ifndef __MACH_MX31_H__ #define __MACH_MX31_H__ -#ifndef __ASSEMBLER__ -#include <linux/io.h> -#endif - /* * IRAM */ @@ -122,16 +118,6 @@ #define MX31_IO_P2V(x) IMX_IO_P2V(x) #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) -#ifndef __ASSEMBLER__ -static inline void mx31_setup_weimcs(size_t cs, - unsigned upper, unsigned lower, unsigned addional) -{ - __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs))); - __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs))); - __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs))); -} -#endif - #define MX31_INT_I2C3 3 #define MX31_INT_I2C2 4 #define MX31_INT_MPEG4_ENCODER 5 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index d13dbfe..80965a9 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -36,7 +36,7 @@ #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) #define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) -#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) +#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) #define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) #define MX35_FEC_BASE_ADDR 0x50038000 #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index dede19a..cdf07c6 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -18,18 +18,6 @@ #define MX51_GPU_CTRL_BASE_ADDR 0x30000000 #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 -#define MX51_DEBUG_BASE_ADDR 0x60000000 -#define MX51_DEBUG_SIZE SZ_1M - -#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) -#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000) -#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000) -#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000) -#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000) -#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000) -#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000) -#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000) - /* * SPBA global module enabled #0 */ @@ -55,7 +43,10 @@ #define MX51_AIPS1_BASE_ADDR 0x73f00000 #define MX51_AIPS1_SIZE SZ_1M -#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) +#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) +#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000) +#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200) +#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400) #define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) #define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) @@ -132,6 +123,7 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 +#define MX51_TZIC_SIZE SZ_16K #define MX51_IO_P2V(x) IMX_IO_P2V(x) #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) @@ -240,117 +232,114 @@ /* * Interrupt numbers */ -#define MX51_MXC_INT_BASE 0 -#define MX51_MXC_INT_RESV0 0 +#define MX51_INT_BASE 0 +#define MX51_INT_RESV0 0 #define MX51_INT_ESDHC1 1 #define MX51_INT_ESDHC2 2 #define MX51_INT_ESDHC3 3 #define MX51_INT_ESDHC4 4 -#define MX51_MXC_INT_RESV5 5 +#define MX51_INT_RESV5 5 #define MX51_INT_SDMA 6 -#define MX51_MXC_INT_IOMUX 7 +#define MX51_INT_IOMUX 7 #define MX51_INT_NFC 8 -#define MX51_MXC_INT_VPU 9 +#define MX51_INT_VPU 9 #define MX51_INT_IPU_ERR 10 #define MX51_INT_IPU_SYN 11 -#define MX51_MXC_INT_GPU 12 -#define MX51_MXC_INT_RESV13 13 -#define MX51_MXC_INT_USB_H1 14 -#define MX51_MXC_INT_EMI 15 -#define MX51_MXC_INT_USB_H2 16 -#define MX51_MXC_INT_USB_H3 17 -#define MX51_MXC_INT_USB_OTG 18 -#define MX51_MXC_INT_SAHARA_H0 19 -#define MX51_MXC_INT_SAHARA_H1 20 -#define MX51_MXC_INT_SCC_SMN 21 -#define MX51_MXC_INT_SCC_STZ 22 -#define MX51_MXC_INT_SCC_SCM 23 -#define MX51_MXC_INT_SRTC_NTZ 24 -#define MX51_MXC_INT_SRTC_TZ 25 -#define MX51_MXC_INT_RTIC 26 -#define MX51_MXC_INT_CSU 27 -#define MX51_MXC_INT_SLIM_B 28 +#define MX51_INT_GPU 12 +#define MX51_INT_RESV13 13 +#define MX51_INT_USB_HS1 14 +#define MX51_INT_EMI 15 +#define MX51_INT_USB_HS2 16 +#define MX51_INT_USB_HS3 17 +#define MX51_INT_USB_OTG 18 +#define MX51_INT_SAHARA_H0 19 +#define MX51_INT_SAHARA_H1 20 +#define MX51_INT_SCC_SMN 21 +#define MX51_INT_SCC_STZ 22 +#define MX51_INT_SCC_SCM 23 +#define MX51_INT_SRTC_NTZ 24 +#define MX51_INT_SRTC_TZ 25 +#define MX51_INT_RTIC 26 +#define MX51_INT_CSU 27 +#define MX51_INT_SLIM_B 28 #define MX51_INT_SSI1 29 #define MX51_INT_SSI2 30 #define MX51_INT_UART1 31 #define MX51_INT_UART2 32 #define MX51_INT_UART3 33 -#define MX51_MXC_INT_RESV34 34 -#define MX51_MXC_INT_RESV35 35 +#define MX51_INT_RESV34 34 +#define MX51_INT_RESV35 35 #define MX51_INT_ECSPI1 36 #define MX51_INT_ECSPI2 37 #define MX51_INT_CSPI 38 -#define MX51_MXC_INT_GPT 39 -#define MX51_MXC_INT_EPIT1 40 -#define MX51_MXC_INT_EPIT2 41 -#define MX51_MXC_INT_GPIO1_INT7 42 -#define MX51_MXC_INT_GPIO1_INT6 43 -#define MX51_MXC_INT_GPIO1_INT5 44 -#define MX51_MXC_INT_GPIO1_INT4 45 -#define MX51_MXC_INT_GPIO1_INT3 46 -#define MX51_MXC_INT_GPIO1_INT2 47 -#define MX51_MXC_INT_GPIO1_INT1 48 -#define MX51_MXC_INT_GPIO1_INT0 49 -#define MX51_MXC_INT_GPIO1_LOW 50 -#define MX51_MXC_INT_GPIO1_HIGH 51 -#define MX51_MXC_INT_GPIO2_LOW 52 -#define MX51_MXC_INT_GPIO2_HIGH 53 -#define MX51_MXC_INT_GPIO3_LOW 54 -#define MX51_MXC_INT_GPIO3_HIGH 55 -#define MX51_MXC_INT_GPIO4_LOW 56 -#define MX51_MXC_INT_GPIO4_HIGH 57 -#define MX51_MXC_INT_WDOG1 58 -#define MX51_MXC_INT_WDOG2 59 +#define MX51_INT_GPT 39 +#define MX51_INT_EPIT1 40 +#define MX51_INT_EPIT2 41 +#define MX51_INT_GPIO1_INT7 42 +#define MX51_INT_GPIO1_INT6 43 +#define MX51_INT_GPIO1_INT5 44 +#define MX51_INT_GPIO1_INT4 45 +#define MX51_INT_GPIO1_INT3 46 +#define MX51_INT_GPIO1_INT2 47 +#define MX51_INT_GPIO1_INT1 48 +#define MX51_INT_GPIO1_INT0 49 +#define MX51_INT_GPIO1_LOW 50 +#define MX51_INT_GPIO1_HIGH 51 +#define MX51_INT_GPIO2_LOW 52 +#define MX51_INT_GPIO2_HIGH 53 +#define MX51_INT_GPIO3_LOW 54 +#define MX51_INT_GPIO3_HIGH 55 +#define MX51_INT_GPIO4_LOW 56 +#define MX51_INT_GPIO4_HIGH 57 +#define MX51_INT_WDOG1 58 +#define MX51_INT_WDOG2 59 #define MX51_INT_KPP 60 #define MX51_INT_PWM1 61 #define MX51_INT_I2C1 62 #define MX51_INT_I2C2 63 -#define MX51_MXC_INT_HS_I2C 64 -#define MX51_MXC_INT_RESV65 65 -#define MX51_MXC_INT_RESV66 66 -#define MX51_MXC_INT_SIM_IPB 67 -#define MX51_MXC_INT_SIM_DAT 68 -#define MX51_MXC_INT_IIM 69 -#define MX51_MXC_INT_ATA 70 -#define MX51_MXC_INT_CCM1 71 -#define MX51_MXC_INT_CCM2 72 -#define MX51_MXC_INT_GPC1 73 -#define MX51_MXC_INT_GPC2 74 -#define MX51_MXC_INT_SRC 75 -#define MX51_MXC_INT_NM 76 -#define MX51_MXC_INT_PMU 77 -#define MX51_MXC_INT_CTI_IRQ 78 -#define MX51_MXC_INT_CTI1_TG0 79 -#define MX51_MXC_INT_CTI1_TG1 80 -#define MX51_MXC_INT_MCG_ERR 81 -#define MX51_MXC_INT_MCG_TMR 82 -#define MX51_MXC_INT_MCG_FUNC 83 -#define MX51_MXC_INT_GPU2_IRQ 84 -#define MX51_MXC_INT_GPU2_BUSY 85 -#define MX51_MXC_INT_RESV86 86 +#define MX51_INT_HS_I2C 64 +#define MX51_INT_RESV65 65 +#define MX51_INT_RESV66 66 +#define MX51_INT_SIM_IPB 67 +#define MX51_INT_SIM_DAT 68 +#define MX51_INT_IIM 69 +#define MX51_INT_ATA 70 +#define MX51_INT_CCM1 71 +#define MX51_INT_CCM2 72 +#define MX51_INT_GPC1 73 +#define MX51_INT_GPC2 74 +#define MX51_INT_SRC 75 +#define MX51_INT_NM 76 +#define MX51_INT_PMU 77 +#define MX51_INT_CTI_IRQ 78 +#define MX51_INT_CTI1_TG0 79 +#define MX51_INT_CTI1_TG1 80 +#define MX51_INT_MCG_ERR 81 +#define MX51_INT_MCG_TMR 82 +#define MX51_INT_MCG_FUNC 83 +#define MX51_INT_GPU2_IRQ 84 +#define MX51_INT_GPU2_BUSY 85 +#define MX51_INT_RESV86 86 #define MX51_INT_FEC 87 -#define MX51_MXC_INT_OWIRE 88 -#define MX51_MXC_INT_CTI1_TG2 89 -#define MX51_MXC_INT_SJC 90 -#define MX51_MXC_INT_SPDIF 91 -#define MX51_MXC_INT_TVE 92 -#define MX51_MXC_INT_FIRI 93 +#define MX51_INT_OWIRE 88 +#define MX51_INT_CTI1_TG2 89 +#define MX51_INT_SJC 90 +#define MX51_INT_SPDIF 91 +#define MX51_INT_TVE 92 +#define MX51_INT_FIRI 93 #define MX51_INT_PWM2 94 -#define MX51_MXC_INT_SLIM_EXP 95 +#define MX51_INT_SLIM_EXP 95 #define MX51_INT_SSI3 96 -#define MX51_MXC_INT_EMI_BOOT 97 -#define MX51_MXC_INT_CTI1_TG3 98 -#define MX51_MXC_INT_SMC_RX 99 -#define MX51_MXC_INT_VPU_IDLE 100 -#define MX51_MXC_INT_EMI_NFC 101 -#define MX51_MXC_INT_GPU_IDLE 102 +#define MX51_INT_EMI_BOOT 97 +#define MX51_INT_CTI1_TG3 98 +#define MX51_INT_SMC_RX 99 +#define MX51_INT_VPU_IDLE 100 +#define MX51_INT_EMI_NFC 101 +#define MX51_INT_GPU_IDLE 102 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx51_revision(void); extern void mx51_display_revision(void); #endif -/* tape-out 1 defines */ -#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000 - #endif /* ifndef __MACH_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 5e3c323..a37e8c3 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -9,6 +9,7 @@ /* TZIC */ #define MX53_TZIC_BASE_ADDR 0x0FFFC000 +#define MX53_TZIC_SIZE SZ_16K /* * AHCI SATA diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 0987923..00a7819 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -183,13 +183,6 @@ struct cpu_op { }; int tzic_enable_wake(int is_idle); -enum mxc_cpu_pwr_mode { - WAIT_CLOCKED, /* wfi only */ - WAIT_UNCLOCKED, /* WAIT */ - WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ - STOP_POWER_ON, /* just STOP */ - STOP_POWER_OFF, /* STOP + SRPG */ -}; extern struct cpu_op *(*get_cpu_op)(int *op); #endif diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 51f02a9..cf88b35 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -17,41 +17,12 @@ #ifndef __ASM_ARCH_MXC_SYSTEM_H__ #define __ASM_ARCH_MXC_SYSTEM_H__ -#include <mach/hardware.h> -#include <mach/common.h> - -extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); +extern void (*imx_idle)(void); static inline void arch_idle(void) { - /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ - if (cpu_is_mx31() || cpu_is_mx35()) { - unsigned long reg = 0; - __asm__ __volatile__( - /* disable I and D cache */ - "mrc p15, 0, %0, c1, c0, 0\n" - "bic %0, %0, #0x00001000\n" - "bic %0, %0, #0x00000004\n" - "mcr p15, 0, %0, c1, c0, 0\n" - /* invalidate I cache */ - "mov %0, #0\n" - "mcr p15, 0, %0, c7, c5, 0\n" - /* clear and invalidate D cache */ - "mov %0, #0\n" - "mcr p15, 0, %0, c7, c14, 0\n" - /* WFI */ - "mov %0, #0\n" - "mcr p15, 0, %0, c7, c0, 4\n" - "nop\n" "nop\n" "nop\n" "nop\n" - "nop\n" "nop\n" "nop\n" - /* enable I and D cache */ - "mrc p15, 0, %0, c1, c0, 0\n" - "orr %0, %0, #0x00001000\n" - "orr %0, %0, #0x00000004\n" - "mcr p15, 0, %0, c1, c0, 0\n" - : "=r" (reg)); - } else if (cpu_is_mx51()) - mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + if (imx_idle != NULL) + (imx_idle)(); else cpu_do_idle(); } diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 8024f2a..9dad8dc 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -28,6 +28,9 @@ #include <asm/system.h> #include <asm/mach-types.h> +void (*imx_idle)(void) = NULL; +void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL; + static void __iomem *wdog_base; /* diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig index ce65901..bca4914 100644 --- a/arch/arm/plat-nomadik/Kconfig +++ b/arch/arm/plat-nomadik/Kconfig @@ -15,10 +15,16 @@ if PLAT_NOMADIK config HAS_MTU bool - select HAVE_SCHED_CLOCK help Support for Multi Timer Unit. MTU provides access to multiple interrupt generating programmable 32-bit free running decrementing counters. +config NOMADIK_MTU_SCHED_CLOCK + bool + depends on HAS_MTU + select HAVE_SCHED_CLOCK + help + Use the Multi Timer Unit as the sched_clock. + endif diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h index 3ba4d8f..9605bf2 100644 --- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h +++ b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h @@ -67,6 +67,9 @@ extern int nmk_gpio_get_mode(int gpio); extern void nmk_gpio_wakeups_suspend(void); extern void nmk_gpio_wakeups_resume(void); +extern void nmk_gpio_clocks_enable(void); +extern void nmk_gpio_clocks_disable(void); + extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up); /* diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h index 65704a3..6508e76 100644 --- a/arch/arm/plat-nomadik/include/plat/mtu.h +++ b/arch/arm/plat-nomadik/include/plat/mtu.h @@ -1,54 +1,11 @@ #ifndef __PLAT_MTU_H #define __PLAT_MTU_H -/* - * Guaranteed runtime conversion range in seconds for - * the clocksource and clockevent. - */ -#define MTU_MIN_RANGE 4 - /* should be set by the platform code */ extern void __iomem *mtu_base; -/* - * The MTU device hosts four different counters, with 4 set of - * registers. These are register names. - */ - -#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ -#define MTU_RIS 0x04 /* Raw interrupt status */ -#define MTU_MIS 0x08 /* Masked interrupt status */ -#define MTU_ICR 0x0C /* Interrupt clear register */ - -/* per-timer registers take 0..3 as argument */ -#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ -#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ -#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ -#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ - -/* bits for the control register */ -#define MTU_CRn_ENA 0x80 -#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ -#define MTU_CRn_PRESCALE_MASK 0x0c -#define MTU_CRn_PRESCALE_1 0x00 -#define MTU_CRn_PRESCALE_16 0x04 -#define MTU_CRn_PRESCALE_256 0x08 -#define MTU_CRn_32BITS 0x02 -#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ - -/* Other registers are usual amba/primecell registers, currently not used */ -#define MTU_ITCR 0xff0 -#define MTU_ITOP 0xff4 - -#define MTU_PERIPH_ID0 0xfe0 -#define MTU_PERIPH_ID1 0xfe4 -#define MTU_PERIPH_ID2 0xfe8 -#define MTU_PERIPH_ID3 0xfeC - -#define MTU_PCELL0 0xff0 -#define MTU_PCELL1 0xff4 -#define MTU_PCELL2 0xff8 -#define MTU_PCELL3 0xffC +void nmdk_clkevt_reset(void); +void nmdk_clksrc_reset(void); #endif /* __PLAT_MTU_H */ diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h index 05a3936..22cb97d 100644 --- a/arch/arm/plat-nomadik/include/plat/pincfg.h +++ b/arch/arm/plat-nomadik/include/plat/pincfg.h @@ -37,7 +37,6 @@ * SLPM value = same as normal * * PIN_CFG - default config with alternate function - * PIN_CFG_PULL - default config with alternate function and pull up/down */ typedef unsigned long pin_cfg_t; @@ -133,10 +132,6 @@ typedef unsigned long pin_cfg_t; (PIN_CFG_DEFAULT |\ (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) -#define PIN_CFG_PULL(num, alt, pull) \ - ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ - (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) - extern int nmk_config_pin(pin_cfg_t cfg, bool sleep); extern int nmk_config_pins(pin_cfg_t *cfgs, int num); extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num); diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index ef74e157..30b6433 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c @@ -21,10 +21,59 @@ #include <asm/mach/time.h> #include <asm/sched_clock.h> -#include <plat/mtu.h> +/* + * Guaranteed runtime conversion range in seconds for + * the clocksource and clockevent. + */ +#define MTU_MIN_RANGE 4 + +/* + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. + */ + +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + +static bool clkevt_periodic; +static u32 clk_prescale; +static u32 nmdk_cycle; /* write-once */ void __iomem *mtu_base; /* Assigned by machine code */ +#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK /* * Override the global weak sched_clock symbol with this * local implementation which uses the clocksource to get some @@ -48,32 +97,56 @@ static void notrace nomadik_update_sched_clock(void) u32 cyc = -readl(mtu_base + MTU_VAL(0)); update_sched_clock(&cd, cyc, (u32)~0); } +#endif /* Clockevent device: use one-shot mode */ +static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) +{ + writel(1 << 1, mtu_base + MTU_IMSC); + writel(evt, mtu_base + MTU_LR(1)); + /* Load highest value, enable device, enable interrupts */ + writel(MTU_CRn_ONESHOT | clk_prescale | + MTU_CRn_32BITS | MTU_CRn_ENA, + mtu_base + MTU_CR(1)); + + return 0; +} + +void nmdk_clkevt_reset(void) +{ + if (clkevt_periodic) { + + /* Timer: configure load and background-load, and fire it up */ + writel(nmdk_cycle, mtu_base + MTU_LR(1)); + writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); + + writel(MTU_CRn_PERIODIC | clk_prescale | + MTU_CRn_32BITS | MTU_CRn_ENA, + mtu_base + MTU_CR(1)); + writel(1 << 1, mtu_base + MTU_IMSC); + } else { + /* Generate an interrupt to start the clockevent again */ + (void) nmdk_clkevt_next(nmdk_cycle, NULL); + } +} + static void nmdk_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) { - u32 cr; switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - pr_err("%s: periodic mode not supported\n", __func__); + clkevt_periodic = true; + nmdk_clkevt_reset(); break; case CLOCK_EVT_MODE_ONESHOT: - /* Load highest value, enable device, enable interrupts */ - cr = readl(mtu_base + MTU_CR(1)); - writel(0, mtu_base + MTU_LR(1)); - writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1)); - writel(1 << 1, mtu_base + MTU_IMSC); + clkevt_periodic = false; break; case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: - /* disable irq */ writel(0, mtu_base + MTU_IMSC); /* disable timer */ - cr = readl(mtu_base + MTU_CR(1)); - cr &= ~MTU_CRn_ENA; - writel(cr, mtu_base + MTU_CR(1)); + writel(0, mtu_base + MTU_CR(1)); /* load some high default value */ writel(0xffffffff, mtu_base + MTU_LR(1)); break; @@ -82,16 +155,9 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode, } } -static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) -{ - /* writing the value has immediate effect */ - writel(evt, mtu_base + MTU_LR(1)); - return 0; -} - static struct clock_event_device nmdk_clkevt = { .name = "mtu_1", - .features = CLOCK_EVT_FEAT_ONESHOT, + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, .rating = 200, .set_mode = nmdk_clkevt_mode, .set_next_event = nmdk_clkevt_next, @@ -116,11 +182,23 @@ static struct irqaction nmdk_timer_irq = { .dev_id = &nmdk_clkevt, }; +void nmdk_clksrc_reset(void) +{ + /* Disable */ + writel(0, mtu_base + MTU_CR(0)); + + /* ClockSource: configure load and background-load, and fire it up */ + writel(nmdk_cycle, mtu_base + MTU_LR(0)); + writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); + + writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, + mtu_base + MTU_CR(0)); +} + void __init nmdk_timer_init(void) { unsigned long rate; struct clk *clk0; - u32 cr = MTU_CRn_32BITS; clk0 = clk_get_sys("mtu0", NULL); BUG_ON(IS_ERR(clk0)); @@ -138,30 +216,28 @@ void __init nmdk_timer_init(void) rate = clk_get_rate(clk0); if (rate > 32000000) { rate /= 16; - cr |= MTU_CRn_PRESCALE_16; + clk_prescale = MTU_CRn_PRESCALE_16; } else { - cr |= MTU_CRn_PRESCALE_1; + clk_prescale = MTU_CRn_PRESCALE_1; } + nmdk_cycle = (rate + HZ/2) / HZ; + + /* Timer 0 is the free running clocksource */ - writel(cr, mtu_base + MTU_CR(0)); - writel(0, mtu_base + MTU_LR(0)); - writel(0, mtu_base + MTU_BGLR(0)); - writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); + nmdk_clksrc_reset(); if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0", rate, 200, 32, clocksource_mmio_readl_down)) pr_err("timer: failed to initialize clock source %s\n", "mtu_0"); - +#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate); - +#endif /* Timer 1 is used for events */ clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE); - writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ - nmdk_clkevt.max_delta_ns = clockevent_delta2ns(0xffffffff, &nmdk_clkevt); nmdk_clkevt.min_delta_ns = diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 95732af..aa59f42 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -14,6 +14,7 @@ config ARCH_OMAP1 select CLKDEV_LOOKUP select CLKSRC_MMIO select GENERIC_IRQ_CHIP + select HAVE_IDE select NEED_MACH_MEMORY_H help "Systems based on omap7xx, omap15xx or omap16xx" @@ -133,18 +134,6 @@ config OMAP_MBOX_KFIFO_SIZE This can also be changed at runtime (via the mbox_kfifo_size module parameter). -config OMAP_IOMMU - tristate - -config OMAP_IOMMU_DEBUG - tristate "Export OMAP IOMMU internals in DebugFS" - depends on OMAP_IOMMU && DEBUG_FS - help - Select this to see extensive information about - the internal state of OMAP IOMMU in debugfs. - - Say N unless you know you need this. - config OMAP_IOMMU_IVA2 bool diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index f0233e6..9852622 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -18,8 +18,6 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_device.o obj-$(CONFIG_ARCH_OMAP4) += omap_device.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o -obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o -obj-$(CONFIG_OMAP_IOMMU_DEBUG) += iommu-debug.o obj-$(CONFIG_CPU_FREQ) += cpu-omap.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 64c3bd4..1971932 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -25,89 +25,8 @@ #include <plat/board.h> #include <plat/mmc.h> #include <plat/menelaus.h> -#include <plat/mcbsp.h> #include <plat/omap44xx.h> -/*-------------------------------------------------------------------------*/ - -#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE) - -static struct platform_device **omap_mcbsp_devices; - -void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, - struct omap_mcbsp_platform_data *config, int size) -{ - int i; - - omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *), - GFP_KERNEL); - if (!omap_mcbsp_devices) { - printk(KERN_ERR "Could not register McBSP devices\n"); - return; - } - - for (i = 0; i < size; i++) { - struct platform_device *new_mcbsp; - int ret; - - new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1); - if (!new_mcbsp) - continue; - platform_device_add_resources(new_mcbsp, &res[i * res_count], - res_count); - new_mcbsp->dev.platform_data = &config[i]; - ret = platform_device_add(new_mcbsp); - if (ret) { - platform_device_put(new_mcbsp); - continue; - } - omap_mcbsp_devices[i] = new_mcbsp; - } -} - -#else -void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, - struct omap_mcbsp_platform_data *config, int size) -{ } -#endif - -/*-------------------------------------------------------------------------*/ - -#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ - defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) - -static struct resource mcpdm_resources[] = { - { - .name = "mcpdm_mem", - .start = OMAP44XX_MCPDM_BASE, - .end = OMAP44XX_MCPDM_BASE + SZ_4K, - .flags = IORESOURCE_MEM, - }, - { - .name = "mcpdm_irq", - .start = OMAP44XX_IRQ_MCPDM, - .end = OMAP44XX_IRQ_MCPDM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device omap_mcpdm_device = { - .name = "omap-mcpdm", - .id = -1, - .num_resources = ARRAY_SIZE(mcpdm_resources), - .resource = mcpdm_resources, -}; - -static void omap_init_mcpdm(void) -{ - (void) platform_device_register(&omap_mcpdm_device); -} -#else -static inline void omap_init_mcpdm(void) {} -#endif - -/*-------------------------------------------------------------------------*/ - #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) @@ -290,7 +209,6 @@ static int __init omap_init_devices(void) * in alphabetical order so they're easier to sort through. */ omap_init_rng(); - omap_init_mcpdm(); omap_init_uwire(); return 0; } diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 75a847d..2def4e1 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -3,6 +3,12 @@ * * OMAP Dual-Mode Timers * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Tarun Kanti DebBarma <tarun.kanti@ti.com> + * Thara Gopinath <thara@ti.com> + * + * dmtimer adaptation to platform_driver. + * * Copyright (C) 2005 Nokia Corporation * OMAP2 support by Juha Yrjola * API improvements and OMAP2 clock framework support by Timo Teras @@ -29,168 +35,80 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/errno.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <linux/delay.h> #include <linux/io.h> -#include <linux/module.h> -#include <mach/hardware.h> -#include <plat/dmtimer.h> -#include <mach/irqs.h> - -static int dm_timer_count; - -#ifdef CONFIG_ARCH_OMAP1 -static struct omap_dm_timer omap1_dm_timers[] = { - { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, - { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, - { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, - { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 }, - { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 }, - { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 }, - { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 }, - { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, -}; - -static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers); - -#else -#define omap1_dm_timers NULL -#define omap1_dm_timer_count 0 -#endif /* CONFIG_ARCH_OMAP1 */ - -#ifdef CONFIG_ARCH_OMAP2 -static struct omap_dm_timer omap2_dm_timers[] = { - { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, - { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, - { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, - { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 }, - { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 }, - { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 }, - { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 }, - { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 }, - { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 }, - { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, - { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, - { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, -}; - -static const char *omap2_dm_source_names[] __initdata = { - "sys_ck", - "func_32k_ck", - "alt_ck", - NULL -}; - -static struct clk *omap2_dm_source_clocks[3]; -static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers); - -#else -#define omap2_dm_timers NULL -#define omap2_dm_timer_count 0 -#define omap2_dm_source_names NULL -#define omap2_dm_source_clocks NULL -#endif /* CONFIG_ARCH_OMAP2 */ - -#ifdef CONFIG_ARCH_OMAP3 -static struct omap_dm_timer omap3_dm_timers[] = { - { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, - { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, - { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 }, - { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 }, - { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 }, - { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 }, - { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 }, - { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 }, - { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 }, - { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, - { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, - { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ }, -}; - -static const char *omap3_dm_source_names[] __initdata = { - "sys_ck", - "omap_32k_fck", - NULL -}; - -static struct clk *omap3_dm_source_clocks[2]; -static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers); +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/pm_runtime.h> -#else -#define omap3_dm_timers NULL -#define omap3_dm_timer_count 0 -#define omap3_dm_source_names NULL -#define omap3_dm_source_clocks NULL -#endif /* CONFIG_ARCH_OMAP3 */ - -#ifdef CONFIG_ARCH_OMAP4 -static struct omap_dm_timer omap4_dm_timers[] = { - { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 }, - { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 }, - { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 }, - { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 }, - { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 }, - { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 }, - { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 }, - { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 }, - { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 }, - { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 }, - { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 }, - { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 }, -}; -static const char *omap4_dm_source_names[] __initdata = { - "sys_clkin_ck", - "sys_32k_ck", - NULL -}; -static struct clk *omap4_dm_source_clocks[2]; -static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers); - -#else -#define omap4_dm_timers NULL -#define omap4_dm_timer_count 0 -#define omap4_dm_source_names NULL -#define omap4_dm_source_clocks NULL -#endif /* CONFIG_ARCH_OMAP4 */ - -static struct omap_dm_timer *dm_timers; -static const char **dm_source_names; -static struct clk **dm_source_clocks; +#include <plat/dmtimer.h> -static spinlock_t dm_timer_lock; +static LIST_HEAD(omap_timer_list); +static DEFINE_SPINLOCK(dm_timer_lock); -/* - * Reads timer registers in posted and non-posted mode. The posted mode bit - * is encoded in reg. Note that in posted mode write pending bit must be - * checked. Otherwise a read of a non completed write will produce an error. +/** + * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode + * @timer: timer pointer over which read operation to perform + * @reg: lowest byte holds the register offset + * + * The posted mode bit is encoded in reg. Note that in posted mode write + * pending bit must be checked. Otherwise a read of a non completed write + * will produce an error. */ static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) { - return __omap_dm_timer_read(timer->io_base, reg, timer->posted); + WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); + return __omap_dm_timer_read(timer, reg, timer->posted); } -/* - * Writes timer registers in posted and non-posted mode. The posted mode bit - * is encoded in reg. Note that in posted mode the write pending bit must be - * checked. Otherwise a write on a register which has a pending write will be - * lost. +/** + * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode + * @timer: timer pointer over which write operation is to perform + * @reg: lowest byte holds the register offset + * @value: data to write into the register + * + * The posted mode bit is encoded in reg. Note that in posted mode the write + * pending bit must be checked. Otherwise a write on a register which has a + * pending write will be lost. */ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, u32 value) { - __omap_dm_timer_write(timer->io_base, reg, value, timer->posted); + WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); + __omap_dm_timer_write(timer, reg, value, timer->posted); +} + +static void omap_timer_restore_context(struct omap_dm_timer *timer) +{ + omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET, + timer->context.tiocp_cfg); + if (timer->revision > 1) + __raw_writel(timer->context.tistat, timer->sys_stat); + + __raw_writel(timer->context.tisr, timer->irq_stat); + omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, + timer->context.twer); + omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, + timer->context.tcrr); + omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, + timer->context.tldr); + omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, + timer->context.tmar); + omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, + timer->context.tsicr); + __raw_writel(timer->context.tier, timer->irq_ena); + omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, + timer->context.tclr); } static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) { int c; + if (!timer->sys_stat) + return; + c = 0; - while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) { + while (!(__raw_readl(timer->sys_stat) & 1)) { c++; if (c > 100000) { printk(KERN_ERR "Timer failed to reset\n"); @@ -201,53 +119,65 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) static void omap_dm_timer_reset(struct omap_dm_timer *timer) { - int autoidle = 0, wakeup = 0; - - if (!cpu_class_is_omap2() || timer != &dm_timers[0]) { + omap_dm_timer_enable(timer); + if (timer->pdev->id != 1) { omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); omap_dm_timer_wait_for_reset(timer); } - omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); - - /* Enable autoidle on OMAP2+ */ - if (cpu_class_is_omap2()) - autoidle = 1; - - /* - * Enable wake-up on OMAP2 CPUs. - */ - if (cpu_class_is_omap2()) - wakeup = 1; - __omap_dm_timer_reset(timer->io_base, autoidle, wakeup); + __omap_dm_timer_reset(timer, 0, 0); + omap_dm_timer_disable(timer); timer->posted = 1; } -void omap_dm_timer_prepare(struct omap_dm_timer *timer) +int omap_dm_timer_prepare(struct omap_dm_timer *timer) { - omap_dm_timer_enable(timer); - omap_dm_timer_reset(timer); + struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; + int ret; + + timer->fclk = clk_get(&timer->pdev->dev, "fck"); + if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { + timer->fclk = NULL; + dev_err(&timer->pdev->dev, ": No fclk handle.\n"); + return -EINVAL; + } + + if (pdata->needs_manual_reset) + omap_dm_timer_reset(timer); + + ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); + + timer->posted = 1; + return ret; } struct omap_dm_timer *omap_dm_timer_request(void) { - struct omap_dm_timer *timer = NULL; + struct omap_dm_timer *timer = NULL, *t; unsigned long flags; - int i; + int ret = 0; spin_lock_irqsave(&dm_timer_lock, flags); - for (i = 0; i < dm_timer_count; i++) { - if (dm_timers[i].reserved) + list_for_each_entry(t, &omap_timer_list, node) { + if (t->reserved) continue; - timer = &dm_timers[i]; + timer = t; timer->reserved = 1; break; } + + if (timer) { + ret = omap_dm_timer_prepare(timer); + if (ret) { + timer->reserved = 0; + timer = NULL; + } + } spin_unlock_irqrestore(&dm_timer_lock, flags); - if (timer != NULL) - omap_dm_timer_prepare(timer); + if (!timer) + pr_debug("%s: timer request failed!\n", __func__); return timer; } @@ -255,74 +185,65 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_request); struct omap_dm_timer *omap_dm_timer_request_specific(int id) { - struct omap_dm_timer *timer; + struct omap_dm_timer *timer = NULL, *t; unsigned long flags; + int ret = 0; spin_lock_irqsave(&dm_timer_lock, flags); - if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) { - spin_unlock_irqrestore(&dm_timer_lock, flags); - printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n", - __FILE__, __LINE__, __func__, id); - dump_stack(); - return NULL; + list_for_each_entry(t, &omap_timer_list, node) { + if (t->pdev->id == id && !t->reserved) { + timer = t; + timer->reserved = 1; + break; + } } - timer = &dm_timers[id-1]; - timer->reserved = 1; + if (timer) { + ret = omap_dm_timer_prepare(timer); + if (ret) { + timer->reserved = 0; + timer = NULL; + } + } spin_unlock_irqrestore(&dm_timer_lock, flags); - omap_dm_timer_prepare(timer); + if (!timer) + pr_debug("%s: timer%d request failed!\n", __func__, id); return timer; } EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); -void omap_dm_timer_free(struct omap_dm_timer *timer) +int omap_dm_timer_free(struct omap_dm_timer *timer) { - omap_dm_timer_enable(timer); - omap_dm_timer_reset(timer); - omap_dm_timer_disable(timer); + if (unlikely(!timer)) + return -EINVAL; + + clk_put(timer->fclk); WARN_ON(!timer->reserved); timer->reserved = 0; + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_free); void omap_dm_timer_enable(struct omap_dm_timer *timer) { - if (timer->enabled) - return; - -#ifdef CONFIG_ARCH_OMAP2PLUS - if (cpu_class_is_omap2()) { - clk_enable(timer->fclk); - clk_enable(timer->iclk); - } -#endif - - timer->enabled = 1; + pm_runtime_get_sync(&timer->pdev->dev); } EXPORT_SYMBOL_GPL(omap_dm_timer_enable); void omap_dm_timer_disable(struct omap_dm_timer *timer) { - if (!timer->enabled) - return; - -#ifdef CONFIG_ARCH_OMAP2PLUS - if (cpu_class_is_omap2()) { - clk_disable(timer->iclk); - clk_disable(timer->fclk); - } -#endif - - timer->enabled = 0; + pm_runtime_put(&timer->pdev->dev); } EXPORT_SYMBOL_GPL(omap_dm_timer_disable); int omap_dm_timer_get_irq(struct omap_dm_timer *timer) { - return timer->irq; + if (timer) + return timer->irq; + return -EINVAL; } EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); @@ -334,24 +255,29 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); */ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) { - int i; + int i = 0; + struct omap_dm_timer *timer = NULL; + unsigned long flags; /* If ARMXOR cannot be idled this function call is unnecessary */ if (!(inputmask & (1 << 1))) return inputmask; /* If any active timer is using ARMXOR return modified mask */ - for (i = 0; i < dm_timer_count; i++) { + spin_lock_irqsave(&dm_timer_lock, flags); + list_for_each_entry(timer, &omap_timer_list, node) { u32 l; - l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG); + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (l & OMAP_TIMER_CTRL_ST) { if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) inputmask &= ~(1 << 1); else inputmask &= ~(1 << 2); } + i++; } + spin_unlock_irqrestore(&dm_timer_lock, flags); return inputmask; } @@ -361,7 +287,9 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) { - return timer->fclk; + if (timer) + return timer->fclk; + return NULL; } EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); @@ -375,70 +303,91 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); #endif -void omap_dm_timer_trigger(struct omap_dm_timer *timer) +int omap_dm_timer_trigger(struct omap_dm_timer *timer) { + if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { + pr_err("%s: timer not available or enabled.\n", __func__); + return -EINVAL; + } + omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); -void omap_dm_timer_start(struct omap_dm_timer *timer) +int omap_dm_timer_start(struct omap_dm_timer *timer) { u32 l; + if (unlikely(!timer)) + return -EINVAL; + + omap_dm_timer_enable(timer); + + if (timer->loses_context) { + u32 ctx_loss_cnt_after = + timer->get_context_loss_count(&timer->pdev->dev); + if (ctx_loss_cnt_after != timer->ctx_loss_count) + omap_timer_restore_context(timer); + } + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (!(l & OMAP_TIMER_CTRL_ST)) { l |= OMAP_TIMER_CTRL_ST; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); } + + /* Save the context */ + timer->context.tclr = l; + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_start); -void omap_dm_timer_stop(struct omap_dm_timer *timer) +int omap_dm_timer_stop(struct omap_dm_timer *timer) { unsigned long rate = 0; + struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; -#ifdef CONFIG_ARCH_OMAP2PLUS - rate = clk_get_rate(timer->fclk); -#endif + if (unlikely(!timer)) + return -EINVAL; - __omap_dm_timer_stop(timer->io_base, timer->posted, rate); + if (!pdata->needs_manual_reset) + rate = clk_get_rate(timer->fclk); + + __omap_dm_timer_stop(timer, timer->posted, rate); + + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_stop); -#ifdef CONFIG_ARCH_OMAP1 - int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { - int n = (timer - dm_timers) << 1; - u32 l; - - l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); - l |= source << n; - omap_writel(l, MOD_CONF_CTRL_1); + int ret; + struct dmtimer_platform_data *pdata; - return 0; -} -EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); + if (unlikely(!timer)) + return -EINVAL; -#else + pdata = timer->pdev->dev.platform_data; -int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) -{ if (source < 0 || source >= 3) return -EINVAL; - return __omap_dm_timer_set_source(timer->fclk, - dm_source_clocks[source]); + ret = pdata->set_timer_src(timer->pdev, source); + + return ret; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); -#endif - -void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, +int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int load) { u32 l; + if (unlikely(!timer)) + return -EINVAL; + + omap_dm_timer_enable(timer); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (autoreload) l |= OMAP_TIMER_CTRL_AR; @@ -448,15 +397,32 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); + /* Save the context */ + timer->context.tclr = l; + timer->context.tldr = load; + omap_dm_timer_disable(timer); + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); /* Optimized set_load which removes costly spin wait in timer_start */ -void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, +int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int load) { u32 l; + if (unlikely(!timer)) + return -EINVAL; + + omap_dm_timer_enable(timer); + + if (timer->loses_context) { + u32 ctx_loss_cnt_after = + timer->get_context_loss_count(&timer->pdev->dev); + if (ctx_loss_cnt_after != timer->ctx_loss_count) + omap_timer_restore_context(timer); + } + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (autoreload) { l |= OMAP_TIMER_CTRL_AR; @@ -466,15 +432,25 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, } l |= OMAP_TIMER_CTRL_ST; - __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted); + __omap_dm_timer_load_start(timer, l, load, timer->posted); + + /* Save the context */ + timer->context.tclr = l; + timer->context.tldr = load; + timer->context.tcrr = load; + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); -void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, +int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match) { u32 l; + if (unlikely(!timer)) + return -EINVAL; + + omap_dm_timer_enable(timer); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); if (enable) l |= OMAP_TIMER_CTRL_CE; @@ -482,14 +458,24 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, l &= ~OMAP_TIMER_CTRL_CE; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); + + /* Save the context */ + timer->context.tclr = l; + timer->context.tmar = match; + omap_dm_timer_disable(timer); + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); -void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, +int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger) { u32 l; + if (unlikely(!timer)) + return -EINVAL; + + omap_dm_timer_enable(timer); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | OMAP_TIMER_CTRL_PT | (0x03 << 10)); @@ -499,13 +485,22 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, l |= OMAP_TIMER_CTRL_PT; l |= trigger << 10; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); + + /* Save the context */ + timer->context.tclr = l; + omap_dm_timer_disable(timer); + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); -void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) +int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) { u32 l; + if (unlikely(!timer)) + return -EINVAL; + + omap_dm_timer_enable(timer); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); if (prescaler >= 0x00 && prescaler <= 0x07) { @@ -513,13 +508,28 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) l |= prescaler << 2; } omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); + + /* Save the context */ + timer->context.tclr = l; + omap_dm_timer_disable(timer); + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); -void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, +int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value) { - __omap_dm_timer_int_enable(timer->io_base, value); + if (unlikely(!timer)) + return -EINVAL; + + omap_dm_timer_enable(timer); + __omap_dm_timer_int_enable(timer, value); + + /* Save the context */ + timer->context.tier = value; + timer->context.twer = value; + omap_dm_timer_disable(timer); + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); @@ -527,40 +537,61 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) { unsigned int l; - l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); + if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { + pr_err("%s: timer not available or enabled.\n", __func__); + return 0; + } + + l = __raw_readl(timer->irq_stat); return l; } EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); -void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) +int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) { - __omap_dm_timer_write_status(timer->io_base, value); + if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) + return -EINVAL; + + __omap_dm_timer_write_status(timer, value); + /* Save the context */ + timer->context.tisr = value; + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) { - return __omap_dm_timer_read_counter(timer->io_base, timer->posted); + if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { + pr_err("%s: timer not iavailable or enabled.\n", __func__); + return 0; + } + + return __omap_dm_timer_read_counter(timer, timer->posted); } EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); -void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) +int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) { + if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { + pr_err("%s: timer not available or enabled.\n", __func__); + return -EINVAL; + } + omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); + + /* Save the context */ + timer->context.tcrr = value; + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); int omap_dm_timers_active(void) { - int i; - - for (i = 0; i < dm_timer_count; i++) { - struct omap_dm_timer *timer; - - timer = &dm_timers[i]; + struct omap_dm_timer *timer; - if (!timer->enabled) + list_for_each_entry(timer, &omap_timer_list, node) { + if (!timer->reserved) continue; if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & @@ -572,69 +603,147 @@ int omap_dm_timers_active(void) } EXPORT_SYMBOL_GPL(omap_dm_timers_active); -static int __init omap_dm_timer_init(void) +/** + * omap_dm_timer_probe - probe function called for every registered device + * @pdev: pointer to current timer platform device + * + * Called by driver framework at the end of device registration for all + * timer devices. + */ +static int __devinit omap_dm_timer_probe(struct platform_device *pdev) { + int ret; + unsigned long flags; struct omap_dm_timer *timer; - int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ + struct resource *mem, *irq, *ioarea; + struct dmtimer_platform_data *pdata = pdev->dev.platform_data; - if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) + if (!pdata) { + dev_err(&pdev->dev, "%s: no platform data.\n", __func__); return -ENODEV; + } - spin_lock_init(&dm_timer_lock); - - if (cpu_class_is_omap1()) { - dm_timers = omap1_dm_timers; - dm_timer_count = omap1_dm_timer_count; - map_size = SZ_2K; - } else if (cpu_is_omap24xx()) { - dm_timers = omap2_dm_timers; - dm_timer_count = omap2_dm_timer_count; - dm_source_names = omap2_dm_source_names; - dm_source_clocks = omap2_dm_source_clocks; - } else if (cpu_is_omap34xx()) { - dm_timers = omap3_dm_timers; - dm_timer_count = omap3_dm_timer_count; - dm_source_names = omap3_dm_source_names; - dm_source_clocks = omap3_dm_source_clocks; - } else if (cpu_is_omap44xx()) { - dm_timers = omap4_dm_timers; - dm_timer_count = omap4_dm_timer_count; - dm_source_names = omap4_dm_source_names; - dm_source_clocks = omap4_dm_source_clocks; + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (unlikely(!irq)) { + dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__); + return -ENODEV; } - if (cpu_class_is_omap2()) - for (i = 0; dm_source_names[i] != NULL; i++) - dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (unlikely(!mem)) { + dev_err(&pdev->dev, "%s: no memory resource.\n", __func__); + return -ENODEV; + } - if (cpu_is_omap243x()) - dm_timers[0].phys_base = 0x49018000; + ioarea = request_mem_region(mem->start, resource_size(mem), + pdev->name); + if (!ioarea) { + dev_err(&pdev->dev, "%s: region already claimed.\n", __func__); + return -EBUSY; + } - for (i = 0; i < dm_timer_count; i++) { - timer = &dm_timers[i]; + timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL); + if (!timer) { + dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n", + __func__); + ret = -ENOMEM; + goto err_free_ioregion; + } - /* Static mapping, never released */ - timer->io_base = ioremap(timer->phys_base, map_size); - BUG_ON(!timer->io_base); + timer->io_base = ioremap(mem->start, resource_size(mem)); + if (!timer->io_base) { + dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__); + ret = -ENOMEM; + goto err_free_mem; + } -#ifdef CONFIG_ARCH_OMAP2PLUS - if (cpu_class_is_omap2()) { - char clk_name[16]; - sprintf(clk_name, "gpt%d_ick", i + 1); - timer->iclk = clk_get(NULL, clk_name); - sprintf(clk_name, "gpt%d_fck", i + 1); - timer->fclk = clk_get(NULL, clk_name); - } + timer->id = pdev->id; + timer->irq = irq->start; + timer->reserved = pdata->reserved; + timer->pdev = pdev; + timer->loses_context = pdata->loses_context; + timer->get_context_loss_count = pdata->get_context_loss_count; + + /* Skip pm_runtime_enable for OMAP1 */ + if (!pdata->needs_manual_reset) { + pm_runtime_enable(&pdev->dev); + pm_runtime_irq_safe(&pdev->dev); + } - /* One or two timers may be set up early for sys_timer */ - if (sys_timer_reserved & (1 << i)) { - timer->reserved = 1; - timer->posted = 1; - } -#endif + if (!timer->reserved) { + pm_runtime_get_sync(&pdev->dev); + __omap_dm_timer_init_regs(timer); + pm_runtime_put(&pdev->dev); } + /* add the timer element to the list */ + spin_lock_irqsave(&dm_timer_lock, flags); + list_add_tail(&timer->node, &omap_timer_list); + spin_unlock_irqrestore(&dm_timer_lock, flags); + + dev_dbg(&pdev->dev, "Device Probed.\n"); + return 0; + +err_free_mem: + kfree(timer); + +err_free_ioregion: + release_mem_region(mem->start, resource_size(mem)); + + return ret; } -arch_initcall(omap_dm_timer_init); +/** + * omap_dm_timer_remove - cleanup a registered timer device + * @pdev: pointer to current timer platform device + * + * Called by driver framework whenever a timer device is unregistered. + * In addition to freeing platform resources it also deletes the timer + * entry from the local list. + */ +static int __devexit omap_dm_timer_remove(struct platform_device *pdev) +{ + struct omap_dm_timer *timer; + unsigned long flags; + int ret = -EINVAL; + + spin_lock_irqsave(&dm_timer_lock, flags); + list_for_each_entry(timer, &omap_timer_list, node) + if (timer->pdev->id == pdev->id) { + list_del(&timer->node); + kfree(timer); + ret = 0; + break; + } + spin_unlock_irqrestore(&dm_timer_lock, flags); + + return ret; +} + +static struct platform_driver omap_dm_timer_driver = { + .probe = omap_dm_timer_probe, + .remove = __devexit_p(omap_dm_timer_remove), + .driver = { + .name = "omap_timer", + }, +}; + +static int __init omap_dm_timer_driver_init(void) +{ + return platform_driver_register(&omap_dm_timer_driver); +} + +static void __exit omap_dm_timer_driver_exit(void) +{ + platform_driver_unregister(&omap_dm_timer_driver); +} + +early_platform_init("earlytimer", &omap_dm_timer_driver); +module_init(omap_dm_timer_driver_init); +module_exit(omap_dm_timer_driver_exit); + +MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); +MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 3341ca4..a162b2c 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -108,6 +108,22 @@ static inline int omap1_i2c_add_bus(int bus_id) res[1].start = INT_I2C; pdata = &i2c_pdata[bus_id - 1]; + /* all OMAP1 have IP version 1 register set */ + pdata->rev = OMAP_I2C_IP_VERSION_1; + + /* all OMAP1 I2C are implemented like this */ + pdata->flags = OMAP_I2C_FLAG_NO_FIFO | + OMAP_I2C_FLAG_SIMPLE_CLOCK | + OMAP_I2C_FLAG_16BIT_DATA_REG | + OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK; + + /* how the cpu bus is wired up differs for 7xx only */ + + if (cpu_is_omap7xx()) + pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1; + else + pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2; + return platform_device_register(pdev); } @@ -135,9 +151,10 @@ static inline int omap2_i2c_add_bus(int bus_id) { int l; struct omap_hwmod *oh; - struct omap_device *od; + struct platform_device *pdev; char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; struct omap_i2c_bus_platform_data *pdata; + struct omap_i2c_dev_attr *dev_attr; omap2_i2c_mux_pins(bus_id); @@ -152,6 +169,16 @@ static inline int omap2_i2c_add_bus(int bus_id) pdata = &i2c_pdata[bus_id - 1]; /* + * pass the hwmod class's CPU-specific knowledge of I2C IP revision in + * use, and functionality implementation flags, up to the OMAP I2C + * driver via platform data + */ + pdata->rev = oh->class->rev; + + dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr; + pdata->flags = dev_attr->flags; + + /* * When waiting for completion of a i2c transfer, we need to * set a wake up latency constraint for the MPU. This is to * ensure quick enough wakeup from idle, when transfer @@ -160,12 +187,12 @@ static inline int omap2_i2c_add_bus(int bus_id) */ if (cpu_is_omap34xx()) pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; - od = omap_device_build(name, bus_id, oh, pdata, + pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(struct omap_i2c_bus_platform_data), omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0); - WARN(IS_ERR(od), "Could not build omap_device for %s\n", name); + WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name); - return PTR_ERR(od); + return PTR_ERR(pdev); } #else static inline int omap2_i2c_add_bus(int bus_id) diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index df4b968..197ca03 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -80,8 +80,6 @@ struct clkops { * * @div is the divisor that should be applied to the parent clock's rate * to produce the current clock's rate. - * - * XXX @flags probably should be replaced with an struct omap_chip. */ struct clksel_rate { u32 val; diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 4564cc6..abda2c7 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -45,6 +45,15 @@ extern unsigned long long notrace omap_32k_sched_clock(void); extern void omap_reserve(void); +void omap2420_init_early(void); +void omap2430_init_early(void); +void omap3430_init_early(void); +void omap35xx_init_early(void); +void omap3630_init_early(void); +void am35xx_init_early(void); +void ti816x_init_early(void); +void omap4430_init_early(void); + /* * IO bases for various OMAP processors * Except the tap base, rest all the io bases @@ -74,7 +83,11 @@ void omap2_set_globals_sdrc(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); +void omap242x_map_io(void); +void omap243x_map_io(void); void omap3_map_io(void); +void omap4_map_io(void); + /** * omap_test_timeout - busy-loop, testing a condition diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 67b3d75..2f90269 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -44,13 +44,6 @@ int omap_type(void); -struct omap_chip_id { - u16 oc; - u8 type; -}; - -#define OMAP_CHIP_INIT(x) { .oc = x } - /* * omap_rev bits: * CPU id bits (0730, 1510, 1710, 2422...) [31:16] @@ -60,19 +53,6 @@ struct omap_chip_id { unsigned int omap_rev(void); /* - * Define CPU revision bits - * - * Verbose meaning of the revision bits may be different for a silicon - * family. This difference can be handled separately. - */ -#define OMAP_REVBITS_00 0x00 -#define OMAP_REVBITS_01 0x01 -#define OMAP_REVBITS_02 0x02 -#define OMAP_REVBITS_03 0x03 -#define OMAP_REVBITS_04 0x04 -#define OMAP_REVBITS_05 0x05 - -/* * Get the CPU revision for OMAP devices */ #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) @@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422) IS_OMAP_TYPE(2423, 0x2423) IS_OMAP_TYPE(2430, 0x2430) IS_OMAP_TYPE(3430, 0x3430) -IS_OMAP_TYPE(3505, 0x3505) +IS_OMAP_TYPE(3505, 0x3517) IS_OMAP_TYPE(3517, 0x3517) #define cpu_is_omap310() 0 @@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517) (!omap3_has_sgx()) && \ (omap3_has_iva())) # define cpu_is_omap3530() (cpu_is_omap3430()) -# define cpu_is_omap3505() is_omap3505() # define cpu_is_omap3517() is_omap3517() +# define cpu_is_omap3505() (cpu_is_omap3517() && \ + !omap3_has_sgx()) # undef cpu_is_omap3630 # define cpu_is_omap3630() is_omap363x() # define cpu_is_ti816x() is_ti816x() @@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517) /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 #define OMAP2420_REV_ES1_0 OMAP242X_CLASS -#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8)) +#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8)) #define OMAP243X_CLASS 0x24300024 #define OMAP2430_REV_ES1_0 OMAP243X_CLASS #define OMAP343X_CLASS 0x34300034 #define OMAP3430_REV_ES1_0 OMAP343X_CLASS -#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8)) -#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8)) -#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8)) -#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8)) -#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8)) +#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8)) +#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8)) +#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8)) +#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8)) +#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8)) #define OMAP363X_CLASS 0x36300034 #define OMAP3630_REV_ES1_0 OMAP363X_CLASS -#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8)) -#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8)) +#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8)) +#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8)) -#define OMAP35XX_CLASS 0x35000034 -#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) -#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8)) -#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8)) -#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8)) -#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8)) -#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) +#define OMAP3517_CLASS 0x35170034 +#define OMAP3517_REV_ES1_0 OMAP3517_CLASS +#define OMAP3517_REV_ES1_1 (OMAP3517_CLASS | (0x1 << 8)) #define TI816X_CLASS 0x81600034 #define TI8168_REV_ES1_0 TI816X_CLASS -#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) +#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) @@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP446X_CLASS 0x44600044 #define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) -/* - * omap_chip bits - * - * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is - * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates - * something that is only valid on that particular ES revision. - * - * These bits may be ORed together to indicate structures that are - * available on multiple chip types. - * - * To test whether a particular structure matches the current OMAP chip type, - * use omap_chip_is(). - * - */ -#define CHIP_IS_OMAP2420 (1 << 0) -#define CHIP_IS_OMAP2430 (1 << 1) -#define CHIP_IS_OMAP3430 (1 << 2) -#define CHIP_IS_OMAP3430ES1 (1 << 3) -#define CHIP_IS_OMAP3430ES2 (1 << 4) -#define CHIP_IS_OMAP3430ES3_0 (1 << 5) -#define CHIP_IS_OMAP3430ES3_1 (1 << 6) -#define CHIP_IS_OMAP3630ES1 (1 << 7) -#define CHIP_IS_OMAP4430ES1 (1 << 8) -#define CHIP_IS_OMAP3630ES1_1 (1 << 9) -#define CHIP_IS_OMAP3630ES1_2 (1 << 10) -#define CHIP_IS_OMAP4430ES2 (1 << 11) -#define CHIP_IS_OMAP4430ES2_1 (1 << 12) -#define CHIP_IS_OMAP4430ES2_2 (1 << 13) -#define CHIP_IS_TI816X (1 << 14) -#define CHIP_IS_OMAP4460ES1_0 (1 << 15) - -#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) - -#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ - CHIP_IS_OMAP4430ES2 | \ - CHIP_IS_OMAP4430ES2_1 | \ - CHIP_IS_OMAP4430ES2_2 | \ - CHIP_IS_OMAP4460ES1_0) - -/* - * "GE" here represents "greater than or equal to" in terms of ES - * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 - * chips at ES2 and beyond, but not, for example, any OMAP lines after - * OMAP3. - */ -#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ - CHIP_IS_OMAP3430ES3_0 | \ - CHIP_GE_OMAP3430ES3_1) -#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1 | \ - CHIP_GE_OMAP3630ES1_1) -#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \ - CHIP_IS_OMAP3630ES1_2) - -int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); /* diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index eb5d16c..d11025e 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -1,5 +1,5 @@ /* - * arch/arm/plat-omap/include/mach/dmtimer.h + * arch/arm/plat-omap/include/plat/dmtimer.h * * OMAP Dual-Mode Timers * @@ -35,6 +35,7 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/platform_device.h> #ifndef __ASM_ARCH_DMTIMER_H #define __ASM_ARCH_DMTIMER_H @@ -59,12 +60,56 @@ * in OMAP4 can be distinguished. */ #define OMAP_TIMER_IP_VERSION_1 0x1 + +/* timer capabilities used in hwmod database */ +#define OMAP_TIMER_SECURE 0x80000000 +#define OMAP_TIMER_ALWON 0x40000000 +#define OMAP_TIMER_HAS_PWM 0x20000000 + +struct omap_timer_capability_dev_attr { + u32 timer_capability; +}; + struct omap_dm_timer; struct clk; +struct timer_regs { + u32 tidr; + u32 tiocp_cfg; + u32 tistat; + u32 tisr; + u32 tier; + u32 twer; + u32 tclr; + u32 tcrr; + u32 tldr; + u32 ttrg; + u32 twps; + u32 tmar; + u32 tcar1; + u32 tsicr; + u32 tcar2; + u32 tpir; + u32 tnir; + u32 tcvr; + u32 tocr; + u32 towr; +}; + +struct dmtimer_platform_data { + int (*set_timer_src)(struct platform_device *pdev, int source); + int timer_ip_version; + u32 needs_manual_reset:1; + bool reserved; + + bool loses_context; + + u32 (*get_context_loss_count)(struct device *dev); +}; + struct omap_dm_timer *omap_dm_timer_request(void); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); -void omap_dm_timer_free(struct omap_dm_timer *timer); +int omap_dm_timer_free(struct omap_dm_timer *timer); void omap_dm_timer_enable(struct omap_dm_timer *timer); void omap_dm_timer_disable(struct omap_dm_timer *timer); @@ -73,23 +118,23 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer); u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer); -void omap_dm_timer_trigger(struct omap_dm_timer *timer); -void omap_dm_timer_start(struct omap_dm_timer *timer); -void omap_dm_timer_stop(struct omap_dm_timer *timer); +int omap_dm_timer_trigger(struct omap_dm_timer *timer); +int omap_dm_timer_start(struct omap_dm_timer *timer); +int omap_dm_timer_stop(struct omap_dm_timer *timer); int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); -void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); -void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); -void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); -void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); -void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); +int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); +int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); +int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); +int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); +int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); -void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); +int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); -void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); +int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); -void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value); +int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value); int omap_dm_timers_active(void); @@ -98,12 +143,30 @@ int omap_dm_timers_active(void); * used by dmtimer.c and sys_timer related code. */ -/* register offsets */ -#define _OMAP_TIMER_ID_OFFSET 0x00 -#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10 -#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14 -#define _OMAP_TIMER_STAT_OFFSET 0x18 -#define _OMAP_TIMER_INT_EN_OFFSET 0x1c +/* + * The interrupt registers are different between v1 and v2 ip. + * These registers are offsets from timer->iobase. + */ +#define OMAP_TIMER_ID_OFFSET 0x00 +#define OMAP_TIMER_OCP_CFG_OFFSET 0x10 + +#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14 +#define OMAP_TIMER_V1_STAT_OFFSET 0x18 +#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c + +#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24 +#define OMAP_TIMER_V2_IRQSTATUS 0x28 +#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c +#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30 + +/* + * The functional registers have a different base on v1 and v2 ip. + * These registers are offsets from timer->func_base. The func_base + * is samae as io_base for v1 and io_base + 0x14 for v2 ip. + * + */ +#define OMAP_TIMER_V2_FUNC_OFFSET 0x14 + #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20 #define _OMAP_TIMER_CTRL_OFFSET 0x24 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14) @@ -147,21 +210,6 @@ int omap_dm_timers_active(void); /* register offsets with the write pending bit encoded */ #define WPSHIFT 16 -#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \ - | (WP_NONE << WPSHIFT)) - #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ | (WP_NONE << WPSHIFT)) @@ -209,49 +257,88 @@ int omap_dm_timers_active(void); struct omap_dm_timer { unsigned long phys_base; + int id; int irq; -#ifdef CONFIG_ARCH_OMAP2PLUS struct clk *iclk, *fclk; -#endif - void __iomem *io_base; + + void __iomem *io_base; + void __iomem *sys_stat; /* TISTAT timer status */ + void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */ + void __iomem *irq_ena; /* irq enable */ + void __iomem *irq_dis; /* irq disable, only on v2 ip */ + void __iomem *pend; /* write pending */ + void __iomem *func_base; /* function register base */ + unsigned long rate; unsigned reserved:1; - unsigned enabled:1; unsigned posted:1; + struct timer_regs context; + bool loses_context; + int ctx_loss_count; + int revision; + struct platform_device *pdev; + struct list_head node; + + u32 (*get_context_loss_count)(struct device *dev); }; -extern u32 sys_timer_reserved; -void omap_dm_timer_prepare(struct omap_dm_timer *timer); +int omap_dm_timer_prepare(struct omap_dm_timer *timer); -static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg, +static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, int posted) { if (posted) - while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) - & (reg >> WPSHIFT)) + while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); - return __raw_readl(base + (reg & 0xff)); + return __raw_readl(timer->func_base + (reg & 0xff)); } -static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val, - int posted) +static inline void __omap_dm_timer_write(struct omap_dm_timer *timer, + u32 reg, u32 val, int posted) { if (posted) - while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) - & (reg >> WPSHIFT)) + while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); - __raw_writel(val, base + (reg & 0xff)); + __raw_writel(val, timer->func_base + (reg & 0xff)); +} + +static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) +{ + u32 tidr; + + /* Assume v1 ip if bits [31:16] are zero */ + tidr = __raw_readl(timer->io_base); + if (!(tidr >> 16)) { + timer->revision = 1; + timer->sys_stat = timer->io_base + + OMAP_TIMER_V1_SYS_STAT_OFFSET; + timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; + timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; + timer->irq_dis = 0; + timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; + timer->func_base = timer->io_base; + } else { + timer->revision = 2; + timer->sys_stat = 0; + timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; + timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; + timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; + timer->pend = timer->io_base + + _OMAP_TIMER_WRITE_PEND_OFFSET + + OMAP_TIMER_V2_FUNC_OFFSET; + timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET; + } } /* Assumes the source clock has been set by caller */ -static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle, - int wakeup) +static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer, + int autoidle, int wakeup) { u32 l; - l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0); + l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); l |= 0x02 << 3; /* Set to smart-idle mode */ l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ @@ -261,10 +348,10 @@ static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle, if (wakeup) l |= 1 << 2; - __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0); + __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); /* Match hardware reset default of posted mode */ - __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG, + __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED, 0); } @@ -286,18 +373,18 @@ static inline int __omap_dm_timer_set_source(struct clk *timer_fck, return ret; } -static inline void __omap_dm_timer_stop(void __iomem *base, int posted, - unsigned long rate) +static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, + int posted, unsigned long rate) { u32 l; - l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted); + l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); if (l & OMAP_TIMER_CTRL_ST) { l &= ~0x1; - __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted); + __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted); #ifdef CONFIG_ARCH_OMAP2PLUS /* Readback to make sure write has completed */ - __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted); + __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); /* * Wait for functional clock period x 3.5 to make sure that * timer is stopped @@ -307,34 +394,34 @@ static inline void __omap_dm_timer_stop(void __iomem *base, int posted, } /* Ack possibly pending interrupt */ - __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, - OMAP_TIMER_INT_OVERFLOW, 0); + __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); } -static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl, - unsigned int load, int posted) +static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer, + u32 ctrl, unsigned int load, + int posted) { - __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted); - __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted); + __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted); + __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted); } -static inline void __omap_dm_timer_int_enable(void __iomem *base, +static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, unsigned int value) { - __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0); - __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0); + __raw_writel(value, timer->irq_ena); + __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0); } -static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base, - int posted) +static inline unsigned int +__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted) { - return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted); + return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted); } -static inline void __omap_dm_timer_write_status(void __iomem *base, +static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) { - __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0); + __raw_writel(value, timer->irq_stat); } #endif /* __ASM_ARCH_DMTIMER_H */ diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index ebe67ea..a93a00d 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -300,7 +300,7 @@ static inline void omap44xx_map_common_io(void) #endif extern void omap2_init_common_infrastructure(void); -extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, +extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1); #define __arch_ioremap omap_ioremap diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 174f1b9..a1d79ee 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -25,16 +25,17 @@ struct iotlb_entry { }; }; -struct iommu { +struct omap_iommu { const char *name; struct module *owner; struct clk *clk; void __iomem *regbase; struct device *dev; void *isr_priv; + struct iommu_domain *domain; unsigned int refcount; - struct mutex iommu_lock; /* global for this whole object */ + spinlock_t iommu_lock; /* global for this whole object */ /* * We don't change iopgd for a situation like pgd for a task, @@ -48,8 +49,6 @@ struct iommu { struct list_head mmap; struct mutex mmap_lock; /* protect mmap */ - int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv); - void *ctx; /* iommu context: registres saved area */ u32 da_start; u32 da_end; @@ -81,25 +80,27 @@ struct iotlb_lock { struct iommu_functions { unsigned long version; - int (*enable)(struct iommu *obj); - void (*disable)(struct iommu *obj); - void (*set_twl)(struct iommu *obj, bool on); - u32 (*fault_isr)(struct iommu *obj, u32 *ra); + int (*enable)(struct omap_iommu *obj); + void (*disable)(struct omap_iommu *obj); + void (*set_twl)(struct omap_iommu *obj, bool on); + u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra); - void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); - void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr); + void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr); + void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr); - struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e); + struct cr_regs *(*alloc_cr)(struct omap_iommu *obj, + struct iotlb_entry *e); int (*cr_valid)(struct cr_regs *cr); u32 (*cr_to_virt)(struct cr_regs *cr); void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e); - ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf); + ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr, + char *buf); u32 (*get_pte_attr)(struct iotlb_entry *e); - void (*save_ctx)(struct iommu *obj); - void (*restore_ctx)(struct iommu *obj); - ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len); + void (*save_ctx)(struct omap_iommu *obj); + void (*restore_ctx)(struct omap_iommu *obj); + ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len); }; struct iommu_platform_data { @@ -150,40 +151,31 @@ struct iommu_platform_data { /* * global functions */ -extern u32 iommu_arch_version(void); - -extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); -extern u32 iotlb_cr_to_virt(struct cr_regs *cr); - -extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); -extern void iommu_set_twl(struct iommu *obj, bool on); -extern void flush_iotlb_page(struct iommu *obj, u32 da); -extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); -extern void flush_iotlb_all(struct iommu *obj); - -extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); -extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, - u32 **ppte); -extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); - -extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); -extern struct iommu *iommu_get(const char *name); -extern void iommu_put(struct iommu *obj); -extern int iommu_set_isr(const char *name, - int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, +extern u32 omap_iommu_arch_version(void); + +extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); + +extern int +omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e); + +extern int omap_iommu_set_isr(const char *name, + int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs, void *priv), void *isr_priv); -extern void iommu_save_ctx(struct iommu *obj); -extern void iommu_restore_ctx(struct iommu *obj); +extern void omap_iommu_save_ctx(struct omap_iommu *obj); +extern void omap_iommu_restore_ctx(struct omap_iommu *obj); -extern int install_iommu_arch(const struct iommu_functions *ops); -extern void uninstall_iommu_arch(const struct iommu_functions *ops); +extern int omap_install_iommu_arch(const struct iommu_functions *ops); +extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops); -extern int foreach_iommu_device(void *data, +extern int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)); -extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len); -extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len); +extern ssize_t +omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len); +extern size_t +omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len); +struct device *omap_find_iommu_device(const char *name); #endif /* __MACH_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/plat/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h index 10ad05f..d4116b5 100644 --- a/arch/arm/plat-omap/include/plat/iommu2.h +++ b/arch/arm/plat-omap/include/plat/iommu2.h @@ -83,12 +83,12 @@ /* * register accessors */ -static inline u32 iommu_read_reg(struct iommu *obj, size_t offs) +static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs) { return __raw_readl(obj->regbase + offs); } -static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs) +static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) { __raw_writel(val, obj->regbase + offs); } diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/include/plat/iopgtable.h index c3e93bb..66a8139 100644 --- a/arch/arm/plat-omap/iopgtable.h +++ b/arch/arm/plat-omap/include/plat/iopgtable.h @@ -56,6 +56,19 @@ #define IOPAGE_MASK IOPTE_MASK +/** + * omap_iommu_translate() - va to pa translation + * @d: omap iommu descriptor + * @va: virtual address + * @mask: omap iommu descriptor mask + * + * va to pa translation + */ +static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask) +{ + return (d & mask) | (va & (~mask)); +} + /* * some descriptor attributes. */ @@ -64,10 +77,15 @@ #define IOPGD_SUPER (1 << 18 | 2 << 0) #define iopgd_is_table(x) (((x) & 3) == IOPGD_TABLE) +#define iopgd_is_section(x) (((x) & (1 << 18 | 3)) == IOPGD_SECTION) +#define iopgd_is_super(x) (((x) & (1 << 18 | 3)) == IOPGD_SUPER) #define IOPTE_SMALL (2 << 0) #define IOPTE_LARGE (1 << 0) +#define iopte_is_small(x) (((x) & 2) == IOPTE_SMALL) +#define iopte_is_large(x) (((x) & 3) == IOPTE_LARGE) + /* to find an entry in a page-table-directory */ #define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) #define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) @@ -97,6 +115,6 @@ static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, } #define to_iommu(dev) \ - (struct iommu *)platform_get_drvdata(to_platform_device(dev)) + (struct omap_iommu *)platform_get_drvdata(to_platform_device(dev)) #endif /* __PLAT_OMAP_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h index e992b96..6af1a91 100644 --- a/arch/arm/plat-omap/include/plat/iovmm.h +++ b/arch/arm/plat-omap/include/plat/iovmm.h @@ -13,8 +13,10 @@ #ifndef __IOMMU_MMAP_H #define __IOMMU_MMAP_H +#include <linux/iommu.h> + struct iovm_struct { - struct iommu *iommu; /* iommu object which this belongs to */ + struct omap_iommu *iommu; /* iommu object which this belongs to */ u32 da_start; /* area definition */ u32 da_end; u32 flags; /* IOVMF_: see below */ @@ -70,20 +72,18 @@ struct iovm_struct { #define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) -extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); -extern u32 iommu_vmap(struct iommu *obj, u32 da, +extern struct iovm_struct *omap_find_iovm_area(struct omap_iommu *obj, u32 da); +extern u32 +omap_iommu_vmap(struct iommu_domain *domain, struct omap_iommu *obj, u32 da, const struct sg_table *sgt, u32 flags); -extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da); -extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, - u32 flags); -extern void iommu_vfree(struct iommu *obj, const u32 da); -extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, - u32 flags); -extern void iommu_kunmap(struct iommu *obj, u32 da); -extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, - u32 flags); -extern void iommu_kfree(struct iommu *obj, u32 da); - -extern void *da_to_va(struct iommu *obj, u32 da); +extern struct sg_table *omap_iommu_vunmap(struct iommu_domain *domain, + struct omap_iommu *obj, u32 da); +extern u32 +omap_iommu_vmalloc(struct iommu_domain *domain, struct omap_iommu *obj, + u32 da, size_t bytes, u32 flags); +extern void +omap_iommu_vfree(struct iommu_domain *domain, struct omap_iommu *obj, + const u32 da); +extern void *omap_da_to_va(struct omap_iommu *obj, u32 da); #endif /* __IOMMU_MMAP_H */ diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 9882c65..8fa74e2 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -25,9 +25,7 @@ #define __ASM_ARCH_OMAP_MCBSP_H #include <linux/spinlock.h> - -#include <mach/hardware.h> -#include <plat/clock.h> +#include <linux/clk.h> /* macro for building platform_device for McBSP ports */ #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \ @@ -40,104 +38,60 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define MCBSP_CONFIG_TYPE3 0x3 #define MCBSP_CONFIG_TYPE4 0x4 -#define OMAP7XX_MCBSP1_BASE 0xfffb1000 -#define OMAP7XX_MCBSP2_BASE 0xfffb1800 - -#define OMAP1510_MCBSP1_BASE 0xe1011800 -#define OMAP1510_MCBSP2_BASE 0xfffb1000 -#define OMAP1510_MCBSP3_BASE 0xe1017000 - -#define OMAP1610_MCBSP1_BASE 0xe1011800 -#define OMAP1610_MCBSP2_BASE 0xfffb1000 -#define OMAP1610_MCBSP3_BASE 0xe1017000 - -#ifdef CONFIG_ARCH_OMAP1 - -#define OMAP_MCBSP_REG_DRR2 0x00 -#define OMAP_MCBSP_REG_DRR1 0x02 -#define OMAP_MCBSP_REG_DXR2 0x04 -#define OMAP_MCBSP_REG_DXR1 0x06 -#define OMAP_MCBSP_REG_DRR 0x02 -#define OMAP_MCBSP_REG_DXR 0x06 -#define OMAP_MCBSP_REG_SPCR2 0x08 -#define OMAP_MCBSP_REG_SPCR1 0x0a -#define OMAP_MCBSP_REG_RCR2 0x0c -#define OMAP_MCBSP_REG_RCR1 0x0e -#define OMAP_MCBSP_REG_XCR2 0x10 -#define OMAP_MCBSP_REG_XCR1 0x12 -#define OMAP_MCBSP_REG_SRGR2 0x14 -#define OMAP_MCBSP_REG_SRGR1 0x16 -#define OMAP_MCBSP_REG_MCR2 0x18 -#define OMAP_MCBSP_REG_MCR1 0x1a -#define OMAP_MCBSP_REG_RCERA 0x1c -#define OMAP_MCBSP_REG_RCERB 0x1e -#define OMAP_MCBSP_REG_XCERA 0x20 -#define OMAP_MCBSP_REG_XCERB 0x22 -#define OMAP_MCBSP_REG_PCR0 0x24 -#define OMAP_MCBSP_REG_RCERC 0x26 -#define OMAP_MCBSP_REG_RCERD 0x28 -#define OMAP_MCBSP_REG_XCERC 0x2A -#define OMAP_MCBSP_REG_XCERD 0x2C -#define OMAP_MCBSP_REG_RCERE 0x2E -#define OMAP_MCBSP_REG_RCERF 0x30 -#define OMAP_MCBSP_REG_XCERE 0x32 -#define OMAP_MCBSP_REG_XCERF 0x34 -#define OMAP_MCBSP_REG_RCERG 0x36 -#define OMAP_MCBSP_REG_RCERH 0x38 -#define OMAP_MCBSP_REG_XCERG 0x3A -#define OMAP_MCBSP_REG_XCERH 0x3C - -/* Dummy defines, these are not available on omap1 */ -#define OMAP_MCBSP_REG_XCCR 0x00 -#define OMAP_MCBSP_REG_RCCR 0x00 - -#else - -#define OMAP_MCBSP_REG_DRR2 0x00 -#define OMAP_MCBSP_REG_DRR1 0x04 -#define OMAP_MCBSP_REG_DXR2 0x08 -#define OMAP_MCBSP_REG_DXR1 0x0C -#define OMAP_MCBSP_REG_DRR 0x00 -#define OMAP_MCBSP_REG_DXR 0x08 -#define OMAP_MCBSP_REG_SPCR2 0x10 -#define OMAP_MCBSP_REG_SPCR1 0x14 -#define OMAP_MCBSP_REG_RCR2 0x18 -#define OMAP_MCBSP_REG_RCR1 0x1C -#define OMAP_MCBSP_REG_XCR2 0x20 -#define OMAP_MCBSP_REG_XCR1 0x24 -#define OMAP_MCBSP_REG_SRGR2 0x28 -#define OMAP_MCBSP_REG_SRGR1 0x2C -#define OMAP_MCBSP_REG_MCR2 0x30 -#define OMAP_MCBSP_REG_MCR1 0x34 -#define OMAP_MCBSP_REG_RCERA 0x38 -#define OMAP_MCBSP_REG_RCERB 0x3C -#define OMAP_MCBSP_REG_XCERA 0x40 -#define OMAP_MCBSP_REG_XCERB 0x44 -#define OMAP_MCBSP_REG_PCR0 0x48 -#define OMAP_MCBSP_REG_RCERC 0x4C -#define OMAP_MCBSP_REG_RCERD 0x50 -#define OMAP_MCBSP_REG_XCERC 0x54 -#define OMAP_MCBSP_REG_XCERD 0x58 -#define OMAP_MCBSP_REG_RCERE 0x5C -#define OMAP_MCBSP_REG_RCERF 0x60 -#define OMAP_MCBSP_REG_XCERE 0x64 -#define OMAP_MCBSP_REG_XCERF 0x68 -#define OMAP_MCBSP_REG_RCERG 0x6C -#define OMAP_MCBSP_REG_RCERH 0x70 -#define OMAP_MCBSP_REG_XCERG 0x74 -#define OMAP_MCBSP_REG_XCERH 0x78 -#define OMAP_MCBSP_REG_SYSCON 0x8C -#define OMAP_MCBSP_REG_THRSH2 0x90 -#define OMAP_MCBSP_REG_THRSH1 0x94 -#define OMAP_MCBSP_REG_IRQST 0xA0 -#define OMAP_MCBSP_REG_IRQEN 0xA4 -#define OMAP_MCBSP_REG_WAKEUPEN 0xA8 -#define OMAP_MCBSP_REG_XCCR 0xAC -#define OMAP_MCBSP_REG_RCCR 0xB0 -#define OMAP_MCBSP_REG_XBUFFSTAT 0xB4 -#define OMAP_MCBSP_REG_RBUFFSTAT 0xB8 -#define OMAP_MCBSP_REG_SSELCR 0xBC +/* McBSP register numbers. Register address offset = num * reg_step */ +enum { + /* Common registers */ + OMAP_MCBSP_REG_SPCR2 = 4, + OMAP_MCBSP_REG_SPCR1, + OMAP_MCBSP_REG_RCR2, + OMAP_MCBSP_REG_RCR1, + OMAP_MCBSP_REG_XCR2, + OMAP_MCBSP_REG_XCR1, + OMAP_MCBSP_REG_SRGR2, + OMAP_MCBSP_REG_SRGR1, + OMAP_MCBSP_REG_MCR2, + OMAP_MCBSP_REG_MCR1, + OMAP_MCBSP_REG_RCERA, + OMAP_MCBSP_REG_RCERB, + OMAP_MCBSP_REG_XCERA, + OMAP_MCBSP_REG_XCERB, + OMAP_MCBSP_REG_PCR0, + OMAP_MCBSP_REG_RCERC, + OMAP_MCBSP_REG_RCERD, + OMAP_MCBSP_REG_XCERC, + OMAP_MCBSP_REG_XCERD, + OMAP_MCBSP_REG_RCERE, + OMAP_MCBSP_REG_RCERF, + OMAP_MCBSP_REG_XCERE, + OMAP_MCBSP_REG_XCERF, + OMAP_MCBSP_REG_RCERG, + OMAP_MCBSP_REG_RCERH, + OMAP_MCBSP_REG_XCERG, + OMAP_MCBSP_REG_XCERH, + + /* OMAP1-OMAP2420 registers */ + OMAP_MCBSP_REG_DRR2 = 0, + OMAP_MCBSP_REG_DRR1, + OMAP_MCBSP_REG_DXR2, + OMAP_MCBSP_REG_DXR1, + + /* OMAP2430 and onwards */ + OMAP_MCBSP_REG_DRR = 0, + OMAP_MCBSP_REG_DXR = 2, + OMAP_MCBSP_REG_SYSCON = 35, + OMAP_MCBSP_REG_THRSH2, + OMAP_MCBSP_REG_THRSH1, + OMAP_MCBSP_REG_IRQST = 40, + OMAP_MCBSP_REG_IRQEN, + OMAP_MCBSP_REG_WAKEUPEN, + OMAP_MCBSP_REG_XCCR, + OMAP_MCBSP_REG_RCCR, + OMAP_MCBSP_REG_XBUFFSTAT, + OMAP_MCBSP_REG_RBUFFSTAT, + OMAP_MCBSP_REG_SSELCR, +}; +/* OMAP3 sidetone control registers */ #define OMAP_ST_REG_REV 0x00 #define OMAP_ST_REG_SYSCONFIG 0x10 #define OMAP_ST_REG_IRQSTATUS 0x18 @@ -146,8 +100,6 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define OMAP_ST_REG_SFIRCR 0x28 #define OMAP_ST_REG_SSELCR 0x2C -#endif - /************************** McBSP SPCR1 bit definitions ***********************/ #define RRST 0x0001 #define RRDY 0x0002 @@ -344,20 +296,20 @@ typedef enum { struct omap_mcbsp_ops { void (*request)(unsigned int); void (*free)(unsigned int); - int (*set_clks_src)(u8, u8); }; struct omap_mcbsp_platform_data { - unsigned long phys_base; - u8 dma_rx_sync, dma_tx_sync; - u16 rx_irq, tx_irq; struct omap_mcbsp_ops *ops; -#ifdef CONFIG_ARCH_OMAP3 - /* Sidetone block for McBSP 2 and 3 */ - unsigned long phys_base_st; -#endif u16 buffer_size; - unsigned int mcbsp_config_type; + u8 reg_size; + u8 reg_step; + + /* McBSP platform and instance specific features */ + bool has_wakeup; /* Wakeup capability */ + bool has_ccr; /* Transceiver has configuration control registers */ + int (*enable_st_clock)(unsigned int, bool); + int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src); + int (*mux_signal)(struct device *dev, const char *signal, const char *src); }; struct omap_mcbsp_st_data { @@ -389,14 +341,12 @@ struct omap_mcbsp { spinlock_t lock; struct omap_mcbsp_platform_data *pdata; struct clk *fclk; -#ifdef CONFIG_ARCH_OMAP3 struct omap_mcbsp_st_data *st_data; int dma_op_mode; u16 max_tx_thres; u16 max_rx_thres; -#endif void *reg_cache; - unsigned int mcbsp_config_type; + int reg_cache_size; }; /** @@ -408,16 +358,10 @@ struct omap_mcbsp_dev_attr { }; extern struct omap_mcbsp **mcbsp_ptr; -extern int omap_mcbsp_count, omap_mcbsp_cache_size; - -#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) -#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; +extern int omap_mcbsp_count; int omap_mcbsp_init(void); -void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, - struct omap_mcbsp_platform_data *config, int size); void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); -#ifdef CONFIG_ARCH_OMAP3 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); @@ -426,18 +370,6 @@ u16 omap_mcbsp_get_fifo_size(unsigned int id); u16 omap_mcbsp_get_tx_delay(unsigned int id); u16 omap_mcbsp_get_rx_delay(unsigned int id); int omap_mcbsp_get_dma_op_mode(unsigned int id); -#else -static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) -{ } -static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) -{ } -static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; } -static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; } -static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; } -static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; } -static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; } -static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; } -#endif int omap_mcbsp_request(unsigned int id); void omap_mcbsp_free(unsigned int id); void omap_mcbsp_start(unsigned int id, int tx, int rx); @@ -453,21 +385,11 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux); int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); -#ifdef CONFIG_ARCH_OMAP3 /* Sidetone specific API */ int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain); int omap_st_enable(unsigned int id); int omap_st_disable(unsigned int id); int omap_st_is_enabled(unsigned int id); -#else -static inline int omap_st_set_chgain(unsigned int id, int channel, - s16 chgain) { return 0; } -static inline int omap_st_get_chgain(unsigned int id, int channel, - s16 *chgain) { return 0; } -static inline int omap_st_enable(unsigned int id) { return 0; } -static inline int omap_st_disable(unsigned int id) { return 0; } -static inline int omap_st_is_enabled(unsigned int id) { return 0; } -#endif #endif diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index c7b8741..94cf70a 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -31,7 +31,24 @@ #define OMAP_MMC_MAX_SLOTS 2 -#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1) +/* + * struct omap_mmc_dev_attr.flags possibilities + * + * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can + * operate with either 1.8Vdc or 3.0Vdc card voltages; this flag + * should be set if this is the case. See for example Section 22.5.3 + * "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia + * Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R). + * + * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers + * don't work correctly on some MMC controller instances on some + * OMAP3 SoCs; this flag should be set if this is the case. See + * for example Advisory 2.1.1.128 "MMC: Multiple Block Read + * Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_ + * Revision F (October 2010) (SPRZ278F). + */ +#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) +#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1) struct omap_mmc_dev_attr { u8 flags; diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index ee405b36..d4d9b96 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -68,7 +68,7 @@ extern struct device omap_device_parent; * */ struct omap_device { - struct platform_device pdev; + struct platform_device *pdev; struct omap_hwmod **hwmods; struct omap_device_pm_latency *pm_lats; u32 dev_wakeup_lat; @@ -88,24 +88,18 @@ int omap_device_shutdown(struct platform_device *pdev); /* Core code interface */ -int omap_device_count_resources(struct omap_device *od); -int omap_device_fill_resources(struct omap_device *od, struct resource *res); - -struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, +struct platform_device *omap_device_build(const char *pdev_name, int pdev_id, struct omap_hwmod *oh, void *pdata, int pdata_len, struct omap_device_pm_latency *pm_lats, int pm_lats_cnt, int is_early_device); -struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, +struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id, struct omap_hwmod **oh, int oh_cnt, void *pdata, int pdata_len, struct omap_device_pm_latency *pm_lats, int pm_lats_cnt, int is_early_device); -int omap_device_register(struct omap_device *od); -int omap_early_device_register(struct omap_device *od); - void __iomem *omap_device_get_rt_va(struct omap_device *od); /* OMAP PM interface */ @@ -122,11 +116,6 @@ int omap_device_enable_hwmods(struct omap_device *od); int omap_device_disable_clocks(struct omap_device *od); int omap_device_enable_clocks(struct omap_device *od); -static inline void omap_device_disable_idle_on_suspend(struct omap_device *od) -{ - od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND; -} - /* * Entries should be kept in latency order ascending * @@ -157,6 +146,17 @@ struct omap_device_pm_latency { #define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1) /* Get omap_device pointer from platform_device pointer */ -#define to_omap_device(x) container_of((x), struct omap_device, pdev) +static inline struct omap_device *to_omap_device(struct platform_device *pdev) +{ + return pdev ? pdev->archdata.od : NULL; +} + +static inline +void omap_device_disable_idle_on_suspend(struct platform_device *pdev) +{ + struct omap_device *od = to_omap_device(pdev); + + od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND; +} #endif diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 0e329ca..5419f1a 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -496,7 +496,6 @@ struct omap_hwmod_class { * @_state: internal-use hwmod state * @_postsetup_state: internal-use state to leave the hwmod in after _setup() * @flags: hwmod flags (documented below) - * @omap_chip: OMAP chips this hwmod is present on * @_lock: spinlock serializing operations on this hwmod * @node: list node for hwmod list (internal use) * @@ -526,7 +525,6 @@ struct omap_hwmod { char *clkdm_name; struct clockdomain *clkdm; char *vdd_name; - struct voltagedomain *voltdm; struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ void *dev_attr; @@ -545,7 +543,6 @@ struct omap_hwmod { u8 _int_flags; u8 _state; u8 _postsetup_state; - const struct omap_chip_id omap_chip; }; int omap_hwmod_register(struct omap_hwmod **ohs); diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h new file mode 100644 index 0000000..0a6a482 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/voltage.h @@ -0,0 +1,20 @@ +/* + * OMAP Voltage Management Routines + * + * Copyright (C) 2011, Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_OMAP_VOLTAGE_H +#define __ARCH_ARM_OMAP_VOLTAGE_H + +struct voltagedomain; + +struct voltagedomain *voltdm_lookup(const char *name); +int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt); +unsigned long voltdm_get_voltage(struct voltagedomain *voltdm); + +#endif diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c deleted file mode 100644 index f07cf2f..0000000 --- a/arch/arm/plat-omap/iommu-debug.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - * omap iommu: debugfs interface - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/uaccess.h> -#include <linux/platform_device.h> -#include <linux/debugfs.h> - -#include <plat/iommu.h> -#include <plat/iovmm.h> - -#include "iopgtable.h" - -#define MAXCOLUMN 100 /* for short messages */ - -static DEFINE_MUTEX(iommu_debug_lock); - -static struct dentry *iommu_debug_root; - -static ssize_t debug_read_ver(struct file *file, char __user *userbuf, - size_t count, loff_t *ppos) -{ - u32 ver = iommu_arch_version(); - char buf[MAXCOLUMN], *p = buf; - - p += sprintf(p, "H/W version: %d.%d\n", (ver >> 4) & 0xf , ver & 0xf); - - return simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); -} - -static ssize_t debug_read_regs(struct file *file, char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct iommu *obj = file->private_data; - char *p, *buf; - ssize_t bytes; - - buf = kmalloc(count, GFP_KERNEL); - if (!buf) - return -ENOMEM; - p = buf; - - mutex_lock(&iommu_debug_lock); - - bytes = iommu_dump_ctx(obj, p, count); - bytes = simple_read_from_buffer(userbuf, count, ppos, buf, bytes); - - mutex_unlock(&iommu_debug_lock); - kfree(buf); - - return bytes; -} - -static ssize_t debug_read_tlb(struct file *file, char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct iommu *obj = file->private_data; - char *p, *buf; - ssize_t bytes, rest; - - buf = kmalloc(count, GFP_KERNEL); - if (!buf) - return -ENOMEM; - p = buf; - - mutex_lock(&iommu_debug_lock); - - p += sprintf(p, "%8s %8s\n", "cam:", "ram:"); - p += sprintf(p, "-----------------------------------------\n"); - rest = count - (p - buf); - p += dump_tlb_entries(obj, p, rest); - - bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); - - mutex_unlock(&iommu_debug_lock); - kfree(buf); - - return bytes; -} - -static ssize_t debug_write_pagetable(struct file *file, - const char __user *userbuf, size_t count, loff_t *ppos) -{ - struct iotlb_entry e; - struct cr_regs cr; - int err; - struct iommu *obj = file->private_data; - char buf[MAXCOLUMN], *p = buf; - - count = min(count, sizeof(buf)); - - mutex_lock(&iommu_debug_lock); - if (copy_from_user(p, userbuf, count)) { - mutex_unlock(&iommu_debug_lock); - return -EFAULT; - } - - sscanf(p, "%x %x", &cr.cam, &cr.ram); - if (!cr.cam || !cr.ram) { - mutex_unlock(&iommu_debug_lock); - return -EINVAL; - } - - iotlb_cr_to_e(&cr, &e); - err = iopgtable_store_entry(obj, &e); - if (err) - dev_err(obj->dev, "%s: fail to store cr\n", __func__); - - mutex_unlock(&iommu_debug_lock); - return count; -} - -#define dump_ioptable_entry_one(lv, da, val) \ - ({ \ - int __err = 0; \ - ssize_t bytes; \ - const int maxcol = 22; \ - const char *str = "%d: %08x %08x\n"; \ - bytes = snprintf(p, maxcol, str, lv, da, val); \ - p += bytes; \ - len -= bytes; \ - if (len < maxcol) \ - __err = -ENOMEM; \ - __err; \ - }) - -static ssize_t dump_ioptable(struct iommu *obj, char *buf, ssize_t len) -{ - int i; - u32 *iopgd; - char *p = buf; - - spin_lock(&obj->page_table_lock); - - iopgd = iopgd_offset(obj, 0); - for (i = 0; i < PTRS_PER_IOPGD; i++, iopgd++) { - int j, err; - u32 *iopte; - u32 da; - - if (!*iopgd) - continue; - - if (!(*iopgd & IOPGD_TABLE)) { - da = i << IOPGD_SHIFT; - - err = dump_ioptable_entry_one(1, da, *iopgd); - if (err) - goto out; - continue; - } - - iopte = iopte_offset(iopgd, 0); - - for (j = 0; j < PTRS_PER_IOPTE; j++, iopte++) { - if (!*iopte) - continue; - - da = (i << IOPGD_SHIFT) + (j << IOPTE_SHIFT); - err = dump_ioptable_entry_one(2, da, *iopgd); - if (err) - goto out; - } - } -out: - spin_unlock(&obj->page_table_lock); - - return p - buf; -} - -static ssize_t debug_read_pagetable(struct file *file, char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct iommu *obj = file->private_data; - char *p, *buf; - size_t bytes; - - buf = (char *)__get_free_page(GFP_KERNEL); - if (!buf) - return -ENOMEM; - p = buf; - - p += sprintf(p, "L: %8s %8s\n", "da:", "pa:"); - p += sprintf(p, "-----------------------------------------\n"); - - mutex_lock(&iommu_debug_lock); - - bytes = PAGE_SIZE - (p - buf); - p += dump_ioptable(obj, p, bytes); - - bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); - - mutex_unlock(&iommu_debug_lock); - free_page((unsigned long)buf); - - return bytes; -} - -static ssize_t debug_read_mmap(struct file *file, char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct iommu *obj = file->private_data; - char *p, *buf; - struct iovm_struct *tmp; - int uninitialized_var(i); - ssize_t bytes; - - buf = (char *)__get_free_page(GFP_KERNEL); - if (!buf) - return -ENOMEM; - p = buf; - - p += sprintf(p, "%-3s %-8s %-8s %6s %8s\n", - "No", "start", "end", "size", "flags"); - p += sprintf(p, "-------------------------------------------------\n"); - - mutex_lock(&iommu_debug_lock); - - list_for_each_entry(tmp, &obj->mmap, list) { - size_t len; - const char *str = "%3d %08x-%08x %6x %8x\n"; - const int maxcol = 39; - - len = tmp->da_end - tmp->da_start; - p += snprintf(p, maxcol, str, - i, tmp->da_start, tmp->da_end, len, tmp->flags); - - if (PAGE_SIZE - (p - buf) < maxcol) - break; - i++; - } - - bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); - - mutex_unlock(&iommu_debug_lock); - free_page((unsigned long)buf); - - return bytes; -} - -static ssize_t debug_read_mem(struct file *file, char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct iommu *obj = file->private_data; - char *p, *buf; - struct iovm_struct *area; - ssize_t bytes; - - count = min_t(ssize_t, count, PAGE_SIZE); - - buf = (char *)__get_free_page(GFP_KERNEL); - if (!buf) - return -ENOMEM; - p = buf; - - mutex_lock(&iommu_debug_lock); - - area = find_iovm_area(obj, (u32)ppos); - if (IS_ERR(area)) { - bytes = -EINVAL; - goto err_out; - } - memcpy(p, area->va, count); - p += count; - - bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); -err_out: - mutex_unlock(&iommu_debug_lock); - free_page((unsigned long)buf); - - return bytes; -} - -static ssize_t debug_write_mem(struct file *file, const char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct iommu *obj = file->private_data; - struct iovm_struct *area; - char *p, *buf; - - count = min_t(size_t, count, PAGE_SIZE); - - buf = (char *)__get_free_page(GFP_KERNEL); - if (!buf) - return -ENOMEM; - p = buf; - - mutex_lock(&iommu_debug_lock); - - if (copy_from_user(p, userbuf, count)) { - count = -EFAULT; - goto err_out; - } - - area = find_iovm_area(obj, (u32)ppos); - if (IS_ERR(area)) { - count = -EINVAL; - goto err_out; - } - memcpy(area->va, p, count); -err_out: - mutex_unlock(&iommu_debug_lock); - free_page((unsigned long)buf); - - return count; -} - -static int debug_open_generic(struct inode *inode, struct file *file) -{ - file->private_data = inode->i_private; - return 0; -} - -#define DEBUG_FOPS(name) \ - static const struct file_operations debug_##name##_fops = { \ - .open = debug_open_generic, \ - .read = debug_read_##name, \ - .write = debug_write_##name, \ - .llseek = generic_file_llseek, \ - }; - -#define DEBUG_FOPS_RO(name) \ - static const struct file_operations debug_##name##_fops = { \ - .open = debug_open_generic, \ - .read = debug_read_##name, \ - .llseek = generic_file_llseek, \ - }; - -DEBUG_FOPS_RO(ver); -DEBUG_FOPS_RO(regs); -DEBUG_FOPS_RO(tlb); -DEBUG_FOPS(pagetable); -DEBUG_FOPS_RO(mmap); -DEBUG_FOPS(mem); - -#define __DEBUG_ADD_FILE(attr, mode) \ - { \ - struct dentry *dent; \ - dent = debugfs_create_file(#attr, mode, parent, \ - obj, &debug_##attr##_fops); \ - if (!dent) \ - return -ENOMEM; \ - } - -#define DEBUG_ADD_FILE(name) __DEBUG_ADD_FILE(name, 600) -#define DEBUG_ADD_FILE_RO(name) __DEBUG_ADD_FILE(name, 400) - -static int iommu_debug_register(struct device *dev, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - struct iommu *obj = platform_get_drvdata(pdev); - struct dentry *d, *parent; - - if (!obj || !obj->dev) - return -EINVAL; - - d = debugfs_create_dir(obj->name, iommu_debug_root); - if (!d) - return -ENOMEM; - parent = d; - - d = debugfs_create_u8("nr_tlb_entries", 400, parent, - (u8 *)&obj->nr_tlb_entries); - if (!d) - return -ENOMEM; - - DEBUG_ADD_FILE_RO(ver); - DEBUG_ADD_FILE_RO(regs); - DEBUG_ADD_FILE_RO(tlb); - DEBUG_ADD_FILE(pagetable); - DEBUG_ADD_FILE_RO(mmap); - DEBUG_ADD_FILE(mem); - - return 0; -} - -static int __init iommu_debug_init(void) -{ - struct dentry *d; - int err; - - d = debugfs_create_dir("iommu", NULL); - if (!d) - return -ENOMEM; - iommu_debug_root = d; - - err = foreach_iommu_device(d, iommu_debug_register); - if (err) - goto err_out; - return 0; - -err_out: - debugfs_remove_recursive(iommu_debug_root); - return err; -} -module_init(iommu_debug_init) - -static void __exit iommu_debugfs_exit(void) -{ - debugfs_remove_recursive(iommu_debug_root); -} -module_exit(iommu_debugfs_exit) - -MODULE_DESCRIPTION("omap iommu: debugfs interface"); -MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); -MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c deleted file mode 100644 index 34fc31e..0000000 --- a/arch/arm/plat-omap/iommu.c +++ /dev/null @@ -1,1102 +0,0 @@ -/* - * omap iommu: tlb and pagetable primitives - * - * Copyright (C) 2008-2010 Nokia Corporation - * - * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, - * Paul Mundt and Toshihiro Kobayashi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/err.h> -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/clk.h> -#include <linux/platform_device.h> - -#include <asm/cacheflush.h> - -#include <plat/iommu.h> - -#include "iopgtable.h" - -#define for_each_iotlb_cr(obj, n, __i, cr) \ - for (__i = 0; \ - (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ - __i++) - -/* accommodate the difference between omap1 and omap2/3 */ -static const struct iommu_functions *arch_iommu; - -static struct platform_driver omap_iommu_driver; -static struct kmem_cache *iopte_cachep; - -/** - * install_iommu_arch - Install archtecure specific iommu functions - * @ops: a pointer to architecture specific iommu functions - * - * There are several kind of iommu algorithm(tlb, pagetable) among - * omap series. This interface installs such an iommu algorighm. - **/ -int install_iommu_arch(const struct iommu_functions *ops) -{ - if (arch_iommu) - return -EBUSY; - - arch_iommu = ops; - return 0; -} -EXPORT_SYMBOL_GPL(install_iommu_arch); - -/** - * uninstall_iommu_arch - Uninstall archtecure specific iommu functions - * @ops: a pointer to architecture specific iommu functions - * - * This interface uninstalls the iommu algorighm installed previously. - **/ -void uninstall_iommu_arch(const struct iommu_functions *ops) -{ - if (arch_iommu != ops) - pr_err("%s: not your arch\n", __func__); - - arch_iommu = NULL; -} -EXPORT_SYMBOL_GPL(uninstall_iommu_arch); - -/** - * iommu_save_ctx - Save registers for pm off-mode support - * @obj: target iommu - **/ -void iommu_save_ctx(struct iommu *obj) -{ - arch_iommu->save_ctx(obj); -} -EXPORT_SYMBOL_GPL(iommu_save_ctx); - -/** - * iommu_restore_ctx - Restore registers for pm off-mode support - * @obj: target iommu - **/ -void iommu_restore_ctx(struct iommu *obj) -{ - arch_iommu->restore_ctx(obj); -} -EXPORT_SYMBOL_GPL(iommu_restore_ctx); - -/** - * iommu_arch_version - Return running iommu arch version - **/ -u32 iommu_arch_version(void) -{ - return arch_iommu->version; -} -EXPORT_SYMBOL_GPL(iommu_arch_version); - -static int iommu_enable(struct iommu *obj) -{ - int err; - - if (!obj) - return -EINVAL; - - if (!arch_iommu) - return -ENODEV; - - clk_enable(obj->clk); - - err = arch_iommu->enable(obj); - - clk_disable(obj->clk); - return err; -} - -static void iommu_disable(struct iommu *obj) -{ - if (!obj) - return; - - clk_enable(obj->clk); - - arch_iommu->disable(obj); - - clk_disable(obj->clk); -} - -/* - * TLB operations - */ -void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) -{ - BUG_ON(!cr || !e); - - arch_iommu->cr_to_e(cr, e); -} -EXPORT_SYMBOL_GPL(iotlb_cr_to_e); - -static inline int iotlb_cr_valid(struct cr_regs *cr) -{ - if (!cr) - return -EINVAL; - - return arch_iommu->cr_valid(cr); -} - -static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj, - struct iotlb_entry *e) -{ - if (!e) - return NULL; - - return arch_iommu->alloc_cr(obj, e); -} - -u32 iotlb_cr_to_virt(struct cr_regs *cr) -{ - return arch_iommu->cr_to_virt(cr); -} -EXPORT_SYMBOL_GPL(iotlb_cr_to_virt); - -static u32 get_iopte_attr(struct iotlb_entry *e) -{ - return arch_iommu->get_pte_attr(e); -} - -static u32 iommu_report_fault(struct iommu *obj, u32 *da) -{ - return arch_iommu->fault_isr(obj, da); -} - -static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l) -{ - u32 val; - - val = iommu_read_reg(obj, MMU_LOCK); - - l->base = MMU_LOCK_BASE(val); - l->vict = MMU_LOCK_VICT(val); - -} - -static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) -{ - u32 val; - - val = (l->base << MMU_LOCK_BASE_SHIFT); - val |= (l->vict << MMU_LOCK_VICT_SHIFT); - - iommu_write_reg(obj, val, MMU_LOCK); -} - -static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr) -{ - arch_iommu->tlb_read_cr(obj, cr); -} - -static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr) -{ - arch_iommu->tlb_load_cr(obj, cr); - - iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); - iommu_write_reg(obj, 1, MMU_LD_TLB); -} - -/** - * iotlb_dump_cr - Dump an iommu tlb entry into buf - * @obj: target iommu - * @cr: contents of cam and ram register - * @buf: output buffer - **/ -static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, - char *buf) -{ - BUG_ON(!cr || !buf); - - return arch_iommu->dump_cr(obj, cr, buf); -} - -/* only used in iotlb iteration for-loop */ -static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n) -{ - struct cr_regs cr; - struct iotlb_lock l; - - iotlb_lock_get(obj, &l); - l.vict = n; - iotlb_lock_set(obj, &l); - iotlb_read_cr(obj, &cr); - - return cr; -} - -/** - * load_iotlb_entry - Set an iommu tlb entry - * @obj: target iommu - * @e: an iommu tlb entry info - **/ -int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) -{ - int err = 0; - struct iotlb_lock l; - struct cr_regs *cr; - - if (!obj || !obj->nr_tlb_entries || !e) - return -EINVAL; - - clk_enable(obj->clk); - - iotlb_lock_get(obj, &l); - if (l.base == obj->nr_tlb_entries) { - dev_warn(obj->dev, "%s: preserve entries full\n", __func__); - err = -EBUSY; - goto out; - } - if (!e->prsvd) { - int i; - struct cr_regs tmp; - - for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) - if (!iotlb_cr_valid(&tmp)) - break; - - if (i == obj->nr_tlb_entries) { - dev_dbg(obj->dev, "%s: full: no entry\n", __func__); - err = -EBUSY; - goto out; - } - - iotlb_lock_get(obj, &l); - } else { - l.vict = l.base; - iotlb_lock_set(obj, &l); - } - - cr = iotlb_alloc_cr(obj, e); - if (IS_ERR(cr)) { - clk_disable(obj->clk); - return PTR_ERR(cr); - } - - iotlb_load_cr(obj, cr); - kfree(cr); - - if (e->prsvd) - l.base++; - /* increment victim for next tlb load */ - if (++l.vict == obj->nr_tlb_entries) - l.vict = l.base; - iotlb_lock_set(obj, &l); -out: - clk_disable(obj->clk); - return err; -} -EXPORT_SYMBOL_GPL(load_iotlb_entry); - -/** - * flush_iotlb_page - Clear an iommu tlb entry - * @obj: target iommu - * @da: iommu device virtual address - * - * Clear an iommu tlb entry which includes 'da' address. - **/ -void flush_iotlb_page(struct iommu *obj, u32 da) -{ - int i; - struct cr_regs cr; - - clk_enable(obj->clk); - - for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { - u32 start; - size_t bytes; - - if (!iotlb_cr_valid(&cr)) - continue; - - start = iotlb_cr_to_virt(&cr); - bytes = iopgsz_to_bytes(cr.cam & 3); - - if ((start <= da) && (da < start + bytes)) { - dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", - __func__, start, da, bytes); - iotlb_load_cr(obj, &cr); - iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); - } - } - clk_disable(obj->clk); - - if (i == obj->nr_tlb_entries) - dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); -} -EXPORT_SYMBOL_GPL(flush_iotlb_page); - -/** - * flush_iotlb_range - Clear an iommu tlb entries - * @obj: target iommu - * @start: iommu device virtual address(start) - * @end: iommu device virtual address(end) - * - * Clear an iommu tlb entry which includes 'da' address. - **/ -void flush_iotlb_range(struct iommu *obj, u32 start, u32 end) -{ - u32 da = start; - - while (da < end) { - flush_iotlb_page(obj, da); - /* FIXME: Optimize for multiple page size */ - da += IOPTE_SIZE; - } -} -EXPORT_SYMBOL_GPL(flush_iotlb_range); - -/** - * flush_iotlb_all - Clear all iommu tlb entries - * @obj: target iommu - **/ -void flush_iotlb_all(struct iommu *obj) -{ - struct iotlb_lock l; - - clk_enable(obj->clk); - - l.base = 0; - l.vict = 0; - iotlb_lock_set(obj, &l); - - iommu_write_reg(obj, 1, MMU_GFLUSH); - - clk_disable(obj->clk); -} -EXPORT_SYMBOL_GPL(flush_iotlb_all); - -/** - * iommu_set_twl - enable/disable table walking logic - * @obj: target iommu - * @on: enable/disable - * - * Function used to enable/disable TWL. If one wants to work - * exclusively with locked TLB entries and receive notifications - * for TLB miss then call this function to disable TWL. - */ -void iommu_set_twl(struct iommu *obj, bool on) -{ - clk_enable(obj->clk); - arch_iommu->set_twl(obj, on); - clk_disable(obj->clk); -} -EXPORT_SYMBOL_GPL(iommu_set_twl); - -#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) - -ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) -{ - if (!obj || !buf) - return -EINVAL; - - clk_enable(obj->clk); - - bytes = arch_iommu->dump_ctx(obj, buf, bytes); - - clk_disable(obj->clk); - - return bytes; -} -EXPORT_SYMBOL_GPL(iommu_dump_ctx); - -static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num) -{ - int i; - struct iotlb_lock saved; - struct cr_regs tmp; - struct cr_regs *p = crs; - - clk_enable(obj->clk); - iotlb_lock_get(obj, &saved); - - for_each_iotlb_cr(obj, num, i, tmp) { - if (!iotlb_cr_valid(&tmp)) - continue; - *p++ = tmp; - } - - iotlb_lock_set(obj, &saved); - clk_disable(obj->clk); - - return p - crs; -} - -/** - * dump_tlb_entries - dump cr arrays to given buffer - * @obj: target iommu - * @buf: output buffer - **/ -size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t bytes) -{ - int i, num; - struct cr_regs *cr; - char *p = buf; - - num = bytes / sizeof(*cr); - num = min(obj->nr_tlb_entries, num); - - cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); - if (!cr) - return 0; - - num = __dump_tlb_entries(obj, cr, num); - for (i = 0; i < num; i++) - p += iotlb_dump_cr(obj, cr + i, p); - kfree(cr); - - return p - buf; -} -EXPORT_SYMBOL_GPL(dump_tlb_entries); - -int foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) -{ - return driver_for_each_device(&omap_iommu_driver.driver, - NULL, data, fn); -} -EXPORT_SYMBOL_GPL(foreach_iommu_device); - -#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ - -/* - * H/W pagetable operations - */ -static void flush_iopgd_range(u32 *first, u32 *last) -{ - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); -} - -static void flush_iopte_range(u32 *first, u32 *last) -{ - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); -} - -static void iopte_free(u32 *iopte) -{ - /* Note: freed iopte's must be clean ready for re-use */ - kmem_cache_free(iopte_cachep, iopte); -} - -static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da) -{ - u32 *iopte; - - /* a table has already existed */ - if (*iopgd) - goto pte_ready; - - /* - * do the allocation outside the page table lock - */ - spin_unlock(&obj->page_table_lock); - iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); - spin_lock(&obj->page_table_lock); - - if (!*iopgd) { - if (!iopte) - return ERR_PTR(-ENOMEM); - - *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; - flush_iopgd_range(iopgd, iopgd); - - dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); - } else { - /* We raced, free the reduniovant table */ - iopte_free(iopte); - } - -pte_ready: - iopte = iopte_offset(iopgd, da); - - dev_vdbg(obj->dev, - "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", - __func__, da, iopgd, *iopgd, iopte, *iopte); - - return iopte; -} - -static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot) -{ - u32 *iopgd = iopgd_offset(obj, da); - - if ((da | pa) & ~IOSECTION_MASK) { - dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", - __func__, da, pa, IOSECTION_SIZE); - return -EINVAL; - } - - *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; - flush_iopgd_range(iopgd, iopgd); - return 0; -} - -static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot) -{ - u32 *iopgd = iopgd_offset(obj, da); - int i; - - if ((da | pa) & ~IOSUPER_MASK) { - dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", - __func__, da, pa, IOSUPER_SIZE); - return -EINVAL; - } - - for (i = 0; i < 16; i++) - *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; - flush_iopgd_range(iopgd, iopgd + 15); - return 0; -} - -static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot) -{ - u32 *iopgd = iopgd_offset(obj, da); - u32 *iopte = iopte_alloc(obj, iopgd, da); - - if (IS_ERR(iopte)) - return PTR_ERR(iopte); - - *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; - flush_iopte_range(iopte, iopte); - - dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", - __func__, da, pa, iopte, *iopte); - - return 0; -} - -static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot) -{ - u32 *iopgd = iopgd_offset(obj, da); - u32 *iopte = iopte_alloc(obj, iopgd, da); - int i; - - if ((da | pa) & ~IOLARGE_MASK) { - dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", - __func__, da, pa, IOLARGE_SIZE); - return -EINVAL; - } - - if (IS_ERR(iopte)) - return PTR_ERR(iopte); - - for (i = 0; i < 16; i++) - *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; - flush_iopte_range(iopte, iopte + 15); - return 0; -} - -static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e) -{ - int (*fn)(struct iommu *, u32, u32, u32); - u32 prot; - int err; - - if (!obj || !e) - return -EINVAL; - - switch (e->pgsz) { - case MMU_CAM_PGSZ_16M: - fn = iopgd_alloc_super; - break; - case MMU_CAM_PGSZ_1M: - fn = iopgd_alloc_section; - break; - case MMU_CAM_PGSZ_64K: - fn = iopte_alloc_large; - break; - case MMU_CAM_PGSZ_4K: - fn = iopte_alloc_page; - break; - default: - fn = NULL; - BUG(); - break; - } - - prot = get_iopte_attr(e); - - spin_lock(&obj->page_table_lock); - err = fn(obj, e->da, e->pa, prot); - spin_unlock(&obj->page_table_lock); - - return err; -} - -/** - * iopgtable_store_entry - Make an iommu pte entry - * @obj: target iommu - * @e: an iommu tlb entry info - **/ -int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e) -{ - int err; - - flush_iotlb_page(obj, e->da); - err = iopgtable_store_entry_core(obj, e); -#ifdef PREFETCH_IOTLB - if (!err) - load_iotlb_entry(obj, e); -#endif - return err; -} -EXPORT_SYMBOL_GPL(iopgtable_store_entry); - -/** - * iopgtable_lookup_entry - Lookup an iommu pte entry - * @obj: target iommu - * @da: iommu device virtual address - * @ppgd: iommu pgd entry pointer to be returned - * @ppte: iommu pte entry pointer to be returned - **/ -void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte) -{ - u32 *iopgd, *iopte = NULL; - - iopgd = iopgd_offset(obj, da); - if (!*iopgd) - goto out; - - if (iopgd_is_table(*iopgd)) - iopte = iopte_offset(iopgd, da); -out: - *ppgd = iopgd; - *ppte = iopte; -} -EXPORT_SYMBOL_GPL(iopgtable_lookup_entry); - -static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) -{ - size_t bytes; - u32 *iopgd = iopgd_offset(obj, da); - int nent = 1; - - if (!*iopgd) - return 0; - - if (iopgd_is_table(*iopgd)) { - int i; - u32 *iopte = iopte_offset(iopgd, da); - - bytes = IOPTE_SIZE; - if (*iopte & IOPTE_LARGE) { - nent *= 16; - /* rewind to the 1st entry */ - iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); - } - bytes *= nent; - memset(iopte, 0, nent * sizeof(*iopte)); - flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); - - /* - * do table walk to check if this table is necessary or not - */ - iopte = iopte_offset(iopgd, 0); - for (i = 0; i < PTRS_PER_IOPTE; i++) - if (iopte[i]) - goto out; - - iopte_free(iopte); - nent = 1; /* for the next L1 entry */ - } else { - bytes = IOPGD_SIZE; - if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { - nent *= 16; - /* rewind to the 1st entry */ - iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); - } - bytes *= nent; - } - memset(iopgd, 0, nent * sizeof(*iopgd)); - flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); -out: - return bytes; -} - -/** - * iopgtable_clear_entry - Remove an iommu pte entry - * @obj: target iommu - * @da: iommu device virtual address - **/ -size_t iopgtable_clear_entry(struct iommu *obj, u32 da) -{ - size_t bytes; - - spin_lock(&obj->page_table_lock); - - bytes = iopgtable_clear_entry_core(obj, da); - flush_iotlb_page(obj, da); - - spin_unlock(&obj->page_table_lock); - - return bytes; -} -EXPORT_SYMBOL_GPL(iopgtable_clear_entry); - -static void iopgtable_clear_entry_all(struct iommu *obj) -{ - int i; - - spin_lock(&obj->page_table_lock); - - for (i = 0; i < PTRS_PER_IOPGD; i++) { - u32 da; - u32 *iopgd; - - da = i << IOPGD_SHIFT; - iopgd = iopgd_offset(obj, da); - - if (!*iopgd) - continue; - - if (iopgd_is_table(*iopgd)) - iopte_free(iopte_offset(iopgd, 0)); - - *iopgd = 0; - flush_iopgd_range(iopgd, iopgd); - } - - flush_iotlb_all(obj); - - spin_unlock(&obj->page_table_lock); -} - -/* - * Device IOMMU generic operations - */ -static irqreturn_t iommu_fault_handler(int irq, void *data) -{ - u32 da, errs; - u32 *iopgd, *iopte; - struct iommu *obj = data; - - if (!obj->refcount) - return IRQ_NONE; - - clk_enable(obj->clk); - errs = iommu_report_fault(obj, &da); - clk_disable(obj->clk); - if (errs == 0) - return IRQ_HANDLED; - - /* Fault callback or TLB/PTE Dynamic loading */ - if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) - return IRQ_HANDLED; - - iommu_disable(obj); - - iopgd = iopgd_offset(obj, da); - - if (!iopgd_is_table(*iopgd)) { - dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " - "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); - return IRQ_NONE; - } - - iopte = iopte_offset(iopgd, da); - - dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " - "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, - iopte, *iopte); - - return IRQ_NONE; -} - -static int device_match_by_alias(struct device *dev, void *data) -{ - struct iommu *obj = to_iommu(dev); - const char *name = data; - - pr_debug("%s: %s %s\n", __func__, obj->name, name); - - return strcmp(obj->name, name) == 0; -} - -/** - * iommu_set_da_range - Set a valid device address range - * @obj: target iommu - * @start Start of valid range - * @end End of valid range - **/ -int iommu_set_da_range(struct iommu *obj, u32 start, u32 end) -{ - - if (!obj) - return -EFAULT; - - if (end < start || !PAGE_ALIGN(start | end)) - return -EINVAL; - - obj->da_start = start; - obj->da_end = end; - - return 0; -} -EXPORT_SYMBOL_GPL(iommu_set_da_range); - -/** - * iommu_get - Get iommu handler - * @name: target iommu name - **/ -struct iommu *iommu_get(const char *name) -{ - int err = -ENOMEM; - struct device *dev; - struct iommu *obj; - - dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, - device_match_by_alias); - if (!dev) - return ERR_PTR(-ENODEV); - - obj = to_iommu(dev); - - mutex_lock(&obj->iommu_lock); - - if (obj->refcount++ == 0) { - err = iommu_enable(obj); - if (err) - goto err_enable; - flush_iotlb_all(obj); - } - - if (!try_module_get(obj->owner)) - goto err_module; - - mutex_unlock(&obj->iommu_lock); - - dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); - return obj; - -err_module: - if (obj->refcount == 1) - iommu_disable(obj); -err_enable: - obj->refcount--; - mutex_unlock(&obj->iommu_lock); - return ERR_PTR(err); -} -EXPORT_SYMBOL_GPL(iommu_get); - -/** - * iommu_put - Put back iommu handler - * @obj: target iommu - **/ -void iommu_put(struct iommu *obj) -{ - if (!obj || IS_ERR(obj)) - return; - - mutex_lock(&obj->iommu_lock); - - if (--obj->refcount == 0) - iommu_disable(obj); - - module_put(obj->owner); - - mutex_unlock(&obj->iommu_lock); - - dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); -} -EXPORT_SYMBOL_GPL(iommu_put); - -int iommu_set_isr(const char *name, - int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, - void *priv), - void *isr_priv) -{ - struct device *dev; - struct iommu *obj; - - dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, - device_match_by_alias); - if (!dev) - return -ENODEV; - - obj = to_iommu(dev); - mutex_lock(&obj->iommu_lock); - if (obj->refcount != 0) { - mutex_unlock(&obj->iommu_lock); - return -EBUSY; - } - obj->isr = isr; - obj->isr_priv = isr_priv; - mutex_unlock(&obj->iommu_lock); - - return 0; -} -EXPORT_SYMBOL_GPL(iommu_set_isr); - -/* - * OMAP Device MMU(IOMMU) detection - */ -static int __devinit omap_iommu_probe(struct platform_device *pdev) -{ - int err = -ENODEV; - void *p; - int irq; - struct iommu *obj; - struct resource *res; - struct iommu_platform_data *pdata = pdev->dev.platform_data; - - if (pdev->num_resources != 2) - return -EINVAL; - - obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); - if (!obj) - return -ENOMEM; - - obj->clk = clk_get(&pdev->dev, pdata->clk_name); - if (IS_ERR(obj->clk)) - goto err_clk; - - obj->nr_tlb_entries = pdata->nr_tlb_entries; - obj->name = pdata->name; - obj->dev = &pdev->dev; - obj->ctx = (void *)obj + sizeof(*obj); - obj->da_start = pdata->da_start; - obj->da_end = pdata->da_end; - - mutex_init(&obj->iommu_lock); - mutex_init(&obj->mmap_lock); - spin_lock_init(&obj->page_table_lock); - INIT_LIST_HEAD(&obj->mmap); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - err = -ENODEV; - goto err_mem; - } - - res = request_mem_region(res->start, resource_size(res), - dev_name(&pdev->dev)); - if (!res) { - err = -EIO; - goto err_mem; - } - - obj->regbase = ioremap(res->start, resource_size(res)); - if (!obj->regbase) { - err = -ENOMEM; - goto err_ioremap; - } - - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - err = -ENODEV; - goto err_irq; - } - err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, - dev_name(&pdev->dev), obj); - if (err < 0) - goto err_irq; - platform_set_drvdata(pdev, obj); - - p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE)); - if (!p) { - err = -ENOMEM; - goto err_pgd; - } - memset(p, 0, IOPGD_TABLE_SIZE); - clean_dcache_area(p, IOPGD_TABLE_SIZE); - obj->iopgd = p; - - BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE)); - - dev_info(&pdev->dev, "%s registered\n", obj->name); - return 0; - -err_pgd: - free_irq(irq, obj); -err_irq: - iounmap(obj->regbase); -err_ioremap: - release_mem_region(res->start, resource_size(res)); -err_mem: - clk_put(obj->clk); -err_clk: - kfree(obj); - return err; -} - -static int __devexit omap_iommu_remove(struct platform_device *pdev) -{ - int irq; - struct resource *res; - struct iommu *obj = platform_get_drvdata(pdev); - - platform_set_drvdata(pdev, NULL); - - iopgtable_clear_entry_all(obj); - free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE)); - - irq = platform_get_irq(pdev, 0); - free_irq(irq, obj); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(res->start, resource_size(res)); - iounmap(obj->regbase); - - clk_put(obj->clk); - dev_info(&pdev->dev, "%s removed\n", obj->name); - kfree(obj); - return 0; -} - -static struct platform_driver omap_iommu_driver = { - .probe = omap_iommu_probe, - .remove = __devexit_p(omap_iommu_remove), - .driver = { - .name = "omap-iommu", - }, -}; - -static void iopte_cachep_ctor(void *iopte) -{ - clean_dcache_area(iopte, IOPTE_TABLE_SIZE); -} - -static int __init omap_iommu_init(void) -{ - struct kmem_cache *p; - const unsigned long flags = SLAB_HWCACHE_ALIGN; - size_t align = 1 << 10; /* L2 pagetable alignement */ - - p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, - iopte_cachep_ctor); - if (!p) - return -ENOMEM; - iopte_cachep = p; - - return platform_driver_register(&omap_iommu_driver); -} -module_init(omap_iommu_init); - -static void __exit omap_iommu_exit(void) -{ - kmem_cache_destroy(iopte_cachep); - - platform_driver_unregister(&omap_iommu_driver); -} -module_exit(omap_iommu_exit); - -MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); -MODULE_ALIAS("platform:omap-iommu"); -MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); -MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c deleted file mode 100644 index 79e7fed..0000000 --- a/arch/arm/plat-omap/iovmm.c +++ /dev/null @@ -1,904 +0,0 @@ -/* - * omap iommu: simple virtual address space management - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/err.h> -#include <linux/slab.h> -#include <linux/vmalloc.h> -#include <linux/device.h> -#include <linux/scatterlist.h> - -#include <asm/cacheflush.h> -#include <asm/mach/map.h> - -#include <plat/iommu.h> -#include <plat/iovmm.h> - -#include "iopgtable.h" - -/* - * A device driver needs to create address mappings between: - * - * - iommu/device address - * - physical address - * - mpu virtual address - * - * There are 4 possible patterns for them: - * - * |iova/ mapping iommu_ page - * | da pa va (d)-(p)-(v) function type - * --------------------------------------------------------------------------- - * 1 | c c c 1 - 1 - 1 _kmap() / _kunmap() s - * 2 | c c,a c 1 - 1 - 1 _kmalloc()/ _kfree() s - * 3 | c d c 1 - n - 1 _vmap() / _vunmap() s - * 4 | c d,a c 1 - n - 1 _vmalloc()/ _vfree() n* - * - * - * 'iova': device iommu virtual address - * 'da': alias of 'iova' - * 'pa': physical address - * 'va': mpu virtual address - * - * 'c': contiguous memory area - * 'd': discontiguous memory area - * 'a': anonymous memory allocation - * '()': optional feature - * - * 'n': a normal page(4KB) size is used. - * 's': multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used. - * - * '*': not yet, but feasible. - */ - -static struct kmem_cache *iovm_area_cachep; - -/* return total bytes of sg buffers */ -static size_t sgtable_len(const struct sg_table *sgt) -{ - unsigned int i, total = 0; - struct scatterlist *sg; - - if (!sgt) - return 0; - - for_each_sg(sgt->sgl, sg, sgt->nents, i) { - size_t bytes; - - bytes = sg->length; - - if (!iopgsz_ok(bytes)) { - pr_err("%s: sg[%d] not iommu pagesize(%x)\n", - __func__, i, bytes); - return 0; - } - - total += bytes; - } - - return total; -} -#define sgtable_ok(x) (!!sgtable_len(x)) - -static unsigned max_alignment(u32 addr) -{ - int i; - unsigned pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, }; - for (i = 0; i < ARRAY_SIZE(pagesize) && addr & (pagesize[i] - 1); i++) - ; - return (i < ARRAY_SIZE(pagesize)) ? pagesize[i] : 0; -} - -/* - * calculate the optimal number sg elements from total bytes based on - * iommu superpages - */ -static unsigned sgtable_nents(size_t bytes, u32 da, u32 pa) -{ - unsigned nr_entries = 0, ent_sz; - - if (!IS_ALIGNED(bytes, PAGE_SIZE)) { - pr_err("%s: wrong size %08x\n", __func__, bytes); - return 0; - } - - while (bytes) { - ent_sz = max_alignment(da | pa); - ent_sz = min_t(unsigned, ent_sz, iopgsz_max(bytes)); - nr_entries++; - da += ent_sz; - pa += ent_sz; - bytes -= ent_sz; - } - - return nr_entries; -} - -/* allocate and initialize sg_table header(a kind of 'superblock') */ -static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags, - u32 da, u32 pa) -{ - unsigned int nr_entries; - int err; - struct sg_table *sgt; - - if (!bytes) - return ERR_PTR(-EINVAL); - - if (!IS_ALIGNED(bytes, PAGE_SIZE)) - return ERR_PTR(-EINVAL); - - if (flags & IOVMF_LINEAR) { - nr_entries = sgtable_nents(bytes, da, pa); - if (!nr_entries) - return ERR_PTR(-EINVAL); - } else - nr_entries = bytes / PAGE_SIZE; - - sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); - if (!sgt) - return ERR_PTR(-ENOMEM); - - err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL); - if (err) { - kfree(sgt); - return ERR_PTR(err); - } - - pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries); - - return sgt; -} - -/* free sg_table header(a kind of superblock) */ -static void sgtable_free(struct sg_table *sgt) -{ - if (!sgt) - return; - - sg_free_table(sgt); - kfree(sgt); - - pr_debug("%s: sgt:%p\n", __func__, sgt); -} - -/* map 'sglist' to a contiguous mpu virtual area and return 'va' */ -static void *vmap_sg(const struct sg_table *sgt) -{ - u32 va; - size_t total; - unsigned int i; - struct scatterlist *sg; - struct vm_struct *new; - const struct mem_type *mtype; - - mtype = get_mem_type(MT_DEVICE); - if (!mtype) - return ERR_PTR(-EINVAL); - - total = sgtable_len(sgt); - if (!total) - return ERR_PTR(-EINVAL); - - new = __get_vm_area(total, VM_IOREMAP, VMALLOC_START, VMALLOC_END); - if (!new) - return ERR_PTR(-ENOMEM); - va = (u32)new->addr; - - for_each_sg(sgt->sgl, sg, sgt->nents, i) { - size_t bytes; - u32 pa; - int err; - - pa = sg_phys(sg); - bytes = sg->length; - - BUG_ON(bytes != PAGE_SIZE); - - err = ioremap_page(va, pa, mtype); - if (err) - goto err_out; - - va += bytes; - } - - flush_cache_vmap((unsigned long)new->addr, - (unsigned long)(new->addr + total)); - return new->addr; - -err_out: - WARN_ON(1); /* FIXME: cleanup some mpu mappings */ - vunmap(new->addr); - return ERR_PTR(-EAGAIN); -} - -static inline void vunmap_sg(const void *va) -{ - vunmap(va); -} - -static struct iovm_struct *__find_iovm_area(struct iommu *obj, const u32 da) -{ - struct iovm_struct *tmp; - - list_for_each_entry(tmp, &obj->mmap, list) { - if ((da >= tmp->da_start) && (da < tmp->da_end)) { - size_t len; - - len = tmp->da_end - tmp->da_start; - - dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", - __func__, tmp->da_start, da, tmp->da_end, len, - tmp->flags); - - return tmp; - } - } - - return NULL; -} - -/** - * find_iovm_area - find iovma which includes @da - * @da: iommu device virtual address - * - * Find the existing iovma starting at @da - */ -struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da) -{ - struct iovm_struct *area; - - mutex_lock(&obj->mmap_lock); - area = __find_iovm_area(obj, da); - mutex_unlock(&obj->mmap_lock); - - return area; -} -EXPORT_SYMBOL_GPL(find_iovm_area); - -/* - * This finds the hole(area) which fits the requested address and len - * in iovmas mmap, and returns the new allocated iovma. - */ -static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, - size_t bytes, u32 flags) -{ - struct iovm_struct *new, *tmp; - u32 start, prev_end, alignment; - - if (!obj || !bytes) - return ERR_PTR(-EINVAL); - - start = da; - alignment = PAGE_SIZE; - - if (~flags & IOVMF_DA_FIXED) { - /* Don't map address 0 */ - start = obj->da_start ? obj->da_start : alignment; - - if (flags & IOVMF_LINEAR) - alignment = iopgsz_max(bytes); - start = roundup(start, alignment); - } else if (start < obj->da_start || start > obj->da_end || - obj->da_end - start < bytes) { - return ERR_PTR(-EINVAL); - } - - tmp = NULL; - if (list_empty(&obj->mmap)) - goto found; - - prev_end = 0; - list_for_each_entry(tmp, &obj->mmap, list) { - - if (prev_end > start) - break; - - if (tmp->da_start > start && (tmp->da_start - start) >= bytes) - goto found; - - if (tmp->da_end >= start && ~flags & IOVMF_DA_FIXED) - start = roundup(tmp->da_end + 1, alignment); - - prev_end = tmp->da_end; - } - - if ((start >= prev_end) && (obj->da_end - start >= bytes)) - goto found; - - dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", - __func__, da, bytes, flags); - - return ERR_PTR(-EINVAL); - -found: - new = kmem_cache_zalloc(iovm_area_cachep, GFP_KERNEL); - if (!new) - return ERR_PTR(-ENOMEM); - - new->iommu = obj; - new->da_start = start; - new->da_end = start + bytes; - new->flags = flags; - - /* - * keep ascending order of iovmas - */ - if (tmp) - list_add_tail(&new->list, &tmp->list); - else - list_add(&new->list, &obj->mmap); - - dev_dbg(obj->dev, "%s: found %08x-%08x-%08x(%x) %08x\n", - __func__, new->da_start, start, new->da_end, bytes, flags); - - return new; -} - -static void free_iovm_area(struct iommu *obj, struct iovm_struct *area) -{ - size_t bytes; - - BUG_ON(!obj || !area); - - bytes = area->da_end - area->da_start; - - dev_dbg(obj->dev, "%s: %08x-%08x(%x) %08x\n", - __func__, area->da_start, area->da_end, bytes, area->flags); - - list_del(&area->list); - kmem_cache_free(iovm_area_cachep, area); -} - -/** - * da_to_va - convert (d) to (v) - * @obj: objective iommu - * @da: iommu device virtual address - * @va: mpu virtual address - * - * Returns mpu virtual addr which corresponds to a given device virtual addr - */ -void *da_to_va(struct iommu *obj, u32 da) -{ - void *va = NULL; - struct iovm_struct *area; - - mutex_lock(&obj->mmap_lock); - - area = __find_iovm_area(obj, da); - if (!area) { - dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da); - goto out; - } - va = area->va; -out: - mutex_unlock(&obj->mmap_lock); - - return va; -} -EXPORT_SYMBOL_GPL(da_to_va); - -static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va) -{ - unsigned int i; - struct scatterlist *sg; - void *va = _va; - void *va_end; - - for_each_sg(sgt->sgl, sg, sgt->nents, i) { - struct page *pg; - const size_t bytes = PAGE_SIZE; - - /* - * iommu 'superpage' isn't supported with 'iommu_vmalloc()' - */ - pg = vmalloc_to_page(va); - BUG_ON(!pg); - sg_set_page(sg, pg, bytes, 0); - - va += bytes; - } - - va_end = _va + PAGE_SIZE * i; -} - -static inline void sgtable_drain_vmalloc(struct sg_table *sgt) -{ - /* - * Actually this is not necessary at all, just exists for - * consistency of the code readability. - */ - BUG_ON(!sgt); -} - -static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, u32 da, - size_t len) -{ - unsigned int i; - struct scatterlist *sg; - - for_each_sg(sgt->sgl, sg, sgt->nents, i) { - unsigned bytes; - - bytes = max_alignment(da | pa); - bytes = min_t(unsigned, bytes, iopgsz_max(len)); - - BUG_ON(!iopgsz_ok(bytes)); - - sg_set_buf(sg, phys_to_virt(pa), bytes); - /* - * 'pa' is cotinuous(linear). - */ - pa += bytes; - da += bytes; - len -= bytes; - } - BUG_ON(len); -} - -static inline void sgtable_drain_kmalloc(struct sg_table *sgt) -{ - /* - * Actually this is not necessary at all, just exists for - * consistency of the code readability - */ - BUG_ON(!sgt); -} - -/* create 'da' <-> 'pa' mapping from 'sgt' */ -static int map_iovm_area(struct iommu *obj, struct iovm_struct *new, - const struct sg_table *sgt, u32 flags) -{ - int err; - unsigned int i, j; - struct scatterlist *sg; - u32 da = new->da_start; - - if (!obj || !sgt) - return -EINVAL; - - BUG_ON(!sgtable_ok(sgt)); - - for_each_sg(sgt->sgl, sg, sgt->nents, i) { - u32 pa; - int pgsz; - size_t bytes; - struct iotlb_entry e; - - pa = sg_phys(sg); - bytes = sg->length; - - flags &= ~IOVMF_PGSZ_MASK; - pgsz = bytes_to_iopgsz(bytes); - if (pgsz < 0) - goto err_out; - flags |= pgsz; - - pr_debug("%s: [%d] %08x %08x(%x)\n", __func__, - i, da, pa, bytes); - - iotlb_init_entry(&e, da, pa, flags); - err = iopgtable_store_entry(obj, &e); - if (err) - goto err_out; - - da += bytes; - } - return 0; - -err_out: - da = new->da_start; - - for_each_sg(sgt->sgl, sg, i, j) { - size_t bytes; - - bytes = iopgtable_clear_entry(obj, da); - - BUG_ON(!iopgsz_ok(bytes)); - - da += bytes; - } - return err; -} - -/* release 'da' <-> 'pa' mapping */ -static void unmap_iovm_area(struct iommu *obj, struct iovm_struct *area) -{ - u32 start; - size_t total = area->da_end - area->da_start; - - BUG_ON((!total) || !IS_ALIGNED(total, PAGE_SIZE)); - - start = area->da_start; - while (total > 0) { - size_t bytes; - - bytes = iopgtable_clear_entry(obj, start); - if (bytes == 0) - bytes = PAGE_SIZE; - else - dev_dbg(obj->dev, "%s: unmap %08x(%x) %08x\n", - __func__, start, bytes, area->flags); - - BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE)); - - total -= bytes; - start += bytes; - } - BUG_ON(total); -} - -/* template function for all unmapping */ -static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da, - void (*fn)(const void *), u32 flags) -{ - struct sg_table *sgt = NULL; - struct iovm_struct *area; - - if (!IS_ALIGNED(da, PAGE_SIZE)) { - dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da); - return NULL; - } - - mutex_lock(&obj->mmap_lock); - - area = __find_iovm_area(obj, da); - if (!area) { - dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da); - goto out; - } - - if ((area->flags & flags) != flags) { - dev_err(obj->dev, "%s: wrong flags(%08x)\n", __func__, - area->flags); - goto out; - } - sgt = (struct sg_table *)area->sgt; - - unmap_iovm_area(obj, area); - - fn(area->va); - - dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", __func__, - area->da_start, da, area->da_end, - area->da_end - area->da_start, area->flags); - - free_iovm_area(obj, area); -out: - mutex_unlock(&obj->mmap_lock); - - return sgt; -} - -static u32 map_iommu_region(struct iommu *obj, u32 da, - const struct sg_table *sgt, void *va, size_t bytes, u32 flags) -{ - int err = -ENOMEM; - struct iovm_struct *new; - - mutex_lock(&obj->mmap_lock); - - new = alloc_iovm_area(obj, da, bytes, flags); - if (IS_ERR(new)) { - err = PTR_ERR(new); - goto err_alloc_iovma; - } - new->va = va; - new->sgt = sgt; - - if (map_iovm_area(obj, new, sgt, new->flags)) - goto err_map; - - mutex_unlock(&obj->mmap_lock); - - dev_dbg(obj->dev, "%s: da:%08x(%x) flags:%08x va:%p\n", - __func__, new->da_start, bytes, new->flags, va); - - return new->da_start; - -err_map: - free_iovm_area(obj, new); -err_alloc_iovma: - mutex_unlock(&obj->mmap_lock); - return err; -} - -static inline u32 __iommu_vmap(struct iommu *obj, u32 da, - const struct sg_table *sgt, void *va, size_t bytes, u32 flags) -{ - return map_iommu_region(obj, da, sgt, va, bytes, flags); -} - -/** - * iommu_vmap - (d)-(p)-(v) address mapper - * @obj: objective iommu - * @sgt: address of scatter gather table - * @flags: iovma and page property - * - * Creates 1-n-1 mapping with given @sgt and returns @da. - * All @sgt element must be io page size aligned. - */ -u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt, - u32 flags) -{ - size_t bytes; - void *va = NULL; - - if (!obj || !obj->dev || !sgt) - return -EINVAL; - - bytes = sgtable_len(sgt); - if (!bytes) - return -EINVAL; - bytes = PAGE_ALIGN(bytes); - - if (flags & IOVMF_MMIO) { - va = vmap_sg(sgt); - if (IS_ERR(va)) - return PTR_ERR(va); - } - - flags |= IOVMF_DISCONT; - flags |= IOVMF_MMIO; - - da = __iommu_vmap(obj, da, sgt, va, bytes, flags); - if (IS_ERR_VALUE(da)) - vunmap_sg(va); - - return da; -} -EXPORT_SYMBOL_GPL(iommu_vmap); - -/** - * iommu_vunmap - release virtual mapping obtained by 'iommu_vmap()' - * @obj: objective iommu - * @da: iommu device virtual address - * - * Free the iommu virtually contiguous memory area starting at - * @da, which was returned by 'iommu_vmap()'. - */ -struct sg_table *iommu_vunmap(struct iommu *obj, u32 da) -{ - struct sg_table *sgt; - /* - * 'sgt' is allocated before 'iommu_vmalloc()' is called. - * Just returns 'sgt' to the caller to free - */ - sgt = unmap_vm_area(obj, da, vunmap_sg, IOVMF_DISCONT | IOVMF_MMIO); - if (!sgt) - dev_dbg(obj->dev, "%s: No sgt\n", __func__); - return sgt; -} -EXPORT_SYMBOL_GPL(iommu_vunmap); - -/** - * iommu_vmalloc - (d)-(p)-(v) address allocator and mapper - * @obj: objective iommu - * @da: contiguous iommu virtual memory - * @bytes: allocation size - * @flags: iovma and page property - * - * Allocate @bytes linearly and creates 1-n-1 mapping and returns - * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set. - */ -u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) -{ - void *va; - struct sg_table *sgt; - - if (!obj || !obj->dev || !bytes) - return -EINVAL; - - bytes = PAGE_ALIGN(bytes); - - va = vmalloc(bytes); - if (!va) - return -ENOMEM; - - flags |= IOVMF_DISCONT; - flags |= IOVMF_ALLOC; - - sgt = sgtable_alloc(bytes, flags, da, 0); - if (IS_ERR(sgt)) { - da = PTR_ERR(sgt); - goto err_sgt_alloc; - } - sgtable_fill_vmalloc(sgt, va); - - da = __iommu_vmap(obj, da, sgt, va, bytes, flags); - if (IS_ERR_VALUE(da)) - goto err_iommu_vmap; - - return da; - -err_iommu_vmap: - sgtable_drain_vmalloc(sgt); - sgtable_free(sgt); -err_sgt_alloc: - vfree(va); - return da; -} -EXPORT_SYMBOL_GPL(iommu_vmalloc); - -/** - * iommu_vfree - release memory allocated by 'iommu_vmalloc()' - * @obj: objective iommu - * @da: iommu device virtual address - * - * Frees the iommu virtually continuous memory area starting at - * @da, as obtained from 'iommu_vmalloc()'. - */ -void iommu_vfree(struct iommu *obj, const u32 da) -{ - struct sg_table *sgt; - - sgt = unmap_vm_area(obj, da, vfree, IOVMF_DISCONT | IOVMF_ALLOC); - if (!sgt) - dev_dbg(obj->dev, "%s: No sgt\n", __func__); - sgtable_free(sgt); -} -EXPORT_SYMBOL_GPL(iommu_vfree); - -static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va, - size_t bytes, u32 flags) -{ - struct sg_table *sgt; - - sgt = sgtable_alloc(bytes, flags, da, pa); - if (IS_ERR(sgt)) - return PTR_ERR(sgt); - - sgtable_fill_kmalloc(sgt, pa, da, bytes); - - da = map_iommu_region(obj, da, sgt, va, bytes, flags); - if (IS_ERR_VALUE(da)) { - sgtable_drain_kmalloc(sgt); - sgtable_free(sgt); - } - - return da; -} - -/** - * iommu_kmap - (d)-(p)-(v) address mapper - * @obj: objective iommu - * @da: contiguous iommu virtual memory - * @pa: contiguous physical memory - * @flags: iovma and page property - * - * Creates 1-1-1 mapping and returns @da again, which can be - * adjusted if 'IOVMF_DA_FIXED' is not set. - */ -u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, - u32 flags) -{ - void *va; - - if (!obj || !obj->dev || !bytes) - return -EINVAL; - - bytes = PAGE_ALIGN(bytes); - - va = ioremap(pa, bytes); - if (!va) - return -ENOMEM; - - flags |= IOVMF_LINEAR; - flags |= IOVMF_MMIO; - - da = __iommu_kmap(obj, da, pa, va, bytes, flags); - if (IS_ERR_VALUE(da)) - iounmap(va); - - return da; -} -EXPORT_SYMBOL_GPL(iommu_kmap); - -/** - * iommu_kunmap - release virtual mapping obtained by 'iommu_kmap()' - * @obj: objective iommu - * @da: iommu device virtual address - * - * Frees the iommu virtually contiguous memory area starting at - * @da, which was passed to and was returned by'iommu_kmap()'. - */ -void iommu_kunmap(struct iommu *obj, u32 da) -{ - struct sg_table *sgt; - typedef void (*func_t)(const void *); - - sgt = unmap_vm_area(obj, da, (func_t)iounmap, - IOVMF_LINEAR | IOVMF_MMIO); - if (!sgt) - dev_dbg(obj->dev, "%s: No sgt\n", __func__); - sgtable_free(sgt); -} -EXPORT_SYMBOL_GPL(iommu_kunmap); - -/** - * iommu_kmalloc - (d)-(p)-(v) address allocator and mapper - * @obj: objective iommu - * @da: contiguous iommu virtual memory - * @bytes: bytes for allocation - * @flags: iovma and page property - * - * Allocate @bytes linearly and creates 1-1-1 mapping and returns - * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set. - */ -u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) -{ - void *va; - u32 pa; - - if (!obj || !obj->dev || !bytes) - return -EINVAL; - - bytes = PAGE_ALIGN(bytes); - - va = kmalloc(bytes, GFP_KERNEL | GFP_DMA); - if (!va) - return -ENOMEM; - pa = virt_to_phys(va); - - flags |= IOVMF_LINEAR; - flags |= IOVMF_ALLOC; - - da = __iommu_kmap(obj, da, pa, va, bytes, flags); - if (IS_ERR_VALUE(da)) - kfree(va); - - return da; -} -EXPORT_SYMBOL_GPL(iommu_kmalloc); - -/** - * iommu_kfree - release virtual mapping obtained by 'iommu_kmalloc()' - * @obj: objective iommu - * @da: iommu device virtual address - * - * Frees the iommu virtually contiguous memory area starting at - * @da, which was passed to and was returned by'iommu_kmalloc()'. - */ -void iommu_kfree(struct iommu *obj, u32 da) -{ - struct sg_table *sgt; - - sgt = unmap_vm_area(obj, da, kfree, IOVMF_LINEAR | IOVMF_ALLOC); - if (!sgt) - dev_dbg(obj->dev, "%s: No sgt\n", __func__); - sgtable_free(sgt); -} -EXPORT_SYMBOL_GPL(iommu_kfree); - - -static int __init iovmm_init(void) -{ - const unsigned long flags = SLAB_HWCACHE_ALIGN; - struct kmem_cache *p; - - p = kmem_cache_create("iovm_area_cache", sizeof(struct iovm_struct), 0, - flags, NULL); - if (!p) - return -ENOMEM; - iovm_area_cachep = p; - - return 0; -} -module_init(iovmm_init); - -static void __exit iovmm_exit(void) -{ - kmem_cache_destroy(iovm_area_cachep); -} -module_exit(iovmm_exit); - -MODULE_DESCRIPTION("omap iommu: simple virtual address space management"); -MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); -MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 6c62af1..4b15cd7 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -24,45 +24,40 @@ #include <linux/slab.h> #include <plat/mcbsp.h> -#include <plat/omap_device.h> #include <linux/pm_runtime.h> -/* XXX These "sideways" includes are a sign that something is wrong */ -#include "../mach-omap2/cm2xxx_3xxx.h" -#include "../mach-omap2/cm-regbits-34xx.h" - struct omap_mcbsp **mcbsp_ptr; -int omap_mcbsp_count, omap_mcbsp_cache_size; +int omap_mcbsp_count; + +#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) +#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { - if (cpu_class_is_omap1()) { - ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; - __raw_writew((u16)val, mcbsp->io_base + reg); - } else if (cpu_is_omap2420()) { - ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val; - __raw_writew((u16)val, mcbsp->io_base + reg); + void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; + + if (mcbsp->pdata->reg_size == 2) { + ((u16 *)mcbsp->reg_cache)[reg] = (u16)val; + __raw_writew((u16)val, addr); } else { - ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val; - __raw_writel(val, mcbsp->io_base + reg); + ((u32 *)mcbsp->reg_cache)[reg] = val; + __raw_writel(val, addr); } } static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) { - if (cpu_class_is_omap1()) { - return !from_cache ? __raw_readw(mcbsp->io_base + reg) : - ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)]; - } else if (cpu_is_omap2420()) { - return !from_cache ? __raw_readw(mcbsp->io_base + reg) : - ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)]; + void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; + + if (mcbsp->pdata->reg_size == 2) { + return !from_cache ? __raw_readw(addr) : + ((u16 *)mcbsp->reg_cache)[reg]; } else { - return !from_cache ? __raw_readl(mcbsp->io_base + reg) : - ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)]; + return !from_cache ? __raw_readl(addr) : + ((u32 *)mcbsp->reg_cache)[reg]; } } -#ifdef CONFIG_ARCH_OMAP3 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { __raw_writel(val, mcbsp->st_data->io_base_st + reg); @@ -72,7 +67,6 @@ static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) { return __raw_readl(mcbsp->st_data->io_base_st + reg); } -#endif #define MCBSP_READ(mcbsp, reg) \ omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) @@ -187,7 +181,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) MCBSP_WRITE(mcbsp, MCR2, config->mcr2); MCBSP_WRITE(mcbsp, MCR1, config->mcr1); MCBSP_WRITE(mcbsp, PCR0, config->pcr0); - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { + if (mcbsp->pdata->has_ccr) { MCBSP_WRITE(mcbsp, XCCR, config->xccr); MCBSP_WRITE(mcbsp, RCCR, config->rccr); } @@ -239,46 +233,28 @@ int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream) } mcbsp = id_to_mcbsp_ptr(id); - data_reg = mcbsp->phys_dma_base; - - if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) { + if (mcbsp->pdata->reg_size == 2) { if (stream) - data_reg += OMAP_MCBSP_REG_DRR1; + data_reg = OMAP_MCBSP_REG_DRR1; else - data_reg += OMAP_MCBSP_REG_DXR1; + data_reg = OMAP_MCBSP_REG_DXR1; } else { if (stream) - data_reg += OMAP_MCBSP_REG_DRR; + data_reg = OMAP_MCBSP_REG_DRR; else - data_reg += OMAP_MCBSP_REG_DXR; + data_reg = OMAP_MCBSP_REG_DXR; } - return data_reg; + return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step; } EXPORT_SYMBOL(omap_mcbsp_dma_reg_params); -#ifdef CONFIG_ARCH_OMAP3 -static struct omap_device *find_omap_device_by_dev(struct device *dev) -{ - struct platform_device *pdev = container_of(dev, - struct platform_device, dev); - return container_of(pdev, struct omap_device, pdev); -} - static void omap_st_on(struct omap_mcbsp *mcbsp) { unsigned int w; - struct omap_device *od; - od = find_omap_device_by_dev(mcbsp->dev); - - /* - * Sidetone uses McBSP ICLK - which must not idle when sidetones - * are enabled or sidetones start sounding ugly. - */ - w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); - w &= ~(1 << (mcbsp->id - 2)); - omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); + if (mcbsp->pdata->enable_st_clock) + mcbsp->pdata->enable_st_clock(mcbsp->id, 1); /* Enable McBSP Sidetone */ w = MCBSP_READ(mcbsp, SSELCR); @@ -292,9 +268,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp) static void omap_st_off(struct omap_mcbsp *mcbsp) { unsigned int w; - struct omap_device *od; - - od = find_omap_device_by_dev(mcbsp->dev); w = MCBSP_ST_READ(mcbsp, SSELCR); MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); @@ -302,17 +275,13 @@ static void omap_st_off(struct omap_mcbsp *mcbsp) w = MCBSP_READ(mcbsp, SSELCR); MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); - w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); - w |= 1 << (mcbsp->id - 2); - omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); + if (mcbsp->pdata->enable_st_clock) + mcbsp->pdata->enable_st_clock(mcbsp->id, 0); } static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) { u16 val, i; - struct omap_device *od; - - od = find_omap_device_by_dev(mcbsp->dev); val = MCBSP_ST_READ(mcbsp, SSELCR); @@ -340,9 +309,6 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp) { u16 w; struct omap_mcbsp_st_data *st_data = mcbsp->st_data; - struct omap_device *od; - - od = find_omap_device_by_dev(mcbsp->dev); w = MCBSP_ST_READ(mcbsp, SSELCR); @@ -525,14 +491,13 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) - return; - if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); return; } mcbsp = id_to_mcbsp_ptr(id); + if (mcbsp->pdata->buffer_size == 0) + return; if (threshold && threshold <= mcbsp->max_tx_thres) MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); @@ -548,14 +513,13 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) - return; - if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); return; } mcbsp = id_to_mcbsp_ptr(id); + if (mcbsp->pdata->buffer_size == 0) + return; if (threshold && threshold <= mcbsp->max_rx_thres) MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); @@ -625,6 +589,8 @@ u16 omap_mcbsp_get_tx_delay(unsigned int id) return -ENODEV; } mcbsp = id_to_mcbsp_ptr(id); + if (mcbsp->pdata->buffer_size == 0) + return 0; /* Returns the number of free locations in the buffer */ buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); @@ -648,6 +614,8 @@ u16 omap_mcbsp_get_rx_delay(unsigned int id) return -ENODEV; } mcbsp = id_to_mcbsp_ptr(id); + if (mcbsp->pdata->buffer_size == 0) + return 0; /* Returns the number of used locations in the buffer */ buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); @@ -683,46 +651,6 @@ int omap_mcbsp_get_dma_op_mode(unsigned int id) } EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode); -static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) -{ - struct omap_device *od; - - od = find_omap_device_by_dev(mcbsp->dev); - /* - * Enable wakup behavior, smart idle and all wakeups - * REVISIT: some wakeups may be unnecessary - */ - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); - } -} - -static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) -{ - struct omap_device *od; - - od = find_omap_device_by_dev(mcbsp->dev); - - /* - * Disable wakup behavior, smart idle and all wakeups - */ - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - /* - * HW bug workaround - If no_idle mode is taken, we need to - * go to smart_idle before going to always_idle, or the - * device will not hit retention anymore. - */ - - MCBSP_WRITE(mcbsp, WAKEUPEN, 0); - } -} -#else -static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {} -static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {} -static inline void omap_st_start(struct omap_mcbsp *mcbsp) {} -static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {} -#endif - int omap_mcbsp_request(unsigned int id) { struct omap_mcbsp *mcbsp; @@ -735,7 +663,7 @@ int omap_mcbsp_request(unsigned int id) } mcbsp = id_to_mcbsp_ptr(id); - reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL); + reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL); if (!reg_cache) { return -ENOMEM; } @@ -757,8 +685,9 @@ int omap_mcbsp_request(unsigned int id) pm_runtime_get_sync(mcbsp->dev); - /* Do procedure specific to omap34xx arch, if applicable */ - omap34xx_mcbsp_request(mcbsp); + /* Enable wakeup behavior */ + if (mcbsp->pdata->has_wakeup) + MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); /* * Make sure that transmitter, receiver and sample-rate generator are @@ -795,8 +724,9 @@ err_clk_disable: if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) mcbsp->pdata->ops->free(id); - /* Do procedure specific to omap34xx arch, if applicable */ - omap34xx_mcbsp_free(mcbsp); + /* Disable wakeup behavior */ + if (mcbsp->pdata->has_wakeup) + MCBSP_WRITE(mcbsp, WAKEUPEN, 0); pm_runtime_put_sync(mcbsp->dev); @@ -825,8 +755,9 @@ void omap_mcbsp_free(unsigned int id) if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) mcbsp->pdata->ops->free(id); - /* Do procedure specific to omap34xx arch, if applicable */ - omap34xx_mcbsp_free(mcbsp); + /* Disable wakeup behavior */ + if (mcbsp->pdata->has_wakeup) + MCBSP_WRITE(mcbsp, WAKEUPEN, 0); pm_runtime_put_sync(mcbsp->dev); @@ -866,7 +797,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) } mcbsp = id_to_mcbsp_ptr(id); - if (cpu_is_omap34xx()) + if (mcbsp->st_data) omap_st_start(mcbsp); /* Only enable SRG, if McBSP is master */ @@ -904,7 +835,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { + if (mcbsp->pdata->has_ccr) { /* Release the transmitter and receiver */ w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); @@ -934,7 +865,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset transmitter */ tx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { + if (mcbsp->pdata->has_ccr) { w = MCBSP_READ_CACHE(mcbsp, XCCR); w |= (tx ? XDISABLE : 0); MCBSP_WRITE(mcbsp, XCCR, w); @@ -944,7 +875,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset receiver */ rx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { + if (mcbsp->pdata->has_ccr) { w = MCBSP_READ_CACHE(mcbsp, RCCR); w |= (rx ? RDISABLE : 0); MCBSP_WRITE(mcbsp, RCCR, w); @@ -961,39 +892,72 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); } - if (cpu_is_omap34xx()) + if (mcbsp->st_data) omap_st_stop(mcbsp); } EXPORT_SYMBOL(omap_mcbsp_stop); -/* - * The following functions are only required on an OMAP1-only build. - * mach-omap2/mcbsp.c contains the real functions - */ -#ifndef CONFIG_ARCH_OMAP2PLUS int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) { - WARN(1, "%s: should never be called on an OMAP1-only kernel\n", - __func__); - return -EINVAL; + struct omap_mcbsp *mcbsp; + const char *src; + + if (!omap_mcbsp_check_valid_id(id)) { + pr_err("%s: Invalid id (%d)\n", __func__, id + 1); + return -EINVAL; + } + mcbsp = id_to_mcbsp_ptr(id); + + if (fck_src_id == MCBSP_CLKS_PAD_SRC) + src = "clks_ext"; + else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) + src = "clks_fclk"; + else + return -EINVAL; + + if (mcbsp->pdata->set_clk_src) + return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src); + else + return -EINVAL; } +EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); void omap2_mcbsp1_mux_clkr_src(u8 mux) { - WARN(1, "%s: should never be called on an OMAP1-only kernel\n", - __func__); - return; + struct omap_mcbsp *mcbsp; + const char *src; + + if (mux == CLKR_SRC_CLKR) + src = "clkr"; + else if (mux == CLKR_SRC_CLKX) + src = "clkx"; + else + return; + + mcbsp = id_to_mcbsp_ptr(0); + if (mcbsp->pdata->mux_signal) + mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src); } +EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src); void omap2_mcbsp1_mux_fsr_src(u8 mux) { - WARN(1, "%s: should never be called on an OMAP1-only kernel\n", - __func__); - return; + struct omap_mcbsp *mcbsp; + const char *src; + + if (mux == FSR_SRC_FSR) + src = "fsr"; + else if (mux == FSR_SRC_FSX) + src = "fsx"; + else + return; + + mcbsp = id_to_mcbsp_ptr(0); + if (mcbsp->pdata->mux_signal) + mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src); } -#endif +EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src); -#ifdef CONFIG_ARCH_OMAP3 #define max_thres(m) (mcbsp->pdata->buffer_size) #define valid_threshold(m, val) ((val) <= max_thres(m)) #define THRESHOLD_PROP_BUILDER(prop) \ @@ -1084,6 +1048,17 @@ unlock: static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store); +static const struct attribute *additional_attrs[] = { + &dev_attr_max_tx_thres.attr, + &dev_attr_max_rx_thres.attr, + &dev_attr_dma_op_mode.attr, + NULL, +}; + +static const struct attribute_group additional_attr_group = { + .attrs = (struct attribute **)additional_attrs, +}; + static ssize_t st_taps_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1142,27 +1117,6 @@ out: static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store); -static const struct attribute *additional_attrs[] = { - &dev_attr_max_tx_thres.attr, - &dev_attr_max_rx_thres.attr, - &dev_attr_dma_op_mode.attr, - NULL, -}; - -static const struct attribute_group additional_attr_group = { - .attrs = (struct attribute **)additional_attrs, -}; - -static inline int __devinit omap_additional_add(struct device *dev) -{ - return sysfs_create_group(&dev->kobj, &additional_attr_group); -} - -static inline void __devexit omap_additional_remove(struct device *dev) -{ - sysfs_remove_group(&dev->kobj, &additional_attr_group); -} - static const struct attribute *sidetone_attrs[] = { &dev_attr_st_taps.attr, NULL, @@ -1172,10 +1126,9 @@ static const struct attribute_group sidetone_attr_group = { .attrs = (struct attribute **)sidetone_attrs, }; -static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) +static int __devinit omap_st_add(struct omap_mcbsp *mcbsp, + struct resource *res) { - struct platform_device *pdev; - struct resource *res; struct omap_mcbsp_st_data *st_data; int err; @@ -1185,9 +1138,6 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) goto err1; } - pdev = container_of(mcbsp->dev, struct platform_device, dev); - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone"); st_data->io_base_st = ioremap(res->start, resource_size(res)); if (!st_data->io_base_st) { err = -ENOMEM; @@ -1214,59 +1164,10 @@ static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp) { struct omap_mcbsp_st_data *st_data = mcbsp->st_data; - if (st_data) { - sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group); - iounmap(st_data->io_base_st); - kfree(st_data); - } -} - -static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) -{ - mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; - if (cpu_is_omap34xx()) { - /* - * Initially configure the maximum thresholds to a safe value. - * The McBSP FIFO usage with these values should not go under - * 16 locations. - * If the whole FIFO without safety buffer is used, than there - * is a possibility that the DMA will be not able to push the - * new data on time, causing channel shifts in runtime. - */ - mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; - mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; - /* - * REVISIT: Set dmap_op_mode to THRESHOLD as default - * for mcbsp2 instances. - */ - if (omap_additional_add(mcbsp->dev)) - dev_warn(mcbsp->dev, - "Unable to create additional controls\n"); - - if (mcbsp->id == 2 || mcbsp->id == 3) - if (omap_st_add(mcbsp)) - dev_warn(mcbsp->dev, - "Unable to create sidetone controls\n"); - - } else { - mcbsp->max_tx_thres = -EINVAL; - mcbsp->max_rx_thres = -EINVAL; - } -} - -static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) -{ - if (cpu_is_omap34xx()) { - omap_additional_remove(mcbsp->dev); - - if (mcbsp->id == 2 || mcbsp->id == 3) - omap_st_remove(mcbsp); - } + sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group); + iounmap(st_data->io_base_st); + kfree(st_data); } -#else -static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {} -static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {} -#endif /* CONFIG_ARCH_OMAP3 */ /* * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. @@ -1316,7 +1217,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) } } mcbsp->phys_base = res->start; - omap_mcbsp_cache_size = resource_size(res); + mcbsp->reg_cache_size = resource_size(res); mcbsp->io_base = ioremap(res->start, resource_size(res)); if (!mcbsp->io_base) { ret = -ENOMEM; @@ -1364,15 +1265,52 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) mcbsp->pdata = pdata; mcbsp->dev = &pdev->dev; mcbsp_ptr[id] = mcbsp; - mcbsp->mcbsp_config_type = pdata->mcbsp_config_type; platform_set_drvdata(pdev, mcbsp); pm_runtime_enable(mcbsp->dev); - /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ - omap34xx_device_init(mcbsp); + mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; + if (mcbsp->pdata->buffer_size) { + /* + * Initially configure the maximum thresholds to a safe value. + * The McBSP FIFO usage with these values should not go under + * 16 locations. + * If the whole FIFO without safety buffer is used, than there + * is a possibility that the DMA will be not able to push the + * new data on time, causing channel shifts in runtime. + */ + mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; + mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; + + ret = sysfs_create_group(&mcbsp->dev->kobj, + &additional_attr_group); + if (ret) { + dev_err(mcbsp->dev, + "Unable to create additional controls\n"); + goto err_thres; + } + } else { + mcbsp->max_tx_thres = -EINVAL; + mcbsp->max_rx_thres = -EINVAL; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone"); + if (res) { + ret = omap_st_add(mcbsp, res); + if (ret) { + dev_err(mcbsp->dev, + "Unable to create sidetone controls\n"); + goto err_st; + } + } return 0; +err_st: + if (mcbsp->pdata->buffer_size) + sysfs_remove_group(&mcbsp->dev->kobj, + &additional_attr_group); +err_thres: + clk_put(mcbsp->fclk); err_res: iounmap(mcbsp->io_base); err_ioremap: @@ -1392,7 +1330,12 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev) mcbsp->pdata->ops->free) mcbsp->pdata->ops->free(mcbsp->id); - omap34xx_device_exit(mcbsp); + if (mcbsp->pdata->buffer_size) + sysfs_remove_group(&mcbsp->dev->kobj, + &additional_attr_group); + + if (mcbsp->st_data) + omap_st_remove(mcbsp); clk_put(mcbsp->fclk); diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 02609ee..26aee5c 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -94,6 +94,9 @@ #define USE_WAKEUP_LAT 0 #define IGNORE_WAKEUP_LAT 1 +static int omap_device_register(struct platform_device *pdev); +static int omap_early_device_register(struct platform_device *pdev); + /* Private functions */ /** @@ -114,7 +117,7 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) { struct timespec a, b, c; - pr_debug("omap_device: %s: activating\n", od->pdev.name); + dev_dbg(&od->pdev->dev, "omap_device: activating\n"); while (od->pm_lat_level > 0) { struct omap_device_pm_latency *odpl; @@ -138,25 +141,24 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) c = timespec_sub(b, a); act_lat = timespec_to_ns(&c); - pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " - "%llu nsec\n", od->pdev.name, od->pm_lat_level, - act_lat); + dev_dbg(&od->pdev->dev, + "omap_device: pm_lat %d: activate: elapsed time " + "%llu nsec\n", od->pm_lat_level, act_lat); if (act_lat > odpl->activate_lat) { odpl->activate_lat_worst = act_lat; if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { odpl->activate_lat = act_lat; - pr_warning("omap_device: %s.%d: new worst case " - "activate latency %d: %llu\n", - od->pdev.name, od->pdev.id, - od->pm_lat_level, act_lat); + dev_dbg(&od->pdev->dev, + "new worst case activate latency " + "%d: %llu\n", + od->pm_lat_level, act_lat); } else - pr_warning("omap_device: %s.%d: activate " - "latency %d higher than exptected. " - "(%llu > %d)\n", - od->pdev.name, od->pdev.id, - od->pm_lat_level, act_lat, - odpl->activate_lat); + dev_warn(&od->pdev->dev, + "activate latency %d " + "higher than exptected. (%llu > %d)\n", + od->pm_lat_level, act_lat, + odpl->activate_lat); } od->dev_wakeup_lat -= odpl->activate_lat; @@ -183,7 +185,7 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) { struct timespec a, b, c; - pr_debug("omap_device: %s: deactivating\n", od->pdev.name); + dev_dbg(&od->pdev->dev, "omap_device: deactivating\n"); while (od->pm_lat_level < od->pm_lats_cnt) { struct omap_device_pm_latency *odpl; @@ -206,28 +208,26 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) c = timespec_sub(b, a); deact_lat = timespec_to_ns(&c); - pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " - "%llu nsec\n", od->pdev.name, od->pm_lat_level, - deact_lat); + dev_dbg(&od->pdev->dev, + "omap_device: pm_lat %d: deactivate: elapsed time " + "%llu nsec\n", od->pm_lat_level, deact_lat); if (deact_lat > odpl->deactivate_lat) { odpl->deactivate_lat_worst = deact_lat; if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { odpl->deactivate_lat = deact_lat; - pr_warning("omap_device: %s.%d: new worst case " - "deactivate latency %d: %llu\n", - od->pdev.name, od->pdev.id, - od->pm_lat_level, deact_lat); + dev_dbg(&od->pdev->dev, + "new worst case deactivate latency " + "%d: %llu\n", + od->pm_lat_level, deact_lat); } else - pr_warning("omap_device: %s.%d: deactivate " - "latency %d higher than exptected. " - "(%llu > %d)\n", - od->pdev.name, od->pdev.id, - od->pm_lat_level, deact_lat, - odpl->deactivate_lat); + dev_warn(&od->pdev->dev, + "deactivate latency %d " + "higher than exptected. (%llu > %d)\n", + od->pm_lat_level, deact_lat, + odpl->deactivate_lat); } - od->dev_wakeup_lat += odpl->activate_lat; od->pm_lat_level++; @@ -245,28 +245,27 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, if (!clk_alias || !clk_name) return; - pr_debug("omap_device: %s: Creating %s -> %s\n", - dev_name(&od->pdev.dev), clk_alias, clk_name); + dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name); - r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias); + r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); if (!IS_ERR(r)) { - pr_warning("omap_device: %s: alias %s already exists\n", - dev_name(&od->pdev.dev), clk_alias); + dev_warn(&od->pdev->dev, + "alias %s already exists\n", clk_alias); clk_put(r); return; } r = omap_clk_get_by_name(clk_name); if (IS_ERR(r)) { - pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n", - dev_name(&od->pdev.dev), clk_name); + dev_err(&od->pdev->dev, + "omap_clk_get_by_name for %s failed\n", clk_name); return; } - l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev)); + l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev)); if (!l) { - pr_err("omap_device: %s: clkdev_alloc for %s failed\n", - dev_name(&od->pdev.dev), clk_alias); + dev_err(&od->pdev->dev, + "clkdev_alloc for %s failed\n", clk_alias); return; } @@ -343,7 +342,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev) * much memory to allocate before calling * omap_device_fill_resources(). Returns the count. */ -int omap_device_count_resources(struct omap_device *od) +static int omap_device_count_resources(struct omap_device *od) { int c = 0; int i; @@ -352,7 +351,7 @@ int omap_device_count_resources(struct omap_device *od) c += omap_hwmod_count_resources(od->hwmods[i]); pr_debug("omap_device: %s: counted %d total resources across %d " - "hwmods\n", od->pdev.name, c, od->hwmods_cnt); + "hwmods\n", od->pdev->name, c, od->hwmods_cnt); return c; } @@ -374,7 +373,8 @@ int omap_device_count_resources(struct omap_device *od) * functions to get device resources. Hacking around the existing * platform_device code wastes memory. Returns 0. */ -int omap_device_fill_resources(struct omap_device *od, struct resource *res) +static int omap_device_fill_resources(struct omap_device *od, + struct resource *res) { int c = 0; int i, r; @@ -405,7 +405,7 @@ int omap_device_fill_resources(struct omap_device *od, struct resource *res) * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise, * passes along the return value of omap_device_build_ss(). */ -struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, +struct platform_device *omap_device_build(const char *pdev_name, int pdev_id, struct omap_hwmod *oh, void *pdata, int pdata_len, struct omap_device_pm_latency *pm_lats, @@ -438,15 +438,15 @@ struct omap_device *omap_device_build(const char *pdev_name, int pdev_id, * platform_device record. Returns an ERR_PTR() on error, or passes * along the return value of omap_device_register(). */ -struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, +struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id, struct omap_hwmod **ohs, int oh_cnt, void *pdata, int pdata_len, struct omap_device_pm_latency *pm_lats, int pm_lats_cnt, int is_early_device) { int ret = -ENOMEM; + struct platform_device *pdev; struct omap_device *od; - char *pdev_name2; struct resource *res = NULL; int i, res_count; struct omap_hwmod **hwmods; @@ -457,72 +457,76 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, if (!pdata && pdata_len > 0) return ERR_PTR(-EINVAL); + pdev = platform_device_alloc(pdev_name, pdev_id); + if (!pdev) { + ret = -ENOMEM; + goto odbs_exit; + } + pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name, oh_cnt); od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); - if (!od) - return ERR_PTR(-ENOMEM); - + if (!od) { + ret = -ENOMEM; + goto odbs_exit1; + } od->hwmods_cnt = oh_cnt; hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL); if (!hwmods) - goto odbs_exit1; + goto odbs_exit2; memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt); od->hwmods = hwmods; - - pdev_name2 = kzalloc(strlen(pdev_name) + 1, GFP_KERNEL); - if (!pdev_name2) - goto odbs_exit2; - strcpy(pdev_name2, pdev_name); - - od->pdev.name = pdev_name2; - od->pdev.id = pdev_id; + od->pdev = pdev; res_count = omap_device_count_resources(od); if (res_count > 0) { res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); if (!res) goto odbs_exit3; - } - omap_device_fill_resources(od, res); - od->pdev.num_resources = res_count; - od->pdev.resource = res; + omap_device_fill_resources(od, res); + + ret = platform_device_add_resources(pdev, res, res_count); + kfree(res); - ret = platform_device_add_data(&od->pdev, pdata, pdata_len); + if (ret) + goto odbs_exit3; + } + + ret = platform_device_add_data(pdev, pdata, pdata_len); if (ret) - goto odbs_exit4; + goto odbs_exit3; - od->pm_lats = pm_lats; - od->pm_lats_cnt = pm_lats_cnt; + pdev->archdata.od = od; if (is_early_device) - ret = omap_early_device_register(od); + ret = omap_early_device_register(pdev); else - ret = omap_device_register(od); + ret = omap_device_register(pdev); + if (ret) + goto odbs_exit3; + + od->pm_lats = pm_lats; + od->pm_lats_cnt = pm_lats_cnt; for (i = 0; i < oh_cnt; i++) { hwmods[i]->od = od; _add_hwmod_clocks_clkdev(od, hwmods[i]); } - if (ret) - goto odbs_exit4; - - return od; + return pdev; -odbs_exit4: - kfree(res); odbs_exit3: - kfree(pdev_name2); -odbs_exit2: kfree(hwmods); -odbs_exit1: +odbs_exit2: kfree(od); +odbs_exit1: + platform_device_put(pdev); +odbs_exit: pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret); @@ -538,11 +542,11 @@ odbs_exit1: * platform_early_add_device() on the underlying platform_device. * Returns 0 by default. */ -int omap_early_device_register(struct omap_device *od) +static int omap_early_device_register(struct platform_device *pdev) { struct platform_device *devices[1]; - devices[0] = &(od->pdev); + devices[0] = pdev; early_platform_add_devices(devices, 1); return 0; } @@ -638,13 +642,13 @@ static struct dev_pm_domain omap_device_pm_domain = { * platform_device_register() on the underlying platform_device. * Returns the return value of platform_device_register(). */ -int omap_device_register(struct omap_device *od) +static int omap_device_register(struct platform_device *pdev) { - pr_debug("omap_device: %s: registering\n", od->pdev.name); + pr_debug("omap_device: %s: registering\n", pdev->name); - od->pdev.dev.parent = &omap_device_parent; - od->pdev.dev.pm_domain = &omap_device_pm_domain; - return platform_device_register(&od->pdev); + pdev->dev.parent = &omap_device_parent; + pdev->dev.pm_domain = &omap_device_pm_domain; + return platform_device_add(pdev); } @@ -671,8 +675,9 @@ int omap_device_enable(struct platform_device *pdev) od = to_omap_device(pdev); if (od->_state == OMAP_DEVICE_STATE_ENABLED) { - WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", - od->pdev.name, od->pdev.id, __func__, od->_state); + dev_warn(&pdev->dev, + "omap_device: %s() called from invalid state %d\n", + __func__, od->_state); return -EINVAL; } @@ -710,8 +715,9 @@ int omap_device_idle(struct platform_device *pdev) od = to_omap_device(pdev); if (od->_state != OMAP_DEVICE_STATE_ENABLED) { - WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", - od->pdev.name, od->pdev.id, __func__, od->_state); + dev_warn(&pdev->dev, + "omap_device: %s() called from invalid state %d\n", + __func__, od->_state); return -EINVAL; } @@ -742,8 +748,9 @@ int omap_device_shutdown(struct platform_device *pdev) if (od->_state != OMAP_DEVICE_STATE_ENABLED && od->_state != OMAP_DEVICE_STATE_IDLE) { - WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", - od->pdev.name, od->pdev.id, __func__, od->_state); + dev_warn(&pdev->dev, + "omap_device: %s() called from invalid state %d\n", + __func__, od->_state); return -EINVAL; } diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 89e68e0..5c79c29 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -456,7 +456,7 @@ struct mfp_addr_map { #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } -void __init mfp_init_base(unsigned long mfpr_base); +void __init mfp_init_base(void __iomem *mfpr_base); void __init mfp_init_addr(struct mfp_addr_map *map); /* diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c index be12ead..2c4dbb1 100644 --- a/arch/arm/plat-pxa/mfp.c +++ b/arch/arm/plat-pxa/mfp.c @@ -229,7 +229,7 @@ void mfp_write(int mfp, unsigned long val) spin_unlock_irqrestore(&mfp_spin_lock, flags); } -void __init mfp_init_base(unsigned long mfpr_base) +void __init mfp_init_base(void __iomem *mfpr_base) { int i; @@ -237,7 +237,7 @@ void __init mfp_init_base(unsigned long mfpr_base) for (i = 0; i < ARRAY_SIZE(mfp_table); i++) mfp_table[i].config = -1; - mfpr_mmio_base = (void __iomem *)mfpr_base; + mfpr_mmio_base = mfpr_base; } void __init mfp_init_addr(struct mfp_addr_map *map) diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h deleted file mode 100644 index bd534d3..0000000 --- a/arch/arm/plat-s3c24xx/include/plat/map.h +++ /dev/null @@ -1,100 +0,0 @@ -/* linux/include/asm-arm/plat-s3c24xx/map.h - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_S3C24XX_MAP_H -#define __ASM_PLAT_S3C24XX_MAP_H - -/* interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ -#define S3C24XX_VA_IRQ S3C_VA_IRQ -#define S3C2410_PA_IRQ (0x4A000000) -#define S3C24XX_SZ_IRQ SZ_1M - -/* memory controller registers */ -#define S3C24XX_VA_MEMCTRL S3C_VA_MEM -#define S3C2410_PA_MEMCTRL (0x48000000) -#define S3C24XX_SZ_MEMCTRL SZ_1M - -/* UARTs */ -#define S3C24XX_VA_UART S3C_VA_UART -#define S3C2410_PA_UART (0x50000000) -#define S3C24XX_SZ_UART SZ_1M -#define S3C_UART_OFFSET (0x4000) - -#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) - -/* Timers */ -#define S3C24XX_VA_TIMER S3C_VA_TIMER -#define S3C2410_PA_TIMER (0x51000000) -#define S3C24XX_SZ_TIMER SZ_1M - -/* Clock and Power management */ -#define S3C24XX_VA_CLKPWR S3C_VA_SYS -#define S3C24XX_SZ_CLKPWR SZ_1M - -/* USB Device port */ -#define S3C2410_PA_USBDEV (0x52000000) -#define S3C24XX_SZ_USBDEV SZ_1M - -/* Watchdog */ -#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG -#define S3C2410_PA_WATCHDOG (0x53000000) -#define S3C24XX_SZ_WATCHDOG SZ_1M - -/* Standard size definitions for peripheral blocks. */ - -#define S3C24XX_SZ_IIS SZ_1M -#define S3C24XX_SZ_ADC SZ_1M -#define S3C24XX_SZ_SPI SZ_1M -#define S3C24XX_SZ_SDI SZ_1M -#define S3C24XX_SZ_NAND SZ_1M - -/* GPIO ports */ - -/* the calculation for the VA of this must ensure that - * it is the same distance apart from the UART in the - * phsyical address space, as the initial mapping for the IO - * is done as a 1:1 mapping. This puts it (currently) at - * 0xFA800000, which is not in the way of any current mapping - * by the base system. -*/ - -#define S3C2410_PA_GPIO (0x56000000) -#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) -#define S3C24XX_SZ_GPIO SZ_1M - - -/* ISA style IO, for each machine to sort out mappings for, if it - * implements it. We reserve two 16M regions for ISA. - */ - -#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) -#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) - -/* deal with the registers that move under the 2412/2413 */ - -#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) -#ifndef __ASSEMBLY__ -extern void __iomem *s3c24xx_va_gpio2; -#endif -#ifdef CONFIG_CPU_S3C2412_ONLY -#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) -#else -#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 -#endif -#else -#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO -#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO -#endif - -#endif /* __ASM_PLAT_S3C24XX_MAP_H */ diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 9843c95..9a197e5 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -22,7 +22,6 @@ config PLAT_S5P select PLAT_SAMSUNG select SAMSUNG_CLKSRC select SAMSUNG_IRQ_VIC_TIMER - select SAMSUNG_IRQ_UART help Base platform code for Samsung's S5P series SoC. diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c index afaf87f..c9308db 100644 --- a/arch/arm/plat-s5p/dev-uart.c +++ b/arch/arm/plat-s5p/dev-uart.c @@ -32,20 +32,10 @@ static struct resource s5p_uart0_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S5P_UART_RX0, - .end = IRQ_S5P_UART_RX0, + .start = IRQ_UART0, + .end = IRQ_UART0, .flags = IORESOURCE_IRQ, }, - [2] = { - .start = IRQ_S5P_UART_TX0, - .end = IRQ_S5P_UART_TX0, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_S5P_UART_ERR0, - .end = IRQ_S5P_UART_ERR0, - .flags = IORESOURCE_IRQ, - } }; static struct resource s5p_uart1_resource[] = { @@ -55,18 +45,8 @@ static struct resource s5p_uart1_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S5P_UART_RX1, - .end = IRQ_S5P_UART_RX1, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S5P_UART_TX1, - .end = IRQ_S5P_UART_TX1, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_S5P_UART_ERR1, - .end = IRQ_S5P_UART_ERR1, + .start = IRQ_UART1, + .end = IRQ_UART1, .flags = IORESOURCE_IRQ, }, }; @@ -78,18 +58,8 @@ static struct resource s5p_uart2_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S5P_UART_RX2, - .end = IRQ_S5P_UART_RX2, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S5P_UART_TX2, - .end = IRQ_S5P_UART_TX2, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_S5P_UART_ERR2, - .end = IRQ_S5P_UART_ERR2, + .start = IRQ_UART2, + .end = IRQ_UART2, .flags = IORESOURCE_IRQ, }, }; @@ -102,18 +72,8 @@ static struct resource s5p_uart3_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S5P_UART_RX3, - .end = IRQ_S5P_UART_RX3, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S5P_UART_TX3, - .end = IRQ_S5P_UART_TX3, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_S5P_UART_ERR3, - .end = IRQ_S5P_UART_ERR3, + .start = IRQ_UART3, + .end = IRQ_UART3, .flags = IORESOURCE_IRQ, }, #endif @@ -127,18 +87,8 @@ static struct resource s5p_uart4_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S5P_UART_RX4, - .end = IRQ_S5P_UART_RX4, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S5P_UART_TX4, - .end = IRQ_S5P_UART_TX4, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_S5P_UART_ERR4, - .end = IRQ_S5P_UART_ERR4, + .start = IRQ_UART4, + .end = IRQ_UART4, .flags = IORESOURCE_IRQ, }, #endif @@ -152,18 +102,8 @@ static struct resource s5p_uart5_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_S5P_UART_RX5, - .end = IRQ_S5P_UART_RX5, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_S5P_UART_TX5, - .end = IRQ_S5P_UART_TX5, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_S5P_UART_ERR5, - .end = IRQ_S5P_UART_ERR5, + .start = IRQ_UART5, + .end = IRQ_UART5, .flags = IORESOURCE_IRQ, }, #endif diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index ba9121c..144dbfc 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -37,41 +37,6 @@ #define IRQ_VIC1_BASE S5P_VIC1_BASE #define IRQ_VIC2_BASE S5P_VIC2_BASE -/* UART interrupts, each UART has 4 intterupts per channel so - * use the space between the ISA and S3C main interrupts. Note, these - * are not in the same order as the S3C24XX series! */ - -#define IRQ_S5P_UART_BASE0 (16) -#define IRQ_S5P_UART_BASE1 (20) -#define IRQ_S5P_UART_BASE2 (24) -#define IRQ_S5P_UART_BASE3 (28) - -#define UART_IRQ_RXD (0) -#define UART_IRQ_ERR (1) -#define UART_IRQ_TXD (2) - -#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD) -#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD) -#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR) - -#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD) -#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD) -#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR) - -#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD) -#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD) -#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR) - -#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD) -#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD) -#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR) - -/* S3C compatibilty defines */ -#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0 -#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1 -#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2 -#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3 - /* VIC based IRQs */ #define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index 1bfd61a..3e21b94 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -123,7 +123,6 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; - kdiv = pll_con1 & PLL46XX_KDIV_MASK; if (pll_type == pll_4650c) kdiv = pll_con1 & PLL4650C_KDIV_MASK; diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index f88216d..c65eb79 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -163,9 +163,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_set_type = s5p_gpioint_set_type, - ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group); - ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group); - ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group); + ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start); + ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start); + ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start); irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST | IRQ_NOPROBE, 0); diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c index a97c089..afdaa10 100644 --- a/arch/arm/plat-s5p/irq.c +++ b/arch/arm/plat-s5p/irq.c @@ -17,42 +17,10 @@ #include <asm/hardware/vic.h> -#include <linux/serial_core.h> #include <mach/map.h> #include <plat/regs-timer.h> -#include <plat/regs-serial.h> #include <plat/cpu.h> #include <plat/irq-vic-timer.h> -#include <plat/irq-uart.h> - -/* - * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] - * are consecutive when looking up the interrupt in the demux routines. - */ -static struct s3c_uart_irq uart_irqs[] = { - [0] = { - .regs = S5P_VA_UART0, - .base_irq = IRQ_S5P_UART_BASE0, - .parent_irq = IRQ_UART0, - }, - [1] = { - .regs = S5P_VA_UART1, - .base_irq = IRQ_S5P_UART_BASE1, - .parent_irq = IRQ_UART1, - }, - [2] = { - .regs = S5P_VA_UART2, - .base_irq = IRQ_S5P_UART_BASE2, - .parent_irq = IRQ_UART2, - }, -#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 - [3] = { - .regs = S5P_VA_UART3, - .base_irq = IRQ_S5P_UART_BASE3, - .parent_irq = IRQ_UART3, - }, -#endif -}; void __init s5p_init_irq(u32 *vic, u32 num_vic) { @@ -65,6 +33,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) #endif s3c_init_vic_timer_irq(5, IRQ_TIMER0); - - s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index b3e1065..dffa37b 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -65,11 +65,6 @@ config SAMSUNG_IRQ_VIC_TIMER help Internal configuration to build the VIC timer interrupt code. -config SAMSUNG_IRQ_UART - bool - help - Internal configuration to build the IRQ UART demux code. - # options for gpio configuration support config SAMSUNG_GPIOLIB_4BIT diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 3de756d..09adb84 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -21,7 +21,6 @@ obj-y += dev-asocdma.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o -obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o # ADC diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c index db7a65c..06825c4 100644 --- a/arch/arm/plat-samsung/dev-hsmmc.c +++ b/arch/arm/plat-samsung/dev-hsmmc.c @@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc0 = { void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) { - struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata; - - set->cd_type = pd->cd_type; - set->ext_cd_init = pd->ext_cd_init; - set->ext_cd_cleanup = pd->ext_cd_cleanup; - set->ext_cd_gpio = pd->ext_cd_gpio; - set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; - - if (pd->max_width) - set->max_width = pd->max_width; - if (pd->cfg_gpio) - set->cfg_gpio = pd->cfg_gpio; - if (pd->cfg_card) - set->cfg_card = pd->cfg_card; - if (pd->host_caps) - set->host_caps |= pd->host_caps; - if (pd->clk_type) - set->clk_type = pd->clk_type; + s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata); } diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c index 2497321..4524ef4 100644 --- a/arch/arm/plat-samsung/dev-hsmmc1.c +++ b/arch/arm/plat-samsung/dev-hsmmc1.c @@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc1 = { void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) { - struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata; - - set->cd_type = pd->cd_type; - set->ext_cd_init = pd->ext_cd_init; - set->ext_cd_cleanup = pd->ext_cd_cleanup; - set->ext_cd_gpio = pd->ext_cd_gpio; - set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; - - if (pd->max_width) - set->max_width = pd->max_width; - if (pd->cfg_gpio) - set->cfg_gpio = pd->cfg_gpio; - if (pd->cfg_card) - set->cfg_card = pd->cfg_card; - if (pd->host_caps) - set->host_caps |= pd->host_caps; - if (pd->clk_type) - set->clk_type = pd->clk_type; + s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata); } diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c index f60aedb..9cede96 100644 --- a/arch/arm/plat-samsung/dev-hsmmc2.c +++ b/arch/arm/plat-samsung/dev-hsmmc2.c @@ -59,22 +59,5 @@ struct platform_device s3c_device_hsmmc2 = { void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) { - struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata; - - set->cd_type = pd->cd_type; - set->ext_cd_init = pd->ext_cd_init; - set->ext_cd_cleanup = pd->ext_cd_cleanup; - set->ext_cd_gpio = pd->ext_cd_gpio; - set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; - - if (pd->max_width) - set->max_width = pd->max_width; - if (pd->cfg_gpio) - set->cfg_gpio = pd->cfg_gpio; - if (pd->cfg_card) - set->cfg_card = pd->cfg_card; - if (pd->host_caps) - set->host_caps |= pd->host_caps; - if (pd->clk_type) - set->clk_type = pd->clk_type; + s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata); } diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c index ede776f..0358ef4 100644 --- a/arch/arm/plat-samsung/dev-hsmmc3.c +++ b/arch/arm/plat-samsung/dev-hsmmc3.c @@ -62,22 +62,5 @@ struct platform_device s3c_device_hsmmc3 = { void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd) { - struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata; - - set->cd_type = pd->cd_type; - set->ext_cd_init = pd->ext_cd_init; - set->ext_cd_cleanup = pd->ext_cd_cleanup; - set->ext_cd_gpio = pd->ext_cd_gpio; - set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; - - if (pd->max_width) - set->max_width = pd->max_width; - if (pd->cfg_gpio) - set->cfg_gpio = pd->cfg_gpio; - if (pd->cfg_card) - set->cfg_card = pd->cfg_card; - if (pd->host_caps) - set->host_caps |= pd->host_caps; - if (pd->clk_type) - set->clk_type = pd->clk_type; + s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata); } diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c index 82543f0..5f3d46a 100644 --- a/arch/arm/plat-samsung/dev-ts.c +++ b/arch/arm/plat-samsung/dev-ts.c @@ -43,8 +43,17 @@ struct platform_device s3c_device_ts = { .resource = s3c_ts_resource, }; +static struct s3c2410_ts_mach_info default_ts_data __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 2, +}; + void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) { + if (!pd) + pd = &default_ts_data; + s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts); } diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h index 336d5ac..ab9bce6 100644 --- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h +++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h @@ -18,11 +18,6 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS]; #define DMA_CH_VALID (1<<31) #define DMA_CH_NEVER (1<<30) -struct s3c24xx_dma_addr { - unsigned long from; - unsigned long to; -}; - /* struct s3c24xx_dma_map * * this holds the mapping information for the channel selected @@ -31,7 +26,6 @@ struct s3c24xx_dma_addr { struct s3c24xx_dma_map { const char *name; - struct s3c24xx_dma_addr hw_addr; unsigned long channels[S3C_DMA_CHANNELS]; unsigned long channels_rx[S3C_DMA_CHANNELS]; diff --git a/arch/arm/plat-samsung/include/plat/map-s3c.h b/arch/arm/plat-samsung/include/plat/map-s3c.h new file mode 100644 index 0000000..7d04875 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/map-s3c.h @@ -0,0 +1,84 @@ +/* linux/arch/arm/plat-samsung/include/plat/map-s3c.h + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_MAP_S3C_H +#define __ASM_PLAT_MAP_S3C_H __FILE__ + +#define S3C24XX_VA_IRQ S3C_VA_IRQ +#define S3C24XX_VA_MEMCTRL S3C_VA_MEM +#define S3C24XX_VA_UART S3C_VA_UART + +#define S3C24XX_VA_TIMER S3C_VA_TIMER +#define S3C24XX_VA_CLKPWR S3C_VA_SYS +#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG + +#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) +#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000) + +#define S3C2410_PA_UART (0x50000000) +#define S3C24XX_PA_UART S3C2410_PA_UART + +#ifndef S3C_UART_OFFSET +#define S3C_UART_OFFSET (0x400) +#endif + +/* + * GPIO ports + * + * the calculation for the VA of this must ensure that + * it is the same distance apart from the UART in the + * phsyical address space, as the initial mapping for the IO + * is done as a 1:1 mapping. This puts it (currently) at + * 0xFA800000, which is not in the way of any current mapping + * by the base system. +*/ + +#define S3C2410_PA_GPIO (0x56000000) +#define S3C24XX_PA_GPIO S3C2410_PA_GPIO + +#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) +#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000) + +#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000) +#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) + +#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY + +/* + * ISA style IO, for each machine to sort out mappings for, + * if it implements it. We reserve two 16M regions for ISA. + */ + +#define S3C2410_ADDR(x) S3C_ADDR(x) + +#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) +#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) + +/* deal with the registers that move under the 2412/2413 */ + +#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) +#ifndef __ASSEMBLY__ +extern void __iomem *s3c24xx_va_gpio2; +#endif +#ifdef CONFIG_CPU_S3C2412_ONLY +#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) +#else +#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 +#endif +#else +#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO +#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO +#endif + +#include <plat/map-s5p.h> + +#endif /* __ASM_PLAT_MAP_S3C_H */ diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h index 36d3551..c2d7bda 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h +/* linux/arch/arm/plat-samsung/include/plat/map-s5p.h * * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -40,8 +40,6 @@ #define S5P_VA_GIC_CPU S3C_ADDR(0x02810000) #define S5P_VA_GIC_DIST S3C_ADDR(0x02820000) -#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000) - #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) #define VA_VIC1 VA_VIC(1) @@ -58,4 +56,6 @@ #define S3C_UART_OFFSET (0x400) #endif +#include <plat/map-s3c.h> + #endif /* __ASM_PLAT_MAP_S5P_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index bac36fa..7207348 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -186,6 +186,11 @@ #define S3C64XX_UINTSP 0x34 #define S3C64XX_UINTM 0x38 +#define S3C64XX_UINTM_RXD (0) +#define S3C64XX_UINTM_TXD (2) +#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD) +#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD) + /* Following are specific to S5PV210 */ #define S5PV210_UCON_CLKMASK (1<<10) #define S5PV210_UCON_PCLK (0<<10) diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 058e096..4a65520 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -86,6 +86,13 @@ struct s3c_sdhci_platdata { struct mmc_card *card); }; +/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data + * @pd: The default platform data for this device. + * @set: Pointer to the platform data to fill in. + */ +extern void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd, + struct s3c_sdhci_platdata *set); + /** * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. * @pd: Platform data to register to device. diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c deleted file mode 100644 index 3014c72..0000000 --- a/arch/arm/plat-samsung/irq-uart.c +++ /dev/null @@ -1,96 +0,0 @@ -/* arch/arm/plat-samsung/irq-uart.c - * originally part of arch/arm/plat-s3c64xx/irq.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Samsung- UART Interrupt handling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/serial_core.h> -#include <linux/irq.h> -#include <linux/io.h> - -#include <asm/mach/irq.h> - -#include <mach/map.h> -#include <plat/irq-uart.h> -#include <plat/regs-serial.h> -#include <plat/cpu.h> - -/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] - * are consecutive when looking up the interrupt in the demux routines. - */ -static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) -{ - struct s3c_uart_irq *uirq = desc->irq_data.handler_data; - struct irq_chip *chip = irq_get_chip(irq); - u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); - int base = uirq->base_irq; - - chained_irq_enter(chip, desc); - - if (pend & (1 << 0)) - generic_handle_irq(base); - if (pend & (1 << 1)) - generic_handle_irq(base + 1); - if (pend & (1 << 2)) - generic_handle_irq(base + 2); - if (pend & (1 << 3)) - generic_handle_irq(base + 3); - - chained_irq_exit(chip, desc); -} - -static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) -{ - void __iomem *reg_base = uirq->regs; - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - /* mask all interrupts at the start. */ - __raw_writel(0xf, reg_base + S3C64XX_UINTM); - - gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, - handle_level_irq); - - if (!gc) { - pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n", - __func__, uirq->base_irq); - return; - } - - ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack_set_bit; - ct->chip.irq_mask = irq_gc_mask_set_bit; - ct->chip.irq_unmask = irq_gc_mask_clr_bit; - ct->regs.ack = S3C64XX_UINTP; - ct->regs.mask = S3C64XX_UINTM; - irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE, - IRQ_NOREQUEST | IRQ_NOPROBE, 0); - - irq_set_handler_data(uirq->parent_irq, uirq); - irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); -} - -/** - * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing - * @irq: The interrupt data for registering - * @nr_irqs: The number of interrupt descriptions in @irq. - * - * Register the UART interrupts specified by @irq including the demuxing - * routines. This supports the S3C6400 and newer style of devices. - */ -void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs) -{ - for (; nr_irqs > 0; nr_irqs--, irq++) - s3c_init_uart_irq(irq); -} diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c index 7cf2e1e..6de1a38 100644 --- a/arch/arm/plat-samsung/platformdata.c +++ b/arch/arm/plat-samsung/platformdata.c @@ -14,6 +14,7 @@ #include <linux/platform_device.h> #include <plat/devs.h> +#include <plat/sdhci.h> void __init *s3c_set_platdata(void *pd, size_t pdsize, struct platform_device *pdev) @@ -35,3 +36,24 @@ void __init *s3c_set_platdata(void *pd, size_t pdsize, pdev->dev.platform_data = npd; return npd; } + +void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd, + struct s3c_sdhci_platdata *set) +{ + set->cd_type = pd->cd_type; + set->ext_cd_init = pd->ext_cd_init; + set->ext_cd_cleanup = pd->ext_cd_cleanup; + set->ext_cd_gpio = pd->ext_cd_gpio; + set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; + + if (pd->max_width) + set->max_width = pd->max_width; + if (pd->cfg_gpio) + set->cfg_gpio = pd->cfg_gpio; + if (pd->cfg_card) + set->cfg_card = pd->cfg_card; + if (pd->host_caps) + set->host_caps |= pd->host_caps; + if (pd->clk_type) + set->clk_type = pd->clk_type; +} diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 62cc8f9..5bdeef9 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,10 +12,9 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# XXX: This is a cut-down version of the file; it contains only machines that -# XXX: are in mainline or have been submitted to the machine database within -# XXX: the last 12 months. If your entry is missing please email rmk at -# XXX: <linux@arm.linux.org.uk> +# This is a cut-down version of the file; it contains only machines that +# are merged into mainline or have been edited in the machine database +# within the last 12 months. References to machine_is_NAME() do not count! # # Last update: Sat May 7 08:48:24 2011 # @@ -65,6 +64,7 @@ h7201 ARCH_H7201 H7201 161 h7202 ARCH_H7202 H7202 162 iq80321 ARCH_IQ80321 IQ80321 169 ks8695 ARCH_KS8695 KS8695 180 +karo ARCH_KARO KARO 190 smdk2410 ARCH_SMDK2410 SMDK2410 193 ceiva ARCH_CEIVA CEIVA 200 voiceblue MACH_VOICEBLUE VOICEBLUE 218 @@ -188,6 +188,7 @@ omap_2430sdp MACH_OMAP_2430SDP OMAP_2430SDP 900 davinci_evm MACH_DAVINCI_EVM DAVINCI_EVM 901 palmz72 MACH_PALMZ72 PALMZ72 904 nxdb500 MACH_NXDB500 NXDB500 905 +apf9328 MACH_APF9328 APF9328 906 palmt5 MACH_PALMT5 PALMT5 917 palmtc MACH_PALMTC PALMTC 918 omap_apollon MACH_OMAP_APOLLON OMAP_APOLLON 919 @@ -271,10 +272,12 @@ pcm038 MACH_PCM038 PCM038 1551 ts_x09 MACH_TS209 TS209 1565 at91cap9adk MACH_AT91CAP9ADK AT91CAP9ADK 1566 mx31moboard MACH_MX31MOBOARD MX31MOBOARD 1574 +vision_ep9307 MACH_VISION_EP9307 VISION_EP9307 1578 terastation_pro2 MACH_TERASTATION_PRO2 TERASTATION_PRO2 1584 linkstation_pro MACH_LINKSTATION_PRO LINKSTATION_PRO 1585 e350 MACH_E350 E350 1596 ts409 MACH_TS409 TS409 1601 +rsi_ews MACH_RSI_EWS RSI_EWS 1609 cm_x300 MACH_CM_X300 CM_X300 1616 at91sam9g20ek MACH_AT91SAM9G20EK AT91SAM9G20EK 1624 smdk6410 MACH_SMDK6410 SMDK6410 1626 @@ -331,6 +334,7 @@ smdkc100 MACH_SMDKC100 SMDKC100 1826 tavorevb MACH_TAVOREVB TAVOREVB 1827 saar MACH_SAAR SAAR 1828 at91sam9m10g45ek MACH_AT91SAM9M10G45EK AT91SAM9M10G45EK 1830 +usb_a9g20 MACH_USB_A9G20 USB_A9G20 1841 mxlads MACH_MXLADS MXLADS 1851 linkstation_mini MACH_LINKSTATION_MINI LINKSTATION_MINI 1858 afeb9260 MACH_AFEB9260 AFEB9260 1859 @@ -369,6 +373,7 @@ pcm043 MACH_PCM043 PCM043 2072 sheevaplug MACH_SHEEVAPLUG SHEEVAPLUG 2097 avengers_lite MACH_AVENGERS_LITE AVENGERS_LITE 2104 mx51_babbage MACH_MX51_BABBAGE MX51_BABBAGE 2125 +tx37 MACH_TX37 TX37 2127 rd78x00_masa MACH_RD78X00_MASA RD78X00_MASA 2135 dm355_leopard MACH_DM355_LEOPARD DM355_LEOPARD 2138 ts219 MACH_TS219 TS219 2139 @@ -379,6 +384,7 @@ omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 btmavb101 MACH_BTMAVB101 BTMAVB101 2172 btmawb101 MACH_BTMAWB101 BTMAWB101 2173 +tx25 MACH_TX25 TX25 2177 omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 anw6410 MACH_ANW6410 ANW6410 2183 imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187 @@ -423,6 +429,7 @@ raumfeld_rc MACH_RAUMFELD_RC RAUMFELD_RC 2413 raumfeld_connector MACH_RAUMFELD_CONNECTOR RAUMFELD_CONNECTOR 2414 raumfeld_speaker MACH_RAUMFELD_SPEAKER RAUMFELD_SPEAKER 2415 tnetv107x MACH_TNETV107X TNETV107X 2418 +mx51_m2id MACH_MX51_M2ID MX51_M2ID 2428 smdkv210 MACH_SMDKV210 SMDKV210 2456 omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464 omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465 @@ -433,14 +440,17 @@ omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495 ts41x MACH_TS41X TS41X 2502 phy3250 MACH_PHY3250 PHY3250 2511 mini6410 MACH_MINI6410 MINI6410 2520 +tx51 MACH_TX51 TX51 2529 mx28evk MACH_MX28EVK MX28EVK 2531 smartq5 MACH_SMARTQ5 SMARTQ5 2534 davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548 mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576 riot_x37 MACH_RIOT_X37 RIOT_X37 2578 +pca101 MACH_PCA101 PCA101 2595 capc7117 MACH_CAPC7117 CAPC7117 2612 icontrol MACH_ICONTROL ICONTROL 2624 +gplugd MACH_GPLUGD GPLUGD 2625 qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627 mx23evk MACH_MX23EVK MX23EVK 2629 ap4evb MACH_AP4EVB AP4EVB 2630 @@ -1113,3 +1123,5 @@ blissc MACH_BLISSC BLISSC 3491 thales_adc MACH_THALES_ADC THALES_ADC 3492 ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493 atdgp318 MACH_ATDGP318 ATDGP318 3494 +smdk4212 MACH_SMDK4212 SMDK4212 3638 +smdk4412 MACH_SMDK4412 SMDK4412 3765 diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile index 6de73aa..a81404c 100644 --- a/arch/arm/vfp/Makefile +++ b/arch/arm/vfp/Makefile @@ -7,7 +7,7 @@ # ccflags-y := -DDEBUG # asflags-y := -DDEBUG -KBUILD_AFLAGS :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp) +KBUILD_AFLAGS :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp -mfloat-abi=soft) LDFLAGS +=--no-warn-mismatch obj-y += vfp.o |