diff options
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/p4080si-post.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 230 |
1 files changed, 226 insertions, 4 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi index 34769a7..5f9b908 100644 --- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi @@ -41,7 +41,7 @@ /* controller at 0x200000 */ &pci0 { - compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; + compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1", "fsl,qoriq-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; @@ -70,7 +70,7 @@ /* controller at 0x201000 */ &pci1 { - compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; + compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1", "fsl,qoriq-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; @@ -99,7 +99,7 @@ /* controller at 0x202000 */ &pci2 { - compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1"; + compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1", "fsl,qoriq-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; @@ -243,6 +243,14 @@ }; +&bportals { +/include/ "qoriq-bman1-portals.dtsi" +}; + +&qportals { +/include/ "qoriq-qman1-portals.dtsi" +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -352,9 +360,107 @@ }; clockgen: global-utilities@e1000 { - compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; + compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0", + "fixed-clock"; reg = <0xe1000 0x1000>; clock-frequency = <0>; + clock-output-names = "sysclk"; + #clock-cells = <0>; + + #address-cells = <1>; + #size-cells = <0>; + pll0: pll0@800 { + #clock-cells = <1>; + reg = <0x800>; + compatible = "fsl,core-pll-clock"; + clocks = <&clockgen>; + clock-output-names = "pll0", "pll0-div2"; + }; + pll1: pll1@820 { + #clock-cells = <1>; + reg = <0x820>; + compatible = "fsl,core-pll-clock"; + clocks = <&clockgen>; + clock-output-names = "pll1", "pll1-div2"; + }; + pll2: pll2@840 { + #clock-cells = <1>; + reg = <0x840>; + compatible = "fsl,core-pll-clock"; + clocks = <&clockgen>; + clock-output-names = "pll2", "pll2-div2"; + }; + pll3: pll2@860 { + #clock-cells = <1>; + reg = <0x860>; + compatible = "fsl,core-pll-clock"; + clocks = <&clockgen>; + clock-output-names = "pll3", "pll3-div2"; + }; + mux0: mux0@0 { + #clock-cells = <0>; + reg = <0x0>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1"; + clock-output-names = "cmux0"; + }; + mux1: mux1@20 { + #clock-cells = <0>; + reg = <0x20>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1"; + clock-output-names = "cmux1"; + }; + mux2: mux2@40 { + #clock-cells = <0>; + reg = <0x40>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1"; + clock-output-names = "cmux2"; + }; + mux3: mux3@60 { + #clock-cells = <0>; + reg = <0x60>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1"; + clock-output-names = "cmux3"; + }; + mux4: mux4@80 { + #clock-cells = <0>; + reg = <0x80>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; + clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1"; + clock-output-names = "cmux4"; + }; + mux5: mux5@a0 { + #clock-cells = <0>; + reg = <0xa0>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; + clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1"; + clock-output-names = "cmux5"; + }; + mux6: mux6@c0 { + #clock-cells = <0>; + reg = <0xc0>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; + clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1"; + clock-output-names = "cmux6"; + }; + mux7: mux7@e0 { + #clock-cells = <0>; + reg = <0xe0>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; + clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1"; + clock-output-names = "cmux7"; + }; }; rcpm: global-utilities@e2000 { @@ -392,6 +498,7 @@ /include/ "qoriq-esdhc-0.dtsi" sdhc@114000 { + compatible = "fsl,p4080-esdhc", "fsl,esdhc"; fsl,iommu-parent = <&pamu1>; fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ voltage-ranges = <3300 3300>; @@ -419,5 +526,120 @@ /include/ "qoriq-sec4.0-0.dtsi" crypto: crypto@300000 { fsl,iommu-parent = <&pamu1>; +}; +/include/ "qoriq-pme-0.dtsi" +/include/ "qoriq-qman1.dtsi" +/include/ "qoriq-bman1.dtsi" +/include/ "qoriq-fman-0.dtsi" +/include/ "qoriq-fman-0-1g-0.dtsi" +/include/ "qoriq-fman-0-1g-1.dtsi" +/include/ "qoriq-fman-0-1g-2.dtsi" +/include/ "qoriq-fman-0-1g-3.dtsi" +/include/ "qoriq-fman-0-10g-0.dtsi" + fman0: fman@400000 { + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x41>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x42>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x43>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x44>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x40>; + }; + /* offline 0 */ + port@81000 { + fsl,qman-channel-id = <0x45>; + }; + /* offline 1 */ + port@82000 { + fsl,qman-channel-id = <0x46>; + }; + /* offline 2 */ + port@83000 { + fsl,qman-channel-id = <0x47>; + }; + /* offline 3 */ + port@84000 { + fsl,qman-channel-id = <0x48>; + }; + /* offline 4 */ + port@85000 { + fsl,qman-channel-id = <0x49>; + }; + /* offline 5 */ + port@86000 { + fsl,qman-channel-id = <0x4a>; + }; + /* offline 6 */ + port@87000 { + fsl,qman-channel-id = <0x4b>; + }; + }; +/include/ "qoriq-fman-1.dtsi" +/include/ "qoriq-fman-1-1g-0.dtsi" +/include/ "qoriq-fman-1-1g-1.dtsi" +/include/ "qoriq-fman-1-1g-2.dtsi" +/include/ "qoriq-fman-1-1g-3.dtsi" +/include/ "qoriq-fman-1-10g-0.dtsi" + fman1: fman@500000 { + /* tx - 1g - 0 */ + port@a8000 { + fsl,qman-channel-id = <0x61>; + }; + /* tx - 1g - 1 */ + port@a9000 { + fsl,qman-channel-id = <0x62>; + }; + /* tx - 1g - 2 */ + port@aa000 { + fsl,qman-channel-id = <0x63>; + }; + /* tx - 1g - 3 */ + port@ab000 { + fsl,qman-channel-id = <0x64>; + }; + /* tx - 10g - 0 */ + port@b0000 { + fsl,qman-channel-id = <0x60>; + }; + /* offline 0 */ + port@81000 { + fsl,qman-channel-id = <0x65>; + }; + /* offline 1 */ + port@82000 { + fsl,qman-channel-id = <0x66>; + }; + /* offline 2 */ + port@83000 { + fsl,qman-channel-id = <0x67>; + }; + /* offline 3 */ + port@84000 { + fsl,qman-channel-id = <0x68>; + }; + /* offline 4 */ + port@85000 { + fsl,qman-channel-id = <0x69>; + }; + /* offline 5 */ + port@86000 { + fsl,qman-channel-id = <0x6a>; + }; + /* offline 6 */ + port@87000 { + fsl,qman-channel-id = <0x6b>; + }; }; }; |