diff options
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi index 8df47fc..ee4b45f 100644 --- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi @@ -6,13 +6,13 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the @@ -74,6 +74,12 @@ rtic_d = &rtic_d; sec_mon = &sec_mon; + rman = &rman; + pme = &pme; + qman = &qman; + bman = &bman; + fman0 = &fman0; + raideng = &raideng; raideng_jr0 = &raideng_jr0; raideng_jr1 = &raideng_jr1; @@ -88,6 +94,7 @@ cpu0: PowerPC,e5500@0 { device_type = "cpu"; reg = <0>; + clocks = <&mux0>; next-level-cache = <&L2_0>; L2_0: l2-cache { next-level-cache = <&cpc>; @@ -96,6 +103,7 @@ cpu1: PowerPC,e5500@1 { device_type = "cpu"; reg = <1>; + clocks = <&mux1>; next-level-cache = <&L2_1>; L2_1: l2-cache { next-level-cache = <&cpc>; |