diff options
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi')
-rw-r--r-- | arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 49 |
1 files changed, 48 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi index a93c55a..40f2845 100644 --- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi @@ -20,7 +20,7 @@ * Foundation, either version 2 of that License or (at your option) any * later version. * - * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY @@ -50,11 +50,39 @@ serial1 = &serial1; serial2 = &serial2; serial3 = &serial3; + + rman = &rman; + lac = &lac; crypto = &crypto; + dce = &dce; + pme = &pme; + qman = &qman; + bman = &bman; + fman0 = &fman0; + fman1 = &fman1; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + ethernet4 = &enet4; + ethernet5 = &enet5; + ethernet6 = &enet6; + ethernet7 = &enet7; + ethernet8 = &enet8; + ethernet9 = &enet9; + ethernet10 = &enet10; + ethernet11 = &enet11; + ethernet12 = &enet12; + ethernet13 = &enet13; + ethernet14 = &enet14; + ethernet15 = &enet15; + pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; pci3 = &pci3; + usb0 = &usb0; + usb1 = &usb1; dma0 = &dma0; dma1 = &dma1; sdhc = &sdhc; @@ -64,64 +92,83 @@ #address-cells = <1>; #size-cells = <0>; + /* + * Temporarily add next-level-cache info in each cpu node so + * that uboot can do L2 cache fixup. This can be removed once + * u-boot can create cpu node with cache info. + */ cpu0: PowerPC,e6500@0 { device_type = "cpu"; reg = <0 1>; + clocks = <&mux0>; next-level-cache = <&L2_1>; }; cpu1: PowerPC,e6500@2 { device_type = "cpu"; reg = <2 3>; + clocks = <&mux0>; next-level-cache = <&L2_1>; }; cpu2: PowerPC,e6500@4 { device_type = "cpu"; reg = <4 5>; + clocks = <&mux0>; next-level-cache = <&L2_1>; }; cpu3: PowerPC,e6500@6 { device_type = "cpu"; reg = <6 7>; + clocks = <&mux0>; next-level-cache = <&L2_1>; }; + cpu4: PowerPC,e6500@8 { device_type = "cpu"; reg = <8 9>; + clocks = <&mux1>; next-level-cache = <&L2_2>; }; cpu5: PowerPC,e6500@10 { device_type = "cpu"; reg = <10 11>; + clocks = <&mux1>; next-level-cache = <&L2_2>; }; cpu6: PowerPC,e6500@12 { device_type = "cpu"; reg = <12 13>; + clocks = <&mux1>; next-level-cache = <&L2_2>; }; cpu7: PowerPC,e6500@14 { device_type = "cpu"; reg = <14 15>; + clocks = <&mux1>; next-level-cache = <&L2_2>; }; + cpu8: PowerPC,e6500@16 { device_type = "cpu"; reg = <16 17>; + clocks = <&mux2>; next-level-cache = <&L2_3>; }; cpu9: PowerPC,e6500@18 { device_type = "cpu"; reg = <18 19>; + clocks = <&mux2>; next-level-cache = <&L2_3>; }; cpu10: PowerPC,e6500@20 { device_type = "cpu"; reg = <20 21>; + clocks = <&mux2>; next-level-cache = <&L2_3>; }; cpu11: PowerPC,e6500@22 { device_type = "cpu"; reg = <22 23>; + clocks = <&mux2>; next-level-cache = <&L2_3>; }; }; |