diff options
Diffstat (limited to 'arch/powerpc/boot/dts/p5040ds.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/p5040ds.dts | 407 |
1 files changed, 401 insertions, 6 deletions
diff --git a/arch/powerpc/boot/dts/p5040ds.dts b/arch/powerpc/boot/dts/p5040ds.dts index 860b5cc..934ebb0 100644 --- a/arch/powerpc/boot/dts/p5040ds.dts +++ b/arch/powerpc/boot/dts/p5040ds.dts @@ -6,13 +6,13 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the @@ -41,6 +41,49 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + aliases { + ethernet0 = &fm1dtsec1; + ethernet1 = &fm1dtsec2; + ethernet2 = &fm1dtsec3; + ethernet3 = &fm1dtsec4; + ethernet4 = &fm1dtsec5; + ethernet5 = &fm1tgec; + ethernet6 = &fm2dtsec1; + ethernet7 = &fm2dtsec2; + ethernet8 = &fm2dtsec3; + ethernet9 = &fm2dtsec4; + ethernet10 = &fm2dtsec5; + ethernet11 = &fm2tgec; + + phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c; + phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d; + phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e; + phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f; + + phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c; + phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d; + phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e; + phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f; + + phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c; + phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d; + phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e; + phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f; + + phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c; + phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d; + phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e; + phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f; + + hydra_rg = &hydra_rg; + hydra_sg_slot2 = &hydra_sg_slot2; + hydra_sg_slot3 = &hydra_sg_slot3; + hydra_sg_slot5 = &hydra_sg_slot5; + hydra_sg_slot6 = &hydra_sg_slot6; + hydra_xg_slot1 = &hydra_xg_slot1; + hydra_xg_slot2 = &hydra_xg_slot2; + }; + memory { device_type = "memory"; }; @@ -49,6 +92,14 @@ ranges = <0x00000000 0xf 0x00000000 0x01008000>; }; + bportals: bman-portals@ff4000000 { + ranges = <0x0 0xf 0xf4000000 0x200000>; + }; + + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; @@ -62,14 +113,17 @@ partition@u-boot { label = "u-boot"; reg = <0x00000000 0x00100000>; + read-only; }; partition@kernel { label = "kernel"; reg = <0x00100000 0x00500000>; + read-only; }; partition@dtb { label = "dtb"; reg = <0x00600000 0x00100000>; + read-only; }; partition@fs { label = "file system"; @@ -100,6 +154,148 @@ reg = <0x4c>; }; }; + + fman0: fman@400000 { + fm1dtsec1: ethernet@e0000 { + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + }; + + mdio0: mdio@e1120 { + tbi0: tbi-phy@8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; + }; + + fm1dtsec2: ethernet@e2000 { + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + mdio@e3120 { + tbi1: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm1dtsec3: ethernet@e4000 { + tbi-handle = <&tbi2>; + phy-connection-type = "sgmii"; + }; + + mdio@e5120 { + tbi2: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm1dtsec4: ethernet@e6000 { + tbi-handle = <&tbi3>; + phy-connection-type = "sgmii"; + }; + + mdio@e7120 { + #address-cells = <1>; + #size-cells = <0>; + tbi3: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm1dtsec5: ethernet@e8000 { + tbi-handle = <&tbi4>; + phy-handle = <&phy_rgmii_0>; + phy-connection-type = "rgmii"; + }; + + mdio@e9120 { + tbi4: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm1tgec: ethernet@f0000 { + phy-handle = <&phy_xgmii_slot_2>; + phy-connection-type = "xgmii"; + }; + + xmdio0: mdio@f1000 { + }; + + }; + + fman1: fman@500000 { + fm2dtsec1: ethernet@e0000 { + tbi-handle = <&tbi5>; + phy-connection-type = "sgmii"; + }; + + mdio@e1120 { + tbi5: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm2dtsec2: ethernet@e2000 { + tbi-handle = <&tbi6>; + phy-connection-type = "sgmii"; + }; + + mdio@e3120 { + tbi6: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm2dtsec3: ethernet@e4000 { + tbi-handle = <&tbi7>; + phy-connection-type = "sgmii"; + }; + + mdio@e5120 { + tbi7: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm2dtsec4: ethernet@e6000 { + tbi-handle = <&tbi8>; + phy-connection-type = "sgmii"; + }; + + mdio@e7120 { + tbi8: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm2dtsec5: ethernet@e8000 { + tbi-handle = <&tbi9>; + phy-handle = <&phy_rgmii_1>; + phy-connection-type = "rgmii"; + }; + + mdio@e9120 { + tbi9: tbi-phy@8 { + reg = <8>; + device_type = "tbi-phy"; + }; + }; + + fm2tgec: ethernet@f0000 { + phy-handle = <&phy_xgmii_slot_1>; + phy-connection-type = "xgmii"; + }; + }; }; lbc: localbus@ffe124000 { @@ -124,6 +320,7 @@ partition@0 { label = "NAND U-Boot Image"; reg = <0x0 0x02000000>; + read-only; }; partition@2000000 { @@ -153,8 +350,150 @@ }; board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis"; - reg = <3 0 0x40>; + reg = <3 0 0x30>; + ranges = <0 3 0 0x30>; + + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <9 1>; // BRDCFG1 + mux-mask = <0x78>; // EMI1 + + /* + * Virtual MDIO for the two on-board RGMII + * ports. The reg property is already correct. + */ + hydra_rg: rgmii-mdio@8 { + status = "disabled"; + reg = <8>; /* EMI1_EN | 0 */ + #address-cells = <1>; + #size-cells = <0>; + + phy_rgmii_0: ethernet-phy@0 { + reg = <0x0>; + }; + phy_rgmii_1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + /* + * Virtual MDIO for the four-port SGMII cards. + */ + hydra_sg_slot2: sgmii-mdio@28 { + reg = <0x28>; /* EMI1_EN | 0x20 */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + phy_sgmii_slot2_1c: ethernet-phy@1c { + reg = <0x1c>; + }; + phy_sgmii_slot2_1d: ethernet-phy@1d { + reg = <0x1d>; + }; + phy_sgmii_slot2_1e: ethernet-phy@1e { + reg = <0x1e>; + }; + phy_sgmii_slot2_1f: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + hydra_sg_slot3: sgmii-mdio@68 { + reg = <0x68>; /* EMI1_EN | 0x60 */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + phy_sgmii_slot3_1c: ethernet-phy@1c { + reg = <0x1c>; + }; + phy_sgmii_slot3_1d: ethernet-phy@1d { + reg = <0x1d>; + }; + phy_sgmii_slot3_1e: ethernet-phy@1e { + reg = <0x1e>; + }; + phy_sgmii_slot3_1f: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + hydra_sg_slot5: sgmii-mdio@38 { + reg = <0x38>; /* EMI1_EN | 0x30 */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + phy_sgmii_slot5_1c: ethernet-phy@1c { + reg = <0x1c>; + }; + phy_sgmii_slot5_1d: ethernet-phy@1d { + reg = <0x1d>; + }; + phy_sgmii_slot5_1e: ethernet-phy@1e { + reg = <0x1e>; + }; + phy_sgmii_slot5_1f: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + hydra_sg_slot6: sgmii-mdio@48 { + reg = <0x48>; /* EMI1_EN | 0x40 */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + phy_sgmii_slot6_1c: ethernet-phy@1c { + reg = <0x1c>; + }; + phy_sgmii_slot6_1d: ethernet-phy@1d { + reg = <0x1d>; + }; + phy_sgmii_slot6_1e: ethernet-phy@1e { + reg = <0x1e>; + }; + phy_sgmii_slot6_1f: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + mdio-mux-emi2 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&xmdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <9 1>; // BRDCFG1 + mux-mask = <0x06>; // EMI2 + + /* FM2 10GEC1 is always on slot 1 */ + hydra_xg_slot1: hydra-xg-slot1@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + phy_xgmii_slot_1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + + /* FM1 10GEC1 is always on slot 2 */ + hydra_xg_slot2: hydra-xg-slot2@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + phy_xgmii_slot_2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; + }; + }; }; }; @@ -202,6 +541,62 @@ 0 0x00010000>; }; }; + + fsl,dpaa { + compatible = "fsl,p5040-dpaa", "fsl,dpaa"; + + ethernet@0 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm1dtsec1>; + status = "disabled"; + }; + ethernet@1 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm1dtsec2>; + }; + ethernet@2 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm1dtsec3>; + }; + ethernet@3 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm1dtsec4>; + }; + ethernet@4 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm1dtsec5>; + }; + ethernet@5 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm1tgec>; + }; + ethernet@6 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm2dtsec1>; + status = "disabled"; + }; + ethernet@7 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm2dtsec2>; + }; + ethernet@8 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm2dtsec3>; + }; + ethernet@9 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm2dtsec4>; + }; + ethernet@10 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm2dtsec5>; + }; + ethernet@11 { + compatible = "fsl,p5040-dpa-ethernet", "fsl,dpa-ethernet"; + fsl,fman-mac = <&fm2tgec>; + }; + }; }; /include/ "fsl/p5040si-post.dtsi" +/include/ "fsl/qoriq-dpaa-res1.dtsi" |