diff options
Diffstat (limited to 'arch/powerpc/include/asm/reg_booke.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index b417de3..8987ca3 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -30,14 +30,23 @@ #define MSR_64BIT MSR_CM #define MSR_ MSR_ME | MSR_CE +#if defined(CONFIG_DEBUG_CW) +#define MSR_KERNEL (MSR_ | MSR_64BIT | MSR_DE) +#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE | MSR_DE) +#else #define MSR_KERNEL MSR_ | MSR_64BIT #define MSR_USER32 MSR_ | MSR_PR | MSR_EE +#endif #define MSR_USER64 MSR_USER32 | MSR_64BIT #elif defined (CONFIG_40x) #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) #else +#if defined(CONFIG_DEBUG_CW) +#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE|MSR_DE) +#else #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) +#endif #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) #endif @@ -170,6 +179,7 @@ #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ #define SPRN_SVR 0x3FF /* System Version Register */ /* @@ -216,6 +226,14 @@ #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ #define CCR1_TCS 0x00000080 /* Timer Clock Select */ +/* Bit definitions for PWRMGTCR0. */ +#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */ +#define PWRMGTCR0_PW20_ENT_SHIFT 8 +#define PWRMGTCR0_PW20_ENT 0x3F00 +#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */ +#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16 +#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000 + /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ @@ -587,6 +605,13 @@ /* Bit definitions for L1CSR2. */ #define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */ +/* Bit definitions for BUCSR. */ +#define BUCSR_STAC_EN 0x01000000 /* Segment Target Address Cache */ +#define BUCSR_LS_EN 0x00400000 /* Link Stack */ +#define BUCSR_BBFI 0x00000200 /* Branch Buffer flash invalidate */ +#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */ +#define BUCSR_INIT (BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN) + /* Bit definitions for L2CSR0. */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ @@ -710,5 +735,26 @@ #define MMUBE1_VBE4 0x00000002 #define MMUBE1_VBE5 0x00000001 +#define TMRN_TMCFG0 0x010 /* Thread Management Configuration Register 0 */ +#define TMRN_TPRI0 0x0C0 /* Thread Priority Register 0 */ +#define TMRN_TPRI1 0x0C1 /* Thread Priority Register 1 */ +#define TMRN_TPRI2 0x0C2 /* Thread Priority Register 2 */ +#define TMRN_INIA0 0x140 /* Next Instruction Address Register 0 */ +#define TMRN_INIA1 0x141 /* Next Instruction Address Register 1 */ +#define TMRN_INIA2 0x142 /* Next Instruction Address Register 2 */ +#define TMRN_IMSR0 0x120 /* Initial MSR Register 0 */ +#define TMRN_IMSR1 0x121 /* Initial MSR Register 1 */ +#define SPRN_TENSR 0x1b5 /* Thread Enable Status Register */ +#define SPRN_TENS 0x1b6 /* Thread Enable Set Register */ +#define SPRN_TENC 0x1b7 /* Thread Enable Clear Register */ + +#define TEN_THREAD(x) (1 << x) + +#define SPRN_PPR32 0x382 /* Processor Priority Register */ + +#define TMRN(x) (((x & 0x1f) << 16) | ((x & 0x3e0) << 6)) +#define MTTMR(tmr, reg) .long (0x7c0003dc | TMRN(tmr) | (reg << 21)) +#define MFTMR(tmr, reg) .long (0x7c0002dc | TMRN(tmr) | (reg << 21)) + #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ #endif /* __KERNEL__ */ |