diff options
Diffstat (limited to 'arch/powerpc/platforms/85xx/mpc85xx_rdb.c')
| -rw-r--r-- | arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 106 |
1 files changed, 83 insertions, 23 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index ede8771..6bbd92f 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -90,6 +90,11 @@ static void __init mpc85xx_rdb_setup_arch(void) struct device_node *np; #endif +#if defined(CONFIG_QUICC_ENGINE) && defined(CONFIG_SPI_FSL_SPI) + struct device_node *qe_spi; +#endif + struct ccsr_guts __iomem *guts; + if (ppc_md.progress) ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); @@ -117,38 +122,71 @@ static void __init mpc85xx_rdb_setup_arch(void) for_each_node_by_name(ucc, "ucc") par_io_of_config(ucc); + /* To P1025 QE/TDM, the name of ucc nodes is "tdm@xxxx" */ + for_each_node_by_name(ucc, "tdm") + par_io_of_config(ucc); +#ifdef CONFIG_SPI_FSL_SPI + for_each_node_by_name(qe_spi, "spi") + par_io_of_config(qe_spi); +#endif /* CONFIG_SPI_FSL_SPI */ } -#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) - if (machine_is(p1025_rdb)) { - - struct ccsr_guts __iomem *guts; - np = of_find_node_by_name(NULL, "global-utilities"); - if (np) { - guts = of_iomap(np, 0); - if (!guts) { - - pr_err("mpc85xx-rdb: could not map global utilities register\n"); - - } else { - /* P1025 has pins muxed for QE and other functions. To - * enable QE UEC mode, we need to set bit QE0 for UCC1 - * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 - * and QE12 for QE MII management singals in PMUXCR - * register. - */ + np = of_find_node_by_name(NULL, "global-utilities"); + if (np) { + guts = of_iomap(np, 0); + if (!guts) + pr_err("mpc85xx-rdb: could not map global " + "utilities register\n"); + else { +#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) + if (machine_is(p1025_rdb)) { + /* + * P1025 has pins muxed for QE and other + * functions. To enable QE UEC mode, we + * need to set bit QE0 for UCC1 in Eth mode, + * QE0 and QE3 for UCC5 in Eth mode, QE9 + * and QE12 for QE MII management singals + * in PMUXCR register. + */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); - iounmap(guts); } - of_node_put(np); - } - - } #endif +#ifdef CONFIG_FSL_UCC_TDM + if (machine_is(p1021_rdb_pc) || machine_is(p1025_rdb)) { + + /* Clear QE12 for releasing the LBCTL */ + clrbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(12)); + /* TDMA */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(5) | + MPC85xx_PMUXCR_QE(11)); + /* TDMB */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | + MPC85xx_PMUXCR_QE(9)); + /* TDMC */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0)); + /* TDMD */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(8) | + MPC85xx_PMUXCR_QE(7)); + } +#endif /* CONFIG_FSL_UCC_TDM */ + +#ifdef CONFIG_SPI_FSL_SPI + if (of_find_compatible_node(NULL, NULL, "fsl,mpc8569-qe-spi")) { + clrbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(12)); + /*QE-SPI*/ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(6) | + MPC85xx_PMUXCR_QE(9) | + MPC85xx_PMUXCR_QE(10)); + } +#endif /* CONFIG_SPI_FSL_SPI */ + iounmap(guts); + } + of_node_put(np); + } qe_fail: #endif /* CONFIG_QUICC_ENGINE */ @@ -160,6 +198,7 @@ machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); +machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); @@ -193,6 +232,13 @@ static int __init p1020_rdb_pc_probe(void) return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC"); } +static int __init p1020_rdb_pd_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PD"); +} + static int __init p1021_rdb_pc_probe(void) { unsigned long root = of_get_flat_dt_root(); @@ -351,6 +397,20 @@ define_machine(p1020_rdb_pc) { .progress = udbg_progress, }; +define_machine(p1020_rdb_pd) { + .name = "P1020RDB-PD", + .probe = p1020_rdb_pd_probe, + .setup_arch = mpc85xx_rdb_setup_arch, + .init_IRQ = mpc85xx_rdb_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; + define_machine(p1024_rdb) { .name = "P1024 RDB", .probe = p1024_rdb_probe, |